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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.34 95.26 97.17 100.00 100.00 98.12 97.97 99.85


Total test records in report: 658
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T533 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.906247078 Jul 12 05:37:30 PM PDT 24 Jul 12 05:37:37 PM PDT 24 39454523 ps
T534 /workspace/coverage/cover_reg_top/11.hmac_intr_test.341325371 Jul 12 05:37:53 PM PDT 24 Jul 12 05:38:15 PM PDT 24 13194427 ps
T535 /workspace/coverage/cover_reg_top/34.hmac_intr_test.304294426 Jul 12 05:37:35 PM PDT 24 Jul 12 05:37:38 PM PDT 24 13293788 ps
T536 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.505815362 Jul 12 05:37:32 PM PDT 24 Jul 12 05:37:39 PM PDT 24 160832636 ps
T537 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.270760198 Jul 12 05:37:18 PM PDT 24 Jul 12 05:37:28 PM PDT 24 47001340 ps
T101 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.659606997 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:28 PM PDT 24 29070912 ps
T538 /workspace/coverage/cover_reg_top/19.hmac_intr_test.132298284 Jul 12 05:37:36 PM PDT 24 Jul 12 05:37:40 PM PDT 24 30816537 ps
T49 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.5103708 Jul 12 05:37:23 PM PDT 24 Jul 12 05:37:35 PM PDT 24 1578549287 ps
T102 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3790450927 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:30 PM PDT 24 29223714 ps
T539 /workspace/coverage/cover_reg_top/3.hmac_intr_test.354398046 Jul 12 05:37:19 PM PDT 24 Jul 12 05:37:26 PM PDT 24 62334871 ps
T540 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.196034754 Jul 12 05:37:37 PM PDT 24 Jul 12 05:37:42 PM PDT 24 1127217853 ps
T50 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.188080472 Jul 12 05:37:45 PM PDT 24 Jul 12 05:37:57 PM PDT 24 448361481 ps
T118 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1981605093 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:33 PM PDT 24 331209540 ps
T541 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1008705693 Jul 12 05:37:38 PM PDT 24 Jul 12 05:37:41 PM PDT 24 27830948 ps
T542 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2023049607 Jul 12 05:38:29 PM PDT 24 Jul 12 05:38:44 PM PDT 24 819527001 ps
T543 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3883331231 Jul 12 05:37:35 PM PDT 24 Jul 12 05:37:39 PM PDT 24 31076612 ps
T544 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2651265283 Jul 12 05:37:33 PM PDT 24 Jul 12 05:37:39 PM PDT 24 166695835 ps
T545 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3593293180 Jul 12 05:37:51 PM PDT 24 Jul 12 05:38:11 PM PDT 24 43183985 ps
T103 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.977144546 Jul 12 05:37:25 PM PDT 24 Jul 12 05:37:45 PM PDT 24 1228914138 ps
T546 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2022479695 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:34 PM PDT 24 105562414 ps
T547 /workspace/coverage/cover_reg_top/45.hmac_intr_test.47445427 Jul 12 05:37:36 PM PDT 24 Jul 12 05:37:39 PM PDT 24 38161199 ps
T548 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3074238209 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:32 PM PDT 24 58577652 ps
T549 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3256581126 Jul 12 05:37:43 PM PDT 24 Jul 12 05:37:46 PM PDT 24 41177380 ps
T550 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1461532405 Jul 12 05:37:27 PM PDT 24 Jul 12 05:37:37 PM PDT 24 506173285 ps
T104 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3624814162 Jul 12 05:38:45 PM PDT 24 Jul 12 05:38:55 PM PDT 24 120090881 ps
T551 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2167540527 Jul 12 05:37:19 PM PDT 24 Jul 12 05:37:26 PM PDT 24 21277714 ps
T552 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3525109548 Jul 12 05:37:51 PM PDT 24 Jul 12 05:38:09 PM PDT 24 15665142 ps
T553 /workspace/coverage/cover_reg_top/36.hmac_intr_test.266094941 Jul 12 05:37:54 PM PDT 24 Jul 12 05:38:17 PM PDT 24 13624491 ps
T554 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2509846585 Jul 12 05:38:07 PM PDT 24 Jul 12 05:38:27 PM PDT 24 15320436 ps
T51 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1996956774 Jul 12 05:37:41 PM PDT 24 Jul 12 05:37:46 PM PDT 24 462754875 ps
T119 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.802501712 Jul 12 05:37:23 PM PDT 24 Jul 12 05:37:31 PM PDT 24 171337348 ps
T120 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.247768969 Jul 12 05:37:23 PM PDT 24 Jul 12 05:37:32 PM PDT 24 119124914 ps
T555 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3550125603 Jul 12 05:37:45 PM PDT 24 Jul 12 05:37:53 PM PDT 24 110591729 ps
T556 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3818124181 Jul 12 05:37:49 PM PDT 24 Jul 12 05:38:09 PM PDT 24 825277473 ps
T557 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1747758593 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:29 PM PDT 24 19240694 ps
T558 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3263675490 Jul 12 05:38:04 PM PDT 24 Jul 12 05:38:26 PM PDT 24 12112750 ps
T559 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3740104409 Jul 12 05:37:31 PM PDT 24 Jul 12 05:37:37 PM PDT 24 190511928 ps
T560 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4003162111 Jul 12 05:37:37 PM PDT 24 Jul 12 05:37:41 PM PDT 24 21399370 ps
T561 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1205472600 Jul 12 05:37:35 PM PDT 24 Jul 12 05:37:41 PM PDT 24 301844750 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2113832239 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:33 PM PDT 24 569783974 ps
T134 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.907731874 Jul 12 05:37:26 PM PDT 24 Jul 12 05:37:36 PM PDT 24 187351691 ps
T562 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3834592227 Jul 12 05:37:48 PM PDT 24 Jul 12 05:38:04 PM PDT 24 1220555879 ps
T121 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3007469356 Jul 12 05:37:19 PM PDT 24 Jul 12 05:37:28 PM PDT 24 34148780 ps
T563 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3043969427 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 20525755 ps
T122 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1405331832 Jul 12 05:37:58 PM PDT 24 Jul 12 05:38:21 PM PDT 24 51506864 ps
T564 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1758578458 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:32 PM PDT 24 105447162 ps
T565 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3301874140 Jul 12 05:37:29 PM PDT 24 Jul 12 05:37:37 PM PDT 24 98629187 ps
T566 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.742834782 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:32 PM PDT 24 115373539 ps
T106 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2100310925 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:40 PM PDT 24 162774194 ps
T567 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2062996267 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:28 PM PDT 24 74916828 ps
T123 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3225920212 Jul 12 05:37:43 PM PDT 24 Jul 12 05:37:48 PM PDT 24 89605883 ps
T568 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1183849405 Jul 12 05:37:27 PM PDT 24 Jul 12 05:37:34 PM PDT 24 22296490 ps
T569 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3950404310 Jul 12 05:37:23 PM PDT 24 Jul 12 05:37:31 PM PDT 24 70827833 ps
T570 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3883186877 Jul 12 05:38:41 PM PDT 24 Jul 12 05:38:49 PM PDT 24 22158354 ps
T571 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3548514690 Jul 12 05:37:35 PM PDT 24 Jul 12 05:37:38 PM PDT 24 50363930 ps
T572 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.293651186 Jul 12 05:37:17 PM PDT 24 Jul 12 05:37:26 PM PDT 24 97346050 ps
T573 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2178925955 Jul 12 05:37:18 PM PDT 24 Jul 12 05:37:25 PM PDT 24 68935481 ps
T574 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1056114774 Jul 12 05:37:35 PM PDT 24 Jul 12 05:37:38 PM PDT 24 34901167 ps
T575 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2937528817 Jul 12 05:37:18 PM PDT 24 Jul 12 05:37:26 PM PDT 24 61682482 ps
T576 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1153309104 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:38 PM PDT 24 854603210 ps
T577 /workspace/coverage/cover_reg_top/47.hmac_intr_test.718346461 Jul 12 05:37:30 PM PDT 24 Jul 12 05:37:35 PM PDT 24 24359912 ps
T578 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2985929434 Jul 12 05:37:32 PM PDT 24 Jul 12 05:37:36 PM PDT 24 20497483 ps
T579 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4162350261 Jul 12 05:37:27 PM PDT 24 Jul 12 05:37:34 PM PDT 24 44698446 ps
T580 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3941918308 Jul 12 05:37:43 PM PDT 24 Jul 12 05:39:40 PM PDT 24 11285779273 ps
T130 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.55141382 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:30 PM PDT 24 1168491287 ps
T581 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2638919892 Jul 12 05:37:34 PM PDT 24 Jul 12 05:38:10 PM PDT 24 2213409713 ps
T135 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1724041682 Jul 12 05:37:17 PM PDT 24 Jul 12 05:37:28 PM PDT 24 164084870 ps
T582 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2616691304 Jul 12 05:37:51 PM PDT 24 Jul 12 05:38:11 PM PDT 24 12923966 ps
T583 /workspace/coverage/cover_reg_top/40.hmac_intr_test.269753667 Jul 12 05:37:41 PM PDT 24 Jul 12 05:37:43 PM PDT 24 21887654 ps
T584 /workspace/coverage/cover_reg_top/26.hmac_intr_test.463670705 Jul 12 05:37:49 PM PDT 24 Jul 12 05:38:05 PM PDT 24 33940196 ps
T585 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2740473377 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 139168437 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.387811279 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:33 PM PDT 24 48572924 ps
T587 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1034491825 Jul 12 05:37:51 PM PDT 24 Jul 12 05:38:09 PM PDT 24 47892859 ps
T132 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1783767602 Jul 12 05:37:34 PM PDT 24 Jul 12 05:37:39 PM PDT 24 305177959 ps
T588 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3981624464 Jul 12 05:37:54 PM PDT 24 Jul 12 05:38:17 PM PDT 24 32998817 ps
T589 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2761965224 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:32 PM PDT 24 167267512 ps
T590 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2904566866 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:27 PM PDT 24 13334955 ps
T107 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3885234930 Jul 12 05:38:45 PM PDT 24 Jul 12 05:38:52 PM PDT 24 16733988 ps
T591 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2132513441 Jul 12 05:37:38 PM PDT 24 Jul 12 05:37:42 PM PDT 24 17037482 ps
T592 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2468519277 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:30 PM PDT 24 46606900 ps
T131 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.962927274 Jul 12 05:38:13 PM PDT 24 Jul 12 05:38:35 PM PDT 24 148150626 ps
T593 /workspace/coverage/cover_reg_top/29.hmac_intr_test.709346269 Jul 12 05:37:37 PM PDT 24 Jul 12 05:37:41 PM PDT 24 197335789 ps
T108 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2155193253 Jul 12 05:37:53 PM PDT 24 Jul 12 05:38:13 PM PDT 24 47197921 ps
T138 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2611649276 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:32 PM PDT 24 775759043 ps
T594 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1825442797 Jul 12 05:37:14 PM PDT 24 Jul 12 05:37:21 PM PDT 24 22647104 ps
T595 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3893615426 Jul 12 05:37:31 PM PDT 24 Jul 12 05:37:36 PM PDT 24 195371457 ps
T136 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2878842575 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:33 PM PDT 24 539985430 ps
T596 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2199445704 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:30 PM PDT 24 193985715 ps
T597 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2673556718 Jul 12 05:37:37 PM PDT 24 Jul 12 05:37:41 PM PDT 24 19392382 ps
T109 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1921171338 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:32 PM PDT 24 16516720 ps
T598 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2206599712 Jul 12 05:37:15 PM PDT 24 Jul 12 05:37:22 PM PDT 24 16697605 ps
T599 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3784637190 Jul 12 05:37:36 PM PDT 24 Jul 12 05:37:40 PM PDT 24 82253908 ps
T600 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1715557326 Jul 12 05:37:33 PM PDT 24 Jul 12 05:37:38 PM PDT 24 253239518 ps
T137 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.105675274 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:31 PM PDT 24 80620671 ps
T133 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3869065574 Jul 12 05:37:14 PM PDT 24 Jul 12 05:37:22 PM PDT 24 172420078 ps
T601 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1133652089 Jul 12 05:37:27 PM PDT 24 Jul 12 05:37:49 PM PDT 24 1084441676 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.339209237 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 21239447 ps
T602 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3408642746 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:30 PM PDT 24 94979530 ps
T603 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.76592617 Jul 12 05:37:26 PM PDT 24 Jul 12 05:37:36 PM PDT 24 732421295 ps
T604 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4287406415 Jul 12 05:37:57 PM PDT 24 Jul 12 05:38:21 PM PDT 24 47407640 ps
T605 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.834661713 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 427338524 ps
T606 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3991905941 Jul 12 05:37:15 PM PDT 24 Jul 12 05:37:27 PM PDT 24 364644044 ps
T607 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1444337387 Jul 12 05:37:30 PM PDT 24 Jul 12 05:37:37 PM PDT 24 306971631 ps
T608 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1713556881 Jul 12 05:37:30 PM PDT 24 Jul 12 05:37:36 PM PDT 24 213219847 ps
T609 /workspace/coverage/cover_reg_top/14.hmac_intr_test.397914236 Jul 12 05:37:30 PM PDT 24 Jul 12 05:37:35 PM PDT 24 20067572 ps
T610 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3508592916 Jul 12 05:37:23 PM PDT 24 Jul 12 05:37:31 PM PDT 24 55845302 ps
T611 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.161108587 Jul 12 05:37:29 PM PDT 24 Jul 12 05:37:35 PM PDT 24 214709045 ps
T612 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1987064041 Jul 12 05:37:38 PM PDT 24 Jul 12 05:37:41 PM PDT 24 14335259 ps
T110 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1591039770 Jul 12 05:37:18 PM PDT 24 Jul 12 05:37:25 PM PDT 24 57774578 ps
T111 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2487900946 Jul 12 05:37:54 PM PDT 24 Jul 12 05:38:17 PM PDT 24 24068443 ps
T613 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2152669266 Jul 12 05:37:39 PM PDT 24 Jul 12 05:37:46 PM PDT 24 1009015686 ps
T614 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1732128994 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:31 PM PDT 24 79392412 ps
T615 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1364912042 Jul 12 05:37:36 PM PDT 24 Jul 12 05:37:40 PM PDT 24 55957247 ps
T616 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2610384383 Jul 12 05:37:24 PM PDT 24 Jul 12 05:37:35 PM PDT 24 63462470 ps
T617 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2304406105 Jul 12 05:37:53 PM PDT 24 Jul 12 05:38:15 PM PDT 24 46341290 ps
T618 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.538427716 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 107161061 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1323803549 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 39575283 ps
T620 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1052061088 Jul 12 05:37:12 PM PDT 24 Jul 12 05:37:20 PM PDT 24 457296521 ps
T621 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4004630986 Jul 12 05:37:26 PM PDT 24 Jul 12 05:37:35 PM PDT 24 46010833 ps
T622 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1213417490 Jul 12 05:37:33 PM PDT 24 Jul 12 05:37:38 PM PDT 24 50979762 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1572795414 Jul 12 05:38:43 PM PDT 24 Jul 12 05:38:52 PM PDT 24 267804506 ps
T624 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3316175057 Jul 12 05:37:19 PM PDT 24 Jul 12 05:37:28 PM PDT 24 87467591 ps
T625 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1193749173 Jul 12 05:37:54 PM PDT 24 Jul 12 05:38:15 PM PDT 24 37024696 ps
T626 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3523908882 Jul 12 05:37:27 PM PDT 24 Jul 12 05:37:34 PM PDT 24 20303776 ps
T627 /workspace/coverage/cover_reg_top/15.hmac_intr_test.4074297132 Jul 12 05:37:35 PM PDT 24 Jul 12 05:37:38 PM PDT 24 16349075 ps
T628 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2245398325 Jul 12 05:37:31 PM PDT 24 Jul 12 05:37:35 PM PDT 24 15915006 ps
T629 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2237151589 Jul 12 05:37:27 PM PDT 24 Jul 12 05:37:36 PM PDT 24 409744521 ps
T630 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1825928863 Jul 12 05:37:34 PM PDT 24 Jul 12 05:37:39 PM PDT 24 95807908 ps
T631 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2537395456 Jul 12 05:37:48 PM PDT 24 Jul 12 05:38:02 PM PDT 24 20644654 ps
T113 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3644799019 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:44 PM PDT 24 1455294556 ps
T632 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1984231171 Jul 12 05:37:19 PM PDT 24 Jul 12 05:37:27 PM PDT 24 55078491 ps
T114 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.959232503 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:29 PM PDT 24 142368198 ps
T633 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1017533821 Jul 12 05:38:04 PM PDT 24 Jul 12 05:38:26 PM PDT 24 29102609 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1527475651 Jul 12 05:37:16 PM PDT 24 Jul 12 05:37:23 PM PDT 24 30726797 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1094617594 Jul 12 05:37:17 PM PDT 24 Jul 12 05:37:35 PM PDT 24 2821947358 ps
T636 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.176093150 Jul 12 05:37:28 PM PDT 24 Jul 12 05:37:35 PM PDT 24 127984174 ps
T637 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3192096716 Jul 12 05:37:53 PM PDT 24 Jul 12 05:38:15 PM PDT 24 15543598 ps
T638 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4015215002 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:31 PM PDT 24 73090997 ps
T639 /workspace/coverage/cover_reg_top/43.hmac_intr_test.839029171 Jul 12 05:37:49 PM PDT 24 Jul 12 05:38:06 PM PDT 24 27000248 ps
T640 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1731066819 Jul 12 05:37:53 PM PDT 24 Jul 12 05:38:15 PM PDT 24 23315310 ps
T641 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1857005008 Jul 12 05:37:37 PM PDT 24 Jul 12 05:37:41 PM PDT 24 15422472 ps
T642 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.671245780 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:30 PM PDT 24 163097567 ps
T643 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2455297174 Jul 12 05:37:36 PM PDT 24 Jul 12 05:37:40 PM PDT 24 255789711 ps
T644 /workspace/coverage/cover_reg_top/48.hmac_intr_test.370376973 Jul 12 05:37:41 PM PDT 24 Jul 12 05:37:43 PM PDT 24 12286990 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3910766785 Jul 12 05:37:34 PM PDT 24 Jul 12 05:37:38 PM PDT 24 29871312 ps
T646 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3744203493 Jul 12 05:37:31 PM PDT 24 Jul 12 05:37:37 PM PDT 24 71112948 ps
T647 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.28727293 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:32 PM PDT 24 728533236 ps
T648 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2620190828 Jul 12 05:37:43 PM PDT 24 Jul 12 05:37:46 PM PDT 24 11920129 ps
T649 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4202260901 Jul 12 05:37:21 PM PDT 24 Jul 12 05:37:31 PM PDT 24 260520512 ps
T650 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4017366175 Jul 12 05:37:21 PM PDT 24 Jul 12 05:40:52 PM PDT 24 26229133819 ps
T651 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2585030936 Jul 12 05:37:23 PM PDT 24 Jul 12 05:37:32 PM PDT 24 472558117 ps
T652 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2693933541 Jul 12 05:37:38 PM PDT 24 Jul 12 05:37:43 PM PDT 24 164666813 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1447330873 Jul 12 05:37:22 PM PDT 24 Jul 12 05:37:34 PM PDT 24 46063482 ps
T654 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1122583752 Jul 12 05:38:18 PM PDT 24 Jul 12 05:38:35 PM PDT 24 196311914 ps
T655 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3133826092 Jul 12 05:37:20 PM PDT 24 Jul 12 05:37:31 PM PDT 24 227943672 ps
T656 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1503241230 Jul 12 05:37:55 PM PDT 24 Jul 12 05:38:19 PM PDT 24 209392507 ps
T657 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2050360535 Jul 12 05:37:48 PM PDT 24 Jul 12 05:38:04 PM PDT 24 145851420 ps
T658 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2526287152 Jul 12 05:37:19 PM PDT 24 Jul 12 05:37:28 PM PDT 24 485020228 ps

Test location /workspace/coverage/default/33.hmac_long_msg.621601962
Short name T5
Test name
Test status
Simulation time 49310254595 ps
CPU time 157.92 seconds
Started Jul 12 05:38:23 PM PDT 24
Finished Jul 12 05:41:15 PM PDT 24
Peak memory 200376 kb
Host smart-61290ae3-6709-4041-a9e7-bd6b4a2b78db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621601962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.621601962
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2050680452
Short name T8
Test name
Test status
Simulation time 95652250714 ps
CPU time 2966.33 seconds
Started Jul 12 05:38:33 PM PDT 24
Finished Jul 12 06:28:09 PM PDT 24
Peak memory 814424 kb
Host smart-0972f1fa-0120-4ec8-a8d8-44d4ad471018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050680452 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2050680452
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3561466686
Short name T21
Test name
Test status
Simulation time 114298995690 ps
CPU time 4216.08 seconds
Started Jul 12 05:37:44 PM PDT 24
Finished Jul 12 06:48:07 PM PDT 24
Peak memory 779888 kb
Host smart-a3a97b6f-c130-434e-898f-258b346b063e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561466686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3561466686
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1037901276
Short name T18
Test name
Test status
Simulation time 9343704672 ps
CPU time 506.96 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:47:10 PM PDT 24
Peak memory 369348 kb
Host smart-bbae3bcd-813f-4d76-8238-959de482fef7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037901276 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1037901276
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.907731874
Short name T134
Test name
Test status
Simulation time 187351691 ps
CPU time 3.13 seconds
Started Jul 12 05:37:26 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 200240 kb
Host smart-72386802-a617-4cf3-8c5f-ae0002b016b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907731874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.907731874
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.172545493
Short name T11
Test name
Test status
Simulation time 255957996648 ps
CPU time 4830 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 06:59:01 PM PDT 24
Peak memory 853592 kb
Host smart-80e948f9-7dc9-4b36-96df-d59ac21e981e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172545493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.172545493
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.451964352
Short name T14
Test name
Test status
Simulation time 240274409 ps
CPU time 0.94 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:38:17 PM PDT 24
Peak memory 218300 kb
Host smart-5e88d1a0-723a-4276-a106-9e0c0c95de2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451964352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.451964352
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/34.hmac_stress_all.4180628253
Short name T36
Test name
Test status
Simulation time 261322852811 ps
CPU time 1836.87 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 06:09:19 PM PDT 24
Peak memory 659348 kb
Host smart-56b1a7a7-dcd1-4fac-822d-478c36d6884a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180628253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.4180628253
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3552957879
Short name T12
Test name
Test status
Simulation time 667664764 ps
CPU time 38.89 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:39:12 PM PDT 24
Peak memory 200264 kb
Host smart-32a550c8-f79e-43fa-a0ce-ff2ed9e97cf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552957879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3552957879
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1583963340
Short name T20
Test name
Test status
Simulation time 77302384979 ps
CPU time 1877.08 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 06:09:58 PM PDT 24
Peak memory 714484 kb
Host smart-f9af31f8-db3e-4743-9156-97825fff2a05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583963340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1583963340
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.96434860
Short name T206
Test name
Test status
Simulation time 1374167997 ps
CPU time 77.91 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:39:49 PM PDT 24
Peak memory 200032 kb
Host smart-93cda2be-bbf8-41d5-9ce7-c10341eaf53f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96434860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.96434860
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3923632835
Short name T33
Test name
Test status
Simulation time 97469254148 ps
CPU time 509.5 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:47:20 PM PDT 24
Peak memory 200340 kb
Host smart-acc96611-6e90-4844-958f-d0f3ea26403b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923632835 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3923632835
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_alert_test.279955645
Short name T160
Test name
Test status
Simulation time 13432540 ps
CPU time 0.59 seconds
Started Jul 12 05:38:24 PM PDT 24
Finished Jul 12 05:38:38 PM PDT 24
Peak memory 196200 kb
Host smart-b1a8ca4e-b75f-40d2-8fd2-908538884e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279955645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.279955645
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.659606997
Short name T101
Test name
Test status
Simulation time 29070912 ps
CPU time 0.85 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 199500 kb
Host smart-24afdc86-7682-4b6b-864e-67e069f9f1ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659606997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.659606997
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.5103708
Short name T49
Test name
Test status
Simulation time 1578549287 ps
CPU time 4.69 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200168 kb
Host smart-2a42ce7b-55f6-4bf4-9277-33da47efa1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5103708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.5103708
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3869065574
Short name T133
Test name
Test status
Simulation time 172420078 ps
CPU time 1.85 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 200272 kb
Host smart-d032eaab-ba88-4019-97fb-a5fdcad346e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869065574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3869065574
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1100850311
Short name T81
Test name
Test status
Simulation time 144928861723 ps
CPU time 2564.89 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 06:21:00 PM PDT 24
Peak memory 216332 kb
Host smart-76abe2c1-101a-442e-8057-c808b131c2e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1100850311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1100850311
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1279562532
Short name T13
Test name
Test status
Simulation time 102984990371 ps
CPU time 823.61 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 05:51:56 PM PDT 24
Peak memory 591152 kb
Host smart-926e9de6-cf76-40ce-b9ab-05c673a9b593
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279562532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1279562532
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.76592617
Short name T603
Test name
Test status
Simulation time 732421295 ps
CPU time 3.12 seconds
Started Jul 12 05:37:26 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 200064 kb
Host smart-c65727e2-76b3-4dde-a25e-235f6e2b8044
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76592617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.76592617
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1133652089
Short name T601
Test name
Test status
Simulation time 1084441676 ps
CPU time 15.8 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:49 PM PDT 24
Peak memory 200252 kb
Host smart-88c4623c-7eb3-4f27-ace8-e4f6b5ab4572
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133652089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1133652089
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1237743139
Short name T100
Test name
Test status
Simulation time 31983537 ps
CPU time 0.91 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 199696 kb
Host smart-6ef318f4-299a-4ddf-8ccd-95f077372e8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237743139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1237743139
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.293651186
Short name T572
Test name
Test status
Simulation time 97346050 ps
CPU time 2.37 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 200364 kb
Host smart-01e8e1cd-f8d7-4fd4-a053-ec6d248b3fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293651186 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.293651186
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1591039770
Short name T110
Test name
Test status
Simulation time 57774578 ps
CPU time 0.95 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:25 PM PDT 24
Peak memory 199764 kb
Host smart-6c53cb1d-0f67-45c3-8086-f8bced871f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591039770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1591039770
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3043969427
Short name T563
Test name
Test status
Simulation time 20525755 ps
CPU time 0.55 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 195184 kb
Host smart-1c39e096-c07f-4565-9f64-87b33eb71bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043969427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3043969427
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.671245780
Short name T642
Test name
Test status
Simulation time 163097567 ps
CPU time 2.42 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 200172 kb
Host smart-b84362e6-c3b1-47a1-ac7d-e6bd0e2fc71e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671245780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.671245780
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1153309104
Short name T576
Test name
Test status
Simulation time 854603210 ps
CPU time 3.74 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 200260 kb
Host smart-9e63dbf7-eb62-43b6-8d27-bacf64baa07c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153309104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1153309104
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3301874140
Short name T565
Test name
Test status
Simulation time 98629187 ps
CPU time 2.72 seconds
Started Jul 12 05:37:29 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 200328 kb
Host smart-dd5fa595-0860-4d05-acd5-442aa2c20c72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301874140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3301874140
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3991905941
Short name T606
Test name
Test status
Simulation time 364644044 ps
CPU time 5.59 seconds
Started Jul 12 05:37:15 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 200164 kb
Host smart-8de64ec8-1984-4229-9d4d-80a39c50c386
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991905941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3991905941
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.977144546
Short name T103
Test name
Test status
Simulation time 1228914138 ps
CPU time 13.63 seconds
Started Jul 12 05:37:25 PM PDT 24
Finished Jul 12 05:37:45 PM PDT 24
Peak memory 200268 kb
Host smart-188b492a-5193-4d80-b71f-d28b0d387d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977144546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.977144546
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2206599712
Short name T598
Test name
Test status
Simulation time 16697605 ps
CPU time 0.73 seconds
Started Jul 12 05:37:15 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 197864 kb
Host smart-985d96fd-bc7b-4e2c-9a38-cca2a4db12cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206599712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2206599712
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4202260901
Short name T649
Test name
Test status
Simulation time 260520512 ps
CPU time 1.73 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200352 kb
Host smart-23feb1e3-ab34-4cec-8f27-f7a107554448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202260901 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4202260901
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.339209237
Short name T112
Test name
Test status
Simulation time 21239447 ps
CPU time 0.8 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 199448 kb
Host smart-52f1cfce-a13d-4040-bb01-41752aa0f04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339209237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.339209237
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1825442797
Short name T594
Test name
Test status
Simulation time 22647104 ps
CPU time 0.59 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:21 PM PDT 24
Peak memory 195200 kb
Host smart-61ec94c7-8e2b-493e-a4d5-b2cb3bfa1b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825442797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1825442797
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3007469356
Short name T121
Test name
Test status
Simulation time 34148780 ps
CPU time 1.62 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 200216 kb
Host smart-7e8f1191-0d21-43d2-9e1e-f072cb2380b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007469356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3007469356
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.270760198
Short name T537
Test name
Test status
Simulation time 47001340 ps
CPU time 2.43 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 200240 kb
Host smart-53aef5fe-3e87-4c8d-b0fb-43f84e8ef7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270760198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.270760198
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1715557326
Short name T600
Test name
Test status
Simulation time 253239518 ps
CPU time 1.85 seconds
Started Jul 12 05:37:33 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 200532 kb
Host smart-45c10427-a5df-4700-9ff2-d090054442fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715557326 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1715557326
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.247768969
Short name T120
Test name
Test status
Simulation time 119124914 ps
CPU time 0.81 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 199404 kb
Host smart-c59720a0-349d-4985-848b-9ca4af96e157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247768969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.247768969
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3523908882
Short name T626
Test name
Test status
Simulation time 20303776 ps
CPU time 0.58 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 195104 kb
Host smart-a1629b66-7dab-4ee8-8e27-1ce2784c6887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523908882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3523908882
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2740473377
Short name T585
Test name
Test status
Simulation time 139168437 ps
CPU time 1.78 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200268 kb
Host smart-808f1028-c68f-4dcb-b567-3f45ac46260e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740473377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2740473377
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1205472600
Short name T561
Test name
Test status
Simulation time 301844750 ps
CPU time 3.34 seconds
Started Jul 12 05:37:35 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 200132 kb
Host smart-2a5dfbf7-778f-42e7-82fd-0fb3f3a44abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205472600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1205472600
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.906247078
Short name T533
Test name
Test status
Simulation time 39454523 ps
CPU time 2.51 seconds
Started Jul 12 05:37:30 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 200188 kb
Host smart-ccdbf84f-9aab-44eb-bd99-b42a2a8cc3cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906247078 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.906247078
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2537395456
Short name T631
Test name
Test status
Simulation time 20644654 ps
CPU time 0.69 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:02 PM PDT 24
Peak memory 198428 kb
Host smart-930ad844-ec1c-4c05-9897-84e2df9c8466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537395456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2537395456
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.341325371
Short name T534
Test name
Test status
Simulation time 13194427 ps
CPU time 0.63 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:15 PM PDT 24
Peak memory 195248 kb
Host smart-18e046e0-c9f6-4202-9326-e839323ff48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341325371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.341325371
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.834661713
Short name T605
Test name
Test status
Simulation time 427338524 ps
CPU time 1.22 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200176 kb
Host smart-b6a76e25-18c9-416d-8eec-83252fd2f9cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834661713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.834661713
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3740104409
Short name T559
Test name
Test status
Simulation time 190511928 ps
CPU time 1.96 seconds
Started Jul 12 05:37:31 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 200236 kb
Host smart-3b03a44c-1cb8-42c1-845f-19071ce73f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740104409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3740104409
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1825928863
Short name T630
Test name
Test status
Simulation time 95807908 ps
CPU time 1.76 seconds
Started Jul 12 05:37:34 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 200232 kb
Host smart-b5498726-1d6e-4afe-9543-9f511dbce2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825928863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1825928863
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1758578458
Short name T564
Test name
Test status
Simulation time 105447162 ps
CPU time 2.47 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200260 kb
Host smart-7d624645-b91c-4f82-acf3-e9b306803cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758578458 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1758578458
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.959232503
Short name T114
Test name
Test status
Simulation time 142368198 ps
CPU time 1.11 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 199848 kb
Host smart-fc0af876-e463-4131-9f52-deb06febb844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959232503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.959232503
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3508592916
Short name T610
Test name
Test status
Simulation time 55845302 ps
CPU time 0.65 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 195220 kb
Host smart-0174ebb1-f44a-4260-8abb-058f993bf25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508592916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3508592916
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1732128994
Short name T614
Test name
Test status
Simulation time 79392412 ps
CPU time 1.64 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200228 kb
Host smart-86427f7e-7d8f-4bee-9fb9-2a94da2dc577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732128994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1732128994
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.387811279
Short name T586
Test name
Test status
Simulation time 48572924 ps
CPU time 1.44 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 200256 kb
Host smart-7870c890-e1ab-4341-8cb6-e53241d4b3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387811279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.387811279
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.188080472
Short name T50
Test name
Test status
Simulation time 448361481 ps
CPU time 4.09 seconds
Started Jul 12 05:37:45 PM PDT 24
Finished Jul 12 05:37:57 PM PDT 24
Peak memory 200260 kb
Host smart-ba3a193d-f9aa-4f72-80dc-f2f9fb6ac200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188080472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.188080472
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3062465965
Short name T532
Test name
Test status
Simulation time 839989185 ps
CPU time 3.83 seconds
Started Jul 12 05:37:28 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 208528 kb
Host smart-7c85e2ff-bc31-4c14-b06a-f0591d759a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062465965 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3062465965
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1405331832
Short name T122
Test name
Test status
Simulation time 51506864 ps
CPU time 0.91 seconds
Started Jul 12 05:37:58 PM PDT 24
Finished Jul 12 05:38:21 PM PDT 24
Peak memory 200048 kb
Host smart-47f8a51b-2aac-4d5e-a5ec-406c4aca13f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405331832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1405331832
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2245398325
Short name T628
Test name
Test status
Simulation time 15915006 ps
CPU time 0.62 seconds
Started Jul 12 05:37:31 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 195152 kb
Host smart-368a7ace-be4e-4c0b-9c72-35be43f70c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245398325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2245398325
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3225920212
Short name T123
Test name
Test status
Simulation time 89605883 ps
CPU time 1.18 seconds
Started Jul 12 05:37:43 PM PDT 24
Finished Jul 12 05:37:48 PM PDT 24
Peak memory 200124 kb
Host smart-4cd5d2d5-d114-40ee-8cfe-df6e6e1ced77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225920212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3225920212
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.176093150
Short name T636
Test name
Test status
Simulation time 127984174 ps
CPU time 1.65 seconds
Started Jul 12 05:37:28 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200272 kb
Host smart-3adb93b3-45d9-4ad0-8256-9e8c322cbf23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176093150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.176093150
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1444337387
Short name T607
Test name
Test status
Simulation time 306971631 ps
CPU time 3.04 seconds
Started Jul 12 05:37:30 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 200180 kb
Host smart-638f4c18-f671-4aec-8a63-19b3fa1c8a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444337387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1444337387
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4017366175
Short name T650
Test name
Test status
Simulation time 26229133819 ps
CPU time 202.55 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:40:52 PM PDT 24
Peak memory 215860 kb
Host smart-b8cc8aea-00b9-4765-b465-0d7fd3deaed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017366175 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4017366175
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2155193253
Short name T108
Test name
Test status
Simulation time 47197921 ps
CPU time 0.81 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:13 PM PDT 24
Peak memory 199496 kb
Host smart-489e5fca-a252-4590-a136-4850c8ecf73d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155193253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2155193253
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.397914236
Short name T609
Test name
Test status
Simulation time 20067572 ps
CPU time 0.56 seconds
Started Jul 12 05:37:30 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 195124 kb
Host smart-700a117a-52f2-4cf5-a439-9e44aa06ca2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397914236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.397914236
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2468519277
Short name T592
Test name
Test status
Simulation time 46606900 ps
CPU time 1.18 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 200068 kb
Host smart-c22093b0-a9b7-4ffb-a0ac-a8b170118539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468519277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2468519277
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3818124181
Short name T556
Test name
Test status
Simulation time 825277473 ps
CPU time 4.24 seconds
Started Jul 12 05:37:49 PM PDT 24
Finished Jul 12 05:38:09 PM PDT 24
Peak memory 200312 kb
Host smart-d6a5b490-d42b-4df9-beea-124421854225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818124181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3818124181
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2878842575
Short name T136
Test name
Test status
Simulation time 539985430 ps
CPU time 4.54 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 200168 kb
Host smart-5901e69a-82fe-43e0-ae98-95a01a86fae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878842575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2878842575
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3941918308
Short name T580
Test name
Test status
Simulation time 11285779273 ps
CPU time 113.31 seconds
Started Jul 12 05:37:43 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 216640 kb
Host smart-64540280-5038-487a-9b1e-c804bed7d2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941918308 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3941918308
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.742834782
Short name T566
Test name
Test status
Simulation time 115373539 ps
CPU time 0.97 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200032 kb
Host smart-cb6b3615-9657-441b-977e-f000407e490c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742834782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.742834782
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4074297132
Short name T627
Test name
Test status
Simulation time 16349075 ps
CPU time 0.62 seconds
Started Jul 12 05:37:35 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 195304 kb
Host smart-1bfad129-e9d1-4a66-9d70-d14209557345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074297132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4074297132
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.802501712
Short name T119
Test name
Test status
Simulation time 171337348 ps
CPU time 1.15 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200224 kb
Host smart-059cfa22-e117-41dd-a462-4589345668f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802501712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.802501712
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.161108587
Short name T611
Test name
Test status
Simulation time 214709045 ps
CPU time 1.45 seconds
Started Jul 12 05:37:29 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200248 kb
Host smart-75401993-c0e9-4632-a770-bfe2a9912710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161108587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.161108587
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3893615426
Short name T595
Test name
Test status
Simulation time 195371457 ps
CPU time 1.81 seconds
Started Jul 12 05:37:31 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 200272 kb
Host smart-82a22139-4991-4fd9-8f30-18ab4df4fc33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893615426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3893615426
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2050360535
Short name T657
Test name
Test status
Simulation time 145851420 ps
CPU time 1.28 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:04 PM PDT 24
Peak memory 200220 kb
Host smart-fa86822b-c1c0-41a7-9150-739d2f0a65e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050360535 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2050360535
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2132513441
Short name T591
Test name
Test status
Simulation time 17037482 ps
CPU time 0.72 seconds
Started Jul 12 05:37:38 PM PDT 24
Finished Jul 12 05:37:42 PM PDT 24
Peak memory 197976 kb
Host smart-6ca34e40-9bb7-4ee0-a6c1-ca2a24bfaf29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132513441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2132513441
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1183849405
Short name T568
Test name
Test status
Simulation time 22296490 ps
CPU time 0.6 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 195252 kb
Host smart-920ee929-2696-4df1-a24c-433e338990a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183849405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1183849405
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2455297174
Short name T643
Test name
Test status
Simulation time 255789711 ps
CPU time 1.67 seconds
Started Jul 12 05:37:36 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 200464 kb
Host smart-49b28117-a555-4c3a-aea6-44d5cf2860f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455297174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2455297174
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.196034754
Short name T540
Test name
Test status
Simulation time 1127217853 ps
CPU time 1.98 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:37:42 PM PDT 24
Peak memory 200476 kb
Host smart-b4b64545-ab02-4bac-8d3b-f4fff9e4b055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196034754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.196034754
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4015215002
Short name T638
Test name
Test status
Simulation time 73090997 ps
CPU time 1.75 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200228 kb
Host smart-b2f99d1f-f46d-4a80-99f0-2ed895a04a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015215002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4015215002
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2237151589
Short name T629
Test name
Test status
Simulation time 409744521 ps
CPU time 2.21 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 200388 kb
Host smart-7b1ce5aa-1060-420b-af57-521e2d9a3a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237151589 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2237151589
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3910766785
Short name T645
Test name
Test status
Simulation time 29871312 ps
CPU time 0.77 seconds
Started Jul 12 05:37:34 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 199256 kb
Host smart-4341dada-9db7-4ee1-aed6-7ea042baf36f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910766785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3910766785
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4162350261
Short name T579
Test name
Test status
Simulation time 44698446 ps
CPU time 0.63 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 195216 kb
Host smart-f7f35ce1-109c-4206-972f-51871e93d198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162350261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4162350261
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1981605093
Short name T118
Test name
Test status
Simulation time 331209540 ps
CPU time 1.69 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 200176 kb
Host smart-6baf6131-a523-4c5e-9c45-1db10737a43d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981605093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1981605093
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2651265283
Short name T544
Test name
Test status
Simulation time 166695835 ps
CPU time 2.77 seconds
Started Jul 12 05:37:33 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 200236 kb
Host smart-e108e4f9-bb73-435f-ba3f-ba4d5cd6db3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651265283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2651265283
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2611649276
Short name T138
Test name
Test status
Simulation time 775759043 ps
CPU time 3.2 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200320 kb
Host smart-b6671074-e09f-4452-ac47-6123e9bd92e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611649276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2611649276
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2638919892
Short name T581
Test name
Test status
Simulation time 2213409713 ps
CPU time 32.71 seconds
Started Jul 12 05:37:34 PM PDT 24
Finished Jul 12 05:38:10 PM PDT 24
Peak memory 216152 kb
Host smart-549cda4d-4f65-4aed-88ad-e7419f4afc64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638919892 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2638919892
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1248890372
Short name T115
Test name
Test status
Simulation time 17130654 ps
CPU time 0.82 seconds
Started Jul 12 05:37:36 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 200112 kb
Host smart-f3dc1f4a-4402-446b-a036-434bba269707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248890372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1248890372
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1857005008
Short name T641
Test name
Test status
Simulation time 15422472 ps
CPU time 0.6 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195272 kb
Host smart-5e44f88f-05b8-4877-8049-024156624457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857005008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1857005008
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1213417490
Short name T622
Test name
Test status
Simulation time 50979762 ps
CPU time 2.22 seconds
Started Jul 12 05:37:33 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 200136 kb
Host smart-afc30524-8eee-4d7d-b675-f6cd6586df71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213417490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1213417490
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3834592227
Short name T562
Test name
Test status
Simulation time 1220555879 ps
CPU time 2.73 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:04 PM PDT 24
Peak memory 200232 kb
Host smart-341558eb-603e-4c2a-bf4f-cd4383682f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834592227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3834592227
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1783767602
Short name T132
Test name
Test status
Simulation time 305177959 ps
CPU time 1.8 seconds
Started Jul 12 05:37:34 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 200236 kb
Host smart-fe4b348b-05e5-43f9-a5a5-7411bedfeea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783767602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1783767602
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1503241230
Short name T656
Test name
Test status
Simulation time 209392507 ps
CPU time 2.3 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:38:19 PM PDT 24
Peak memory 200288 kb
Host smart-0c082d20-e3e7-46ad-9be3-1d75af7dcfda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503241230 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1503241230
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2487900946
Short name T111
Test name
Test status
Simulation time 24068443 ps
CPU time 0.87 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:38:17 PM PDT 24
Peak memory 199636 kb
Host smart-e1c695c6-e415-4c4b-8ad3-c5d3747e81e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487900946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2487900946
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.132298284
Short name T538
Test name
Test status
Simulation time 30816537 ps
CPU time 0.6 seconds
Started Jul 12 05:37:36 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 195124 kb
Host smart-61e7c3d3-1e0c-4b91-a0b1-ef02684b9935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132298284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.132298284
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1731066819
Short name T640
Test name
Test status
Simulation time 23315310 ps
CPU time 1.08 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:15 PM PDT 24
Peak memory 200148 kb
Host smart-efc00652-c7e1-4ef4-aea1-7359e8630594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731066819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1731066819
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.505815362
Short name T536
Test name
Test status
Simulation time 160832636 ps
CPU time 3.45 seconds
Started Jul 12 05:37:32 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 200256 kb
Host smart-055495ce-2815-44db-b2e8-8a7e977b7f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505815362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.505815362
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1996956774
Short name T51
Test name
Test status
Simulation time 462754875 ps
CPU time 3.08 seconds
Started Jul 12 05:37:41 PM PDT 24
Finished Jul 12 05:37:46 PM PDT 24
Peak memory 200260 kb
Host smart-a34171d1-0c73-48ab-8eaa-57e52520b99d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996956774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1996956774
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2113832239
Short name T105
Test name
Test status
Simulation time 569783974 ps
CPU time 3.34 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 200156 kb
Host smart-e07eab5e-b528-40bb-a8c7-e84dd70f4bf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113832239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2113832239
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1094617594
Short name T635
Test name
Test status
Simulation time 2821947358 ps
CPU time 11.05 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200352 kb
Host smart-d7a081bf-6f2e-418b-9f88-71216da00a83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094617594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1094617594
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2062996267
Short name T567
Test name
Test status
Simulation time 74916828 ps
CPU time 1.02 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 200116 kb
Host smart-208e73e1-b924-4c69-8a65-e52c0ce22768
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062996267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2062996267
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3316175057
Short name T624
Test name
Test status
Simulation time 87467591 ps
CPU time 2.32 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 200380 kb
Host smart-b27f1582-5e3a-4744-bab7-6f300cb18897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316175057 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3316175057
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1527475651
Short name T634
Test name
Test status
Simulation time 30726797 ps
CPU time 0.96 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 200024 kb
Host smart-aff09285-6858-406d-9758-11aa9cdfdef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527475651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1527475651
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3408642746
Short name T602
Test name
Test status
Simulation time 94979530 ps
CPU time 0.56 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 195144 kb
Host smart-f96d6060-0275-47c5-9f6e-ec8bcd09cdfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408642746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3408642746
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1052061088
Short name T620
Test name
Test status
Simulation time 457296521 ps
CPU time 1.67 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:20 PM PDT 24
Peak memory 200256 kb
Host smart-a8267407-3336-468e-b230-8fbd34c2b286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052061088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1052061088
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1461532405
Short name T550
Test name
Test status
Simulation time 506173285 ps
CPU time 4.29 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 200280 kb
Host smart-07a2b050-beaa-426a-b272-ae6860b1bc46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461532405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1461532405
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.105675274
Short name T137
Test name
Test status
Simulation time 80620671 ps
CPU time 1.96 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200204 kb
Host smart-3fa32b56-5013-4d11-ab58-16b43a1f09ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105675274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.105675274
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2509846585
Short name T554
Test name
Test status
Simulation time 15320436 ps
CPU time 0.65 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:38:27 PM PDT 24
Peak memory 195184 kb
Host smart-b6f9dfde-8a4e-4a8c-b9cb-b9177f9d0b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509846585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2509846585
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3525109548
Short name T552
Test name
Test status
Simulation time 15665142 ps
CPU time 0.58 seconds
Started Jul 12 05:37:51 PM PDT 24
Finished Jul 12 05:38:09 PM PDT 24
Peak memory 195256 kb
Host smart-2ccd75d8-8469-457c-b5f7-c7d1458512ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525109548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3525109548
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3883331231
Short name T543
Test name
Test status
Simulation time 31076612 ps
CPU time 0.61 seconds
Started Jul 12 05:37:35 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 195160 kb
Host smart-7edd9922-4748-4e0c-8d03-c90ded98ca91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883331231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3883331231
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3550125603
Short name T555
Test name
Test status
Simulation time 110591729 ps
CPU time 0.58 seconds
Started Jul 12 05:37:45 PM PDT 24
Finished Jul 12 05:37:53 PM PDT 24
Peak memory 195240 kb
Host smart-0142fa09-d013-4c3c-ba39-04ca68ff429d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550125603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3550125603
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1034491825
Short name T587
Test name
Test status
Simulation time 47892859 ps
CPU time 0.58 seconds
Started Jul 12 05:37:51 PM PDT 24
Finished Jul 12 05:38:09 PM PDT 24
Peak memory 195232 kb
Host smart-3a33bf50-347e-4613-a259-18288a67ccfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034491825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1034491825
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3256581126
Short name T549
Test name
Test status
Simulation time 41177380 ps
CPU time 0.55 seconds
Started Jul 12 05:37:43 PM PDT 24
Finished Jul 12 05:37:46 PM PDT 24
Peak memory 195040 kb
Host smart-8e56f48e-4dc0-4b63-a5e9-e35590229bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256581126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3256581126
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.463670705
Short name T584
Test name
Test status
Simulation time 33940196 ps
CPU time 0.62 seconds
Started Jul 12 05:37:49 PM PDT 24
Finished Jul 12 05:38:05 PM PDT 24
Peak memory 195228 kb
Host smart-a7e94a05-c0a6-4db9-b896-2649027836ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463670705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.463670705
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2673556718
Short name T597
Test name
Test status
Simulation time 19392382 ps
CPU time 0.61 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195168 kb
Host smart-add19fb3-8cbe-470f-8b9a-8166c345de3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673556718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2673556718
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1017533821
Short name T633
Test name
Test status
Simulation time 29102609 ps
CPU time 0.59 seconds
Started Jul 12 05:38:04 PM PDT 24
Finished Jul 12 05:38:26 PM PDT 24
Peak memory 195168 kb
Host smart-bb9c4aff-0b68-48a6-b6da-5f1f041714fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017533821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1017533821
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.709346269
Short name T593
Test name
Test status
Simulation time 197335789 ps
CPU time 0.59 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195220 kb
Host smart-d169166f-7fdd-4ecb-80f5-940eaee56c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709346269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.709346269
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2022479695
Short name T546
Test name
Test status
Simulation time 105562414 ps
CPU time 2.92 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 200176 kb
Host smart-5d08dca8-c5d2-488d-809d-08074cb7872a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022479695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2022479695
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3644799019
Short name T113
Test name
Test status
Simulation time 1455294556 ps
CPU time 14.63 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:44 PM PDT 24
Peak memory 199440 kb
Host smart-1ca8b80f-ca76-4e4a-ac19-31eaf66e3943
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644799019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3644799019
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1323803549
Short name T619
Test name
Test status
Simulation time 39575283 ps
CPU time 0.73 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 198108 kb
Host smart-1d58fe9c-d549-4184-be70-fe316728ab10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323803549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1323803549
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1572795414
Short name T623
Test name
Test status
Simulation time 267804506 ps
CPU time 2.17 seconds
Started Jul 12 05:38:43 PM PDT 24
Finished Jul 12 05:38:52 PM PDT 24
Peak memory 200272 kb
Host smart-46e14707-e7d1-4909-b749-b0f0efc50fcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572795414 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1572795414
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1447330873
Short name T653
Test name
Test status
Simulation time 46063482 ps
CPU time 0.77 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 199268 kb
Host smart-eaf4bed5-e93f-499d-97c7-f834d35b7f31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447330873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1447330873
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.354398046
Short name T539
Test name
Test status
Simulation time 62334871 ps
CPU time 0.61 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 195172 kb
Host smart-754890a1-c58b-41d7-a740-98815d3b4c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354398046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.354398046
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.538427716
Short name T618
Test name
Test status
Simulation time 107161061 ps
CPU time 1.83 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200056 kb
Host smart-f4825fe1-3aac-40bd-a034-774fe23f2dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538427716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.538427716
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2526287152
Short name T658
Test name
Test status
Simulation time 485020228 ps
CPU time 2.54 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 200272 kb
Host smart-5d18d0f8-7f7d-4380-a711-0f087baf14cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526287152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2526287152
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2152669266
Short name T613
Test name
Test status
Simulation time 1009015686 ps
CPU time 3.81 seconds
Started Jul 12 05:37:39 PM PDT 24
Finished Jul 12 05:37:46 PM PDT 24
Peak memory 200324 kb
Host smart-af904621-0d97-477e-aff6-922a1f01c9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152669266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2152669266
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4003162111
Short name T560
Test name
Test status
Simulation time 21399370 ps
CPU time 0.6 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195152 kb
Host smart-2ffbdde1-cc87-437b-aad6-bb680a1166cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003162111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4003162111
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1008705693
Short name T541
Test name
Test status
Simulation time 27830948 ps
CPU time 0.59 seconds
Started Jul 12 05:37:38 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195228 kb
Host smart-ef07c1f5-edf4-49a0-bbf4-e96c12a8b683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008705693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1008705693
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3593293180
Short name T545
Test name
Test status
Simulation time 43183985 ps
CPU time 0.55 seconds
Started Jul 12 05:37:51 PM PDT 24
Finished Jul 12 05:38:11 PM PDT 24
Peak memory 195148 kb
Host smart-f8b5a330-7d22-4b88-a351-88dfddb9130f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593293180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3593293180
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3981624464
Short name T588
Test name
Test status
Simulation time 32998817 ps
CPU time 0.6 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:38:17 PM PDT 24
Peak memory 195232 kb
Host smart-47589eed-810b-48b1-9b92-fc599f2d574c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981624464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3981624464
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.304294426
Short name T535
Test name
Test status
Simulation time 13293788 ps
CPU time 0.61 seconds
Started Jul 12 05:37:35 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 195164 kb
Host smart-2ae82437-ab9e-4354-bce9-b9482b5a8cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304294426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.304294426
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2620190828
Short name T648
Test name
Test status
Simulation time 11920129 ps
CPU time 0.6 seconds
Started Jul 12 05:37:43 PM PDT 24
Finished Jul 12 05:37:46 PM PDT 24
Peak memory 195120 kb
Host smart-101ab9ee-7bd6-45c7-830c-436ccb88a2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620190828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2620190828
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.266094941
Short name T553
Test name
Test status
Simulation time 13624491 ps
CPU time 0.59 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:38:17 PM PDT 24
Peak memory 195168 kb
Host smart-471cab47-5353-40d3-886b-393fbdc38b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266094941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.266094941
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1364912042
Short name T615
Test name
Test status
Simulation time 55957247 ps
CPU time 0.58 seconds
Started Jul 12 05:37:36 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 195236 kb
Host smart-0ff76f47-99b9-4398-8190-65cc8e1339f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364912042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1364912042
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1193749173
Short name T625
Test name
Test status
Simulation time 37024696 ps
CPU time 0.58 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:38:15 PM PDT 24
Peak memory 195232 kb
Host smart-311c6de0-654c-4fa3-92f6-f62ae7635be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193749173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1193749173
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3263675490
Short name T558
Test name
Test status
Simulation time 12112750 ps
CPU time 0.58 seconds
Started Jul 12 05:38:04 PM PDT 24
Finished Jul 12 05:38:26 PM PDT 24
Peak memory 195148 kb
Host smart-e4dcc068-ba32-41c0-8226-fd36afe13f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263675490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3263675490
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2100310925
Short name T106
Test name
Test status
Simulation time 162774194 ps
CPU time 8.35 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 200260 kb
Host smart-f362047c-d9dc-4333-87c9-043754045632
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100310925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2100310925
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3624814162
Short name T104
Test name
Test status
Simulation time 120090881 ps
CPU time 4.61 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:38:55 PM PDT 24
Peak memory 200068 kb
Host smart-2b8f249c-0742-4c79-92ad-8d5bbb570b0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624814162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3624814162
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2985929434
Short name T578
Test name
Test status
Simulation time 20497483 ps
CPU time 0.74 seconds
Started Jul 12 05:37:32 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 198248 kb
Host smart-c19e013f-c492-4dd4-8556-1afbd9a37ed3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985929434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2985929434
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1713556881
Short name T608
Test name
Test status
Simulation time 213219847 ps
CPU time 1.33 seconds
Started Jul 12 05:37:30 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 200264 kb
Host smart-d3775a96-e9e4-42f7-99d3-9ca670a1c2a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713556881 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1713556881
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3885234930
Short name T107
Test name
Test status
Simulation time 16733988 ps
CPU time 0.84 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:38:52 PM PDT 24
Peak memory 199512 kb
Host smart-0f58020d-b87a-4416-baeb-acba4076c55f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885234930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3885234930
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2167540527
Short name T551
Test name
Test status
Simulation time 21277714 ps
CPU time 0.6 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 195096 kb
Host smart-f17159f4-ffef-4b97-ba89-221944f96246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167540527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2167540527
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2485016824
Short name T117
Test name
Test status
Simulation time 101250217 ps
CPU time 1.18 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 200096 kb
Host smart-0e30521a-c3be-42f0-81e5-c7b6b17ca8a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485016824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2485016824
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3074238209
Short name T548
Test name
Test status
Simulation time 58577652 ps
CPU time 1.25 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200224 kb
Host smart-10a1cbf5-f31b-4009-9804-7132f4341bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074238209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3074238209
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.269753667
Short name T583
Test name
Test status
Simulation time 21887654 ps
CPU time 0.61 seconds
Started Jul 12 05:37:41 PM PDT 24
Finished Jul 12 05:37:43 PM PDT 24
Peak memory 195212 kb
Host smart-7a413727-04a0-43fc-b1f5-e4d2172b3363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269753667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.269753667
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3192096716
Short name T637
Test name
Test status
Simulation time 15543598 ps
CPU time 0.62 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:15 PM PDT 24
Peak memory 195128 kb
Host smart-dd32c286-ff22-4d42-961b-983b8402a28d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192096716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3192096716
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4287406415
Short name T604
Test name
Test status
Simulation time 47407640 ps
CPU time 0.6 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:38:21 PM PDT 24
Peak memory 195132 kb
Host smart-74f9ea8d-0bcc-41b1-b689-b00b1c8d090b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287406415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4287406415
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.839029171
Short name T639
Test name
Test status
Simulation time 27000248 ps
CPU time 0.62 seconds
Started Jul 12 05:37:49 PM PDT 24
Finished Jul 12 05:38:06 PM PDT 24
Peak memory 195184 kb
Host smart-096868ed-7de8-41a8-b099-5196320d4035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839029171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.839029171
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1987064041
Short name T612
Test name
Test status
Simulation time 14335259 ps
CPU time 0.61 seconds
Started Jul 12 05:37:38 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195128 kb
Host smart-f519361d-fae7-4599-af79-2fa702a78b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987064041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1987064041
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.47445427
Short name T547
Test name
Test status
Simulation time 38161199 ps
CPU time 0.6 seconds
Started Jul 12 05:37:36 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 195152 kb
Host smart-94d0bbfe-57f6-4c27-99c1-cadebff7fdbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47445427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.47445427
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1056114774
Short name T574
Test name
Test status
Simulation time 34901167 ps
CPU time 0.62 seconds
Started Jul 12 05:37:35 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 195240 kb
Host smart-c4fb6acb-1763-4105-aef1-68a09f8132a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056114774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1056114774
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.718346461
Short name T577
Test name
Test status
Simulation time 24359912 ps
CPU time 0.62 seconds
Started Jul 12 05:37:30 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 195128 kb
Host smart-02f46f15-0039-4af5-b19f-ea6390150f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718346461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.718346461
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.370376973
Short name T644
Test name
Test status
Simulation time 12286990 ps
CPU time 0.58 seconds
Started Jul 12 05:37:41 PM PDT 24
Finished Jul 12 05:37:43 PM PDT 24
Peak memory 195228 kb
Host smart-b4384357-425c-46f3-ab51-ce247cf7cf11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370376973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.370376973
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2616691304
Short name T582
Test name
Test status
Simulation time 12923966 ps
CPU time 0.63 seconds
Started Jul 12 05:37:51 PM PDT 24
Finished Jul 12 05:38:11 PM PDT 24
Peak memory 195164 kb
Host smart-37da6a15-2ba0-422e-b123-402932d19f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616691304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2616691304
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3744203493
Short name T646
Test name
Test status
Simulation time 71112948 ps
CPU time 2.19 seconds
Started Jul 12 05:37:31 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 208488 kb
Host smart-2dab94ea-9b93-46f2-b452-5ae44b5b5591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744203493 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3744203493
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3790450927
Short name T102
Test name
Test status
Simulation time 29223714 ps
CPU time 0.93 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 199724 kb
Host smart-54162488-c3af-4f4f-8941-46fb6d522d85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790450927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3790450927
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2904566866
Short name T590
Test name
Test status
Simulation time 13334955 ps
CPU time 0.59 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 195096 kb
Host smart-afec3337-0355-4961-b22d-4eb06acab8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904566866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2904566866
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1984231171
Short name T632
Test name
Test status
Simulation time 55078491 ps
CPU time 1.14 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 200224 kb
Host smart-cd231b24-a0ed-42f1-975c-77651f57dd31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984231171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1984231171
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2761965224
Short name T589
Test name
Test status
Simulation time 167267512 ps
CPU time 2.39 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200280 kb
Host smart-3dc44725-7d98-4be1-a2ad-d226091ff0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761965224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2761965224
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.962927274
Short name T131
Test name
Test status
Simulation time 148150626 ps
CPU time 3.8 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 200112 kb
Host smart-a36891d6-7e69-47c6-a50f-0c16033d5ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962927274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.962927274
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1747758593
Short name T557
Test name
Test status
Simulation time 19240694 ps
CPU time 1.02 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 200084 kb
Host smart-9b1b7c1a-1eea-494b-a759-f52ef988b8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747758593 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1747758593
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2178925955
Short name T573
Test name
Test status
Simulation time 68935481 ps
CPU time 0.7 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:25 PM PDT 24
Peak memory 198476 kb
Host smart-b75c5f85-6e8a-4976-8ad4-51a765cd918a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178925955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2178925955
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3883186877
Short name T570
Test name
Test status
Simulation time 22158354 ps
CPU time 0.54 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 194908 kb
Host smart-14ed2006-6c1b-44ed-9b55-c17d5650265e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883186877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3883186877
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2610384383
Short name T616
Test name
Test status
Simulation time 63462470 ps
CPU time 1.27 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200304 kb
Host smart-4a67e7ef-4aec-4f35-8506-87beeab0d8cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610384383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2610384383
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2023049607
Short name T542
Test name
Test status
Simulation time 819527001 ps
CPU time 3.92 seconds
Started Jul 12 05:38:29 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200132 kb
Host smart-170d8e7a-987f-4fe7-87a7-0fd94f6292e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023049607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2023049607
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2199445704
Short name T596
Test name
Test status
Simulation time 193985715 ps
CPU time 1.77 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 200464 kb
Host smart-87994ecd-8397-4ee6-a4d8-5dcf582f89fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199445704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2199445704
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2937528817
Short name T575
Test name
Test status
Simulation time 61682482 ps
CPU time 1.59 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 200324 kb
Host smart-57c4e584-8a73-4151-9823-9d33f613e01d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937528817 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2937528817
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3548514690
Short name T571
Test name
Test status
Simulation time 50363930 ps
CPU time 0.58 seconds
Started Jul 12 05:37:35 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 195132 kb
Host smart-eb4373ee-0795-43c9-b382-84e9dbb8fbd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548514690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3548514690
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2585030936
Short name T651
Test name
Test status
Simulation time 472558117 ps
CPU time 2.31 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200188 kb
Host smart-b0053b94-1cee-4302-89e5-bd5e70557e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585030936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2585030936
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2693933541
Short name T652
Test name
Test status
Simulation time 164666813 ps
CPU time 2.13 seconds
Started Jul 12 05:37:38 PM PDT 24
Finished Jul 12 05:37:43 PM PDT 24
Peak memory 200236 kb
Host smart-425e9551-ade7-443f-92a5-cf350784c5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693933541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2693933541
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.55141382
Short name T130
Test name
Test status
Simulation time 1168491287 ps
CPU time 3.37 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 200272 kb
Host smart-93529e78-c85b-4f6c-8f19-c659da95dafc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55141382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.55141382
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1213827279
Short name T53
Test name
Test status
Simulation time 221573199 ps
CPU time 1.31 seconds
Started Jul 12 05:37:28 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200200 kb
Host smart-6e08a727-0639-40f5-94dc-1719ee3c5664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213827279 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1213827279
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1921171338
Short name T109
Test name
Test status
Simulation time 16516720 ps
CPU time 0.9 seconds
Started Jul 12 05:37:24 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200016 kb
Host smart-1998c7ee-a6a4-4096-9e76-be56af143dc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921171338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1921171338
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1122583752
Short name T654
Test name
Test status
Simulation time 196311914 ps
CPU time 0.62 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 194144 kb
Host smart-06ac3da7-dfa8-4dce-b379-8b2ceb9c4689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122583752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1122583752
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.789637944
Short name T116
Test name
Test status
Simulation time 221811795 ps
CPU time 1.88 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 200272 kb
Host smart-0f23df6a-2e63-4893-8c23-187f6efe6147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789637944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.789637944
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3133826092
Short name T655
Test name
Test status
Simulation time 227943672 ps
CPU time 3.99 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 200268 kb
Host smart-2b84bd07-10b7-404b-a503-7e0c187d0058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133826092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3133826092
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.28727293
Short name T647
Test name
Test status
Simulation time 728533236 ps
CPU time 3.89 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 200264 kb
Host smart-f6283c61-4721-4cf8-8a79-4bf32ef06bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28727293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.28727293
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3784637190
Short name T599
Test name
Test status
Simulation time 82253908 ps
CPU time 1.81 seconds
Started Jul 12 05:37:36 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 200296 kb
Host smart-1c6caf07-f392-4891-9f78-6c2817dc0606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784637190 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3784637190
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3950404310
Short name T569
Test name
Test status
Simulation time 70827833 ps
CPU time 0.74 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 198052 kb
Host smart-7abab449-9587-4d39-a36d-7b91571e1ce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950404310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3950404310
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2304406105
Short name T617
Test name
Test status
Simulation time 46341290 ps
CPU time 0.61 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:15 PM PDT 24
Peak memory 195140 kb
Host smart-68630928-30b6-4a15-a881-91f3ce625e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304406105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2304406105
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4004630986
Short name T621
Test name
Test status
Simulation time 46010833 ps
CPU time 2.13 seconds
Started Jul 12 05:37:26 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 200240 kb
Host smart-e723a900-4999-400a-a2c4-ae69c2c9256f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004630986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4004630986
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1417632077
Short name T54
Test name
Test status
Simulation time 60282099 ps
CPU time 2.91 seconds
Started Jul 12 05:37:42 PM PDT 24
Finished Jul 12 05:37:48 PM PDT 24
Peak memory 200236 kb
Host smart-75b21839-602c-4411-ac16-501dec240abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417632077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1417632077
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1724041682
Short name T135
Test name
Test status
Simulation time 164084870 ps
CPU time 3.01 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 200484 kb
Host smart-93b4924a-6567-45d0-b825-a6253e64e188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724041682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1724041682
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4078157531
Short name T390
Test name
Test status
Simulation time 38423615 ps
CPU time 0.56 seconds
Started Jul 12 05:37:38 PM PDT 24
Finished Jul 12 05:37:41 PM PDT 24
Peak memory 195808 kb
Host smart-ed8af482-4b62-405f-a6c4-22d5d5d389eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078157531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4078157531
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2434572736
Short name T371
Test name
Test status
Simulation time 532516743 ps
CPU time 28.05 seconds
Started Jul 12 05:37:50 PM PDT 24
Finished Jul 12 05:38:37 PM PDT 24
Peak memory 200144 kb
Host smart-e691e04b-7a3d-4679-9c03-85fb8b1e402b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434572736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2434572736
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2756338924
Short name T315
Test name
Test status
Simulation time 21793847394 ps
CPU time 68.71 seconds
Started Jul 12 05:37:32 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200336 kb
Host smart-c32643ac-8f03-4838-874f-2108d7c0482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756338924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2756338924
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2077026412
Short name T413
Test name
Test status
Simulation time 23062149172 ps
CPU time 1066.37 seconds
Started Jul 12 05:37:31 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 727496 kb
Host smart-d5848dfc-54d2-4012-8899-a7ebf2c816c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077026412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2077026412
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1038230937
Short name T512
Test name
Test status
Simulation time 62381479634 ps
CPU time 182.21 seconds
Started Jul 12 05:37:50 PM PDT 24
Finished Jul 12 05:41:09 PM PDT 24
Peak memory 200352 kb
Host smart-26510027-0996-4ed9-acf7-bdec54095041
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038230937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1038230937
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2537836247
Short name T415
Test name
Test status
Simulation time 39699058313 ps
CPU time 179.28 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:40:55 PM PDT 24
Peak memory 200320 kb
Host smart-58e237d3-922a-442c-94b0-da3c0be4803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537836247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2537836247
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2724199487
Short name T45
Test name
Test status
Simulation time 178094436 ps
CPU time 1.05 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 05:38:11 PM PDT 24
Peak memory 219384 kb
Host smart-9cb4c00c-e8cd-4410-8d5d-4c66e42f946e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724199487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2724199487
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.129837943
Short name T245
Test name
Test status
Simulation time 44302852 ps
CPU time 2.29 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:38:19 PM PDT 24
Peak memory 200208 kb
Host smart-0b1c797b-16b0-4cd3-8b92-c54d9f186577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129837943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.129837943
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1784487279
Short name T405
Test name
Test status
Simulation time 12150257171 ps
CPU time 1926.35 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 06:10:10 PM PDT 24
Peak memory 814728 kb
Host smart-08969858-1e12-4109-bc6e-2547dc83a1f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784487279 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1784487279
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2435169278
Short name T9
Test name
Test status
Simulation time 23540297831 ps
CPU time 2101.96 seconds
Started Jul 12 05:37:38 PM PDT 24
Finished Jul 12 06:12:47 PM PDT 24
Peak memory 707416 kb
Host smart-ccf85f24-afa2-42ff-afd8-63a146ff9f0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435169278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2435169278
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2793417415
Short name T159
Test name
Test status
Simulation time 3142798161 ps
CPU time 48.08 seconds
Started Jul 12 05:37:49 PM PDT 24
Finished Jul 12 05:38:55 PM PDT 24
Peak memory 200372 kb
Host smart-c443c1b6-3644-4c6c-aa72-2b146ea55295
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2793417415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2793417415
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.947464265
Short name T242
Test name
Test status
Simulation time 3026643927 ps
CPU time 95.92 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:39:52 PM PDT 24
Peak memory 200384 kb
Host smart-acf90fbf-5c44-4b7c-b510-c7817b73bb6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=947464265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.947464265
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3412557828
Short name T192
Test name
Test status
Simulation time 2263262953 ps
CPU time 77.28 seconds
Started Jul 12 05:37:33 PM PDT 24
Finished Jul 12 05:38:53 PM PDT 24
Peak memory 200324 kb
Host smart-1a0686e6-65e2-4ce2-946e-1136867b3511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3412557828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3412557828
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3569792799
Short name T362
Test name
Test status
Simulation time 174154341841 ps
CPU time 673.58 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 200308 kb
Host smart-7cbdddd3-839f-4b61-ab27-1f0184d6da6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3569792799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3569792799
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1454234437
Short name T460
Test name
Test status
Simulation time 145873936903 ps
CPU time 2346.5 seconds
Started Jul 12 05:37:50 PM PDT 24
Finished Jul 12 06:17:15 PM PDT 24
Peak memory 215872 kb
Host smart-4d3599a8-55c8-42b8-90eb-d3445e4bff67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1454234437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1454234437
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1508847576
Short name T235
Test name
Test status
Simulation time 13334516494 ps
CPU time 51.92 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:39:08 PM PDT 24
Peak memory 200332 kb
Host smart-dacdeed2-e5e5-4866-a198-613edf8aef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508847576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1508847576
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1917107937
Short name T389
Test name
Test status
Simulation time 13496230 ps
CPU time 0.59 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:38:21 PM PDT 24
Peak memory 196104 kb
Host smart-990923d2-0a30-47f8-977a-8e1585e79368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917107937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1917107937
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2782586410
Short name T436
Test name
Test status
Simulation time 283807694 ps
CPU time 16.76 seconds
Started Jul 12 05:38:01 PM PDT 24
Finished Jul 12 05:38:40 PM PDT 24
Peak memory 200360 kb
Host smart-e17d8813-89b2-4876-a987-2294d8840486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782586410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2782586410
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2154032055
Short name T149
Test name
Test status
Simulation time 2867407897 ps
CPU time 23.71 seconds
Started Jul 12 05:37:43 PM PDT 24
Finished Jul 12 05:38:11 PM PDT 24
Peak memory 200328 kb
Host smart-60dc57f8-c4b8-4c17-ba1f-8b487196fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154032055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2154032055
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1357790454
Short name T471
Test name
Test status
Simulation time 18166215946 ps
CPU time 2132.81 seconds
Started Jul 12 05:38:05 PM PDT 24
Finished Jul 12 06:13:59 PM PDT 24
Peak memory 806520 kb
Host smart-7b91c55a-da7e-485a-a03e-256dcc8ddc8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357790454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1357790454
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2518586370
Short name T200
Test name
Test status
Simulation time 925327957 ps
CPU time 12.46 seconds
Started Jul 12 05:37:41 PM PDT 24
Finished Jul 12 05:37:55 PM PDT 24
Peak memory 200264 kb
Host smart-51063a23-bb7b-497b-b1a2-5487756fb5e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518586370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2518586370
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4263126133
Short name T445
Test name
Test status
Simulation time 12264923896 ps
CPU time 54.36 seconds
Started Jul 12 05:37:37 PM PDT 24
Finished Jul 12 05:38:34 PM PDT 24
Peak memory 200404 kb
Host smart-e0e3b9ca-873e-4282-af97-406bea65f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263126133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4263126133
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3520211008
Short name T47
Test name
Test status
Simulation time 58087046 ps
CPU time 0.88 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 05:38:13 PM PDT 24
Peak memory 218276 kb
Host smart-e170bc71-dc20-47ed-94af-df87c2be901f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520211008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3520211008
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3708906099
Short name T284
Test name
Test status
Simulation time 46729683 ps
CPU time 2.25 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:04 PM PDT 24
Peak memory 200384 kb
Host smart-a9ba56bf-558e-4880-ac03-6fe4a3e661c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708906099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3708906099
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1683923688
Short name T71
Test name
Test status
Simulation time 93848858932 ps
CPU time 684.03 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 05:49:34 PM PDT 24
Peak memory 517412 kb
Host smart-70ede370-0bcc-475c-9339-b470b2304c6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683923688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1683923688
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.4046619412
Short name T22
Test name
Test status
Simulation time 96076267903 ps
CPU time 8009.52 seconds
Started Jul 12 05:37:45 PM PDT 24
Finished Jul 12 07:51:23 PM PDT 24
Peak memory 909584 kb
Host smart-8e0d7b96-2b5b-4fc6-b7ca-66443aa46417
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046619412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.4046619412
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1059707529
Short name T400
Test name
Test status
Simulation time 4373967556 ps
CPU time 64.69 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 200356 kb
Host smart-9b93c694-8e18-428f-a35d-8d4996fb96f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1059707529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1059707529
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3219064537
Short name T323
Test name
Test status
Simulation time 10013736026 ps
CPU time 98.86 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:40:10 PM PDT 24
Peak memory 200408 kb
Host smart-fd0d7416-666f-4508-b08d-e6346fc9bb9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3219064537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3219064537
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1432615987
Short name T259
Test name
Test status
Simulation time 13882300845 ps
CPU time 74.78 seconds
Started Jul 12 05:38:01 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 200348 kb
Host smart-cab2fce1-5253-4e73-a4da-e3bea01cd31f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1432615987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1432615987
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3461414753
Short name T57
Test name
Test status
Simulation time 43687871072 ps
CPU time 578.97 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:47:54 PM PDT 24
Peak memory 200248 kb
Host smart-3292c5fa-bd19-45b4-ad7a-08d6550367bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3461414753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3461414753
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.4237120417
Short name T374
Test name
Test status
Simulation time 40638750776 ps
CPU time 2225.12 seconds
Started Jul 12 05:38:00 PM PDT 24
Finished Jul 12 06:15:29 PM PDT 24
Peak memory 215932 kb
Host smart-73b5dcdf-5128-4d70-8680-584549ff5e62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4237120417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.4237120417
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4183623432
Short name T356
Test name
Test status
Simulation time 561019119771 ps
CPU time 2217.72 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 06:15:11 PM PDT 24
Peak memory 215884 kb
Host smart-e0a47c1d-c612-46ab-9c23-2568bf88f1e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4183623432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4183623432
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2728993295
Short name T196
Test name
Test status
Simulation time 8287487008 ps
CPU time 62.74 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 200280 kb
Host smart-24f74bec-1600-4937-973d-306249b740f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728993295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2728993295
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3713158731
Short name T495
Test name
Test status
Simulation time 119820975 ps
CPU time 0.6 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:38:40 PM PDT 24
Peak memory 196860 kb
Host smart-3310432f-9985-4dbc-b7fd-d7d699909a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713158731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3713158731
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3471083851
Short name T261
Test name
Test status
Simulation time 180790261 ps
CPU time 2.76 seconds
Started Jul 12 05:38:10 PM PDT 24
Finished Jul 12 05:38:32 PM PDT 24
Peak memory 200316 kb
Host smart-27fe678f-b019-4a1d-8edf-4741414c2f14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471083851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3471083851
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1545899411
Short name T253
Test name
Test status
Simulation time 3308720834 ps
CPU time 60.2 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 200396 kb
Host smart-196fd616-9708-4b38-bdcf-e1724af066dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545899411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1545899411
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2806189862
Short name T301
Test name
Test status
Simulation time 902620747 ps
CPU time 168.2 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:41:05 PM PDT 24
Peak memory 617236 kb
Host smart-c3ce221d-1a6b-470f-b419-3ca6b1cb8d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806189862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2806189862
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2758906703
Short name T491
Test name
Test status
Simulation time 44596500353 ps
CPU time 234.92 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:42:25 PM PDT 24
Peak memory 200576 kb
Host smart-e9677d49-0590-4dbd-9cc9-0652857491c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758906703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2758906703
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3099789958
Short name T175
Test name
Test status
Simulation time 1238625330 ps
CPU time 21.85 seconds
Started Jul 12 05:37:59 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200220 kb
Host smart-1de4faba-a995-404b-bb20-25653142ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099789958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3099789958
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2083599007
Short name T166
Test name
Test status
Simulation time 2734612303 ps
CPU time 9.18 seconds
Started Jul 12 05:38:10 PM PDT 24
Finished Jul 12 05:38:37 PM PDT 24
Peak memory 200244 kb
Host smart-71f4689d-8b18-45a9-bb7b-f5888da3f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083599007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2083599007
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.191978195
Short name T150
Test name
Test status
Simulation time 4470379007 ps
CPU time 194.14 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:41:45 PM PDT 24
Peak memory 215368 kb
Host smart-bd5b7afc-19a6-4cf4-8b9a-15383beba713
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191978195 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.191978195
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2851240412
Short name T243
Test name
Test status
Simulation time 121236777885 ps
CPU time 117.52 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:40:31 PM PDT 24
Peak memory 200416 kb
Host smart-2d621d42-e0ae-47fb-b4eb-994a4dcbd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851240412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2851240412
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.737354889
Short name T407
Test name
Test status
Simulation time 41559272 ps
CPU time 0.59 seconds
Started Jul 12 05:38:00 PM PDT 24
Finished Jul 12 05:38:23 PM PDT 24
Peak memory 196760 kb
Host smart-b3c2d32d-a5bc-4596-8074-34dc77d81f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737354889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.737354889
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2498143407
Short name T442
Test name
Test status
Simulation time 532715756 ps
CPU time 28.84 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:38:56 PM PDT 24
Peak memory 200344 kb
Host smart-bcf9afe4-1baf-40b6-ba9f-915fe2283baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498143407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2498143407
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3346774337
Short name T322
Test name
Test status
Simulation time 6461926246 ps
CPU time 41.32 seconds
Started Jul 12 05:37:58 PM PDT 24
Finished Jul 12 05:39:01 PM PDT 24
Peak memory 200360 kb
Host smart-5669323f-10b2-4d34-bf40-01c6e319c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346774337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3346774337
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4098077160
Short name T170
Test name
Test status
Simulation time 13230630991 ps
CPU time 553.12 seconds
Started Jul 12 05:37:58 PM PDT 24
Finished Jul 12 05:47:35 PM PDT 24
Peak memory 527732 kb
Host smart-daea546d-4c53-44cd-8bf6-37e68e677df9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098077160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4098077160
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2322160279
Short name T363
Test name
Test status
Simulation time 1001736889 ps
CPU time 17.1 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:48 PM PDT 24
Peak memory 200276 kb
Host smart-da882e08-5de4-418c-826b-1dc847616070
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322160279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2322160279
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2101292172
Short name T313
Test name
Test status
Simulation time 2511118343 ps
CPU time 32.01 seconds
Started Jul 12 05:38:08 PM PDT 24
Finished Jul 12 05:38:59 PM PDT 24
Peak memory 200252 kb
Host smart-d4569044-886b-4b53-9810-77bf4021bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101292172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2101292172
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.651760480
Short name T392
Test name
Test status
Simulation time 1427087367 ps
CPU time 4.43 seconds
Started Jul 12 05:38:00 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 200292 kb
Host smart-3688ee24-f2b7-4e5b-9891-19b55b7d593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651760480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.651760480
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1011590338
Short name T65
Test name
Test status
Simulation time 43071103983 ps
CPU time 830.71 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:52:22 PM PDT 24
Peak memory 476448 kb
Host smart-3ab714b0-3080-4546-a69c-aa7da521a4ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011590338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1011590338
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1069406081
Short name T205
Test name
Test status
Simulation time 30512564626 ps
CPU time 129.12 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:40:36 PM PDT 24
Peak memory 200216 kb
Host smart-5ef4ddc1-451e-468b-96a8-ac3d0a4657d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069406081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1069406081
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.36169208
Short name T487
Test name
Test status
Simulation time 22522027 ps
CPU time 0.58 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 05:38:20 PM PDT 24
Peak memory 196236 kb
Host smart-75047f23-b408-499f-aa43-6d886cd0e036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36169208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.36169208
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1539294071
Short name T173
Test name
Test status
Simulation time 2820253869 ps
CPU time 40.47 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:39:01 PM PDT 24
Peak memory 200264 kb
Host smart-a17afcce-469b-455f-85c7-404e9959cc0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539294071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1539294071
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.752635134
Short name T19
Test name
Test status
Simulation time 588459297 ps
CPU time 32.34 seconds
Started Jul 12 05:38:02 PM PDT 24
Finished Jul 12 05:38:57 PM PDT 24
Peak memory 200352 kb
Host smart-4254f767-8dfd-4521-9905-eeb076b48c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752635134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.752635134
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.259694803
Short name T169
Test name
Test status
Simulation time 694801939 ps
CPU time 73.06 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 260360 kb
Host smart-039ce533-9038-440a-9373-5da3a9072fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259694803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.259694803
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1676571036
Short name T164
Test name
Test status
Simulation time 21101359826 ps
CPU time 176.97 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:41:28 PM PDT 24
Peak memory 200336 kb
Host smart-61d0d1c3-2276-4667-9a32-f55fe8c0ca16
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676571036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1676571036
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3897849592
Short name T377
Test name
Test status
Simulation time 17821854960 ps
CPU time 151.29 seconds
Started Jul 12 05:38:03 PM PDT 24
Finished Jul 12 05:40:56 PM PDT 24
Peak memory 216748 kb
Host smart-d5c4255b-6a17-4cd9-a0b2-ce0821e27336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897849592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3897849592
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3534287782
Short name T344
Test name
Test status
Simulation time 724275344 ps
CPU time 8.6 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 200204 kb
Host smart-29a68a5c-347b-4573-8002-c6b3b22b11cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534287782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3534287782
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1361052750
Short name T124
Test name
Test status
Simulation time 57654549165 ps
CPU time 249.52 seconds
Started Jul 12 05:38:06 PM PDT 24
Finished Jul 12 05:42:36 PM PDT 24
Peak memory 200344 kb
Host smart-4076f875-1f2b-4481-a1ac-0e68a7660432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361052750 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1361052750
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3831457388
Short name T494
Test name
Test status
Simulation time 1265452605 ps
CPU time 65.14 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 200296 kb
Host smart-ab90d3dc-1b7c-4782-8c2e-11814006fc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831457388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3831457388
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3389879935
Short name T412
Test name
Test status
Simulation time 64392570 ps
CPU time 0.58 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:31 PM PDT 24
Peak memory 196864 kb
Host smart-0cc4f18e-5584-475b-bc18-5cf261c291b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389879935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3389879935
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3474468599
Short name T140
Test name
Test status
Simulation time 3019387810 ps
CPU time 86.08 seconds
Started Jul 12 05:37:59 PM PDT 24
Finished Jul 12 05:39:48 PM PDT 24
Peak memory 200240 kb
Host smart-d6d279b2-d5dc-4899-a1ad-e48cd1a3d377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474468599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3474468599
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1568716710
Short name T273
Test name
Test status
Simulation time 2755710267 ps
CPU time 50.07 seconds
Started Jul 12 05:38:10 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 200412 kb
Host smart-cb86475c-b06e-4d53-8a69-badd54761e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568716710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1568716710
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1988981736
Short name T521
Test name
Test status
Simulation time 6635091428 ps
CPU time 613.68 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 05:48:32 PM PDT 24
Peak memory 538144 kb
Host smart-fce3855c-854c-4943-ac2b-40178b4cd491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988981736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1988981736
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3580588765
Short name T256
Test name
Test status
Simulation time 7008005958 ps
CPU time 89.37 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:40:00 PM PDT 24
Peak memory 200384 kb
Host smart-7759f0af-5d7d-4ac6-9e2e-f533338de668
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580588765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3580588765
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2888278910
Short name T204
Test name
Test status
Simulation time 5427573293 ps
CPU time 96.15 seconds
Started Jul 12 05:37:59 PM PDT 24
Finished Jul 12 05:39:58 PM PDT 24
Peak memory 200360 kb
Host smart-0eff02c1-921a-463a-a8bc-d2c951fc04b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888278910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2888278910
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.24255069
Short name T201
Test name
Test status
Simulation time 82487073 ps
CPU time 1.52 seconds
Started Jul 12 05:37:58 PM PDT 24
Finished Jul 12 05:38:24 PM PDT 24
Peak memory 200212 kb
Host smart-033f01d0-1e1f-4f02-91b8-49d9e30b3fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24255069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.24255069
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1220251111
Short name T463
Test name
Test status
Simulation time 147053605596 ps
CPU time 2926.25 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 06:27:04 PM PDT 24
Peak memory 787548 kb
Host smart-9ff822ec-5c02-41d1-b61c-fe27a6afb959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220251111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1220251111
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3115454135
Short name T452
Test name
Test status
Simulation time 2201366777 ps
CPU time 35.84 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:39:08 PM PDT 24
Peak memory 200384 kb
Host smart-77f964a5-5da1-49e9-8e88-ed84829a49cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115454135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3115454135
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2296473514
Short name T384
Test name
Test status
Simulation time 2067141291 ps
CPU time 58.42 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 200264 kb
Host smart-6dddf0ea-a96a-4b17-b264-39cb1a57427b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296473514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2296473514
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4279138040
Short name T450
Test name
Test status
Simulation time 686766627 ps
CPU time 9.6 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:38:40 PM PDT 24
Peak memory 200256 kb
Host smart-0dcab1bb-d4bb-4b17-ae16-6cf13b4c278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279138040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4279138040
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1035340432
Short name T287
Test name
Test status
Simulation time 4901709426 ps
CPU time 512.78 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:47:05 PM PDT 24
Peak memory 703632 kb
Host smart-f5096073-b0f8-4dec-b653-512634030e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035340432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1035340432
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3867797644
Short name T475
Test name
Test status
Simulation time 1063587167 ps
CPU time 55.84 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 05:39:26 PM PDT 24
Peak memory 200256 kb
Host smart-854e9028-ec90-4c8a-9663-45b9a66df4a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867797644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3867797644
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3447926389
Short name T341
Test name
Test status
Simulation time 17311541004 ps
CPU time 49.82 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:39:24 PM PDT 24
Peak memory 200356 kb
Host smart-563c63c4-cb33-42c0-b02d-10f040aed3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447926389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3447926389
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1513654642
Short name T404
Test name
Test status
Simulation time 256090128 ps
CPU time 10.01 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 05:38:40 PM PDT 24
Peak memory 200204 kb
Host smart-abe8a81a-a276-4a50-8820-09d852083606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513654642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1513654642
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.913134344
Short name T428
Test name
Test status
Simulation time 7246561040 ps
CPU time 44.1 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:16 PM PDT 24
Peak memory 200300 kb
Host smart-62b1d8b3-3215-4834-86ad-efe8ed48cb90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913134344 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.913134344
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3016752926
Short name T292
Test name
Test status
Simulation time 2260642577 ps
CPU time 110.7 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:40:22 PM PDT 24
Peak memory 200188 kb
Host smart-e7bb5913-f024-4fb5-87c1-b77c4f2c98d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016752926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3016752926
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1999306030
Short name T331
Test name
Test status
Simulation time 43326916 ps
CPU time 0.6 seconds
Started Jul 12 05:38:08 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 196740 kb
Host smart-9851ba19-18ea-46bc-841a-c62480d92ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999306030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1999306030
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.476100842
Short name T144
Test name
Test status
Simulation time 1522760141 ps
CPU time 43.68 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 200276 kb
Host smart-1c95784e-2737-4194-9308-0200394e5dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476100842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.476100842
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2088920299
Short name T298
Test name
Test status
Simulation time 117223106 ps
CPU time 1.86 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 05:38:32 PM PDT 24
Peak memory 200216 kb
Host smart-43413686-2396-45b1-a84c-d1d79f03501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088920299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2088920299
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1973301142
Short name T264
Test name
Test status
Simulation time 22038843176 ps
CPU time 1089.13 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:56:40 PM PDT 24
Peak memory 771240 kb
Host smart-ce13cd70-34f3-42f0-bb61-fd1a63c099d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973301142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1973301142
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.712225826
Short name T318
Test name
Test status
Simulation time 8189356818 ps
CPU time 110.99 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:40:23 PM PDT 24
Peak memory 200220 kb
Host smart-9e99de12-b650-4cb6-bec6-a7899b9f3229
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712225826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.712225826
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2127895626
Short name T379
Test name
Test status
Simulation time 70270184029 ps
CPU time 217.76 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 05:42:05 PM PDT 24
Peak memory 200400 kb
Host smart-74d9309f-6b8c-4e10-93ab-103ca15ef6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127895626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2127895626
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2794291271
Short name T228
Test name
Test status
Simulation time 1118795256 ps
CPU time 15.16 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 200304 kb
Host smart-67e4bcad-cda5-4282-b1cb-428849ccf0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794291271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2794291271
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1947593982
Short name T88
Test name
Test status
Simulation time 22878420520 ps
CPU time 2028.15 seconds
Started Jul 12 05:38:02 PM PDT 24
Finished Jul 12 06:12:13 PM PDT 24
Peak memory 721812 kb
Host smart-dfe450b0-7827-4cb1-aa85-68256118e3c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947593982 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1947593982
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3052905447
Short name T87
Test name
Test status
Simulation time 4228625303 ps
CPU time 51.04 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 200400 kb
Host smart-7c2047e9-5c47-47d9-b35c-add0daa89848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052905447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3052905447
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.145397995
Short name T409
Test name
Test status
Simulation time 13272994 ps
CPU time 0.57 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:38:36 PM PDT 24
Peak memory 195820 kb
Host smart-f13bc6db-9ac9-4d17-94ca-de2a54d1c7e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145397995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.145397995
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3822950906
Short name T403
Test name
Test status
Simulation time 2380273525 ps
CPU time 66.96 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 200236 kb
Host smart-3d3885d8-e768-4b54-9731-280ccd6d0921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822950906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3822950906
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1941661554
Short name T94
Test name
Test status
Simulation time 596534629 ps
CPU time 5.28 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 05:38:33 PM PDT 24
Peak memory 200312 kb
Host smart-0b8b0a5c-9b6a-4746-b7c5-9261d92773eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941661554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1941661554
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2521757690
Short name T176
Test name
Test status
Simulation time 6896545283 ps
CPU time 203.65 seconds
Started Jul 12 05:37:59 PM PDT 24
Finished Jul 12 05:41:46 PM PDT 24
Peak memory 634820 kb
Host smart-b03d459e-4920-49ec-bf37-cf44d7237c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521757690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2521757690
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.281847450
Short name T496
Test name
Test status
Simulation time 1861850476 ps
CPU time 103.57 seconds
Started Jul 12 05:38:00 PM PDT 24
Finished Jul 12 05:40:07 PM PDT 24
Peak memory 200288 kb
Host smart-a528d473-626b-4b2d-95bd-dc19a07bbb18
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281847450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.281847450
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.50046163
Short name T335
Test name
Test status
Simulation time 498020332 ps
CPU time 19.54 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:51 PM PDT 24
Peak memory 200160 kb
Host smart-df1d852c-c9af-4a1e-9dfa-984f74b09793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50046163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.50046163
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3720347870
Short name T231
Test name
Test status
Simulation time 908164727 ps
CPU time 11.28 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 199680 kb
Host smart-35d559f8-edc6-4b43-950f-f81e1179e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720347870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3720347870
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2204495297
Short name T66
Test name
Test status
Simulation time 227689071465 ps
CPU time 704.96 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:50:12 PM PDT 24
Peak memory 208536 kb
Host smart-3c2b9b8e-3159-4219-a36e-28593281b063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204495297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2204495297
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3900323475
Short name T74
Test name
Test status
Simulation time 3192698602 ps
CPU time 10.37 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200528 kb
Host smart-698d65da-d498-4bfc-a1c5-69030bee4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900323475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3900323475
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3214530373
Short name T258
Test name
Test status
Simulation time 19578094 ps
CPU time 0.58 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:38:43 PM PDT 24
Peak memory 195052 kb
Host smart-cc5dd903-c851-451c-a27a-5de215c5570f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214530373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3214530373
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1235578067
Short name T203
Test name
Test status
Simulation time 1902174371 ps
CPU time 28.12 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:39:04 PM PDT 24
Peak memory 200268 kb
Host smart-2570031f-e5ff-4a37-b243-06e8dfe090c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235578067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1235578067
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3331167642
Short name T502
Test name
Test status
Simulation time 786768728 ps
CPU time 10.08 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:38:43 PM PDT 24
Peak memory 200192 kb
Host smart-654b49ae-9fcf-4da7-9325-f4bebfa69deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331167642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3331167642
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3092265425
Short name T269
Test name
Test status
Simulation time 148025710 ps
CPU time 9.93 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:38:43 PM PDT 24
Peak memory 201904 kb
Host smart-b71f6643-3983-4c19-a53c-7d2e96aa8949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092265425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3092265425
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3220881447
Short name T15
Test name
Test status
Simulation time 1778434798 ps
CPU time 49.39 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 200092 kb
Host smart-29cec1f7-48da-4c53-9655-b06fe4689804
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220881447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3220881447
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.543171814
Short name T359
Test name
Test status
Simulation time 10217702136 ps
CPU time 129.92 seconds
Started Jul 12 05:38:08 PM PDT 24
Finished Jul 12 05:40:37 PM PDT 24
Peak memory 200356 kb
Host smart-1fae09bf-38e3-4a91-ae30-5517f2cc4d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543171814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.543171814
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2666613045
Short name T514
Test name
Test status
Simulation time 4404914325 ps
CPU time 13.7 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 05:38:41 PM PDT 24
Peak memory 200364 kb
Host smart-8b2b55e5-9540-4ed4-8322-08869f84e0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666613045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2666613045
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2465836525
Short name T96
Test name
Test status
Simulation time 468483830984 ps
CPU time 5855.43 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 07:16:08 PM PDT 24
Peak memory 894992 kb
Host smart-68fd4986-eca1-4e5b-9809-26e533114e53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465836525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2465836525
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.475639397
Short name T127
Test name
Test status
Simulation time 4488131094 ps
CPU time 83.53 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:39:55 PM PDT 24
Peak memory 200480 kb
Host smart-bef6939e-dd97-41ed-a441-4a246f565f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475639397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.475639397
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.795167632
Short name T332
Test name
Test status
Simulation time 45038545 ps
CPU time 0.59 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:31 PM PDT 24
Peak memory 196832 kb
Host smart-809b946c-68a9-44ea-805d-e200d8dca017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795167632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.795167632
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.497350859
Short name T224
Test name
Test status
Simulation time 474105594 ps
CPU time 13.61 seconds
Started Jul 12 05:38:04 PM PDT 24
Finished Jul 12 05:38:39 PM PDT 24
Peak memory 200208 kb
Host smart-ad400371-6ca9-4c07-a1d4-1c5644362a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497350859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.497350859
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3627578105
Short name T307
Test name
Test status
Simulation time 22497133474 ps
CPU time 31.04 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 200608 kb
Host smart-9aea2014-236d-4567-b21e-2f4242b6acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627578105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3627578105
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3045890863
Short name T531
Test name
Test status
Simulation time 10341983306 ps
CPU time 505.68 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:47:04 PM PDT 24
Peak memory 719268 kb
Host smart-29e29a94-b1be-40c1-bff6-be96302fdabc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045890863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3045890863
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1801000954
Short name T153
Test name
Test status
Simulation time 1778548273 ps
CPU time 50.41 seconds
Started Jul 12 05:38:21 PM PDT 24
Finished Jul 12 05:39:25 PM PDT 24
Peak memory 200268 kb
Host smart-f173a26c-0c3f-4907-a90e-c8ad354aadc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801000954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1801000954
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1979564238
Short name T410
Test name
Test status
Simulation time 9766745534 ps
CPU time 126.47 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:40:37 PM PDT 24
Peak memory 200408 kb
Host smart-5f059188-3be3-4e3e-bfec-7f3b39d04c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979564238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1979564238
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3243474201
Short name T312
Test name
Test status
Simulation time 1801685903 ps
CPU time 8.41 seconds
Started Jul 12 05:38:06 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 200292 kb
Host smart-be4bcc05-a777-4298-9aa4-d00ffc483022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243474201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3243474201
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.505766566
Short name T126
Test name
Test status
Simulation time 150594745060 ps
CPU time 3627.09 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 06:38:58 PM PDT 24
Peak memory 829304 kb
Host smart-6736844a-c620-44b4-893c-2e15f96178ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505766566 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.505766566
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2970874534
Short name T125
Test name
Test status
Simulation time 7256135823 ps
CPU time 119.87 seconds
Started Jul 12 05:38:00 PM PDT 24
Finished Jul 12 05:40:23 PM PDT 24
Peak memory 200404 kb
Host smart-0c21c79f-62c0-401e-b251-1be2aec41963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970874534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2970874534
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1254217296
Short name T249
Test name
Test status
Simulation time 32317442 ps
CPU time 0.58 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:38:34 PM PDT 24
Peak memory 195032 kb
Host smart-d1fc28f8-967b-4b17-8a13-3950dc764c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254217296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1254217296
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2104116396
Short name T474
Test name
Test status
Simulation time 4068928500 ps
CPU time 55.88 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:39:26 PM PDT 24
Peak memory 200292 kb
Host smart-ca52ec75-61ec-4d72-9924-0f12d03d2a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104116396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2104116396
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.76990608
Short name T435
Test name
Test status
Simulation time 1843112919 ps
CPU time 9.05 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:40 PM PDT 24
Peak memory 200268 kb
Host smart-aa3409e4-b9ab-4d41-aa70-735a3b1dec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76990608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.76990608
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1217274836
Short name T41
Test name
Test status
Simulation time 750832403 ps
CPU time 127.14 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:40:47 PM PDT 24
Peak memory 462532 kb
Host smart-e5570294-0608-4c11-926f-9b2b9c2f8a55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217274836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1217274836
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3017580851
Short name T280
Test name
Test status
Simulation time 7007718502 ps
CPU time 58.76 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:39:30 PM PDT 24
Peak memory 200336 kb
Host smart-a0ceecdf-45fc-41a0-bde9-1e71d12be322
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017580851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3017580851
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4173447478
Short name T230
Test name
Test status
Simulation time 4622493306 ps
CPU time 132.35 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:40:45 PM PDT 24
Peak memory 200360 kb
Host smart-5df7682a-31cb-4249-92ad-a0fd49cb45e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173447478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4173447478
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2750948830
Short name T63
Test name
Test status
Simulation time 19599849 ps
CPU time 0.77 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 198296 kb
Host smart-adb86b25-36ff-4c3d-a8cf-d44394aefb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750948830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2750948830
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.467549699
Short name T505
Test name
Test status
Simulation time 33737667126 ps
CPU time 960.6 seconds
Started Jul 12 05:38:20 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 694840 kb
Host smart-0f51fb16-84b2-4579-bd69-7925965fd250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467549699 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.467549699
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3810056300
Short name T327
Test name
Test status
Simulation time 4430054437 ps
CPU time 51.49 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 200360 kb
Host smart-7d2579cd-1ddf-493b-9338-e7375f82a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810056300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3810056300
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2919574073
Short name T34
Test name
Test status
Simulation time 14182963 ps
CPU time 0.6 seconds
Started Jul 12 05:37:44 PM PDT 24
Finished Jul 12 05:37:51 PM PDT 24
Peak memory 196884 kb
Host smart-60828f9d-6ccf-434e-a4d8-3d55968f7f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919574073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2919574073
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.540891138
Short name T425
Test name
Test status
Simulation time 3188352948 ps
CPU time 94.02 seconds
Started Jul 12 05:37:41 PM PDT 24
Finished Jul 12 05:39:17 PM PDT 24
Peak memory 216896 kb
Host smart-77540626-489f-4570-a5b7-94ed10b74b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540891138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.540891138
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2081990141
Short name T310
Test name
Test status
Simulation time 3216483607 ps
CPU time 15.34 seconds
Started Jul 12 05:37:43 PM PDT 24
Finished Jul 12 05:38:02 PM PDT 24
Peak memory 200348 kb
Host smart-d759aa2a-be4a-489b-adce-418c019f3858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081990141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2081990141
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.148504154
Short name T518
Test name
Test status
Simulation time 31719733555 ps
CPU time 1730.18 seconds
Started Jul 12 05:37:41 PM PDT 24
Finished Jul 12 06:06:33 PM PDT 24
Peak memory 787820 kb
Host smart-01a2477f-0208-4a20-af44-2287332a8af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148504154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.148504154
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1520595881
Short name T226
Test name
Test status
Simulation time 5737736872 ps
CPU time 40.41 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:39:07 PM PDT 24
Peak memory 200336 kb
Host smart-e504ddb8-7450-4853-934c-b6063b7b6476
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520595881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1520595881
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2151949036
Short name T236
Test name
Test status
Simulation time 1359920888 ps
CPU time 19.11 seconds
Started Jul 12 05:37:44 PM PDT 24
Finished Jul 12 05:38:09 PM PDT 24
Peak memory 200268 kb
Host smart-41c1d793-4a01-45d6-aac7-b9d31934d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151949036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2151949036
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3676560177
Short name T48
Test name
Test status
Simulation time 107053937 ps
CPU time 0.88 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:38:17 PM PDT 24
Peak memory 218168 kb
Host smart-35e893fd-61d9-4dda-95d9-4c1a3bf59b0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676560177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3676560177
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2712978915
Short name T468
Test name
Test status
Simulation time 1007564617 ps
CPU time 8.93 seconds
Started Jul 12 05:37:44 PM PDT 24
Finished Jul 12 05:37:58 PM PDT 24
Peak memory 200316 kb
Host smart-3e92bcc6-2392-4284-8872-3e37a30b23db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712978915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2712978915
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3284278123
Short name T520
Test name
Test status
Simulation time 49089820143 ps
CPU time 1011.51 seconds
Started Jul 12 05:37:42 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 549024 kb
Host smart-d85f0ee7-d342-4343-931c-7e991645b1ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284278123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3284278123
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3104568319
Short name T198
Test name
Test status
Simulation time 12735367450 ps
CPU time 70.13 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:39:26 PM PDT 24
Peak memory 200256 kb
Host smart-4d7be364-47a2-4456-871e-56e4d1e82f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3104568319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3104568319
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1222564303
Short name T358
Test name
Test status
Simulation time 34700450324 ps
CPU time 103.26 seconds
Started Jul 12 05:37:45 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 200240 kb
Host smart-c3d89f20-7ae4-4710-9821-e94d4944bbba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1222564303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1222564303
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1975264424
Short name T277
Test name
Test status
Simulation time 5879064548 ps
CPU time 86.12 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 200268 kb
Host smart-5db32328-037e-4073-b55f-55cf443b0eec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1975264424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1975264424
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2130621685
Short name T56
Test name
Test status
Simulation time 69495241153 ps
CPU time 604.2 seconds
Started Jul 12 05:37:44 PM PDT 24
Finished Jul 12 05:47:53 PM PDT 24
Peak memory 200332 kb
Host smart-b31a44e5-0118-4d12-b305-cbaa32f2f1df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2130621685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2130621685
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.346413817
Short name T217
Test name
Test status
Simulation time 720922500253 ps
CPU time 2360.57 seconds
Started Jul 12 05:38:06 PM PDT 24
Finished Jul 12 06:17:47 PM PDT 24
Peak memory 216340 kb
Host smart-d3926a87-f3a8-44c8-b762-2c129d4c638a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=346413817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.346413817
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3972081926
Short name T364
Test name
Test status
Simulation time 1123063284787 ps
CPU time 2400.03 seconds
Started Jul 12 05:37:44 PM PDT 24
Finished Jul 12 06:17:50 PM PDT 24
Peak memory 216528 kb
Host smart-1e041cde-3c30-408d-b382-2c015818c23f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3972081926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3972081926
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2495788276
Short name T346
Test name
Test status
Simulation time 3509774103 ps
CPU time 60.53 seconds
Started Jul 12 05:38:02 PM PDT 24
Finished Jul 12 05:39:25 PM PDT 24
Peak memory 200320 kb
Host smart-f0fe3173-16bf-4729-8ae3-bc81eb118822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495788276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2495788276
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1935475213
Short name T43
Test name
Test status
Simulation time 17670370 ps
CPU time 0.59 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:38:34 PM PDT 24
Peak memory 196148 kb
Host smart-d1787277-ba45-40ce-a968-4f5c05423af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935475213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1935475213
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4122254321
Short name T406
Test name
Test status
Simulation time 1343729466 ps
CPU time 71.14 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:39:43 PM PDT 24
Peak memory 200316 kb
Host smart-885eb873-a01c-45d2-aab7-601a4b9b9075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122254321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4122254321
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2194720575
Short name T215
Test name
Test status
Simulation time 7857413274 ps
CPU time 36.39 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 200524 kb
Host smart-c811bcaf-666c-4ad9-817b-8023482b11f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194720575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2194720575
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2607294282
Short name T457
Test name
Test status
Simulation time 5190401448 ps
CPU time 941.67 seconds
Started Jul 12 05:38:23 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 699504 kb
Host smart-0f6a2ec0-ea00-4f91-9fe1-5cbb11bf500a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607294282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2607294282
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2520515078
Short name T333
Test name
Test status
Simulation time 5097866148 ps
CPU time 68.76 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 200320 kb
Host smart-6c898077-d8e1-464d-82a1-12e11c165272
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520515078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2520515078
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3953472957
Short name T78
Test name
Test status
Simulation time 39014031019 ps
CPU time 106.45 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:40:19 PM PDT 24
Peak memory 200696 kb
Host smart-29a2b325-e52f-4018-9257-b029c6fa4a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953472957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3953472957
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.175914528
Short name T418
Test name
Test status
Simulation time 1616070334 ps
CPU time 10.83 seconds
Started Jul 12 05:38:24 PM PDT 24
Finished Jul 12 05:38:48 PM PDT 24
Peak memory 200260 kb
Host smart-3a18032f-3de4-4b77-96a2-92ae04ab75d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175914528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.175914528
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1741138783
Short name T146
Test name
Test status
Simulation time 91718710145 ps
CPU time 2937.49 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 06:27:31 PM PDT 24
Peak memory 747860 kb
Host smart-09951b61-e0eb-4508-858d-570ef0c92bfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741138783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1741138783
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3835239784
Short name T508
Test name
Test status
Simulation time 10102017893 ps
CPU time 126.65 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:40:40 PM PDT 24
Peak memory 200228 kb
Host smart-b417b28c-1c50-4b77-8e4f-49039077900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835239784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3835239784
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2287491902
Short name T58
Test name
Test status
Simulation time 23695249 ps
CPU time 0.6 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:32 PM PDT 24
Peak memory 195328 kb
Host smart-9631f90d-4e6d-42bd-9ad7-32cb4070f667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287491902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2287491902
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3511898764
Short name T183
Test name
Test status
Simulation time 826409648 ps
CPU time 50.3 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 200308 kb
Host smart-5691e8d5-2095-454c-8ceb-7d118a2f1666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511898764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3511898764
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3656149443
Short name T467
Test name
Test status
Simulation time 4618744488 ps
CPU time 26.06 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:58 PM PDT 24
Peak memory 200364 kb
Host smart-32f49e38-3535-4ff8-8b04-71751917f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656149443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3656149443
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1400266751
Short name T399
Test name
Test status
Simulation time 6225385684 ps
CPU time 1133.89 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:57:32 PM PDT 24
Peak memory 729168 kb
Host smart-52366f89-f3b5-4a33-9743-d57ebdfe7c8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400266751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1400266751
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1024387600
Short name T212
Test name
Test status
Simulation time 32054649133 ps
CPU time 103.86 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:40:20 PM PDT 24
Peak memory 200344 kb
Host smart-50fad572-1696-44de-9b70-48a963ef8b0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024387600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1024387600
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.949731222
Short name T509
Test name
Test status
Simulation time 22222046786 ps
CPU time 221.51 seconds
Started Jul 12 05:38:23 PM PDT 24
Finished Jul 12 05:42:18 PM PDT 24
Peak memory 200340 kb
Host smart-4e284122-17e5-4354-8d8a-be645e1aeb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949731222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.949731222
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1451343084
Short name T440
Test name
Test status
Simulation time 17246370 ps
CPU time 1.04 seconds
Started Jul 12 05:38:21 PM PDT 24
Finished Jul 12 05:38:36 PM PDT 24
Peak memory 199904 kb
Host smart-a168caa6-366e-4d2f-8de4-ad47d49f20e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451343084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1451343084
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1624989320
Short name T91
Test name
Test status
Simulation time 63342848407 ps
CPU time 1075.53 seconds
Started Jul 12 05:46:28 PM PDT 24
Finished Jul 12 06:04:25 PM PDT 24
Peak memory 538720 kb
Host smart-1d2ce42b-6cef-4a8c-975c-518e3538a3c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624989320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1624989320
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3436249402
Short name T89
Test name
Test status
Simulation time 2084088903 ps
CPU time 91.18 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:40:11 PM PDT 24
Peak memory 200300 kb
Host smart-00df4677-35d2-455d-a897-fe0d1125a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436249402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3436249402
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3835954967
Short name T297
Test name
Test status
Simulation time 42214556 ps
CPU time 0.57 seconds
Started Jul 12 05:38:23 PM PDT 24
Finished Jul 12 05:38:37 PM PDT 24
Peak memory 196864 kb
Host smart-eeccbe6f-1792-4eef-9793-5570741c856d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835954967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3835954967
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.169139959
Short name T507
Test name
Test status
Simulation time 2108343110 ps
CPU time 59.11 seconds
Started Jul 12 05:38:30 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 200324 kb
Host smart-b045984d-ea81-4c30-8170-d113d4ffcff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169139959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.169139959
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1866507980
Short name T378
Test name
Test status
Simulation time 266444689 ps
CPU time 1.83 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 200292 kb
Host smart-2a74220f-f177-46cc-9a32-d40a02751ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866507980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1866507980
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1786127916
Short name T216
Test name
Test status
Simulation time 4959205893 ps
CPU time 148.3 seconds
Started Jul 12 05:38:24 PM PDT 24
Finished Jul 12 05:41:05 PM PDT 24
Peak memory 573628 kb
Host smart-2c834ef2-40ef-488f-878c-87ba0a543bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786127916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1786127916
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2051515506
Short name T500
Test name
Test status
Simulation time 20588961401 ps
CPU time 68.61 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:41 PM PDT 24
Peak memory 200332 kb
Host smart-4e641fbf-eb6a-48b4-b687-ab4a9ac244d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051515506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2051515506
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.153333180
Short name T80
Test name
Test status
Simulation time 7405481478 ps
CPU time 98.77 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:40:10 PM PDT 24
Peak memory 200344 kb
Host smart-c76f2ac1-5fd7-4e2e-b296-35ee72feb8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153333180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.153333180
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1202678848
Short name T414
Test name
Test status
Simulation time 1249742633 ps
CPU time 15.77 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:48 PM PDT 24
Peak memory 200292 kb
Host smart-849d3bdb-fe4f-4eda-961e-e43302793ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202678848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1202678848
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.36041186
Short name T30
Test name
Test status
Simulation time 8916000690 ps
CPU time 128.54 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:40:40 PM PDT 24
Peak memory 200316 kb
Host smart-e427185f-309a-4a84-ad36-9e8f3df29cb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36041186 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.36041186
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3512021182
Short name T186
Test name
Test status
Simulation time 2764711883 ps
CPU time 57.23 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 200316 kb
Host smart-47dd60c3-f3d9-4e09-b742-7053e82c220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512021182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3512021182
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.381124767
Short name T398
Test name
Test status
Simulation time 39665857 ps
CPU time 0.55 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 195812 kb
Host smart-3300ee5b-991e-45f7-971e-2ef36c297895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381124767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.381124767
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.863265865
Short name T361
Test name
Test status
Simulation time 522007524 ps
CPU time 28.74 seconds
Started Jul 12 05:38:23 PM PDT 24
Finished Jul 12 05:39:05 PM PDT 24
Peak memory 200188 kb
Host smart-0258a134-28a2-449b-a239-99c463baf580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863265865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.863265865
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.737718811
Short name T38
Test name
Test status
Simulation time 11966936968 ps
CPU time 72.16 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 200348 kb
Host smart-a0b0fe44-2f1a-4851-b067-a280d589eea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737718811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.737718811
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1313725979
Short name T40
Test name
Test status
Simulation time 5724237718 ps
CPU time 199.91 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:41:51 PM PDT 24
Peak memory 429488 kb
Host smart-60b90611-cce5-4983-9fa1-ad55da1fc34e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313725979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1313725979
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.706438691
Short name T155
Test name
Test status
Simulation time 2474752445 ps
CPU time 66.67 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:39:45 PM PDT 24
Peak memory 200244 kb
Host smart-6c2c561b-cca9-4383-beaa-2a08ac855766
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706438691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.706438691
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1410825144
Short name T157
Test name
Test status
Simulation time 2285101944 ps
CPU time 127.66 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:40:40 PM PDT 24
Peak memory 200324 kb
Host smart-46ed0999-eaf1-4ed5-8506-70c9cdb60d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410825144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1410825144
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4274631602
Short name T248
Test name
Test status
Simulation time 188833078 ps
CPU time 2.8 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 200196 kb
Host smart-5528e35d-9dbd-4945-adb5-61e6e94eeccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274631602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4274631602
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1164635945
Short name T439
Test name
Test status
Simulation time 50607385 ps
CPU time 0.59 seconds
Started Jul 12 05:38:19 PM PDT 24
Finished Jul 12 05:38:36 PM PDT 24
Peak memory 195952 kb
Host smart-28f06656-b455-4392-8b1a-d9d39a3d916d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164635945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1164635945
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.944023711
Short name T367
Test name
Test status
Simulation time 2693358496 ps
CPU time 35.2 seconds
Started Jul 12 05:38:26 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 200364 kb
Host smart-bd45b0ae-7a17-4d73-bd19-605e3038263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944023711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.944023711
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4216565948
Short name T388
Test name
Test status
Simulation time 21271142 ps
CPU time 0.59 seconds
Started Jul 12 05:38:20 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 196164 kb
Host smart-b9faee3e-ad8e-4a22-b7cc-1c701a869ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216565948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4216565948
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3248359953
Short name T430
Test name
Test status
Simulation time 1589490750 ps
CPU time 38.71 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 05:39:08 PM PDT 24
Peak memory 200336 kb
Host smart-448adc9a-8ff6-4c4b-bb76-7167718c4e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248359953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3248359953
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.787673654
Short name T59
Test name
Test status
Simulation time 642234283 ps
CPU time 3.26 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:34 PM PDT 24
Peak memory 200324 kb
Host smart-d0c6d97f-2ca4-45c9-9c23-1be5199817b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787673654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.787673654
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.146858161
Short name T220
Test name
Test status
Simulation time 19355105940 ps
CPU time 795.74 seconds
Started Jul 12 05:38:08 PM PDT 24
Finished Jul 12 05:51:43 PM PDT 24
Peak memory 666820 kb
Host smart-8ebfad12-10a4-4dbb-946d-17c0f3abfad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146858161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.146858161
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3690184233
Short name T303
Test name
Test status
Simulation time 3180170817 ps
CPU time 68.07 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 200312 kb
Host smart-3d897ff1-8071-4842-b273-fad211946699
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690184233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3690184233
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3766726992
Short name T26
Test name
Test status
Simulation time 13120948084 ps
CPU time 21 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 200264 kb
Host smart-2b61058e-cf00-4116-ad24-e0ff4706f726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766726992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3766726992
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1744066392
Short name T448
Test name
Test status
Simulation time 138527587 ps
CPU time 6.2 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:37 PM PDT 24
Peak memory 200304 kb
Host smart-fa7c0f8a-3200-4827-b8cd-472d60973472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744066392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1744066392
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3560530761
Short name T69
Test name
Test status
Simulation time 1275567525632 ps
CPU time 1949.86 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 06:11:02 PM PDT 24
Peak memory 735468 kb
Host smart-3057f25f-19b9-43e2-b761-21785ac1249c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560530761 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3560530761
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1834203389
Short name T32
Test name
Test status
Simulation time 49895806642 ps
CPU time 119.88 seconds
Started Jul 12 05:43:09 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 200372 kb
Host smart-257b6cc2-74a8-4008-b05d-d512e91b6fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834203389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1834203389
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1429205974
Short name T237
Test name
Test status
Simulation time 14455972 ps
CPU time 0.58 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:38:39 PM PDT 24
Peak memory 196088 kb
Host smart-6c030f73-6d72-4d86-8ffb-97963546d95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429205974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1429205974
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3745278735
Short name T477
Test name
Test status
Simulation time 157523418 ps
CPU time 9.19 seconds
Started Jul 12 05:38:19 PM PDT 24
Finished Jul 12 05:38:43 PM PDT 24
Peak memory 200268 kb
Host smart-50403753-aa6c-4b1d-9b49-ab989247de3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745278735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3745278735
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3929214225
Short name T95
Test name
Test status
Simulation time 9341938627 ps
CPU time 17.65 seconds
Started Jul 12 05:38:19 PM PDT 24
Finished Jul 12 05:38:52 PM PDT 24
Peak memory 200492 kb
Host smart-dd63686b-5403-4b11-bac5-ba3ce1c2d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929214225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3929214225
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3665984612
Short name T464
Test name
Test status
Simulation time 2861087777 ps
CPU time 459.5 seconds
Started Jul 12 05:38:17 PM PDT 24
Finished Jul 12 05:46:13 PM PDT 24
Peak memory 677540 kb
Host smart-ce3d3105-260e-4fc0-80cf-4640872576a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665984612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3665984612
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3153374260
Short name T485
Test name
Test status
Simulation time 5721575050 ps
CPU time 156.33 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:41:17 PM PDT 24
Peak memory 200240 kb
Host smart-f954a072-20c9-4683-b70b-59306f8ee230
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153374260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3153374260
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4059080110
Short name T181
Test name
Test status
Simulation time 8401568476 ps
CPU time 119.9 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:40:38 PM PDT 24
Peak memory 200368 kb
Host smart-f7f6ef18-e26a-4449-8680-e963d263bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059080110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4059080110
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.997584496
Short name T375
Test name
Test status
Simulation time 224458752 ps
CPU time 10.18 seconds
Started Jul 12 05:38:19 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200308 kb
Host smart-a3dba198-1227-41a1-9f4d-ffde1c8b4421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997584496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.997584496
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2116736162
Short name T444
Test name
Test status
Simulation time 38618564996 ps
CPU time 737.35 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:50:50 PM PDT 24
Peak memory 679920 kb
Host smart-fb375dc5-e393-4b2c-af6f-946d70b2d038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116736162 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2116736162
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.83833266
Short name T281
Test name
Test status
Simulation time 450821445 ps
CPU time 12.04 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200308 kb
Host smart-f3953812-2e33-4298-a255-ed89c4fd7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83833266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.83833266
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1353410540
Short name T365
Test name
Test status
Simulation time 14854104 ps
CPU time 0.55 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:38:32 PM PDT 24
Peak memory 196200 kb
Host smart-499d4099-604c-4c95-95b3-99ca74338ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353410540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1353410540
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.472379924
Short name T240
Test name
Test status
Simulation time 6092220952 ps
CPU time 94.01 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:40:05 PM PDT 24
Peak memory 200268 kb
Host smart-fb5214c4-5f0c-40ad-97f8-209ed144da5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472379924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.472379924
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1914856431
Short name T172
Test name
Test status
Simulation time 339256153 ps
CPU time 5.14 seconds
Started Jul 12 05:38:19 PM PDT 24
Finished Jul 12 05:38:39 PM PDT 24
Peak memory 200148 kb
Host smart-62351ca5-e7b7-4e45-b553-4188ab31e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914856431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1914856431
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3867199308
Short name T171
Test name
Test status
Simulation time 7908549117 ps
CPU time 319.59 seconds
Started Jul 12 05:38:14 PM PDT 24
Finished Jul 12 05:43:51 PM PDT 24
Peak memory 638156 kb
Host smart-d460de1c-61a7-4d99-b139-af5e60c5d87e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867199308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3867199308
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2093068360
Short name T465
Test name
Test status
Simulation time 560637006 ps
CPU time 10.46 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:38:43 PM PDT 24
Peak memory 200132 kb
Host smart-3fd4e3b9-3525-4436-9eba-45dfc6762db9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093068360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2093068360
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2831807296
Short name T142
Test name
Test status
Simulation time 33139412854 ps
CPU time 107.25 seconds
Started Jul 12 05:38:24 PM PDT 24
Finished Jul 12 05:40:24 PM PDT 24
Peak memory 200276 kb
Host smart-23022a99-8ba8-4c79-b050-d1bfc471c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831807296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2831807296
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.976750898
Short name T82
Test name
Test status
Simulation time 696357143 ps
CPU time 2.48 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 200180 kb
Host smart-5cda8029-04ed-4fb4-bc31-b45d25c6a5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976750898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.976750898
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3225383053
Short name T458
Test name
Test status
Simulation time 124967640521 ps
CPU time 383.42 seconds
Started Jul 12 05:38:24 PM PDT 24
Finished Jul 12 05:45:00 PM PDT 24
Peak memory 208572 kb
Host smart-e005cbc6-e835-4e34-9317-e1175b6df1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225383053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3225383053
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2408820185
Short name T317
Test name
Test status
Simulation time 3668995594 ps
CPU time 92.19 seconds
Started Jul 12 05:38:23 PM PDT 24
Finished Jul 12 05:40:08 PM PDT 24
Peak memory 200268 kb
Host smart-4c7cac92-d6d6-4063-a507-cb0f628ee9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408820185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2408820185
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.247116626
Short name T438
Test name
Test status
Simulation time 18731079 ps
CPU time 0.58 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:38:42 PM PDT 24
Peak memory 195780 kb
Host smart-640a7cf0-1c15-4d4c-803b-4669d5bcca73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247116626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.247116626
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1470610640
Short name T461
Test name
Test status
Simulation time 1239465422 ps
CPU time 74.87 seconds
Started Jul 12 05:38:39 PM PDT 24
Finished Jul 12 05:40:02 PM PDT 24
Peak memory 200156 kb
Host smart-876b0222-fc78-4b97-a4dd-f12bb1ec97ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470610640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1470610640
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3417137734
Short name T27
Test name
Test status
Simulation time 4774749404 ps
CPU time 65.11 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:39:48 PM PDT 24
Peak memory 200248 kb
Host smart-b930883e-6aa7-42b1-8512-e61ed375a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417137734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3417137734
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2119449398
Short name T208
Test name
Test status
Simulation time 3507346948 ps
CPU time 683.97 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:50:04 PM PDT 24
Peak memory 691796 kb
Host smart-b28b9979-c151-4ef2-9ffc-59cc115999b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119449398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2119449398
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1031994294
Short name T267
Test name
Test status
Simulation time 128640036771 ps
CPU time 234.82 seconds
Started Jul 12 05:38:43 PM PDT 24
Finished Jul 12 05:42:44 PM PDT 24
Peak memory 200396 kb
Host smart-241bafd2-ffc0-4735-afe6-75c070458d03
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031994294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1031994294
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2132228495
Short name T381
Test name
Test status
Simulation time 19747482676 ps
CPU time 152.11 seconds
Started Jul 12 05:38:20 PM PDT 24
Finished Jul 12 05:41:06 PM PDT 24
Peak memory 200416 kb
Host smart-b943e8be-e020-48b4-840a-de5d4aa6ae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132228495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2132228495
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2389444004
Short name T238
Test name
Test status
Simulation time 10494579640 ps
CPU time 16.53 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:47 PM PDT 24
Peak memory 200340 kb
Host smart-fe9e8a14-788f-4f01-b096-e100081b0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389444004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2389444004
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3305991812
Short name T355
Test name
Test status
Simulation time 2183093055 ps
CPU time 22.6 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:39:05 PM PDT 24
Peak memory 200316 kb
Host smart-83765a6b-e155-4c79-be2a-08363bf11f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305991812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3305991812
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.111081407
Short name T319
Test name
Test status
Simulation time 35753380 ps
CPU time 0.58 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 196192 kb
Host smart-04ce3d4e-e45b-4bb9-a06a-ee645c2c5ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111081407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.111081407
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1376675209
Short name T528
Test name
Test status
Simulation time 1370031940 ps
CPU time 74.73 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:40:03 PM PDT 24
Peak memory 200288 kb
Host smart-29c2bd16-063c-472c-a202-dd57a42c1751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376675209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1376675209
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1003646338
Short name T4
Test name
Test status
Simulation time 8949655507 ps
CPU time 51 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 200372 kb
Host smart-93c30d92-664b-4271-9bfc-9e8bf4959a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003646338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1003646338
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.212216000
Short name T337
Test name
Test status
Simulation time 373168059 ps
CPU time 69.16 seconds
Started Jul 12 05:38:43 PM PDT 24
Finished Jul 12 05:39:59 PM PDT 24
Peak memory 401932 kb
Host smart-254f2608-f83d-4f26-8353-9565dbf34194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212216000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.212216000
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1614244200
Short name T191
Test name
Test status
Simulation time 3295183290 ps
CPU time 171.71 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:41:26 PM PDT 24
Peak memory 200392 kb
Host smart-66f15988-f951-4319-ba26-398d9276d3b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614244200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1614244200
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3372181566
Short name T314
Test name
Test status
Simulation time 5884285778 ps
CPU time 105.9 seconds
Started Jul 12 05:38:30 PM PDT 24
Finished Jul 12 05:40:26 PM PDT 24
Peak memory 200560 kb
Host smart-6c79b791-9a38-4061-b47c-bf3e2041e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372181566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3372181566
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.366139329
Short name T526
Test name
Test status
Simulation time 1017105236 ps
CPU time 11.02 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 200332 kb
Host smart-de755682-9225-4997-8e20-eb99b215e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366139329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.366139329
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3439044424
Short name T401
Test name
Test status
Simulation time 368695188555 ps
CPU time 3933.58 seconds
Started Jul 12 05:38:39 PM PDT 24
Finished Jul 12 06:44:21 PM PDT 24
Peak memory 810928 kb
Host smart-b6992084-d7a0-4f90-b46b-ce19ebfe7d99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439044424 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3439044424
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.230494669
Short name T72
Test name
Test status
Simulation time 3944629761 ps
CPU time 19 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:38:58 PM PDT 24
Peak memory 200424 kb
Host smart-181c851a-448f-4c0d-8f1c-c03a3f940a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230494669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.230494669
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3121174432
Short name T247
Test name
Test status
Simulation time 23453656 ps
CPU time 0.61 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:38:36 PM PDT 24
Peak memory 196820 kb
Host smart-aafe000e-da44-4eed-91c1-fbf677c14215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121174432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3121174432
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.966357134
Short name T289
Test name
Test status
Simulation time 4860979684 ps
CPU time 90.1 seconds
Started Jul 12 05:38:42 PM PDT 24
Finished Jul 12 05:40:19 PM PDT 24
Peak memory 200368 kb
Host smart-ece978de-6395-4c39-82e3-5c42625e95d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966357134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.966357134
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3836347154
Short name T387
Test name
Test status
Simulation time 2067450312 ps
CPU time 15.84 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:39:06 PM PDT 24
Peak memory 200324 kb
Host smart-d4616527-1bb1-4fbe-a6c4-598cfe01b57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836347154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3836347154
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3099409791
Short name T266
Test name
Test status
Simulation time 17879200250 ps
CPU time 758.52 seconds
Started Jul 12 05:38:43 PM PDT 24
Finished Jul 12 05:51:28 PM PDT 24
Peak memory 736748 kb
Host smart-052bf523-c773-4d6a-92cf-206de942a6ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099409791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3099409791
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.299254193
Short name T252
Test name
Test status
Simulation time 15854455823 ps
CPU time 71.53 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:39:54 PM PDT 24
Peak memory 200288 kb
Host smart-f5666719-48ee-4e17-a5fa-51441f43bd15
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299254193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.299254193
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.313776084
Short name T419
Test name
Test status
Simulation time 15736593330 ps
CPU time 207.84 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:42:03 PM PDT 24
Peak memory 200392 kb
Host smart-1c202ec4-367d-4e0d-85a8-1969b6187e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313776084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.313776084
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1995996252
Short name T184
Test name
Test status
Simulation time 1284009909 ps
CPU time 15.69 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 200296 kb
Host smart-667635e1-654c-4658-ac63-cf00e8b3b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995996252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1995996252
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2950961337
Short name T270
Test name
Test status
Simulation time 87354809254 ps
CPU time 1090.65 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:56:54 PM PDT 24
Peak memory 719276 kb
Host smart-e2a6c772-0464-4b00-be95-0466a9d045d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950961337 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2950961337
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3168971519
Short name T489
Test name
Test status
Simulation time 6232075368 ps
CPU time 19.73 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 200240 kb
Host smart-42b21bd3-4881-4042-bac7-1c5687025e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168971519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3168971519
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2212476891
Short name T254
Test name
Test status
Simulation time 21796621 ps
CPU time 0.59 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 196152 kb
Host smart-aef984c5-a354-435c-ada3-a6a488e2c87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212476891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2212476891
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4033206038
Short name T370
Test name
Test status
Simulation time 1143317621 ps
CPU time 15.53 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:38:12 PM PDT 24
Peak memory 200276 kb
Host smart-ec64e5b6-5834-412f-8e38-71a6b7ca71bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033206038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4033206038
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.172381677
Short name T257
Test name
Test status
Simulation time 1664280370 ps
CPU time 17.27 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 200288 kb
Host smart-3d589a92-c327-4aee-bc27-99519a19054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172381677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.172381677
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3726965156
Short name T524
Test name
Test status
Simulation time 4534027451 ps
CPU time 430.78 seconds
Started Jul 12 05:37:42 PM PDT 24
Finished Jul 12 05:44:54 PM PDT 24
Peak memory 648876 kb
Host smart-0df5770b-b6cc-4e44-9e50-dbcc60a45b01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726965156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3726965156
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1125834565
Short name T42
Test name
Test status
Simulation time 3082840414 ps
CPU time 170.2 seconds
Started Jul 12 05:37:47 PM PDT 24
Finished Jul 12 05:40:50 PM PDT 24
Peak memory 200340 kb
Host smart-7f4d5397-4201-4c38-b161-120fb9c0ca9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125834565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1125834565
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.434397948
Short name T350
Test name
Test status
Simulation time 27313233257 ps
CPU time 205.41 seconds
Started Jul 12 05:38:04 PM PDT 24
Finished Jul 12 05:41:51 PM PDT 24
Peak memory 216636 kb
Host smart-ac917521-873a-4b89-a86f-0d25fe3bd3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434397948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.434397948
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1547466795
Short name T46
Test name
Test status
Simulation time 396948538 ps
CPU time 0.96 seconds
Started Jul 12 05:38:08 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 219416 kb
Host smart-e67805d8-1359-4a2e-b7af-9a3fd3f30e7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547466795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1547466795
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3718313510
Short name T451
Test name
Test status
Simulation time 1844903463 ps
CPU time 6.99 seconds
Started Jul 12 05:38:05 PM PDT 24
Finished Jul 12 05:38:33 PM PDT 24
Peak memory 200176 kb
Host smart-5f385332-4479-4b93-8546-69226fccab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718313510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3718313510
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3624097256
Short name T67
Test name
Test status
Simulation time 311515931861 ps
CPU time 2890.74 seconds
Started Jul 12 05:38:01 PM PDT 24
Finished Jul 12 06:26:34 PM PDT 24
Peak memory 780104 kb
Host smart-721db5b8-b13a-40a4-8f18-0c0c135f8fda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624097256 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3624097256
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3329664187
Short name T202
Test name
Test status
Simulation time 3277182749 ps
CPU time 65.72 seconds
Started Jul 12 05:37:45 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 200320 kb
Host smart-8c91defb-229e-43b4-a0ee-8568b683ad31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3329664187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3329664187
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.448143081
Short name T187
Test name
Test status
Simulation time 1756741593 ps
CPU time 65.98 seconds
Started Jul 12 05:38:08 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 200284 kb
Host smart-4d1fee65-23b3-4c32-9cbd-37b529bbbf57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=448143081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.448143081
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3653479099
Short name T178
Test name
Test status
Simulation time 25882512302 ps
CPU time 111.52 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:39:47 PM PDT 24
Peak memory 200352 kb
Host smart-1198bdb3-d4ec-483a-befc-247ef25443c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3653479099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3653479099
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3610984226
Short name T497
Test name
Test status
Simulation time 72362006479 ps
CPU time 684.87 seconds
Started Jul 12 05:38:06 PM PDT 24
Finished Jul 12 05:49:51 PM PDT 24
Peak memory 200280 kb
Host smart-7f743261-e9b6-40e1-bfc8-700226cba383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3610984226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3610984226
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2120382179
Short name T426
Test name
Test status
Simulation time 444067744190 ps
CPU time 2677.04 seconds
Started Jul 12 05:37:42 PM PDT 24
Finished Jul 12 06:22:22 PM PDT 24
Peak memory 216040 kb
Host smart-e7df45e5-51a0-46fe-9c13-a4b0002036e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2120382179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2120382179
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2398515920
Short name T3
Test name
Test status
Simulation time 41186680275 ps
CPU time 2107.74 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 06:13:38 PM PDT 24
Peak memory 215884 kb
Host smart-76c5522d-f122-46fd-8aea-7a477b743d6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2398515920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2398515920
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.244899837
Short name T75
Test name
Test status
Simulation time 1100239258 ps
CPU time 5.11 seconds
Started Jul 12 05:38:01 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 200276 kb
Host smart-88e28589-dfdb-4d27-ba01-6262a87b3678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244899837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.244899837
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4181662588
Short name T290
Test name
Test status
Simulation time 66088451 ps
CPU time 0.62 seconds
Started Jul 12 05:38:30 PM PDT 24
Finished Jul 12 05:38:41 PM PDT 24
Peak memory 196388 kb
Host smart-d5f0d2e7-054e-40bd-b2e1-bbaf15ff20ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181662588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4181662588
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2283023642
Short name T316
Test name
Test status
Simulation time 1458674619 ps
CPU time 79.48 seconds
Started Jul 12 05:38:30 PM PDT 24
Finished Jul 12 05:40:00 PM PDT 24
Peak memory 200280 kb
Host smart-11c2d3c6-89e8-41f7-bb18-6b7fbfcfa326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283023642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2283023642
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.188766516
Short name T385
Test name
Test status
Simulation time 1106156357 ps
CPU time 59.11 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 200316 kb
Host smart-fcb2268f-2b85-441e-b424-b2772a9ba8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188766516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.188766516
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.910356866
Short name T527
Test name
Test status
Simulation time 175765395 ps
CPU time 7 seconds
Started Jul 12 05:38:29 PM PDT 24
Finished Jul 12 05:38:47 PM PDT 24
Peak memory 200340 kb
Host smart-b74b838f-e534-4211-b5b3-39bfbab1cec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910356866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.910356866
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2561206689
Short name T338
Test name
Test status
Simulation time 63470037551 ps
CPU time 193.56 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:42:04 PM PDT 24
Peak memory 200372 kb
Host smart-86236c4f-2c53-4c38-b132-5db643a89112
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561206689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2561206689
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2021366808
Short name T152
Test name
Test status
Simulation time 1149848220 ps
CPU time 64.89 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:39:50 PM PDT 24
Peak memory 200332 kb
Host smart-ad32b2e4-e319-4a44-90d7-ebce8db77a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021366808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2021366808
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3922225307
Short name T499
Test name
Test status
Simulation time 184487094 ps
CPU time 7.9 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:38:44 PM PDT 24
Peak memory 200256 kb
Host smart-ca3783a6-1e4d-4cb1-8a30-aeaaf8565b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922225307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3922225307
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2531790567
Short name T480
Test name
Test status
Simulation time 113857583406 ps
CPU time 3465.82 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 807940 kb
Host smart-0172a53d-e1b1-40be-8bd9-e4d735f1232d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531790567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2531790567
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2730047357
Short name T279
Test name
Test status
Simulation time 3662003923 ps
CPU time 83.07 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:39:59 PM PDT 24
Peak memory 200412 kb
Host smart-fcdbe2f7-9feb-4f43-8658-a6aba5ef3d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730047357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2730047357
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1934311393
Short name T227
Test name
Test status
Simulation time 15929384 ps
CPU time 0.58 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:38:46 PM PDT 24
Peak memory 196204 kb
Host smart-f36a2308-5ad9-4221-a6b5-e323b3c5b672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934311393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1934311393
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2119229196
Short name T219
Test name
Test status
Simulation time 102763477 ps
CPU time 5.77 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 200232 kb
Host smart-f9aea599-b227-4b80-8847-a675628b7d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119229196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2119229196
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2707151854
Short name T443
Test name
Test status
Simulation time 1447201662 ps
CPU time 44.11 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 200300 kb
Host smart-827d01c6-676c-4659-84ba-0e16c04307a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707151854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2707151854
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1985013067
Short name T255
Test name
Test status
Simulation time 89368513277 ps
CPU time 727.84 seconds
Started Jul 12 05:38:33 PM PDT 24
Finished Jul 12 05:50:50 PM PDT 24
Peak memory 721896 kb
Host smart-1f735604-14b0-46e4-ba9c-6ed43f31034f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985013067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1985013067
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3469212265
Short name T99
Test name
Test status
Simulation time 2597341506 ps
CPU time 19.48 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:39:01 PM PDT 24
Peak memory 200504 kb
Host smart-5567b6f1-688a-4760-a4dd-a88314134ae8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469212265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3469212265
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1342450347
Short name T454
Test name
Test status
Simulation time 108766838495 ps
CPU time 177.49 seconds
Started Jul 12 05:38:42 PM PDT 24
Finished Jul 12 05:41:46 PM PDT 24
Peak memory 208492 kb
Host smart-3d982073-0c38-47aa-ae17-3dee31e71c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342450347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1342450347
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3919340011
Short name T39
Test name
Test status
Simulation time 196492101 ps
CPU time 8.41 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:38:57 PM PDT 24
Peak memory 200264 kb
Host smart-3f5c53f1-1092-4a04-8d4f-b402eadd228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919340011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3919340011
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.207521182
Short name T441
Test name
Test status
Simulation time 13579414963 ps
CPU time 681.23 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:50:03 PM PDT 24
Peak memory 701428 kb
Host smart-eff9d066-6276-4b62-bd97-0882f429caba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207521182 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.207521182
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1816238611
Short name T207
Test name
Test status
Simulation time 3013865198 ps
CPU time 20.77 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:39:11 PM PDT 24
Peak memory 200344 kb
Host smart-fbcb4ecd-8624-4bfe-9458-4095c4a2cba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816238611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1816238611
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.89734325
Short name T285
Test name
Test status
Simulation time 32929466 ps
CPU time 0.57 seconds
Started Jul 12 05:38:25 PM PDT 24
Finished Jul 12 05:38:38 PM PDT 24
Peak memory 195836 kb
Host smart-75542d8a-799a-496c-91ba-65ccc9de32b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89734325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.89734325
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1737370852
Short name T352
Test name
Test status
Simulation time 1220657284 ps
CPU time 68.91 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:39:53 PM PDT 24
Peak memory 200164 kb
Host smart-5cc1892a-37ee-4bce-bae5-fe828c9b2a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737370852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1737370852
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2114786082
Short name T147
Test name
Test status
Simulation time 2380971972 ps
CPU time 51.29 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 200396 kb
Host smart-814db198-f870-4a35-b758-d1f5eb093190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114786082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2114786082
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.95904545
Short name T165
Test name
Test status
Simulation time 5442866434 ps
CPU time 963.27 seconds
Started Jul 12 05:38:29 PM PDT 24
Finished Jul 12 05:54:44 PM PDT 24
Peak memory 720792 kb
Host smart-940ecbe3-fbad-4bc5-8f50-cec85d6d6b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95904545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.95904545
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1678938424
Short name T351
Test name
Test status
Simulation time 25736878300 ps
CPU time 103.65 seconds
Started Jul 12 05:38:26 PM PDT 24
Finished Jul 12 05:40:22 PM PDT 24
Peak memory 200380 kb
Host smart-8cd6c547-c33f-41f6-a1f7-344f2ece9f11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678938424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1678938424
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1697581196
Short name T232
Test name
Test status
Simulation time 7526812128 ps
CPU time 66.37 seconds
Started Jul 12 05:38:21 PM PDT 24
Finished Jul 12 05:39:41 PM PDT 24
Peak memory 200340 kb
Host smart-791d1d25-c5a2-47ab-94c8-6fd3ac1ef4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697581196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1697581196
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1676346421
Short name T486
Test name
Test status
Simulation time 742598381 ps
CPU time 6.03 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:38:53 PM PDT 24
Peak memory 200252 kb
Host smart-29073cd2-87a3-415f-a833-c890f7347b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676346421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1676346421
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1392864495
Short name T347
Test name
Test status
Simulation time 366124154684 ps
CPU time 2335.42 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 06:17:41 PM PDT 24
Peak memory 810380 kb
Host smart-430c37a8-9509-4d6a-a34b-4a2ecded9931
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392864495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1392864495
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3108965056
Short name T7
Test name
Test status
Simulation time 1468388558 ps
CPU time 19.15 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:39:05 PM PDT 24
Peak memory 200296 kb
Host smart-cca36f14-e057-4774-8b61-1efcf27c0e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108965056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3108965056
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1774040498
Short name T522
Test name
Test status
Simulation time 20716422 ps
CPU time 0.56 seconds
Started Jul 12 05:38:42 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 196880 kb
Host smart-a2f0c6d8-8316-4788-9e11-349cd32753c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774040498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1774040498
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.260034559
Short name T330
Test name
Test status
Simulation time 1968632357 ps
CPU time 92.96 seconds
Started Jul 12 05:38:29 PM PDT 24
Finished Jul 12 05:40:13 PM PDT 24
Peak memory 200292 kb
Host smart-f3bb6040-5f00-4377-b83c-6b23e99431d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260034559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.260034559
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.164314904
Short name T523
Test name
Test status
Simulation time 6081200524 ps
CPU time 26.02 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 05:39:18 PM PDT 24
Peak memory 200376 kb
Host smart-208409d2-b221-464d-864a-c511cbca411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164314904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.164314904
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1072368383
Short name T366
Test name
Test status
Simulation time 25885945 ps
CPU time 0.86 seconds
Started Jul 12 05:38:30 PM PDT 24
Finished Jul 12 05:38:41 PM PDT 24
Peak memory 200088 kb
Host smart-0ed20ad5-2727-43a9-a8ef-730f19ca4a8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072368383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1072368383
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2277355884
Short name T29
Test name
Test status
Simulation time 26461726906 ps
CPU time 169.83 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:41:33 PM PDT 24
Peak memory 200392 kb
Host smart-582a89ba-fc8f-4a90-844b-2237262fb0d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277355884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2277355884
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_smoke.4096201295
Short name T484
Test name
Test status
Simulation time 435751075 ps
CPU time 10.09 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 200320 kb
Host smart-f1ab1059-fc90-417e-8963-92a324abbf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096201295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4096201295
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3312301521
Short name T453
Test name
Test status
Simulation time 169721419022 ps
CPU time 1056.2 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:56:24 PM PDT 24
Peak memory 722836 kb
Host smart-b25a5a67-e6ad-4e7c-8e8a-bd1afcfa5203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312301521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3312301521
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2317659017
Short name T62
Test name
Test status
Simulation time 1565817625 ps
CPU time 22.36 seconds
Started Jul 12 05:38:29 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 200352 kb
Host smart-dfccfa2d-dfbc-4d1a-a67f-0f12cb9592c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317659017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2317659017
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3911435963
Short name T386
Test name
Test status
Simulation time 42104165 ps
CPU time 0.57 seconds
Started Jul 12 05:38:39 PM PDT 24
Finished Jul 12 05:38:47 PM PDT 24
Peak memory 196088 kb
Host smart-c8ae1752-8c9d-4bf5-b4f7-b5d743d8fae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911435963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3911435963
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3631596381
Short name T37
Test name
Test status
Simulation time 2919292475 ps
CPU time 86.07 seconds
Started Jul 12 05:38:26 PM PDT 24
Finished Jul 12 05:40:05 PM PDT 24
Peak memory 208608 kb
Host smart-243f8da1-98ff-4263-b8b7-b8f7fbd5a890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631596381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3631596381
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2794805657
Short name T479
Test name
Test status
Simulation time 5473145498 ps
CPU time 48.88 seconds
Started Jul 12 05:38:24 PM PDT 24
Finished Jul 12 05:39:26 PM PDT 24
Peak memory 200360 kb
Host smart-2b7da78e-8965-41a6-9754-bf8589902eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794805657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2794805657
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2212317841
Short name T447
Test name
Test status
Simulation time 14927350565 ps
CPU time 1424.12 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 06:02:24 PM PDT 24
Peak memory 738992 kb
Host smart-9cb140d7-a1e6-405d-bda9-1f08bd858370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212317841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2212317841
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.4145685526
Short name T218
Test name
Test status
Simulation time 1832610855 ps
CPU time 34.39 seconds
Started Jul 12 05:38:35 PM PDT 24
Finished Jul 12 05:39:18 PM PDT 24
Peak memory 200136 kb
Host smart-f05c4d2a-4eb4-44d0-84e9-0ad8a1c4d0a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145685526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4145685526
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3832712516
Short name T262
Test name
Test status
Simulation time 6904584776 ps
CPU time 60.56 seconds
Started Jul 12 05:38:30 PM PDT 24
Finished Jul 12 05:39:41 PM PDT 24
Peak memory 200600 kb
Host smart-8b586346-6daf-410b-b247-4593058abcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832712516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3832712516
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3999383436
Short name T286
Test name
Test status
Simulation time 1096526754 ps
CPU time 10.82 seconds
Started Jul 12 05:38:46 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 200160 kb
Host smart-89373e3c-4dbb-4e71-8d17-ae054561f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999383436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3999383436
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2940332540
Short name T210
Test name
Test status
Simulation time 66497125 ps
CPU time 3.71 seconds
Started Jul 12 05:38:33 PM PDT 24
Finished Jul 12 05:38:46 PM PDT 24
Peak memory 200292 kb
Host smart-043eec6b-fc10-474e-a906-4125b4b7fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940332540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2940332540
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2268697348
Short name T421
Test name
Test status
Simulation time 13517440 ps
CPU time 0.59 seconds
Started Jul 12 05:38:39 PM PDT 24
Finished Jul 12 05:38:47 PM PDT 24
Peak memory 196188 kb
Host smart-7dde75bb-496e-425f-8ced-2aad207bbb1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268697348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2268697348
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1929124115
Short name T340
Test name
Test status
Simulation time 1183511559 ps
CPU time 66.18 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:39:53 PM PDT 24
Peak memory 200292 kb
Host smart-4000754e-55d7-4a62-9306-d27d8f9e41b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929124115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1929124115
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3417939273
Short name T148
Test name
Test status
Simulation time 6003814638 ps
CPU time 43.73 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:39:25 PM PDT 24
Peak memory 208508 kb
Host smart-a7afed7b-55cf-4206-9cbf-a5779e449732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417939273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3417939273
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1393961851
Short name T516
Test name
Test status
Simulation time 1766256407 ps
CPU time 75.41 seconds
Started Jul 12 05:38:50 PM PDT 24
Finished Jul 12 05:40:08 PM PDT 24
Peak memory 346100 kb
Host smart-e7d96186-54f4-4d9d-b998-1bbd60c60f3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393961851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1393961851
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1095640855
Short name T162
Test name
Test status
Simulation time 7908099622 ps
CPU time 110.71 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:40:30 PM PDT 24
Peak memory 200276 kb
Host smart-bab7bc6c-5013-4c6a-a864-c1b145012b52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095640855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1095640855
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3203348012
Short name T393
Test name
Test status
Simulation time 507667834 ps
CPU time 4.22 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:38:43 PM PDT 24
Peak memory 200176 kb
Host smart-57505625-d73e-41e3-af6c-b371aa18958f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203348012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3203348012
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1285931385
Short name T174
Test name
Test status
Simulation time 143657910 ps
CPU time 6.26 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:38:47 PM PDT 24
Peak memory 200304 kb
Host smart-865ca2f1-7f17-4286-8348-2e1bf8b0c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285931385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1285931385
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.925525272
Short name T70
Test name
Test status
Simulation time 440133195963 ps
CPU time 3335.1 seconds
Started Jul 12 05:38:47 PM PDT 24
Finished Jul 12 06:34:27 PM PDT 24
Peak memory 802748 kb
Host smart-538d9ea5-9523-4f35-b520-d2b7248faef1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925525272 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.925525272
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.553541665
Short name T372
Test name
Test status
Simulation time 704894484 ps
CPU time 13.36 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:38:54 PM PDT 24
Peak memory 200272 kb
Host smart-35b36cc6-e4a4-40bb-913a-1dd181167619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553541665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.553541665
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.242961378
Short name T195
Test name
Test status
Simulation time 13613952 ps
CPU time 0.59 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:38:51 PM PDT 24
Peak memory 195164 kb
Host smart-6bda87ca-476a-4ebb-8b58-c7ffa225ffaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242961378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.242961378
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3629390350
Short name T498
Test name
Test status
Simulation time 787192600 ps
CPU time 21.82 seconds
Started Jul 12 05:38:46 PM PDT 24
Finished Jul 12 05:39:13 PM PDT 24
Peak memory 200276 kb
Host smart-4fbe7acf-c516-4ad2-974e-320989c2df5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629390350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3629390350
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1375932216
Short name T145
Test name
Test status
Simulation time 2747145210 ps
CPU time 65.43 seconds
Started Jul 12 05:38:29 PM PDT 24
Finished Jul 12 05:39:46 PM PDT 24
Peak memory 200364 kb
Host smart-043628b8-ea92-40a2-bc27-25f4836dcb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375932216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1375932216
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1438802153
Short name T417
Test name
Test status
Simulation time 1903101864 ps
CPU time 327.71 seconds
Started Jul 12 05:38:21 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 674436 kb
Host smart-6f5f95ba-b4d4-4079-8407-f85ee1b69fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438802153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1438802153
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.757803272
Short name T383
Test name
Test status
Simulation time 25673132749 ps
CPU time 209.22 seconds
Started Jul 12 05:38:22 PM PDT 24
Finished Jul 12 05:42:05 PM PDT 24
Peak memory 200316 kb
Host smart-da4ca1e4-d4f1-4619-ba15-0893a1187f8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757803272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.757803272
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.263076223
Short name T302
Test name
Test status
Simulation time 16145047921 ps
CPU time 214.34 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:42:23 PM PDT 24
Peak memory 216784 kb
Host smart-6d6c244c-f9cc-4c76-b0ab-46c2d75ca343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263076223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.263076223
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3291921747
Short name T179
Test name
Test status
Simulation time 974530013 ps
CPU time 17.3 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 05:38:57 PM PDT 24
Peak memory 200292 kb
Host smart-e041ec80-31e4-4d6b-a2d8-7a856fc3c7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291921747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3291921747
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2255097980
Short name T28
Test name
Test status
Simulation time 191907558754 ps
CPU time 2475.68 seconds
Started Jul 12 05:38:27 PM PDT 24
Finished Jul 12 06:19:55 PM PDT 24
Peak memory 769444 kb
Host smart-21a3e42c-861d-4342-9f5b-31e61edbb543
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255097980 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2255097980
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3517027138
Short name T278
Test name
Test status
Simulation time 43139275716 ps
CPU time 139.25 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 05:41:11 PM PDT 24
Peak memory 200368 kb
Host smart-6b755b17-6eac-4171-9d05-64065d2127b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517027138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3517027138
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.628727001
Short name T429
Test name
Test status
Simulation time 83590895 ps
CPU time 0.63 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 195828 kb
Host smart-56c160ba-536f-47f4-8ec5-e625489f6cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628727001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.628727001
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.419059570
Short name T455
Test name
Test status
Simulation time 1061973397 ps
CPU time 63.61 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:39:45 PM PDT 24
Peak memory 200328 kb
Host smart-4e8be25f-5a3b-4323-96a4-383795262f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419059570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.419059570
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4102024409
Short name T432
Test name
Test status
Simulation time 159611084 ps
CPU time 8.43 seconds
Started Jul 12 05:38:42 PM PDT 24
Finished Jul 12 05:38:57 PM PDT 24
Peak memory 200296 kb
Host smart-8c6a4669-23c9-4bce-ba40-9d95aa5c972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102024409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4102024409
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3846166482
Short name T234
Test name
Test status
Simulation time 9506416883 ps
CPU time 1951.4 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 06:11:14 PM PDT 24
Peak memory 810572 kb
Host smart-701ad666-3742-474f-9d8c-e7b544dc6fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846166482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3846166482
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2002132059
Short name T472
Test name
Test status
Simulation time 3311845462 ps
CPU time 21.16 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:39:12 PM PDT 24
Peak memory 200260 kb
Host smart-e197d2d2-9dee-4d78-87ff-cd54fd7a2017
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002132059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2002132059
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3981885781
Short name T272
Test name
Test status
Simulation time 4199522167 ps
CPU time 19.9 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 200396 kb
Host smart-e47c994b-720d-42e2-9020-05e320bbbf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981885781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3981885781
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.959059177
Short name T376
Test name
Test status
Simulation time 573733638 ps
CPU time 13.7 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 05:39:06 PM PDT 24
Peak memory 200316 kb
Host smart-c82f0a5d-7e69-4c30-b59b-38857ee09597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959059177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.959059177
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.583519845
Short name T456
Test name
Test status
Simulation time 1924952451 ps
CPU time 6.69 seconds
Started Jul 12 05:38:39 PM PDT 24
Finished Jul 12 05:38:53 PM PDT 24
Peak memory 200252 kb
Host smart-de8f1161-67c6-4fae-aa47-3bbe20d2ec14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583519845 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.583519845
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2724506143
Short name T60
Test name
Test status
Simulation time 8980635357 ps
CPU time 95.16 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:40:25 PM PDT 24
Peak memory 200224 kb
Host smart-722985c9-7202-44f9-bbbd-10811758a955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724506143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2724506143
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.784862233
Short name T44
Test name
Test status
Simulation time 12068479 ps
CPU time 0.55 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 195708 kb
Host smart-43cd18a6-547c-4437-a53c-08a9f388413d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784862233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.784862233
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1620654249
Short name T163
Test name
Test status
Simulation time 2672048371 ps
CPU time 25.89 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:39:16 PM PDT 24
Peak memory 200344 kb
Host smart-377e8259-205b-4bea-8988-9d6434aaa523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620654249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1620654249
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1305186566
Short name T35
Test name
Test status
Simulation time 2037716228 ps
CPU time 23.89 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:39:08 PM PDT 24
Peak memory 200164 kb
Host smart-e3637905-da95-4c17-99b2-70fae6134adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305186566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1305186566
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1179411410
Short name T395
Test name
Test status
Simulation time 1903424501 ps
CPU time 39.86 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:39:26 PM PDT 24
Peak memory 236548 kb
Host smart-aab47ed5-0c52-40a1-80d1-eb2cbc8a592c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179411410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1179411410
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3289434986
Short name T469
Test name
Test status
Simulation time 714264470 ps
CPU time 40.75 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:39:25 PM PDT 24
Peak memory 200324 kb
Host smart-5b27a2b0-9e16-49bc-9614-1df9a0a34ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289434986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3289434986
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1013411575
Short name T329
Test name
Test status
Simulation time 1941601332 ps
CPU time 33.06 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:39:13 PM PDT 24
Peak memory 200328 kb
Host smart-9198a6a6-61e2-402c-9bdb-e37de3fced0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013411575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1013411575
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1753103151
Short name T510
Test name
Test status
Simulation time 586004492 ps
CPU time 13.56 seconds
Started Jul 12 05:38:39 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 200324 kb
Host smart-e58cdbb2-de68-48f5-b56d-1643a63be020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753103151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1753103151
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2934157725
Short name T85
Test name
Test status
Simulation time 30418056263 ps
CPU time 574.29 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:48:19 PM PDT 24
Peak memory 431540 kb
Host smart-ca7ec27c-a5d8-4d2b-a535-6c6e8a5e27da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934157725 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2934157725
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2768699779
Short name T128
Test name
Test status
Simulation time 45775700133 ps
CPU time 139.63 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:41:05 PM PDT 24
Peak memory 200228 kb
Host smart-4c6f5945-f228-4224-9b34-960ecf31a896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768699779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2768699779
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.375627356
Short name T324
Test name
Test status
Simulation time 30729493 ps
CPU time 0.59 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 05:38:53 PM PDT 24
Peak memory 195668 kb
Host smart-f388b626-3b2f-41de-868b-f739995cd1e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375627356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.375627356
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1636132173
Short name T31
Test name
Test status
Simulation time 68118217 ps
CPU time 4.27 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:38:54 PM PDT 24
Peak memory 200136 kb
Host smart-0c04db8d-4219-40b1-9dec-2d4e317cd995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636132173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1636132173
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3728740160
Short name T431
Test name
Test status
Simulation time 3018625714 ps
CPU time 27.5 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:39:18 PM PDT 24
Peak memory 208428 kb
Host smart-7034c614-00ee-42f4-9e86-e0b5e583fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728740160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3728740160
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1886684339
Short name T492
Test name
Test status
Simulation time 7591403411 ps
CPU time 701.28 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:50:31 PM PDT 24
Peak memory 682164 kb
Host smart-13d51f0a-44e6-4cc0-81d5-7e1a74fe85e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886684339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1886684339
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.404560943
Short name T325
Test name
Test status
Simulation time 5263961064 ps
CPU time 145.25 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:41:15 PM PDT 24
Peak memory 200336 kb
Host smart-5e01d18f-c349-4425-8409-bf3b8c9225fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404560943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.404560943
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1936086675
Short name T423
Test name
Test status
Simulation time 49779765668 ps
CPU time 150.3 seconds
Started Jul 12 05:38:34 PM PDT 24
Finished Jul 12 05:41:12 PM PDT 24
Peak memory 200360 kb
Host smart-b3f10b4d-df1b-45ac-9bb3-cb3ef685667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936086675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1936086675
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1225262314
Short name T349
Test name
Test status
Simulation time 133464411 ps
CPU time 5.57 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:38:57 PM PDT 24
Peak memory 200340 kb
Host smart-c8cd0e8a-d020-441f-9b66-45c162531c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225262314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1225262314
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.714717581
Short name T504
Test name
Test status
Simulation time 48876610264 ps
CPU time 871.03 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:53:13 PM PDT 24
Peak memory 401384 kb
Host smart-d27d72fc-daa4-4ae7-a509-b5ce92fa7105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714717581 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.714717581
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2089322967
Short name T427
Test name
Test status
Simulation time 11904781757 ps
CPU time 52.41 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 200364 kb
Host smart-50cdc80b-fde6-403f-ac0d-c40455cffd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089322967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2089322967
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2044387988
Short name T55
Test name
Test status
Simulation time 61189528 ps
CPU time 0.58 seconds
Started Jul 12 05:37:56 PM PDT 24
Finished Jul 12 05:38:20 PM PDT 24
Peak memory 196180 kb
Host smart-6949e803-a601-4d6a-be5a-a3c852070dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044387988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2044387988
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1611717641
Short name T265
Test name
Test status
Simulation time 863274828 ps
CPU time 12.28 seconds
Started Jul 12 05:37:51 PM PDT 24
Finished Jul 12 05:38:21 PM PDT 24
Peak memory 200284 kb
Host smart-50d7ff05-39d8-47f2-b7ae-4d81fb46d7b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611717641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1611717641
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3137088267
Short name T470
Test name
Test status
Simulation time 2321974758 ps
CPU time 9.93 seconds
Started Jul 12 05:37:51 PM PDT 24
Finished Jul 12 05:38:20 PM PDT 24
Peak memory 200384 kb
Host smart-f106531c-cdc8-4287-bf55-746eda68c502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137088267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3137088267
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3781697933
Short name T168
Test name
Test status
Simulation time 319621527 ps
CPU time 24.38 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:39 PM PDT 24
Peak memory 248020 kb
Host smart-f42b06cc-887f-4037-8c61-11991c7cbb8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781697933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3781697933
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2785884944
Short name T348
Test name
Test status
Simulation time 21068023504 ps
CPU time 197.2 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:41:34 PM PDT 24
Peak memory 200296 kb
Host smart-f35f8faf-e510-49fd-b43f-cf595607ac09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785884944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2785884944
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4119327195
Short name T354
Test name
Test status
Simulation time 16245328301 ps
CPU time 197.12 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:41:32 PM PDT 24
Peak memory 216924 kb
Host smart-12614f7f-82e1-417e-b648-b829bae3e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119327195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4119327195
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.1464471150
Short name T139
Test name
Test status
Simulation time 1450209271 ps
CPU time 6.74 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:38:02 PM PDT 24
Peak memory 200312 kb
Host smart-8ea475fb-24cc-45a3-83b0-13be6b261cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464471150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1464471150
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1701400513
Short name T459
Test name
Test status
Simulation time 79478162590 ps
CPU time 3093.61 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 06:29:50 PM PDT 24
Peak memory 767536 kb
Host smart-04348302-c790-4306-b293-13fa6c31b3ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701400513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1701400513
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.658361415
Short name T396
Test name
Test status
Simulation time 7085278147 ps
CPU time 79.67 seconds
Started Jul 12 05:38:02 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 200204 kb
Host smart-e4a904e4-2f43-4e9c-9457-5e92d49e49bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=658361415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.658361415
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.857317579
Short name T61
Test name
Test status
Simulation time 28359299052 ps
CPU time 107.24 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:40:07 PM PDT 24
Peak memory 200256 kb
Host smart-5d47fb60-aeea-4648-8da6-26f520ba75e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=857317579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.857317579
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1526475496
Short name T424
Test name
Test status
Simulation time 36787289289 ps
CPU time 89.45 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:39:46 PM PDT 24
Peak memory 200344 kb
Host smart-69dc4df6-179f-4bd3-b26d-4dd3536de43b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1526475496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1526475496
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.4220160562
Short name T241
Test name
Test status
Simulation time 11304686713 ps
CPU time 601.12 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 05:48:29 PM PDT 24
Peak memory 200316 kb
Host smart-fb924131-1bae-4082-92d9-8f0c1fe9c5ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4220160562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.4220160562
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1451344307
Short name T530
Test name
Test status
Simulation time 273176767810 ps
CPU time 2308.58 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 06:16:59 PM PDT 24
Peak memory 216468 kb
Host smart-8b8a91c9-7edd-4fc3-bac6-75ca341c4c4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1451344307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1451344307
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1323394818
Short name T449
Test name
Test status
Simulation time 369256112022 ps
CPU time 2137.44 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 06:14:05 PM PDT 24
Peak memory 215752 kb
Host smart-8e13db22-928c-4113-a5f5-c3d394b43578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1323394818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1323394818
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1640428029
Short name T416
Test name
Test status
Simulation time 207625091 ps
CPU time 12.05 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:38:26 PM PDT 24
Peak memory 200288 kb
Host smart-0dbfbcfb-458c-46ef-8819-213035574af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640428029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1640428029
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2341780817
Short name T473
Test name
Test status
Simulation time 67483620 ps
CPU time 0.59 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 196196 kb
Host smart-1162a45d-d0c8-4d29-9289-35ecdf6e87b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341780817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2341780817
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3258771389
Short name T283
Test name
Test status
Simulation time 1649085775 ps
CPU time 92.45 seconds
Started Jul 12 05:38:32 PM PDT 24
Finished Jul 12 05:40:14 PM PDT 24
Peak memory 200288 kb
Host smart-2eab0d4f-194e-4509-a80c-87551f7b437f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258771389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3258771389
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4248108859
Short name T300
Test name
Test status
Simulation time 25948389237 ps
CPU time 67.72 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:39:54 PM PDT 24
Peak memory 200408 kb
Host smart-6a4ec96b-d5ab-4672-8719-a7382e55ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248108859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4248108859
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2767898090
Short name T309
Test name
Test status
Simulation time 412111135 ps
CPU time 78.53 seconds
Started Jul 12 05:38:36 PM PDT 24
Finished Jul 12 05:40:03 PM PDT 24
Peak memory 408524 kb
Host smart-03495c28-44a7-4474-9ec6-10a8fd962b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767898090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2767898090
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1279910176
Short name T334
Test name
Test status
Simulation time 2556836774 ps
CPU time 145.08 seconds
Started Jul 12 05:38:28 PM PDT 24
Finished Jul 12 05:41:05 PM PDT 24
Peak memory 200248 kb
Host smart-e8b6bd2e-78df-4cbf-b120-d5b450257164
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279910176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1279910176
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3646975638
Short name T308
Test name
Test status
Simulation time 188271833 ps
CPU time 10.41 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:39:01 PM PDT 24
Peak memory 200304 kb
Host smart-cc43c650-cafb-4932-9fa2-e53d8ce0498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646975638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3646975638
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2722045527
Short name T321
Test name
Test status
Simulation time 150241010 ps
CPU time 2.32 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:38:52 PM PDT 24
Peak memory 200168 kb
Host smart-8ef39956-fca9-4d8d-a8f6-f0f7741b704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722045527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2722045527
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1893092771
Short name T182
Test name
Test status
Simulation time 19623311443 ps
CPU time 134.66 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:40:56 PM PDT 24
Peak memory 200360 kb
Host smart-0300d53b-ec54-40ed-a17a-18a8050170dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893092771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1893092771
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1435113330
Short name T293
Test name
Test status
Simulation time 38163549 ps
CPU time 0.59 seconds
Started Jul 12 05:38:38 PM PDT 24
Finished Jul 12 05:38:46 PM PDT 24
Peak memory 195832 kb
Host smart-7f64126a-9240-4a57-92d0-e5f408d39a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435113330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1435113330
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.98474953
Short name T17
Test name
Test status
Simulation time 7206823473 ps
CPU time 99.96 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:40:27 PM PDT 24
Peak memory 200372 kb
Host smart-c93c3d7c-dc8b-4659-9fec-5534abe328c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98474953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.98474953
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3865252440
Short name T357
Test name
Test status
Simulation time 463221918 ps
CPU time 6.62 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:38:55 PM PDT 24
Peak memory 200296 kb
Host smart-4d83545d-ed7a-4e94-bafe-6b05c241e6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865252440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3865252440
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2647799462
Short name T408
Test name
Test status
Simulation time 8459005265 ps
CPU time 984.15 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:55:11 PM PDT 24
Peak memory 728476 kb
Host smart-790b89cd-31d4-4be7-befb-8ec55de5c15b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647799462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2647799462
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3877475199
Short name T158
Test name
Test status
Simulation time 3320229125 ps
CPU time 186.26 seconds
Started Jul 12 05:38:47 PM PDT 24
Finished Jul 12 05:41:58 PM PDT 24
Peak memory 200348 kb
Host smart-c9d8aa94-ffd7-4ef0-a9d5-5b09dc6ad688
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877475199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3877475199
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1672055313
Short name T276
Test name
Test status
Simulation time 9897625357 ps
CPU time 121.01 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:40:49 PM PDT 24
Peak memory 200216 kb
Host smart-4f290d14-8960-4e2e-912e-09217e232413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672055313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1672055313
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2267508063
Short name T129
Test name
Test status
Simulation time 307005430 ps
CPU time 5.54 seconds
Started Jul 12 05:38:43 PM PDT 24
Finished Jul 12 05:38:55 PM PDT 24
Peak memory 200360 kb
Host smart-73c6b799-5b96-4af0-8755-626854dd42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267508063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2267508063
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1359163499
Short name T90
Test name
Test status
Simulation time 12371386661 ps
CPU time 159.72 seconds
Started Jul 12 05:38:42 PM PDT 24
Finished Jul 12 05:41:28 PM PDT 24
Peak memory 200368 kb
Host smart-440fc00f-5c21-45cd-8e2c-68bbe913956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359163499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1359163499
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3079440614
Short name T482
Test name
Test status
Simulation time 40668599 ps
CPU time 0.6 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 195820 kb
Host smart-94e28ff3-2ec5-4d66-b892-e858268b7182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079440614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3079440614
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3164667371
Short name T189
Test name
Test status
Simulation time 1270179309 ps
CPU time 38.18 seconds
Started Jul 12 05:38:45 PM PDT 24
Finished Jul 12 05:39:29 PM PDT 24
Peak memory 200284 kb
Host smart-1406b07d-cafe-428a-b35c-7a2dc3270339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164667371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3164667371
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1002324022
Short name T275
Test name
Test status
Simulation time 16486256650 ps
CPU time 60.84 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:39:49 PM PDT 24
Peak memory 200368 kb
Host smart-8bcf2fc7-018c-4884-972c-ce6855eb515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002324022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1002324022
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4054919509
Short name T84
Test name
Test status
Simulation time 1269553054 ps
CPU time 203.56 seconds
Started Jul 12 05:38:42 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 443096 kb
Host smart-668a3c57-e46a-41ba-a0bf-93343a5b6a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054919509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4054919509
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.90729130
Short name T97
Test name
Test status
Simulation time 22901091143 ps
CPU time 154.81 seconds
Started Jul 12 05:38:33 PM PDT 24
Finished Jul 12 05:41:17 PM PDT 24
Peak memory 200296 kb
Host smart-5362159f-31ea-48ec-8712-45839bfa5c9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90729130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.90729130
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1708376070
Short name T433
Test name
Test status
Simulation time 172070987701 ps
CPU time 148.19 seconds
Started Jul 12 05:38:43 PM PDT 24
Finished Jul 12 05:41:18 PM PDT 24
Peak memory 200360 kb
Host smart-dd338205-ee22-4905-b23e-cdff630d236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708376070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1708376070
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.111826787
Short name T466
Test name
Test status
Simulation time 3522125428 ps
CPU time 13.9 seconds
Started Jul 12 05:38:40 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 200212 kb
Host smart-0a8a7689-7e8e-4110-a498-6aeec35d2aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111826787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.111826787
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.187859268
Short name T493
Test name
Test status
Simulation time 5841030050 ps
CPU time 76.3 seconds
Started Jul 12 05:38:37 PM PDT 24
Finished Jul 12 05:40:01 PM PDT 24
Peak memory 200328 kb
Host smart-5ca03ea6-83ca-463b-9efb-2d2ec9734555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187859268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.187859268
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1409665076
Short name T369
Test name
Test status
Simulation time 15071761 ps
CPU time 0.61 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:38:51 PM PDT 24
Peak memory 196136 kb
Host smart-a08f2767-929a-4d07-889f-2a0fb6fe10e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409665076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1409665076
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.14576851
Short name T268
Test name
Test status
Simulation time 2780671832 ps
CPU time 82.95 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:40:11 PM PDT 24
Peak memory 200352 kb
Host smart-bdf2ac9a-eac3-4150-8c86-0431bf5925fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14576851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.14576851
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4015226781
Short name T422
Test name
Test status
Simulation time 770663363 ps
CPU time 22.14 seconds
Started Jul 12 05:38:54 PM PDT 24
Finished Jul 12 05:39:17 PM PDT 24
Peak memory 200308 kb
Host smart-69475565-519a-4379-926f-2122ccfe0295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015226781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4015226781
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2771388076
Short name T156
Test name
Test status
Simulation time 1159370326 ps
CPU time 184.74 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:41:55 PM PDT 24
Peak memory 595452 kb
Host smart-b7735faf-7619-4c47-ba08-a1f95af34953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771388076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2771388076
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.376346521
Short name T437
Test name
Test status
Simulation time 4243108953 ps
CPU time 64.57 seconds
Started Jul 12 05:38:49 PM PDT 24
Finished Jul 12 05:39:57 PM PDT 24
Peak memory 200576 kb
Host smart-6938e438-ac68-4adc-b58a-bf59f97dc04f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376346521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.376346521
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2620672887
Short name T517
Test name
Test status
Simulation time 24174671533 ps
CPU time 71.2 seconds
Started Jul 12 05:38:41 PM PDT 24
Finished Jul 12 05:40:00 PM PDT 24
Peak memory 200360 kb
Host smart-ff01eb26-2e4b-45ba-87d3-ad60410aa4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620672887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2620672887
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.671719572
Short name T77
Test name
Test status
Simulation time 4006014330 ps
CPU time 12.77 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 200360 kb
Host smart-c34a1b4c-9cf3-4a90-b17e-70321f283720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671719572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.671719572
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.816119523
Short name T299
Test name
Test status
Simulation time 71643049061 ps
CPU time 2113.19 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 06:14:05 PM PDT 24
Peak memory 739576 kb
Host smart-7fae9e35-0f5a-4008-9994-4a175310906e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816119523 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.816119523
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1129010250
Short name T260
Test name
Test status
Simulation time 10507074823 ps
CPU time 18.02 seconds
Started Jul 12 05:38:46 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 200428 kb
Host smart-e50c31a3-9503-43b7-85c8-79934736c381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129010250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1129010250
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.630908034
Short name T223
Test name
Test status
Simulation time 20623553 ps
CPU time 0.61 seconds
Started Jul 12 05:38:50 PM PDT 24
Finished Jul 12 05:38:53 PM PDT 24
Peak memory 195824 kb
Host smart-b50ed1b5-33d6-442b-ac4d-44c801851ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630908034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.630908034
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3651235670
Short name T288
Test name
Test status
Simulation time 529994595 ps
CPU time 14.81 seconds
Started Jul 12 05:38:53 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 200192 kb
Host smart-8a09240f-84eb-4d01-80df-02087d3eb476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651235670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3651235670
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3615993094
Short name T271
Test name
Test status
Simulation time 3178478673 ps
CPU time 34.53 seconds
Started Jul 12 05:38:53 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 200368 kb
Host smart-c6c39790-c849-4901-879a-3761dc66c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615993094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3615993094
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.145463664
Short name T420
Test name
Test status
Simulation time 10518561667 ps
CPU time 228.61 seconds
Started Jul 12 05:38:58 PM PDT 24
Finished Jul 12 05:42:48 PM PDT 24
Peak memory 444660 kb
Host smart-06a03688-06a4-42e7-a321-bd7f37924bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145463664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.145463664
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1922818500
Short name T296
Test name
Test status
Simulation time 837989190 ps
CPU time 10.65 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 200288 kb
Host smart-54ecb790-bdc6-4193-8e8a-cd463b9e6e45
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922818500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1922818500
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2154255669
Short name T141
Test name
Test status
Simulation time 5628578169 ps
CPU time 48.52 seconds
Started Jul 12 05:38:36 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 200360 kb
Host smart-3d9de4e5-4e1a-4380-b921-413f40b05479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154255669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2154255669
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3404448626
Short name T239
Test name
Test status
Simulation time 310657711 ps
CPU time 5.31 seconds
Started Jul 12 05:38:44 PM PDT 24
Finished Jul 12 05:38:55 PM PDT 24
Peak memory 200256 kb
Host smart-11b9c71a-6a1d-4afa-a618-2ec809c0ec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404448626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3404448626
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.855281146
Short name T68
Test name
Test status
Simulation time 544655241940 ps
CPU time 519.91 seconds
Started Jul 12 05:38:48 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 321800 kb
Host smart-e6846d09-2163-4985-a0e0-18c87b08b64d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855281146 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.855281146
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2576778923
Short name T525
Test name
Test status
Simulation time 1181971106 ps
CPU time 30.68 seconds
Started Jul 12 05:38:55 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 200344 kb
Host smart-38011ef5-8984-4095-8bdd-7e36327aec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576778923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2576778923
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2388235974
Short name T16
Test name
Test status
Simulation time 45262477 ps
CPU time 0.6 seconds
Started Jul 12 05:38:52 PM PDT 24
Finished Jul 12 05:38:54 PM PDT 24
Peak memory 195168 kb
Host smart-b5b8b967-bb74-4f9b-b59e-54dbec73967b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388235974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2388235974
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1320164771
Short name T462
Test name
Test status
Simulation time 5639693042 ps
CPU time 67.47 seconds
Started Jul 12 05:38:51 PM PDT 24
Finished Jul 12 05:40:00 PM PDT 24
Peak memory 200184 kb
Host smart-2d4f4adc-6cd4-4a20-b81a-4e2d466e4f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320164771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1320164771
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4099938160
Short name T98
Test name
Test status
Simulation time 548186834 ps
CPU time 28.67 seconds
Started Jul 12 05:38:54 PM PDT 24
Finished Jul 12 05:39:23 PM PDT 24
Peak memory 200356 kb
Host smart-06f7dbe9-a127-407d-9614-4648c5a6ad9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099938160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4099938160
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1827956067
Short name T304
Test name
Test status
Simulation time 10801052274 ps
CPU time 725.54 seconds
Started Jul 12 05:38:53 PM PDT 24
Finished Jul 12 05:50:59 PM PDT 24
Peak memory 708224 kb
Host smart-de571541-efdd-4a14-8d5c-9810e8062d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827956067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1827956067
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2588225933
Short name T529
Test name
Test status
Simulation time 16981557675 ps
CPU time 255.99 seconds
Started Jul 12 05:38:49 PM PDT 24
Finished Jul 12 05:43:08 PM PDT 24
Peak memory 200308 kb
Host smart-bac9b6e5-6f88-4979-9ab2-ad924a029362
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588225933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2588225933
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.220849659
Short name T214
Test name
Test status
Simulation time 4651731200 ps
CPU time 85.59 seconds
Started Jul 12 05:38:52 PM PDT 24
Finished Jul 12 05:40:19 PM PDT 24
Peak memory 200420 kb
Host smart-73380799-9f46-48ea-9a9a-3638e6c85b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220849659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.220849659
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2713175466
Short name T25
Test name
Test status
Simulation time 759474795 ps
CPU time 11.37 seconds
Started Jul 12 05:38:50 PM PDT 24
Finished Jul 12 05:39:04 PM PDT 24
Peak memory 200084 kb
Host smart-cd2a08e6-000a-49b3-9fb0-d2cf45fe2142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713175466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2713175466
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2508078296
Short name T86
Test name
Test status
Simulation time 17845413592 ps
CPU time 2371.01 seconds
Started Jul 12 05:38:50 PM PDT 24
Finished Jul 12 06:18:24 PM PDT 24
Peak memory 803296 kb
Host smart-57300add-172f-4907-adf5-1d1ef0af5bd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508078296 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2508078296
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2858786126
Short name T397
Test name
Test status
Simulation time 2055422190 ps
CPU time 98.84 seconds
Started Jul 12 05:38:55 PM PDT 24
Finished Jul 12 05:40:35 PM PDT 24
Peak memory 200300 kb
Host smart-6f774f88-dc55-48a4-8c51-52668e211419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858786126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2858786126
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1640204662
Short name T402
Test name
Test status
Simulation time 16403887 ps
CPU time 0.6 seconds
Started Jul 12 05:38:51 PM PDT 24
Finished Jul 12 05:38:54 PM PDT 24
Peak memory 196120 kb
Host smart-940357d6-f330-4a26-8ed6-9e55283610e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640204662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1640204662
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3080666339
Short name T488
Test name
Test status
Simulation time 3116900712 ps
CPU time 46.92 seconds
Started Jul 12 05:38:55 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 200360 kb
Host smart-d0f2c6cd-7b50-472c-b9a1-1233592f8379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080666339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3080666339
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.652951687
Short name T93
Test name
Test status
Simulation time 6183209465 ps
CPU time 48.83 seconds
Started Jul 12 05:38:56 PM PDT 24
Finished Jul 12 05:39:46 PM PDT 24
Peak memory 200324 kb
Host smart-24f854e4-ad60-423f-97f4-74a92866e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652951687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.652951687
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.4151712816
Short name T476
Test name
Test status
Simulation time 10185444701 ps
CPU time 438.28 seconds
Started Jul 12 05:38:57 PM PDT 24
Finished Jul 12 05:46:16 PM PDT 24
Peak memory 683852 kb
Host smart-98b62cc8-f480-4625-9b1d-cb10ad3a5144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151712816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.4151712816
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1744082505
Short name T339
Test name
Test status
Simulation time 8500801155 ps
CPU time 237.75 seconds
Started Jul 12 05:38:57 PM PDT 24
Finished Jul 12 05:42:55 PM PDT 24
Peak memory 200224 kb
Host smart-07fcd983-be77-431a-b247-f63c722a76a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744082505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1744082505
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1430691504
Short name T343
Test name
Test status
Simulation time 11897498117 ps
CPU time 140.77 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:41:29 PM PDT 24
Peak memory 200440 kb
Host smart-84767789-e01b-477d-b1de-f2c56326ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430691504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1430691504
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3470169157
Short name T1
Test name
Test status
Simulation time 6591845934 ps
CPU time 12.83 seconds
Started Jul 12 05:38:53 PM PDT 24
Finished Jul 12 05:39:07 PM PDT 24
Peak memory 200404 kb
Host smart-72494683-b529-463c-952e-d99e0bc8d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470169157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3470169157
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.4072821101
Short name T24
Test name
Test status
Simulation time 22498681054 ps
CPU time 1946.8 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 06:11:29 PM PDT 24
Peak memory 752900 kb
Host smart-44d64e84-3a66-4ec3-9868-2df48e0b6e11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072821101 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4072821101
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2910484858
Short name T213
Test name
Test status
Simulation time 2881233223 ps
CPU time 53.6 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 05:39:55 PM PDT 24
Peak memory 200360 kb
Host smart-17e201fa-5417-49bb-bd0d-02f21d590d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910484858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2910484858
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1182944872
Short name T336
Test name
Test status
Simulation time 19544814 ps
CPU time 0.62 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:01 PM PDT 24
Peak memory 196068 kb
Host smart-3fd7c442-2d27-469c-aba4-1cb884e09730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182944872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1182944872
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3110257749
Short name T282
Test name
Test status
Simulation time 1120477565 ps
CPU time 61.53 seconds
Started Jul 12 05:38:53 PM PDT 24
Finished Jul 12 05:39:55 PM PDT 24
Peak memory 200284 kb
Host smart-1d3e3bda-8835-4c9a-a520-ef2cdb22558d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110257749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3110257749
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3797390074
Short name T368
Test name
Test status
Simulation time 5996399500 ps
CPU time 40.28 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 200372 kb
Host smart-0b636e81-c044-4dc8-994c-c06927d04629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797390074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3797390074
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.681008937
Short name T353
Test name
Test status
Simulation time 810806230 ps
CPU time 137.63 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:41:26 PM PDT 24
Peak memory 587608 kb
Host smart-db20df65-eac6-4b30-a348-7f67abede3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681008937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.681008937
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.837315373
Short name T360
Test name
Test status
Simulation time 20612034263 ps
CPU time 178.91 seconds
Started Jul 12 05:38:57 PM PDT 24
Finished Jul 12 05:41:56 PM PDT 24
Peak memory 200240 kb
Host smart-90c1b205-2ffa-4be2-bab9-509b35cde4b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837315373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.837315373
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3809958810
Short name T263
Test name
Test status
Simulation time 32896873966 ps
CPU time 110.69 seconds
Started Jul 12 05:38:51 PM PDT 24
Finished Jul 12 05:40:44 PM PDT 24
Peak memory 200596 kb
Host smart-f3926682-9521-4b99-ad3a-a34bfe35e0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809958810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3809958810
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2527527364
Short name T2
Test name
Test status
Simulation time 40401804 ps
CPU time 2.02 seconds
Started Jul 12 05:39:04 PM PDT 24
Finished Jul 12 05:39:07 PM PDT 24
Peak memory 200420 kb
Host smart-94f74a6b-80da-4de4-93fc-887b0a37b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527527364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2527527364
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.465920123
Short name T511
Test name
Test status
Simulation time 171388848742 ps
CPU time 801.04 seconds
Started Jul 12 05:38:51 PM PDT 24
Finished Jul 12 05:52:14 PM PDT 24
Peak memory 715140 kb
Host smart-b1fc09d1-eb41-47bc-b33f-1ba8a12d31f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465920123 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.465920123
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1799139770
Short name T190
Test name
Test status
Simulation time 6363675049 ps
CPU time 112.73 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:41:00 PM PDT 24
Peak memory 200484 kb
Host smart-1e363d3a-8719-4c1f-809a-8a5ce73b248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799139770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1799139770
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1560481709
Short name T345
Test name
Test status
Simulation time 57692032 ps
CPU time 0.59 seconds
Started Jul 12 05:38:59 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 195040 kb
Host smart-593f574b-1a35-4243-87d1-08b8cea3ceba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560481709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1560481709
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3832885299
Short name T503
Test name
Test status
Simulation time 5715342274 ps
CPU time 85.89 seconds
Started Jul 12 05:39:05 PM PDT 24
Finished Jul 12 05:40:31 PM PDT 24
Peak memory 200420 kb
Host smart-33c10611-edb9-428c-b9f5-8e181505cd54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832885299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3832885299
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3168027661
Short name T342
Test name
Test status
Simulation time 3012263794 ps
CPU time 54.04 seconds
Started Jul 12 05:38:56 PM PDT 24
Finished Jul 12 05:39:51 PM PDT 24
Peak memory 216580 kb
Host smart-5b8b9bd6-ccf1-4c6e-bcab-f36bfe5c4d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168027661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3168027661
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1332529690
Short name T194
Test name
Test status
Simulation time 24599873681 ps
CPU time 909.38 seconds
Started Jul 12 05:38:55 PM PDT 24
Finished Jul 12 05:54:05 PM PDT 24
Peak memory 747596 kb
Host smart-579283fb-ba24-44a8-908e-1acbcc918a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332529690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1332529690
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1175513676
Short name T328
Test name
Test status
Simulation time 1198726369 ps
CPU time 69.21 seconds
Started Jul 12 05:39:06 PM PDT 24
Finished Jul 12 05:40:15 PM PDT 24
Peak memory 200156 kb
Host smart-62d314b3-e904-4806-b133-078809019aae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175513676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1175513676
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1668042774
Short name T6
Test name
Test status
Simulation time 5104310777 ps
CPU time 68.83 seconds
Started Jul 12 05:38:56 PM PDT 24
Finished Jul 12 05:40:06 PM PDT 24
Peak memory 200228 kb
Host smart-708ecf35-9436-462b-a8d5-f4b38b9d37d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668042774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1668042774
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2284147607
Short name T209
Test name
Test status
Simulation time 510333251 ps
CPU time 6.38 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:07 PM PDT 24
Peak memory 200224 kb
Host smart-79f2b519-18ab-47a1-bad7-7eda053c9eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284147607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2284147607
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.719113811
Short name T295
Test name
Test status
Simulation time 155782994651 ps
CPU time 757.96 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:51:39 PM PDT 24
Peak memory 557624 kb
Host smart-398d5003-4288-46cd-8797-d63ce80b0a5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719113811 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.719113811
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2972721191
Short name T233
Test name
Test status
Simulation time 17769923013 ps
CPU time 112.67 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 05:40:55 PM PDT 24
Peak memory 200372 kb
Host smart-c2cd1bb0-8745-45b7-8c3c-ccc07e230556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972721191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2972721191
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3791620809
Short name T501
Test name
Test status
Simulation time 23968066 ps
CPU time 0.63 seconds
Started Jul 12 05:39:02 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 196180 kb
Host smart-abd02cdc-3111-4628-99d3-1fe0dd788da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791620809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3791620809
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.355313459
Short name T373
Test name
Test status
Simulation time 1834429448 ps
CPU time 20.44 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:21 PM PDT 24
Peak memory 200208 kb
Host smart-a8d8007c-a099-486b-89d7-bf51c09606a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355313459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.355313459
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2553758924
Short name T446
Test name
Test status
Simulation time 7620858881 ps
CPU time 30.08 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 208560 kb
Host smart-7024ba9d-24ef-4f20-8aa1-3b15a03f1284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553758924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2553758924
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3486394186
Short name T490
Test name
Test status
Simulation time 2357589447 ps
CPU time 158.27 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:41:38 PM PDT 24
Peak memory 363840 kb
Host smart-fbded349-3fb8-475c-99b1-9d489adcc25a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486394186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3486394186
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2862613060
Short name T193
Test name
Test status
Simulation time 1275403153 ps
CPU time 63.07 seconds
Started Jul 12 05:38:59 PM PDT 24
Finished Jul 12 05:40:02 PM PDT 24
Peak memory 200172 kb
Host smart-85b70fdb-5e09-4188-93fd-2f9c30a5e8ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862613060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2862613060
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2577247776
Short name T382
Test name
Test status
Simulation time 10877205780 ps
CPU time 190.11 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:42:18 PM PDT 24
Peak memory 200332 kb
Host smart-e6ee0761-5f24-4f95-a4a9-bdc068b524f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577247776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2577247776
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1395742026
Short name T478
Test name
Test status
Simulation time 1417428517 ps
CPU time 16.25 seconds
Started Jul 12 05:39:02 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 200308 kb
Host smart-5eb57196-620b-4405-8404-ca80a797e493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395742026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1395742026
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.59667665
Short name T64
Test name
Test status
Simulation time 123699014389 ps
CPU time 2944.92 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 06:28:07 PM PDT 24
Peak memory 767200 kb
Host smart-ffb0c7de-79f0-4305-9053-02c4c6e7d9ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59667665 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.59667665
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1988463712
Short name T291
Test name
Test status
Simulation time 110011569295 ps
CPU time 123.81 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 05:41:06 PM PDT 24
Peak memory 200388 kb
Host smart-c9706b05-2fbd-426b-9110-e19848767721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988463712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1988463712
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4220223513
Short name T320
Test name
Test status
Simulation time 10685545 ps
CPU time 0.58 seconds
Started Jul 12 05:38:05 PM PDT 24
Finished Jul 12 05:38:26 PM PDT 24
Peak memory 195828 kb
Host smart-27f8a188-58a9-4318-bb44-3f5795611980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220223513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4220223513
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2481955977
Short name T251
Test name
Test status
Simulation time 1867084472 ps
CPU time 102.2 seconds
Started Jul 12 05:38:02 PM PDT 24
Finished Jul 12 05:40:06 PM PDT 24
Peak memory 200168 kb
Host smart-39432d94-5862-4476-ab5b-3c311a637138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481955977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2481955977
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2754423722
Short name T411
Test name
Test status
Simulation time 499487763 ps
CPU time 9.34 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:12 PM PDT 24
Peak memory 200228 kb
Host smart-5db9f4a3-963a-4e82-982b-e945710307d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754423722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2754423722
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2616794548
Short name T154
Test name
Test status
Simulation time 37301699489 ps
CPU time 678.21 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:49:34 PM PDT 24
Peak memory 697308 kb
Host smart-a256a904-a851-4df2-abdf-b0ff378f33bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616794548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2616794548
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.513674884
Short name T311
Test name
Test status
Simulation time 4484495375 ps
CPU time 120.83 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:40:04 PM PDT 24
Peak memory 200316 kb
Host smart-feee105c-6120-48a1-a205-11380e44216f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513674884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.513674884
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.350277406
Short name T177
Test name
Test status
Simulation time 3969025307 ps
CPU time 53.68 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 200368 kb
Host smart-ff6dbe4b-4d6f-497b-a6a3-c11aec79df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350277406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.350277406
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.396513429
Short name T161
Test name
Test status
Simulation time 2110717038 ps
CPU time 6.86 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:38:27 PM PDT 24
Peak memory 200208 kb
Host smart-8bc098f0-9508-41a6-88f7-dc241d2759d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396513429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.396513429
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3798765971
Short name T197
Test name
Test status
Simulation time 32255995821 ps
CPU time 230.98 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:42:07 PM PDT 24
Peak memory 200736 kb
Host smart-1abd04f8-c5a7-4795-b9f7-bf1bff5d7e70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798765971 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3798765971
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2963656681
Short name T167
Test name
Test status
Simulation time 238421834 ps
CPU time 2.06 seconds
Started Jul 12 05:37:55 PM PDT 24
Finished Jul 12 05:38:18 PM PDT 24
Peak memory 200248 kb
Host smart-ffd12d5a-85a0-4744-8dd9-2d7a8660c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963656681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2963656681
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3126849258
Short name T83
Test name
Test status
Simulation time 20286692 ps
CPU time 0.59 seconds
Started Jul 12 05:38:10 PM PDT 24
Finished Jul 12 05:38:28 PM PDT 24
Peak memory 196216 kb
Host smart-305ed562-9beb-42d0-a24d-2af3ab1751dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126849258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3126849258
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3079336418
Short name T92
Test name
Test status
Simulation time 2178822611 ps
CPU time 63.68 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 200388 kb
Host smart-d92c3452-8ebd-4f0c-a1ab-3246a4f81076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079336418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3079336418
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.228542192
Short name T391
Test name
Test status
Simulation time 1798691391 ps
CPU time 17.04 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:38:47 PM PDT 24
Peak memory 200244 kb
Host smart-6ec4e98d-ac29-48c4-9741-fa5939f9300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228542192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.228542192
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3734268680
Short name T481
Test name
Test status
Simulation time 4866358342 ps
CPU time 728.73 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:50:23 PM PDT 24
Peak memory 672488 kb
Host smart-5934aa3d-567e-437e-8603-04abdd71e9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734268680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3734268680
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2218621653
Short name T221
Test name
Test status
Simulation time 3949597674 ps
CPU time 69.88 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:39:41 PM PDT 24
Peak memory 200100 kb
Host smart-daab9807-c2a8-4138-947c-628cd25f1858
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218621653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2218621653
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2454925072
Short name T326
Test name
Test status
Simulation time 6992955113 ps
CPU time 111.84 seconds
Started Jul 12 05:37:53 PM PDT 24
Finished Jul 12 05:40:04 PM PDT 24
Peak memory 216832 kb
Host smart-82e4e10f-efb6-4962-91c9-552788cedcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454925072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2454925072
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1945943590
Short name T380
Test name
Test status
Simulation time 199821094 ps
CPU time 8.62 seconds
Started Jul 12 05:37:50 PM PDT 24
Finished Jul 12 05:38:17 PM PDT 24
Peak memory 200368 kb
Host smart-3b6d8408-8f48-4812-804c-ac7bf03c5453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945943590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1945943590
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.734469259
Short name T143
Test name
Test status
Simulation time 17033075524 ps
CPU time 226.04 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:42:02 PM PDT 24
Peak memory 436284 kb
Host smart-0bd9fd13-1157-4038-ad87-dccabc14ad09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734469259 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.734469259
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.4106651229
Short name T23
Test name
Test status
Simulation time 145738195739 ps
CPU time 3378.8 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 06:34:46 PM PDT 24
Peak memory 744612 kb
Host smart-0c3e3370-67e2-4ea7-b01d-68aef128b4bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106651229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.4106651229
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2742368303
Short name T225
Test name
Test status
Simulation time 1872809294 ps
CPU time 32.66 seconds
Started Jul 12 05:37:54 PM PDT 24
Finished Jul 12 05:38:49 PM PDT 24
Peak memory 200180 kb
Host smart-c38d9b6a-acb6-4f4f-ab7b-6e5204a29a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742368303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2742368303
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.725868599
Short name T250
Test name
Test status
Simulation time 12994905 ps
CPU time 0.63 seconds
Started Jul 12 05:37:50 PM PDT 24
Finished Jul 12 05:38:08 PM PDT 24
Peak memory 195040 kb
Host smart-60b205a8-5785-4a02-a588-207b9957cc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725868599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.725868599
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1552531011
Short name T506
Test name
Test status
Simulation time 5851207132 ps
CPU time 27.26 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:29 PM PDT 24
Peak memory 200324 kb
Host smart-7ef1646c-e5ab-4513-a5f8-b90dbbeb9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552531011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1552531011
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.436781226
Short name T151
Test name
Test status
Simulation time 9862389977 ps
CPU time 797.99 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:51:49 PM PDT 24
Peak memory 693228 kb
Host smart-8a9acac3-2845-48f4-9bd8-d00ac3084e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436781226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.436781226
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1649853679
Short name T185
Test name
Test status
Simulation time 1741157831 ps
CPU time 21.82 seconds
Started Jul 12 05:37:47 PM PDT 24
Finished Jul 12 05:38:22 PM PDT 24
Peak memory 200236 kb
Host smart-29b302f4-e298-4740-bdd1-ff8d466ec1fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649853679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1649853679
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2351562494
Short name T274
Test name
Test status
Simulation time 556838776 ps
CPU time 33.29 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 200468 kb
Host smart-f21052a6-ecf6-422f-82d1-8e5ece42ad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351562494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2351562494
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.887429088
Short name T434
Test name
Test status
Simulation time 1123950395 ps
CPU time 13.48 seconds
Started Jul 12 05:38:09 PM PDT 24
Finished Jul 12 05:38:41 PM PDT 24
Peak memory 200164 kb
Host smart-1ab51d08-6917-492f-b4d7-27a181adafe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887429088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.887429088
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.225093219
Short name T513
Test name
Test status
Simulation time 4101151588 ps
CPU time 738.34 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:50:21 PM PDT 24
Peak memory 754188 kb
Host smart-60fa3d88-fc47-4fdd-88d5-f08700399095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225093219 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.225093219
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2070511532
Short name T10
Test name
Test status
Simulation time 55216037475 ps
CPU time 1180.79 seconds
Started Jul 12 05:37:52 PM PDT 24
Finished Jul 12 05:57:51 PM PDT 24
Peak memory 643120 kb
Host smart-17ef6978-b5fd-40c8-b4ba-b14c4c39a2dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070511532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2070511532
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2436926183
Short name T483
Test name
Test status
Simulation time 11591857853 ps
CPU time 129.42 seconds
Started Jul 12 05:38:00 PM PDT 24
Finished Jul 12 05:40:33 PM PDT 24
Peak memory 200392 kb
Host smart-5009ee2b-64db-4826-8626-b9d41d4977cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436926183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2436926183
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1579037758
Short name T211
Test name
Test status
Simulation time 18474868 ps
CPU time 0.59 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:38:32 PM PDT 24
Peak memory 196204 kb
Host smart-097fab8a-363a-4cde-be1a-b1ca0c7bcc65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579037758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1579037758
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1387474165
Short name T180
Test name
Test status
Simulation time 1484761337 ps
CPU time 84.08 seconds
Started Jul 12 05:38:16 PM PDT 24
Finished Jul 12 05:39:56 PM PDT 24
Peak memory 200264 kb
Host smart-fc580795-3ec0-4387-83ad-9d3be41a701e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387474165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1387474165
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2887730859
Short name T222
Test name
Test status
Simulation time 1977857870 ps
CPU time 33.28 seconds
Started Jul 12 05:38:11 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 200268 kb
Host smart-a0c3c5ce-e007-4d48-ae5d-27c8f967ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887730859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2887730859
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.260044870
Short name T306
Test name
Test status
Simulation time 463806368 ps
CPU time 72.02 seconds
Started Jul 12 05:37:58 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 347520 kb
Host smart-0653c6e9-d66d-4c4f-80c7-f503801e90b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260044870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.260044870
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4033839015
Short name T305
Test name
Test status
Simulation time 1589674686 ps
CPU time 45.06 seconds
Started Jul 12 05:37:59 PM PDT 24
Finished Jul 12 05:39:07 PM PDT 24
Peak memory 200480 kb
Host smart-8cc04588-8b54-498c-be99-3d5bedb2d153
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033839015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4033839015
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3318207476
Short name T519
Test name
Test status
Simulation time 262870037 ps
CPU time 3.76 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:38:24 PM PDT 24
Peak memory 200132 kb
Host smart-4f6ed342-7709-4071-9aa6-29cb758a07b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318207476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3318207476
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.961700449
Short name T76
Test name
Test status
Simulation time 237507939 ps
CPU time 9.64 seconds
Started Jul 12 05:38:04 PM PDT 24
Finished Jul 12 05:38:35 PM PDT 24
Peak memory 200300 kb
Host smart-3f3c0ee6-7e69-4714-94de-b54dbebd37ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961700449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.961700449
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.328796476
Short name T294
Test name
Test status
Simulation time 14687429463 ps
CPU time 247.86 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:42:39 PM PDT 24
Peak memory 200356 kb
Host smart-118c339f-92d5-4f48-a2a6-61d5082cccac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328796476 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.328796476
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2179029925
Short name T229
Test name
Test status
Simulation time 1051861630 ps
CPU time 57.56 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:39:18 PM PDT 24
Peak memory 200344 kb
Host smart-f36c1219-7101-4c65-a443-3dd85d344300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179029925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2179029925
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3992477368
Short name T188
Test name
Test status
Simulation time 173104096 ps
CPU time 0.57 seconds
Started Jul 12 05:38:18 PM PDT 24
Finished Jul 12 05:38:34 PM PDT 24
Peak memory 195260 kb
Host smart-3ac4c026-b717-4df5-a04c-b81b811f63c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992477368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3992477368
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2943935840
Short name T394
Test name
Test status
Simulation time 904776914 ps
CPU time 46.98 seconds
Started Jul 12 05:38:07 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 200356 kb
Host smart-7a86d85e-bbdc-4f84-8d41-005d43c431a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943935840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2943935840
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.791043910
Short name T515
Test name
Test status
Simulation time 2438730915 ps
CPU time 197.98 seconds
Started Jul 12 05:38:12 PM PDT 24
Finished Jul 12 05:41:49 PM PDT 24
Peak memory 464692 kb
Host smart-e76fc058-45f2-4eb6-bfa3-881c950b14fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791043910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.791043910
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1008137760
Short name T79
Test name
Test status
Simulation time 13640301744 ps
CPU time 181.66 seconds
Started Jul 12 05:37:59 PM PDT 24
Finished Jul 12 05:41:24 PM PDT 24
Peak memory 200260 kb
Host smart-5a2227a8-f945-45b2-b7a4-431a00e918bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008137760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1008137760
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3613380514
Short name T199
Test name
Test status
Simulation time 14538233061 ps
CPU time 126.28 seconds
Started Jul 12 05:38:13 PM PDT 24
Finished Jul 12 05:40:37 PM PDT 24
Peak memory 200556 kb
Host smart-0d37c816-44c0-40b5-aebb-fbafc4b579b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613380514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3613380514
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1714716150
Short name T246
Test name
Test status
Simulation time 247118581 ps
CPU time 5.8 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:38:38 PM PDT 24
Peak memory 200308 kb
Host smart-0a0eedc7-334b-4879-96d3-bc2efe3c2295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714716150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1714716150
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1339643902
Short name T244
Test name
Test status
Simulation time 101394593461 ps
CPU time 378 seconds
Started Jul 12 05:38:05 PM PDT 24
Finished Jul 12 05:44:44 PM PDT 24
Peak memory 200400 kb
Host smart-5e971742-3f53-4cb2-bcbb-fe513cdf6147
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339643902 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1339643902
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1319788304
Short name T52
Test name
Test status
Simulation time 102054031548 ps
CPU time 960.9 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:54:21 PM PDT 24
Peak memory 368220 kb
Host smart-3f8770ae-dabe-47ed-928a-f091bcef7c67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319788304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1319788304
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.124108631
Short name T73
Test name
Test status
Simulation time 21923452427 ps
CPU time 66.53 seconds
Started Jul 12 05:38:15 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 200360 kb
Host smart-22c882d1-8143-4cb2-bfb4-5ae337041782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124108631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.124108631
Directory /workspace/9.hmac_wipe_secret/latest
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