Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18500445	1			T1	3274		T3	8474		T4	68172
all_values[1]	18500445	1			T1	3274		T3	8474		T4	68172
all_values[2]	18500445	1			T1	3274		T3	8474		T4	68172

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242168

1

T3

2809

T4

5860

T9

1712

auto[1]

55259167

1

T1

9822

T3

22613

T4

198656

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47259848

1

T1

8123

T3

20050

T4

181871

auto[1]

8241487

1

T1

1699

T3

5372

T4

22645

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	89315	1			T3	2809		T4	5828		T9	1712
all_values[0]	auto[0]	auto[1]	354	1			T4	2		T21	2		T30	3
all_values[0]	auto[1]	auto[0]	18390181	1			T1	3269		T3	5642		T4	62180
all_values[0]	auto[1]	auto[1]	20595	1			T1	5		T3	23		T4	162
all_values[1]	auto[0]	auto[0]	93433	1			T21	33		T14	561		T28	2
all_values[1]	auto[0]	auto[1]	227	1			T49	1		T10	16		T8	2
all_values[1]	auto[1]	auto[0]	18406442	1			T1	3274		T3	8474		T4	68172
all_values[1]	auto[1]	auto[1]	343	1			T49	1		T10	13		T8	1
all_values[2]	auto[0]	auto[0]	36512	1			T4	30		T66	121		T29	13
all_values[2]	auto[0]	auto[1]	22327	1			T66	353		T29	30		T49	17
all_values[2]	auto[1]	auto[0]	10243965	1			T1	1580		T3	3125		T4	45661
all_values[2]	auto[1]	auto[1]	8197641	1			T1	1694		T3	5349		T4	22481