Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141392

1

T1

4

T3

30

T4

4138

auto[1]

133558

1

T1

10

T3

38

T4

1708

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	102232	1			T1	7		T3	5		T4	2595
len_1026_2046	5453	1			T3	1		T4	98		T5	2
len_514_1022	4770	1			T3	1		T4	62		T6	32
len_2_510	4383	1			T3	1		T4	40		T6	15
len_2056	331	1			T3	1		T4	2		T6	3
len_2048	401	1			T3	1		T4	10		T6	7
len_2040	262	1			T3	4		T4	2		T6	5
len_1032	133	1			T3	2		T21	1		T14	1
len_1024	1744	1			T4	15		T5	1		T6	2
len_1016	397	1			T3	5		T4	2		T6	3
len_520	568	1			T3	3		T4	4		T6	2
len_512	406	1			T3	5		T4	7		T5	1
len_504	216	1			T3	3		T4	13		T21	5
len_8	997	1			T6	2		T9	12		T47	1
len_0	15182	1			T3	2		T4	73		T6	12

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

138

1

T4

9

T21

2

T137

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	53978	1			T1	2		T3	1		T4	1846
auto[0]	len_1026_2046	2993	1			T3	1		T4	75		T5	2
auto[0]	len_514_1022	2706	1			T3	1		T4	39		T6	21
auto[0]	len_2_510	2677	1			T3	1		T4	31		T6	11
auto[0]	len_2056	249	1			T3	1		T4	1		T6	1
auto[0]	len_2048	227	1			T4	4		T6	3		T21	1
auto[0]	len_2040	117	1			T4	2		T21	1		T32	2
auto[0]	len_1032	60	1			T49	2		T88	1		T10	4
auto[0]	len_1024	256	1			T4	11		T5	1		T6	2
auto[0]	len_1016	174	1			T3	3		T4	1		T21	2
auto[0]	len_520	478	1			T4	1		T47	1		T14	3
auto[0]	len_512	244	1			T3	4		T4	5		T6	3
auto[0]	len_504	126	1			T3	3		T4	5		T21	3
auto[0]	len_8	33	1			T47	1		T74	1		T67	5
auto[0]	len_0	6378	1			T4	48		T6	8		T17	1
auto[1]	len_2050_plus	48254	1			T1	5		T3	4		T4	749
auto[1]	len_1026_2046	2460	1			T4	23		T6	4		T21	1
auto[1]	len_514_1022	2064	1			T4	23		T6	11		T19	2
auto[1]	len_2_510	1706	1			T4	9		T6	4		T137	19
auto[1]	len_2056	82	1			T4	1		T6	2		T10	6
auto[1]	len_2048	174	1			T3	1		T4	6		T6	4
auto[1]	len_2040	145	1			T3	4		T6	5		T28	8
auto[1]	len_1032	73	1			T3	2		T21	1		T14	1
auto[1]	len_1024	1488	1			T4	4		T21	1		T137	2
auto[1]	len_1016	223	1			T3	2		T4	1		T6	3
auto[1]	len_520	90	1			T3	3		T4	3		T6	2
auto[1]	len_512	162	1			T3	1		T4	2		T5	1
auto[1]	len_504	90	1			T4	8		T21	2		T14	3
auto[1]	len_8	964	1			T6	2		T9	12		T14	9
auto[1]	len_0	8804	1			T3	2		T4	25		T6	4

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

91

1

T4

9

T137

1

T7

1

auto[1]

len_upper

47

1

T21

2

T45

2

T138

1