Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4661251 1 T1 6 T3 1663 T4 17743
auto[1] 2876646 1 T1 5 T3 494 T4 24424


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2896589 1 T1 8 T3 302 T4 13929
auto[1] 4641308 1 T1 3 T3 1855 T4 28238


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3428300 1 T1 4 T3 721 T4 19562
auto[1] 4109597 1 T1 7 T3 1436 T4 22605


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4619042 1 T1 6 T3 1199 T4 18968
auto[1] 2918855 1 T1 5 T3 958 T4 23199


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6768014 1 T1 7 T3 2118 T4 41216
fifo_depth[1] 126126 1 T1 1 T3 27 T4 510
fifo_depth[2] 98229 1 T1 1 T3 8 T4 262
fifo_depth[3] 76666 1 T3 2 T4 64 T5 4
fifo_depth[4] 69652 1 T4 69 T5 2 T6 97
fifo_depth[5] 54507 1 T1 1 T3 1 T4 19
fifo_depth[6] 44125 1 T3 1 T4 19 T5 1
fifo_depth[7] 28624 1 T4 4 T6 5 T9 164


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 769883 1 T1 4 T3 39 T4 951
auto[1] 6768014 1 T1 7 T3 2118 T4 41216


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7520595 1 T1 11 T3 2157 T4 42167
auto[1] 17302 1 T8 1055 T20 9 T15 996


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 33448 1 T4 101 T6 83 T21 1
auto[0] auto[0] auto[0] auto[0] auto[1] 36651 1 T1 1 T4 14 T5 1
auto[0] auto[0] auto[0] auto[1] auto[0] 41580 1 T4 117 T6 26 T17 559
auto[0] auto[0] auto[0] auto[1] auto[1] 37956 1 T4 24 T6 145 T17 455
auto[0] auto[0] auto[1] auto[0] auto[0] 157219 1 T3 1 T4 84 T5 1
auto[0] auto[0] auto[1] auto[0] auto[1] 27139 1 T3 25 T4 180 T5 2
auto[0] auto[0] auto[1] auto[1] auto[0] 41382 1 T4 60 T5 1 T6 56
auto[0] auto[0] auto[1] auto[1] auto[1] 29053 1 T4 29 T5 2 T6 167
auto[0] auto[1] auto[0] auto[0] auto[0] 40979 1 T4 48 T5 2 T6 144
auto[0] auto[1] auto[0] auto[0] auto[1] 43592 1 T1 1 T4 24 T5 1
auto[0] auto[1] auto[0] auto[1] auto[0] 46847 1 T1 2 T3 2 T4 6
auto[0] auto[1] auto[0] auto[1] auto[1] 46614 1 T4 31 T5 2 T6 167
auto[0] auto[1] auto[1] auto[0] auto[0] 51023 1 T3 6 T4 16 T5 1
auto[0] auto[1] auto[1] auto[0] auto[1] 47847 1 T3 3 T4 15 T5 2
auto[0] auto[1] auto[1] auto[1] auto[0] 43415 1 T4 92 T6 34 T9 1478
auto[0] auto[1] auto[1] auto[1] auto[1] 45138 1 T3 2 T4 110 T6 79
auto[1] auto[0] auto[0] auto[0] auto[0] 177168 1 T3 41 T4 2568 T5 1
auto[1] auto[0] auto[0] auto[0] auto[1] 194970 1 T1 1 T3 10 T4 1549
auto[1] auto[0] auto[0] auto[1] auto[0] 184505 1 T3 12 T4 1964 T5 3
auto[1] auto[0] auto[0] auto[1] auto[1] 185978 1 T1 1 T3 48 T4 618
auto[1] auto[0] auto[1] auto[0] auto[0] 1731158 1 T3 92 T4 2545 T5 1
auto[1] auto[0] auto[1] auto[0] auto[1] 190369 1 T3 422 T4 5567 T5 1
auto[1] auto[0] auto[1] auto[1] auto[0] 180705 1 T1 1 T3 62 T4 2986
auto[1] auto[0] auto[1] auto[1] auto[1] 179019 1 T3 8 T4 1156 T5 3
auto[1] auto[1] auto[0] auto[0] auto[0] 448691 1 T1 1 T3 96 T4 1604
auto[1] auto[1] auto[0] auto[0] auto[1] 457302 1 T1 1 T3 59 T4 1257
auto[1] auto[1] auto[0] auto[1] auto[0] 463658 1 T3 34 T4 1177 T5 1
auto[1] auto[1] auto[0] auto[1] auto[1] 456650 1 T4 2827 T5 1 T6 4437
auto[1] auto[1] auto[1] auto[0] auto[0] 524873 1 T1 1 T3 537 T4 654
auto[1] auto[1] auto[1] auto[0] auto[1] 498822 1 T3 371 T4 1517 T6 3928
auto[1] auto[1] auto[1] auto[1] auto[0] 452391 1 T1 1 T3 316 T4 4946
auto[1] auto[1] auto[1] auto[1] auto[1] 441755 1 T3 10 T4 8281 T5 4


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 209465 1 T3 41 T4 2669 T5 1
auto[0] auto[0] auto[0] auto[0] auto[1] 230867 1 T1 2 T3 10 T4 1563
auto[0] auto[0] auto[0] auto[1] auto[0] 223948 1 T3 12 T4 2081 T5 3
auto[0] auto[0] auto[0] auto[1] auto[1] 222477 1 T1 1 T3 48 T4 642
auto[0] auto[0] auto[1] auto[0] auto[0] 1887686 1 T3 93 T4 2629 T5 2
auto[0] auto[0] auto[1] auto[0] auto[1] 216639 1 T3 447 T4 5747 T5 3
auto[0] auto[0] auto[1] auto[1] auto[0] 220030 1 T1 1 T3 62 T4 3046
auto[0] auto[0] auto[1] auto[1] auto[1] 207056 1 T3 8 T4 1185 T5 5
auto[0] auto[1] auto[0] auto[0] auto[0] 489401 1 T1 1 T3 96 T4 1652
auto[0] auto[1] auto[0] auto[0] auto[1] 500385 1 T1 2 T3 59 T4 1281
auto[0] auto[1] auto[0] auto[1] auto[0] 508581 1 T1 2 T3 36 T4 1183
auto[0] auto[1] auto[0] auto[1] auto[1] 502100 1 T4 2858 T5 3 T6 4604
auto[0] auto[1] auto[1] auto[0] auto[0] 574940 1 T1 1 T3 543 T4 670
auto[0] auto[1] auto[1] auto[0] auto[1] 546113 1 T3 374 T4 1532 T5 2
auto[0] auto[1] auto[1] auto[1] auto[0] 494669 1 T1 1 T3 316 T4 5038
auto[0] auto[1] auto[1] auto[1] auto[1] 486238 1 T3 12 T4 8391 T5 4
auto[1] auto[0] auto[0] auto[0] auto[0] 1151 1 T20 5 T15 2 T44 10
auto[1] auto[0] auto[0] auto[0] auto[1] 754 1 T15 91 T45 6 T140 73
auto[1] auto[0] auto[0] auto[1] auto[0] 2137 1 T8 1002 T15 44 T44 4
auto[1] auto[0] auto[0] auto[1] auto[1] 1457 1 T15 91 T141 390 T140 3
auto[1] auto[0] auto[1] auto[0] auto[0] 691 1 T15 19 T45 1 T141 20
auto[1] auto[0] auto[1] auto[0] auto[1] 869 1 T20 2 T140 33 T23 10
auto[1] auto[0] auto[1] auto[1] auto[0] 2057 1 T8 1 T15 9 T44 10
auto[1] auto[0] auto[1] auto[1] auto[1] 1016 1 T15 392 T44 1 T67 1
auto[1] auto[1] auto[0] auto[0] auto[0] 269 1 T15 26 T44 1 T45 30
auto[1] auto[1] auto[0] auto[0] auto[1] 509 1 T140 12 T142 17 T35 120
auto[1] auto[1] auto[0] auto[1] auto[0] 1924 1 T8 52 T15 12 T44 16
auto[1] auto[1] auto[0] auto[1] auto[1] 1164 1 T15 152 T44 547 T140 7
auto[1] auto[1] auto[1] auto[0] auto[0] 956 1 T15 108 T44 8 T140 11
auto[1] auto[1] auto[1] auto[0] auto[1] 556 1 T20 2 T15 9 T44 96
auto[1] auto[1] auto[1] auto[1] auto[0] 1137 1 T15 12 T140 1 T143 3
auto[1] auto[1] auto[1] auto[1] auto[1] 655 1 T15 29 T45 110 T141 7


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 177168 1 T3 41 T4 2568 T5 1
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 194970 1 T1 1 T3 10 T4 1549
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 184505 1 T3 12 T4 1964 T5 3
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 185978 1 T1 1 T3 48 T4 618
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1731158 1 T3 92 T4 2545 T5 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 190369 1 T3 422 T4 5567 T5 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 180705 1 T1 1 T3 62 T4 2986
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 179019 1 T3 8 T4 1156 T5 3
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 448691 1 T1 1 T3 96 T4 1604
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 457302 1 T1 1 T3 59 T4 1257
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 463658 1 T3 34 T4 1177 T5 1
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 456650 1 T4 2827 T5 1 T6 4437
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 524873 1 T1 1 T3 537 T4 654
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 498822 1 T3 371 T4 1517 T6 3928
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 452391 1 T1 1 T3 316 T4 4946
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 441755 1 T3 10 T4 8281 T5 4
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4155 1 T4 52 T6 35 T21 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4135 1 T1 1 T4 12 T6 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4048 1 T4 39 T6 3 T17 126
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3868 1 T4 14 T6 78 T17 89
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 45291 1 T4 38 T6 32 T47 1257
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3827 1 T3 20 T4 89 T6 131
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3762 1 T4 35 T6 35 T19 6
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3821 1 T4 15 T6 51 T19 4
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6160 1 T4 23 T6 37 T137 18
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6372 1 T4 5 T6 70 T19 15
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5667 1 T3 2 T4 4 T6 102
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6230 1 T4 23 T6 104 T9 11
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8429 1 T3 2 T4 7 T6 20
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7410 1 T3 3 T4 13 T6 13
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6210 1 T4 70 T6 8 T9 221
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6741 1 T4 71 T6 52 T9 18
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3304 1 T4 24 T6 19 T137 16
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3561 1 T4 1 T17 45 T46 6
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3500 1 T4 25 T6 9 T17 140
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3113 1 T4 6 T6 51 T17 84
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 30467 1 T3 1 T4 34 T6 15
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2905 1 T3 4 T4 56 T6 53
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3270 1 T4 19 T6 14 T19 9
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3267 1 T4 10 T6 42 T19 8
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5181 1 T4 12 T6 26 T137 13
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5504 1 T1 1 T4 13 T6 43
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4752 1 T4 1 T6 67 T17 16
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5250 1 T4 7 T6 50 T9 7
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6791 1 T3 3 T4 4 T6 15
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 6272 1 T4 2 T6 6 T17 28
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5271 1 T4 18 T6 3 T9 213
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5821 1 T4 30 T6 19 T9 18
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2584 1 T4 13 T6 6 T137 4
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2672 1 T4 1 T17 33 T46 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2731 1 T4 18 T6 6 T17 122
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2322 1 T4 3 T6 13 T17 85
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 21205 1 T4 1 T6 3 T47 34
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2298 1 T4 12 T6 18 T18 15
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2471 1 T5 1 T6 4 T19 9
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2356 1 T4 1 T5 1 T6 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4408 1 T4 2 T6 28 T137 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4879 1 T6 11 T19 12 T14 251
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4087 1 T4 1 T6 20 T17 14
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4298 1 T4 1 T5 1 T6 8
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5719 1 T4 3 T6 3 T9 36
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5182 1 T5 1 T6 4 T17 31
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4503 1 T4 4 T6 1 T9 195
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4951 1 T3 2 T4 4 T6 7
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2667 1 T4 7 T6 7 T137 10
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2617 1 T17 14 T46 3 T137 9
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2986 1 T4 18 T6 2 T17 107
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2432 1 T4 1 T6 2 T17 76
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 15394 1 T4 10 T5 1 T47 4
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2401 1 T4 13 T5 1 T6 4
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2550 1 T4 3 T6 2 T19 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2668 1 T4 2 T6 34 T19 7
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4123 1 T4 6 T6 17 T14 92
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4770 1 T4 5 T6 7 T19 9
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3934 1 T6 1 T17 28 T14 18
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4028 1 T6 4 T9 9 T19 7
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5175 1 T4 2 T6 1 T9 35
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4806 1 T6 2 T17 18 T18 10
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4340 1 T6 13 T9 201 T137 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4761 1 T4 2 T6 1 T9 14
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2035 1 T4 4 T6 6 T137 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2046 1 T17 5 T14 1 T26 14
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1937 1 T4 10 T6 3 T17 36
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1774 1 T6 1 T17 62 T26 53
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 10711 1 T4 1 T66 14 T14 3
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1758 1 T4 2 T6 2 T18 13
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1771 1 T6 1 T19 8 T46 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1853 1 T19 7 T137 1 T66 20
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3476 1 T6 19 T14 81 T30 41
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4051 1 T6 1 T19 11 T14 197
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3324 1 T1 1 T17 14 T14 17
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3372 1 T9 5 T19 5 T66 26
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4406 1 T3 1 T9 28 T18 7
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4164 1 T6 1 T17 8 T18 6
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3758 1 T9 191 T66 1 T14 99
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4071 1 T4 2 T9 8 T18 15
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1720 1 T4 1 T6 2 T14 59
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1609 1 T46 1 T26 13 T49 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1575 1 T4 3 T6 1 T17 24
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1579 1 T17 33 T46 8 T137 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7888 1 T137 2 T66 11 T91 18
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1385 1 T3 1 T4 7 T18 7
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1656 1 T4 3 T19 8 T46 1
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1662 1 T4 1 T6 24 T19 5
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2898 1 T4 3 T5 1 T6 14
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3211 1 T4 1 T6 1 T19 5
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2813 1 T6 1 T17 8 T14 11
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2969 1 T6 1 T9 4 T19 4
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3524 1 T9 26 T18 9 T137 9
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3339 1 T17 4 T18 8 T66 17
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3068 1 T9 193 T137 2 T14 87
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3229 1 T9 4 T18 9 T19 7
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 945 1 T6 1 T14 34 T77 2
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1206 1 T14 1 T26 6 T91 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 888 1 T4 3 T17 2 T19 4
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1047 1 T17 17 T137 1 T26 22
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4253 1 T66 9 T91 10 T144 7
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 958 1 T18 4 T66 3 T26 5
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1166 1 T19 5 T46 1 T66 4
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 955 1 T6 1 T19 1 T137 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2016 1 T6 2 T14 58 T30 25
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2283 1 T19 1 T14 98 T49 1
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1912 1 T17 6 T14 5 T95 20
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2062 1 T9 1 T19 6 T66 9
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2474 1 T9 24 T18 4 T137 3
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2153 1 T18 3 T66 7 T14 4
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2137 1 T6 1 T9 136 T14 64
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2169 1 T4 1 T9 3 T18 7

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