Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18500445	1			T1	3274		T3	8474		T4	68172
all_pins[1]	18500445	1			T1	3274		T3	8474		T4	68172
all_pins[2]	18500445	1			T1	3274		T3	8474		T4	68172

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47281850	1			T1	8123		T3	20050		T4	181862
values[0x1]	8219485	1			T1	1699		T3	5372		T4	22654
transitions[0x0=>0x1]	8219308	1			T1	1699		T3	5372		T4	22654
transitions[0x1=>0x0]	8219326	1			T1	1699		T3	5372		T4	22654

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18478973	1			T1	3269		T3	8451		T4	67999
all_pins[0]	values[0x1]	21472	1			T1	5		T3	23		T4	173
all_pins[0]	transitions[0x0=>0x1]	21397	1			T1	5		T3	23		T4	173
all_pins[0]	transitions[0x1=>0x0]	8197584	1			T1	1694		T3	5349		T4	22481
all_pins[1]	values[0x0]	18500073	1			T1	3274		T3	8474		T4	68172
all_pins[1]	values[0x1]	372	1			T49	1		T10	13		T8	1
all_pins[1]	transitions[0x0=>0x1]	319	1			T49	1		T10	9		T8	1
all_pins[1]	transitions[0x1=>0x0]	21419	1			T1	5		T3	23		T4	173
all_pins[2]	values[0x0]	10302804	1			T1	1580		T3	3125		T4	45691
all_pins[2]	values[0x1]	8197641	1			T1	1694		T3	5349		T4	22481
all_pins[2]	transitions[0x0=>0x1]	8197592	1			T1	1694		T3	5349		T4	22481
all_pins[2]	transitions[0x1=>0x0]	323	1			T49	1		T10	11		T8	1