Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 942 1 T49 4 T10 59 T8 4
all_values[1] 942 1 T49 4 T10 59 T8 4
all_values[2] 942 1 T49 4 T10 59 T8 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1440 1 T49 2 T10 84 T8 6
auto[1] 1386 1 T49 10 T10 93 T8 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 973 1 T49 2 T10 58 T8 1
auto[1] 1853 1 T49 10 T10 119 T8 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1605 1 T49 5 T10 97 T8 5
auto[1] 1221 1 T49 7 T10 80 T8 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 182 1 T10 10 T80 3 T11 2
all_values[0] auto[0] auto[0] auto[1] 98 1 T10 8 T8 1 T11 3
all_values[0] auto[0] auto[1] auto[0] 169 1 T10 10 T80 3 T11 1
all_values[0] auto[0] auto[1] auto[1] 92 1 T49 1 T10 4 T80 1
all_values[0] auto[1] auto[0] auto[1] 205 1 T10 15 T8 1 T80 2
all_values[0] auto[1] auto[1] auto[1] 196 1 T49 3 T10 12 T8 2
all_values[1] auto[0] auto[0] auto[0] 126 1 T10 4 T8 1 T80 1
all_values[1] auto[0] auto[0] auto[1] 143 1 T10 10 T8 1 T80 2
all_values[1] auto[0] auto[1] auto[0] 149 1 T49 1 T10 11 T80 1
all_values[1] auto[0] auto[1] auto[1] 111 1 T49 1 T10 5 T80 2
all_values[1] auto[1] auto[0] auto[1] 227 1 T49 1 T10 11 T8 1
all_values[1] auto[1] auto[1] auto[1] 186 1 T49 1 T10 18 T8 1
all_values[2] auto[0] auto[0] auto[0] 182 1 T10 10 T80 2 T11 2
all_values[2] auto[0] auto[0] auto[1] 92 1 T10 6 T8 1 T80 1
all_values[2] auto[0] auto[1] auto[0] 165 1 T49 1 T10 13 T80 2
all_values[2] auto[0] auto[1] auto[1] 96 1 T49 1 T10 6 T8 1
all_values[2] auto[1] auto[0] auto[1] 185 1 T49 1 T10 10 T80 2
all_values[2] auto[1] auto[1] auto[1] 222 1 T49 1 T10 14 T8 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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