Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4481	1			T1	2		T3	11		T4	37
sha2_none	4487	1			T1	1		T3	9		T4	52
sha2_512	7853	1			T1	3		T3	9		T4	46
sha2_384	7633	1			T1	3		T3	7		T4	54
sha2_256	6678	1			T1	2		T3	11		T4	69

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19587

1

T1

6

T3

29

T4

137

auto[1]

11935

1

T1

5

T3

18

T4

127

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11956

1

T1

8

T3

19

T4

131

auto[1]

19566

1

T1

3

T3

28

T4

133

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16165

1

T1

7

T3

28

T4

130

disabled

15357

1

T1

4

T3

19

T4

134

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4853	1			T1	2		T3	13		T4	45
key_none	7986	1			T1	2		T3	11		T4	40
key_1024	4530	1			T1	1		T3	5		T4	43
key_512	4052	1			T3	1		T4	33		T5	1
key_384	3659	1			T1	3		T3	6		T4	35
key_256	3238	1			T1	1		T3	7		T4	30
key_128	3125	1			T1	2		T3	4		T4	36

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19579

1

T1

6

T3

28

T4

136

auto[1]

11943

1

T1

5

T3

19

T4

128

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31327

1

T1

11

T3

46

T4

264

disabled

195

1

T3

1

T17

2

T14

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1630

1

T1

1

T3

4

T4

16

enabled

auto[0]

auto[0]

auto[1]

1657

1

T1

2

T3

4

T4

16

enabled

auto[0]

auto[1]

auto[0]

1669

1

T1

2

T3

3

T4

20

enabled

auto[0]

auto[1]

auto[1]

1676

1

T4

14

T5

3

T6

16

enabled

auto[1]

auto[0]

auto[0]

4422

1

T1

1

T3

6

T4

14

enabled

auto[1]

auto[0]

auto[1]

1681

1

T3

4

T4

14

T5

2

enabled

auto[1]

auto[1]

auto[0]

1772

1

T1

1

T3

4

T4

14

enabled

auto[1]

auto[1]

auto[1]

1658

1

T3

3

T4

22

T5

4

disabled

auto[0]

auto[0]

auto[0]

1333

1

T3

4

T4

20

T5

1

disabled

auto[0]

auto[0]

auto[1]

1350

1

T1

2

T3

1

T4

16

disabled

auto[0]

auto[1]

auto[0]

1338

1

T3

1

T4

18

T5

3

disabled

auto[0]

auto[1]

auto[1]

1303

1

T1

1

T3

2

T4

11

disabled

auto[1]

auto[0]

auto[0]

6147

1

T3

3

T4

18

T5

2

disabled

auto[1]

auto[0]

auto[1]

1367

1

T3

3

T4

23

T5

3

disabled

auto[1]

auto[1]

auto[0]

1268

1

T1

1

T3

3

T4

16

disabled

auto[1]

auto[1]

auto[1]

1251

1

T3

2

T4

12

T5

5

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16094

1

T1

7

T3

28

T4

130

enabled

disabled

71

1

T17

1

T94

2

T10

1

disabled

disabled

124

1

T3

1

T17

1

T14

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15233

1

T1

4

T3

18

T4

134

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1173	1			T1	1		T3	3		T4	10
key_invalid	sha2_none	875	1			T3	4		T4	7		T5	2
key_invalid	sha2_512	885	1			T1	1		T3	2		T4	6
key_invalid	sha2_384	895	1			T3	2		T4	8		T5	3
key_invalid	sha2_256	930	1			T3	2		T4	14		T5	3
key_none	sha2_invalid	536	1			T3	1		T4	3		T5	2
key_none	sha2_none	581	1			T3	2		T4	8		T5	2
key_none	sha2_512	2576	1			T3	4		T4	10		T5	2
key_none	sha2_384	2609	1			T1	2		T3	1		T4	10
key_none	sha2_256	1630	1			T3	3		T4	7		T5	3
key_1024	sha2_invalid	543	1			T3	2		T4	6		T5	2
key_1024	sha2_none	604	1			T3	1		T4	11		T5	1
key_1024	sha2_512	1773	1			T4	8		T5	2		T6	11
key_1024	sha2_384	926	1			T1	1		T4	6		T6	6
key_512	sha2_invalid	566	1			T3	1		T4	3		T6	7
key_512	sha2_none	630	1			T4	9		T5	1		T6	5
key_512	sha2_512	644	1			T4	8		T6	7		T17	1
key_512	sha2_384	1248	1			T4	4		T6	2		T18	1
key_512	sha2_256	916	1			T4	7		T6	3		T9	1
key_384	sha2_invalid	565	1			T3	2		T4	4		T5	2
key_384	sha2_none	594	1			T3	1		T4	7		T5	1
key_384	sha2_512	644	1			T1	2		T3	2		T4	1
key_384	sha2_384	665	1			T3	1		T4	13		T5	1
key_384	sha2_256	1140	1			T1	1		T4	10		T5	1
key_256	sha2_invalid	544	1			T3	1		T4	1		T5	1
key_256	sha2_none	592	1			T1	1		T3	1		T4	4
key_256	sha2_512	638	1			T4	8		T5	4		T6	6
key_256	sha2_384	635	1			T3	3		T4	6		T5	1
key_256	sha2_256	786	1			T3	2		T4	10		T5	2
key_128	sha2_invalid	535	1			T1	1		T3	1		T4	10
key_128	sha2_none	598	1			T4	5		T5	1		T6	6
key_128	sha2_512	681	1			T3	1		T4	5		T5	2
key_128	sha2_384	635	1			T4	6		T5	1		T6	5
key_128	sha2_256	633	1			T1	1		T3	2		T4	10

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

628

1

T3

2

T4

11

T6

6

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1173	1			T1	1		T3	3		T4	10
key_invalid	sha2_none	875	1			T3	4		T4	7		T5	2
key_invalid	sha2_512	885	1			T1	1		T3	2		T4	6
key_invalid	sha2_384	895	1			T3	2		T4	8		T5	3
key_invalid	sha2_256	930	1			T3	2		T4	14		T5	3
key_none	sha2_invalid	536	1			T3	1		T4	3		T5	2
key_none	sha2_none	581	1			T3	2		T4	8		T5	2
key_none	sha2_512	2576	1			T3	4		T4	10		T5	2
key_none	sha2_384	2609	1			T1	2		T3	1		T4	10
key_none	sha2_256	1630	1			T3	3		T4	7		T5	3
key_1024	sha2_invalid	543	1			T3	2		T4	6		T5	2
key_1024	sha2_none	604	1			T3	1		T4	11		T5	1
key_1024	sha2_512	1773	1			T4	8		T5	2		T6	11
key_1024	sha2_384	926	1			T1	1		T4	6		T6	6
key_1024	sha2_256	628	1			T3	2		T4	11		T6	6
key_512	sha2_invalid	566	1			T3	1		T4	3		T6	7
key_512	sha2_none	630	1			T4	9		T5	1		T6	5
key_512	sha2_512	644	1			T4	8		T6	7		T17	1
key_512	sha2_384	1248	1			T4	4		T6	2		T18	1
key_512	sha2_256	916	1			T4	7		T6	3		T9	1
key_384	sha2_invalid	565	1			T3	2		T4	4		T5	2
key_384	sha2_none	594	1			T3	1		T4	7		T5	1
key_384	sha2_512	644	1			T1	2		T3	2		T4	1
key_384	sha2_384	665	1			T3	1		T4	13		T5	1
key_384	sha2_256	1140	1			T1	1		T4	10		T5	1
key_256	sha2_invalid	544	1			T3	1		T4	1		T5	1
key_256	sha2_none	592	1			T1	1		T3	1		T4	4
key_256	sha2_512	638	1			T4	8		T5	4		T6	6
key_256	sha2_384	635	1			T3	3		T4	6		T5	1
key_256	sha2_256	786	1			T3	2		T4	10		T5	2
key_128	sha2_invalid	535	1			T1	1		T3	1		T4	10
key_128	sha2_none	598	1			T4	5		T5	1		T6	6
key_128	sha2_512	681	1			T3	1		T4	5		T5	2
key_128	sha2_384	635	1			T4	6		T5	1		T6	5
key_128	sha2_256	633	1			T1	1		T3	2		T4	10