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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 95.40 97.17 100.00 94.12 98.27 98.48 99.85


Total test records in report: 660
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T535 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1654933339 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:54 PM PDT 24 86530948 ps
T536 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2469634868 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:53 PM PDT 24 120610855 ps
T537 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1538358687 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:16 PM PDT 24 12817978 ps
T538 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1597320947 Jul 13 06:06:51 PM PDT 24 Jul 13 06:07:28 PM PDT 24 16504866 ps
T539 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1982772880 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:52 PM PDT 24 22846782 ps
T540 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2445927313 Jul 13 06:07:00 PM PDT 24 Jul 13 06:07:58 PM PDT 24 50365969 ps
T541 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3624262770 Jul 13 06:06:33 PM PDT 24 Jul 13 06:06:40 PM PDT 24 336920565 ps
T542 /workspace/coverage/cover_reg_top/16.hmac_intr_test.473771972 Jul 13 06:07:06 PM PDT 24 Jul 13 06:08:12 PM PDT 24 32774059 ps
T543 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1615371907 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:51 PM PDT 24 173219174 ps
T544 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4234184501 Jul 13 06:07:05 PM PDT 24 Jul 13 06:08:13 PM PDT 24 65967699 ps
T545 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.290665393 Jul 13 06:07:00 PM PDT 24 Jul 13 06:08:00 PM PDT 24 337848781 ps
T64 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3682105906 Jul 13 06:07:04 PM PDT 24 Jul 13 06:08:11 PM PDT 24 66942545 ps
T546 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2613992919 Jul 13 06:07:09 PM PDT 24 Jul 13 06:08:15 PM PDT 24 34927819 ps
T547 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3341670442 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:57 PM PDT 24 13904593 ps
T118 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1032674486 Jul 13 06:06:40 PM PDT 24 Jul 13 06:06:50 PM PDT 24 298492429 ps
T548 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.658971908 Jul 13 06:07:01 PM PDT 24 Jul 13 06:08:00 PM PDT 24 26508789 ps
T549 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1332511734 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:16 PM PDT 24 14704337 ps
T119 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4225347126 Jul 13 06:06:53 PM PDT 24 Jul 13 06:07:39 PM PDT 24 116909755 ps
T550 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3790499416 Jul 13 06:06:37 PM PDT 24 Jul 13 06:06:40 PM PDT 24 40715297 ps
T551 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2187486933 Jul 13 06:07:04 PM PDT 24 Jul 13 06:08:12 PM PDT 24 400931061 ps
T552 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2515630667 Jul 13 06:06:51 PM PDT 24 Jul 13 06:07:29 PM PDT 24 109090209 ps
T553 /workspace/coverage/cover_reg_top/30.hmac_intr_test.215418050 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:16 PM PDT 24 36384162 ps
T554 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3473059748 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:51 PM PDT 24 56831833 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1258765345 Jul 13 06:06:33 PM PDT 24 Jul 13 06:06:36 PM PDT 24 128788746 ps
T555 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1818686961 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:53 PM PDT 24 139837208 ps
T556 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.682326062 Jul 13 06:07:04 PM PDT 24 Jul 13 06:08:08 PM PDT 24 118410277 ps
T557 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3777411441 Jul 13 06:07:09 PM PDT 24 Jul 13 06:08:15 PM PDT 24 54606108 ps
T558 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2635898123 Jul 13 06:07:12 PM PDT 24 Jul 13 06:08:19 PM PDT 24 13309636 ps
T101 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1053655914 Jul 13 06:06:43 PM PDT 24 Jul 13 06:07:01 PM PDT 24 2053899003 ps
T65 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3551220410 Jul 13 06:07:06 PM PDT 24 Jul 13 06:08:16 PM PDT 24 567429480 ps
T128 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1490645350 Jul 13 06:06:33 PM PDT 24 Jul 13 06:06:40 PM PDT 24 133728424 ps
T559 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3179015493 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:16 PM PDT 24 57573360 ps
T560 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1492897928 Jul 13 06:06:50 PM PDT 24 Jul 13 06:07:27 PM PDT 24 17384095 ps
T561 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1827218960 Jul 13 06:06:51 PM PDT 24 Jul 13 06:07:29 PM PDT 24 70600364 ps
T562 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2121650522 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:13 PM PDT 24 42159172 ps
T563 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2799811438 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:45 PM PDT 24 140145481 ps
T564 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3027302796 Jul 13 06:07:13 PM PDT 24 Jul 13 06:08:19 PM PDT 24 29569075 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1797694091 Jul 13 06:06:49 PM PDT 24 Jul 13 06:07:23 PM PDT 24 82251966 ps
T565 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3440588409 Jul 13 06:06:44 PM PDT 24 Jul 13 06:07:05 PM PDT 24 224948724 ps
T566 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.845364826 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:54 PM PDT 24 178900497 ps
T567 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3271118895 Jul 13 06:06:44 PM PDT 24 Jul 13 06:07:00 PM PDT 24 30142850 ps
T568 /workspace/coverage/cover_reg_top/5.hmac_intr_test.406179327 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:09 PM PDT 24 15869890 ps
T569 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2728661461 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:52 PM PDT 24 14643687 ps
T570 /workspace/coverage/cover_reg_top/46.hmac_intr_test.577484236 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 54369153 ps
T571 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.400363709 Jul 13 06:06:38 PM PDT 24 Jul 13 06:06:44 PM PDT 24 185705560 ps
T130 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.688935867 Jul 13 06:07:00 PM PDT 24 Jul 13 06:07:59 PM PDT 24 361129157 ps
T129 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3801981770 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:53 PM PDT 24 639099809 ps
T572 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3969818048 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:52 PM PDT 24 58221351 ps
T573 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2622540988 Jul 13 06:06:49 PM PDT 24 Jul 13 06:07:23 PM PDT 24 51229277 ps
T120 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1872896550 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:44 PM PDT 24 28362407 ps
T136 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2288813915 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:18 PM PDT 24 3562482334 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.273655856 Jul 13 06:06:44 PM PDT 24 Jul 13 06:07:05 PM PDT 24 431124636 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1236687518 Jul 13 06:06:48 PM PDT 24 Jul 13 06:07:19 PM PDT 24 33023845 ps
T575 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2616262820 Jul 13 06:07:01 PM PDT 24 Jul 13 06:07:59 PM PDT 24 68988885 ps
T576 /workspace/coverage/cover_reg_top/40.hmac_intr_test.376178576 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:16 PM PDT 24 46803256 ps
T132 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4101830059 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:52 PM PDT 24 157366026 ps
T577 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2981430614 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:54 PM PDT 24 70847143 ps
T131 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1351726696 Jul 13 06:06:52 PM PDT 24 Jul 13 06:07:32 PM PDT 24 340000848 ps
T104 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2932954866 Jul 13 06:06:50 PM PDT 24 Jul 13 06:07:28 PM PDT 24 46822238 ps
T578 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2152077805 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:44 PM PDT 24 228623250 ps
T579 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2518064685 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:54 PM PDT 24 73161833 ps
T121 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3933307314 Jul 13 06:06:51 PM PDT 24 Jul 13 06:07:29 PM PDT 24 84388519 ps
T580 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2622130332 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:15 PM PDT 24 24611740 ps
T581 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1720122016 Jul 13 06:06:42 PM PDT 24 Jul 13 06:07:04 PM PDT 24 1463510556 ps
T105 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2424112712 Jul 13 06:06:47 PM PDT 24 Jul 13 06:07:15 PM PDT 24 21497752 ps
T106 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.212281816 Jul 13 06:07:03 PM PDT 24 Jul 13 06:08:06 PM PDT 24 40725215 ps
T134 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.406129991 Jul 13 06:06:33 PM PDT 24 Jul 13 06:06:40 PM PDT 24 237123266 ps
T582 /workspace/coverage/cover_reg_top/41.hmac_intr_test.4020283237 Jul 13 06:07:22 PM PDT 24 Jul 13 06:08:35 PM PDT 24 23460478 ps
T583 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3557501399 Jul 13 06:07:00 PM PDT 24 Jul 13 06:07:58 PM PDT 24 13680250 ps
T584 /workspace/coverage/cover_reg_top/19.hmac_intr_test.150727782 Jul 13 06:07:02 PM PDT 24 Jul 13 06:08:04 PM PDT 24 24763951 ps
T585 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1807478333 Jul 13 06:07:06 PM PDT 24 Jul 13 06:08:15 PM PDT 24 65063906 ps
T586 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1325338580 Jul 13 06:06:50 PM PDT 24 Jul 13 06:07:27 PM PDT 24 18633670 ps
T587 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.360162783 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:45 PM PDT 24 68371245 ps
T588 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1789273277 Jul 13 06:07:12 PM PDT 24 Jul 13 06:08:19 PM PDT 24 30164084 ps
T589 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3388815659 Jul 13 06:07:00 PM PDT 24 Jul 13 06:08:00 PM PDT 24 108520148 ps
T590 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2826142048 Jul 13 06:07:09 PM PDT 24 Jul 13 06:08:15 PM PDT 24 46275304 ps
T591 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.25423454 Jul 13 06:07:03 PM PDT 24 Jul 13 06:08:09 PM PDT 24 333205739 ps
T592 /workspace/coverage/cover_reg_top/44.hmac_intr_test.271917327 Jul 13 06:07:11 PM PDT 24 Jul 13 06:08:16 PM PDT 24 14849041 ps
T593 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1726397615 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:51 PM PDT 24 24897344 ps
T594 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.726111245 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:45 PM PDT 24 173765780 ps
T107 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.96476423 Jul 13 06:07:01 PM PDT 24 Jul 13 06:07:59 PM PDT 24 20426246 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.439663158 Jul 13 06:06:33 PM PDT 24 Jul 13 06:06:40 PM PDT 24 59286155 ps
T595 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2770760823 Jul 13 06:06:41 PM PDT 24 Jul 13 06:06:52 PM PDT 24 580081614 ps
T109 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2089393253 Jul 13 06:07:02 PM PDT 24 Jul 13 06:08:05 PM PDT 24 32737982 ps
T122 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3819816290 Jul 13 06:06:34 PM PDT 24 Jul 13 06:06:38 PM PDT 24 48571380 ps
T596 /workspace/coverage/cover_reg_top/35.hmac_intr_test.445265401 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 37395242 ps
T123 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1763038465 Jul 13 06:06:47 PM PDT 24 Jul 13 06:07:13 PM PDT 24 108017529 ps
T597 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3006062755 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 14243158 ps
T598 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2428589538 Jul 13 06:06:44 PM PDT 24 Jul 13 06:07:01 PM PDT 24 242040584 ps
T599 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3820284103 Jul 13 06:06:48 PM PDT 24 Jul 13 06:07:20 PM PDT 24 342180866 ps
T135 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3666215739 Jul 13 06:07:05 PM PDT 24 Jul 13 06:08:15 PM PDT 24 294481536 ps
T600 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4208462135 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:10 PM PDT 24 73144914 ps
T601 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2446779161 Jul 13 06:07:04 PM PDT 24 Jul 13 06:08:07 PM PDT 24 64317374 ps
T602 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2560398911 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:10 PM PDT 24 65601908 ps
T603 /workspace/coverage/cover_reg_top/13.hmac_intr_test.767809197 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:44 PM PDT 24 33929065 ps
T110 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3497035078 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:51 PM PDT 24 101620746 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3596048313 Jul 13 06:06:37 PM PDT 24 Jul 13 06:06:41 PM PDT 24 39345780 ps
T112 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.993650749 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:53 PM PDT 24 18825313 ps
T604 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3592061306 Jul 13 06:06:53 PM PDT 24 Jul 13 06:07:38 PM PDT 24 532726226 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.262985744 Jul 13 06:06:43 PM PDT 24 Jul 13 06:06:59 PM PDT 24 29824780 ps
T116 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.147155510 Jul 13 06:06:41 PM PDT 24 Jul 13 06:06:56 PM PDT 24 1962897420 ps
T606 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2783496411 Jul 13 06:07:09 PM PDT 24 Jul 13 06:08:15 PM PDT 24 36193938 ps
T607 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.965102071 Jul 13 06:06:42 PM PDT 24 Jul 13 06:06:54 PM PDT 24 85943568 ps
T608 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1131935109 Jul 13 06:07:04 PM PDT 24 Jul 13 06:08:06 PM PDT 24 117492273 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2875644007 Jul 13 06:06:42 PM PDT 24 Jul 13 06:06:53 PM PDT 24 20448519 ps
T133 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2343138166 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:54 PM PDT 24 94344596 ps
T610 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3013636890 Jul 13 06:06:37 PM PDT 24 Jul 13 06:06:41 PM PDT 24 48258932 ps
T611 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2680050088 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:55 PM PDT 24 187097787 ps
T612 /workspace/coverage/cover_reg_top/39.hmac_intr_test.643949622 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 33287219 ps
T613 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2854061301 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:53 PM PDT 24 408047807 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1084084846 Jul 13 06:07:02 PM PDT 24 Jul 13 06:08:05 PM PDT 24 55224487 ps
T615 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2178108750 Jul 13 06:06:56 PM PDT 24 Jul 13 06:07:45 PM PDT 24 43951298 ps
T616 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2798363042 Jul 13 06:07:06 PM PDT 24 Jul 13 06:08:12 PM PDT 24 23767389 ps
T617 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3825369246 Jul 13 06:06:50 PM PDT 24 Jul 13 06:07:27 PM PDT 24 85220943 ps
T618 /workspace/coverage/cover_reg_top/2.hmac_intr_test.99486398 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:09 PM PDT 24 50645052 ps
T619 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4244445244 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:51 PM PDT 24 68798665 ps
T113 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3042810823 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:52 PM PDT 24 79196594 ps
T620 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4093998464 Jul 13 06:06:49 PM PDT 24 Jul 13 06:07:25 PM PDT 24 154484626 ps
T621 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1506740467 Jul 13 06:07:03 PM PDT 24 Jul 13 06:08:06 PM PDT 24 22151610 ps
T622 /workspace/coverage/cover_reg_top/0.hmac_intr_test.861550994 Jul 13 06:06:33 PM PDT 24 Jul 13 06:06:37 PM PDT 24 20635532 ps
T623 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1292720110 Jul 13 06:07:07 PM PDT 24 Jul 13 06:08:12 PM PDT 24 43986968 ps
T624 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2708873396 Jul 13 06:06:48 PM PDT 24 Jul 13 06:07:25 PM PDT 24 226509404 ps
T625 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2859637623 Jul 13 06:07:11 PM PDT 24 Jul 13 06:08:16 PM PDT 24 28246113 ps
T626 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2876600000 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 12018367 ps
T627 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2832865814 Jul 13 06:07:00 PM PDT 24 Jul 13 06:07:59 PM PDT 24 269576105 ps
T628 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2092193971 Jul 13 06:06:55 PM PDT 24 Jul 13 06:07:44 PM PDT 24 43423040 ps
T114 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3166809040 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:50 PM PDT 24 54169890 ps
T629 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2737047795 Jul 13 06:07:10 PM PDT 24 Jul 13 06:08:15 PM PDT 24 15245396 ps
T630 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.142827589 Jul 13 06:07:01 PM PDT 24 Jul 13 06:08:00 PM PDT 24 27626970 ps
T631 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2689296159 Jul 13 06:06:37 PM PDT 24 Jul 13 06:06:46 PM PDT 24 431938333 ps
T632 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3800264683 Jul 13 06:07:00 PM PDT 24 Jul 13 06:08:00 PM PDT 24 207582988 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2894618836 Jul 13 06:06:40 PM PDT 24 Jul 13 06:06:53 PM PDT 24 2122489676 ps
T634 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1273868948 Jul 13 06:06:57 PM PDT 24 Jul 13 06:07:52 PM PDT 24 105036772 ps
T635 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.416498834 Jul 13 06:06:37 PM PDT 24 Jul 13 06:06:41 PM PDT 24 25169684 ps
T636 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1312443920 Jul 13 06:07:02 PM PDT 24 Jul 13 06:08:05 PM PDT 24 56897896 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.458383254 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:14 PM PDT 24 44292929 ps
T638 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.5973995 Jul 13 06:07:01 PM PDT 24 Jul 13 06:07:59 PM PDT 24 25533912 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4051695557 Jul 13 06:07:02 PM PDT 24 Jul 13 06:08:06 PM PDT 24 29598007 ps
T640 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1581303841 Jul 13 06:06:59 PM PDT 24 Jul 13 06:18:10 PM PDT 24 190125664190 ps
T641 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.577120315 Jul 13 06:07:01 PM PDT 24 Jul 13 06:08:02 PM PDT 24 794303690 ps
T642 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1773601882 Jul 13 06:07:09 PM PDT 24 Jul 13 06:08:15 PM PDT 24 16521464 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3062564149 Jul 13 06:06:44 PM PDT 24 Jul 13 06:07:03 PM PDT 24 652893277 ps
T644 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3054082614 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 57746502 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.821227660 Jul 13 06:06:38 PM PDT 24 Jul 13 06:06:45 PM PDT 24 83657104 ps
T646 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2653092020 Jul 13 06:07:03 PM PDT 24 Jul 13 06:08:07 PM PDT 24 133320818 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2648007594 Jul 13 06:06:41 PM PDT 24 Jul 13 06:06:50 PM PDT 24 29951789 ps
T648 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1881754778 Jul 13 06:06:45 PM PDT 24 Jul 13 06:07:06 PM PDT 24 37199828 ps
T649 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2650865299 Jul 13 06:07:00 PM PDT 24 Jul 13 06:08:01 PM PDT 24 331756993 ps
T650 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2605821606 Jul 13 06:07:01 PM PDT 24 Jul 13 06:07:59 PM PDT 24 41835970 ps
T651 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3022162723 Jul 13 06:07:03 PM PDT 24 Jul 13 06:08:06 PM PDT 24 38891931 ps
T115 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.562616536 Jul 13 06:06:46 PM PDT 24 Jul 13 06:07:18 PM PDT 24 215038711 ps
T652 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.420455893 Jul 13 06:06:58 PM PDT 24 Jul 13 06:07:53 PM PDT 24 26163959 ps
T653 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1166983804 Jul 13 06:06:41 PM PDT 24 Jul 13 06:06:51 PM PDT 24 333969449 ps
T654 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1389173957 Jul 13 06:06:41 PM PDT 24 Jul 13 06:06:50 PM PDT 24 90211614 ps
T655 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2935696474 Jul 13 06:07:02 PM PDT 24 Jul 13 06:08:07 PM PDT 24 185164380 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.808035201 Jul 13 06:06:59 PM PDT 24 Jul 13 06:07:53 PM PDT 24 136791116 ps
T657 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2347418525 Jul 13 06:06:44 PM PDT 24 Jul 13 06:07:02 PM PDT 24 157443141 ps
T658 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4206591700 Jul 13 06:06:51 PM PDT 24 Jul 13 06:07:28 PM PDT 24 41218630 ps
T659 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2138273278 Jul 13 06:07:08 PM PDT 24 Jul 13 06:08:15 PM PDT 24 43404148 ps
T660 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.739539121 Jul 13 06:06:55 PM PDT 24 Jul 13 06:07:45 PM PDT 24 170788725 ps

Test location /workspace/coverage/default/10.hmac_stress_all.2687974856
Short name T6
Test name
Test status
Simulation time 31107008710 ps
CPU time 646.26 seconds
Started Jul 13 06:07:57 PM PDT 24
Finished Jul 13 06:19:59 PM PDT 24
Peak memory 623124 kb
Host smart-6429268f-a3ee-476b-8278-7ee3a3b3cd8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687974856 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2687974856
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.779779507
Short name T10
Test name
Test status
Simulation time 454127578890 ps
CPU time 1916.77 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:40:46 PM PDT 24
Peak memory 708100 kb
Host smart-5973d038-7669-4c99-b4b7-859c45de7660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779779507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.779779507
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2026160501
Short name T15
Test name
Test status
Simulation time 36526844807 ps
CPU time 486.87 seconds
Started Jul 13 06:10:01 PM PDT 24
Finished Jul 13 06:19:31 PM PDT 24
Peak memory 223664 kb
Host smart-ba450219-68f8-4367-8cbb-2c40ee46f4aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026160501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2026160501
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3551220410
Short name T65
Test name
Test status
Simulation time 567429480 ps
CPU time 4.44 seconds
Started Jul 13 06:07:06 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 198676 kb
Host smart-06c230c0-c011-401d-b5c3-2ba86662f8ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551220410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3551220410
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3581827664
Short name T4
Test name
Test status
Simulation time 71260249558 ps
CPU time 505.54 seconds
Started Jul 13 06:08:02 PM PDT 24
Finished Jul 13 06:17:40 PM PDT 24
Peak memory 558088 kb
Host smart-88ae7fb5-6b5c-463d-970e-e85793afe48a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581827664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3581827664
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2068186592
Short name T50
Test name
Test status
Simulation time 128103556 ps
CPU time 0.8 seconds
Started Jul 13 06:07:21 PM PDT 24
Finished Jul 13 06:08:35 PM PDT 24
Peak memory 218424 kb
Host smart-b0b6f7ef-5d53-4e10-974f-a0b755a03c26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068186592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2068186592
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2322133773
Short name T14
Test name
Test status
Simulation time 9956029956 ps
CPU time 949.65 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:24:20 PM PDT 24
Peak memory 713216 kb
Host smart-ff467f71-5d8e-4220-8e40-54cc5be80128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322133773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2322133773
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2089393253
Short name T109
Test name
Test status
Simulation time 32737982 ps
CPU time 0.95 seconds
Started Jul 13 06:07:02 PM PDT 24
Finished Jul 13 06:08:05 PM PDT 24
Peak memory 200116 kb
Host smart-2cfecca6-f2fa-4a2f-8d1d-2fe0cd7aff7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089393253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2089393253
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/default/35.hmac_stress_all.957684305
Short name T22
Test name
Test status
Simulation time 36268952009 ps
CPU time 5265.02 seconds
Started Jul 13 06:09:19 PM PDT 24
Finished Jul 13 07:38:21 PM PDT 24
Peak memory 856036 kb
Host smart-45b41d58-185d-4fb5-9746-210968646efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957684305 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.957684305
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3666215739
Short name T135
Test name
Test status
Simulation time 294481536 ps
CPU time 4.2 seconds
Started Jul 13 06:07:05 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 200180 kb
Host smart-b5ee446d-9cd4-4b9d-9aff-1e18838d21c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666215739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3666215739
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/32.hmac_stress_all.82516321
Short name T140
Test name
Test status
Simulation time 17392707989 ps
CPU time 1128.8 seconds
Started Jul 13 06:09:11 PM PDT 24
Finished Jul 13 06:29:15 PM PDT 24
Peak memory 615980 kb
Host smart-86943aea-3b2f-4a6a-859f-d095feabe66d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82516321 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.82516321
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3120230897
Short name T31
Test name
Test status
Simulation time 47663189 ps
CPU time 0.6 seconds
Started Jul 13 06:08:09 PM PDT 24
Finished Jul 13 06:09:21 PM PDT 24
Peak memory 196132 kb
Host smart-7b4058cb-6c86-4987-a2b8-36b207e2f698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120230897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3120230897
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3801981770
Short name T129
Test name
Test status
Simulation time 639099809 ps
CPU time 1.88 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 200312 kb
Host smart-921968d1-c001-4c4c-8b25-022e409b0815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801981770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3801981770
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.204774345
Short name T47
Test name
Test status
Simulation time 893811461772 ps
CPU time 2841.78 seconds
Started Jul 13 06:07:13 PM PDT 24
Finished Jul 13 06:55:41 PM PDT 24
Peak memory 215984 kb
Host smart-e1c827db-f821-4f2e-86a8-a9f7a9d3a156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=204774345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.204774345
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_error.1898838331
Short name T17
Test name
Test status
Simulation time 2783883474 ps
CPU time 142.95 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:10:53 PM PDT 24
Peak memory 200112 kb
Host smart-fe581809-d846-4581-a076-3a754d9f909c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898838331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1898838331
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.439663158
Short name T108
Test name
Test status
Simulation time 59286155 ps
CPU time 3.04 seconds
Started Jul 13 06:06:33 PM PDT 24
Finished Jul 13 06:06:40 PM PDT 24
Peak memory 200216 kb
Host smart-f4564849-5173-42eb-9b9e-6385cd708976
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439663158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.439663158
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2689296159
Short name T631
Test name
Test status
Simulation time 431938333 ps
CPU time 5.15 seconds
Started Jul 13 06:06:37 PM PDT 24
Finished Jul 13 06:06:46 PM PDT 24
Peak memory 200312 kb
Host smart-fd042508-3f26-4acb-a001-d51adafbf92a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689296159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2689296159
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1258765345
Short name T100
Test name
Test status
Simulation time 128788746 ps
CPU time 1.02 seconds
Started Jul 13 06:06:33 PM PDT 24
Finished Jul 13 06:06:36 PM PDT 24
Peak memory 199772 kb
Host smart-621195f6-2e2f-465c-b736-741ad07c83c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258765345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1258765345
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3624262770
Short name T541
Test name
Test status
Simulation time 336920565 ps
CPU time 3.33 seconds
Started Jul 13 06:06:33 PM PDT 24
Finished Jul 13 06:06:40 PM PDT 24
Peak memory 208540 kb
Host smart-84abef93-287b-40c1-a7b0-76b6a416796d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624262770 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3624262770
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.416498834
Short name T635
Test name
Test status
Simulation time 25169684 ps
CPU time 0.86 seconds
Started Jul 13 06:06:37 PM PDT 24
Finished Jul 13 06:06:41 PM PDT 24
Peak memory 199572 kb
Host smart-6fc6b47f-d86c-4656-a5c4-6c2900ed54da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416498834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.416498834
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.861550994
Short name T622
Test name
Test status
Simulation time 20635532 ps
CPU time 0.7 seconds
Started Jul 13 06:06:33 PM PDT 24
Finished Jul 13 06:06:37 PM PDT 24
Peak memory 195228 kb
Host smart-8307a665-7e19-4e8b-a525-0518c3362b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861550994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.861550994
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3819816290
Short name T122
Test name
Test status
Simulation time 48571380 ps
CPU time 1.19 seconds
Started Jul 13 06:06:34 PM PDT 24
Finished Jul 13 06:06:38 PM PDT 24
Peak memory 198808 kb
Host smart-b0e4a8e6-9eb2-4a47-9c70-5391e84db39e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819816290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3819816290
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.400363709
Short name T571
Test name
Test status
Simulation time 185705560 ps
CPU time 2.57 seconds
Started Jul 13 06:06:38 PM PDT 24
Finished Jul 13 06:06:44 PM PDT 24
Peak memory 200344 kb
Host smart-155554b6-d3d4-4887-8e0c-16ffb8801b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400363709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.400363709
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1490645350
Short name T128
Test name
Test status
Simulation time 133728424 ps
CPU time 4.13 seconds
Started Jul 13 06:06:33 PM PDT 24
Finished Jul 13 06:06:40 PM PDT 24
Peak memory 200280 kb
Host smart-cb3ca400-aad9-42b9-b9e1-bd790aac40d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490645350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1490645350
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.273655856
Short name T574
Test name
Test status
Simulation time 431124636 ps
CPU time 5.8 seconds
Started Jul 13 06:06:44 PM PDT 24
Finished Jul 13 06:07:05 PM PDT 24
Peak memory 200424 kb
Host smart-a6b7cbc8-b05c-4689-b9d0-12440dd78a06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273655856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.273655856
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3440588409
Short name T565
Test name
Test status
Simulation time 224948724 ps
CPU time 5.21 seconds
Started Jul 13 06:06:44 PM PDT 24
Finished Jul 13 06:07:05 PM PDT 24
Peak memory 199536 kb
Host smart-74f8cb1e-f151-461c-8eed-cbeea854690c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440588409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3440588409
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3596048313
Short name T111
Test name
Test status
Simulation time 39345780 ps
CPU time 1 seconds
Started Jul 13 06:06:37 PM PDT 24
Finished Jul 13 06:06:41 PM PDT 24
Peak memory 200096 kb
Host smart-be95d835-ded8-43d9-ab0b-b60b1a86d671
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596048313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3596048313
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2428589538
Short name T598
Test name
Test status
Simulation time 242040584 ps
CPU time 1.66 seconds
Started Jul 13 06:06:44 PM PDT 24
Finished Jul 13 06:07:01 PM PDT 24
Peak memory 200584 kb
Host smart-f3d8cf33-6173-4e9d-bd8b-265deb5cc2b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428589538 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2428589538
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3271118895
Short name T567
Test name
Test status
Simulation time 30142850 ps
CPU time 0.73 seconds
Started Jul 13 06:06:44 PM PDT 24
Finished Jul 13 06:07:00 PM PDT 24
Peak memory 198460 kb
Host smart-fc080ba3-50b3-43a2-bf48-e34b07fe9d0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271118895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3271118895
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3790499416
Short name T550
Test name
Test status
Simulation time 40715297 ps
CPU time 0.58 seconds
Started Jul 13 06:06:37 PM PDT 24
Finished Jul 13 06:06:40 PM PDT 24
Peak memory 195180 kb
Host smart-c9dcaa01-7c62-4185-bac1-b6532908e6d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790499416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3790499416
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3013636890
Short name T610
Test name
Test status
Simulation time 48258932 ps
CPU time 1.18 seconds
Started Jul 13 06:06:37 PM PDT 24
Finished Jul 13 06:06:41 PM PDT 24
Peak memory 200184 kb
Host smart-ed624c38-733c-4f26-a8e6-cd6cf95d187a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013636890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3013636890
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2347418525
Short name T657
Test name
Test status
Simulation time 157443141 ps
CPU time 3.01 seconds
Started Jul 13 06:06:44 PM PDT 24
Finished Jul 13 06:07:02 PM PDT 24
Peak memory 200476 kb
Host smart-457700c6-690e-4d15-af4e-075596c01e08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347418525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2347418525
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.821227660
Short name T645
Test name
Test status
Simulation time 83657104 ps
CPU time 1.87 seconds
Started Jul 13 06:06:38 PM PDT 24
Finished Jul 13 06:06:45 PM PDT 24
Peak memory 200240 kb
Host smart-d61735ca-6b89-4751-9d7f-df945f79b4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821227660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.821227660
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.360162783
Short name T587
Test name
Test status
Simulation time 68371245 ps
CPU time 1.93 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:45 PM PDT 24
Peak memory 200332 kb
Host smart-5117a594-57ce-481e-939b-d9f3cd216b33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360162783 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.360162783
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1726397615
Short name T593
Test name
Test status
Simulation time 24897344 ps
CPU time 0.83 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:51 PM PDT 24
Peak memory 200096 kb
Host smart-e6069bf7-d4d4-4b51-9033-714cfd7508b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726397615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1726397615
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1492897928
Short name T560
Test name
Test status
Simulation time 17384095 ps
CPU time 0.6 seconds
Started Jul 13 06:06:50 PM PDT 24
Finished Jul 13 06:07:27 PM PDT 24
Peak memory 195156 kb
Host smart-6e689b31-2fc7-4134-8a74-a561b2d551a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492897928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1492897928
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3825369246
Short name T617
Test name
Test status
Simulation time 85220943 ps
CPU time 1.13 seconds
Started Jul 13 06:06:50 PM PDT 24
Finished Jul 13 06:07:27 PM PDT 24
Peak memory 200184 kb
Host smart-f6f96748-4426-4147-99f0-9a2cb28afde9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825369246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3825369246
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2680050088
Short name T611
Test name
Test status
Simulation time 187097787 ps
CPU time 3.95 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:55 PM PDT 24
Peak memory 200284 kb
Host smart-a35c1d78-ce9c-4b2c-ac2a-e4abcd65f23e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680050088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2680050088
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.739539121
Short name T660
Test name
Test status
Simulation time 170788725 ps
CPU time 1.75 seconds
Started Jul 13 06:06:55 PM PDT 24
Finished Jul 13 06:07:45 PM PDT 24
Peak memory 200276 kb
Host smart-38d5f9b8-c23e-4c3b-ac95-55ea4f93f32d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739539121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.739539121
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2152077805
Short name T578
Test name
Test status
Simulation time 228623250 ps
CPU time 1.23 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:44 PM PDT 24
Peak memory 200244 kb
Host smart-85ec6c62-8e43-4a33-9f45-0cf51e6df813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152077805 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2152077805
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.993650749
Short name T112
Test name
Test status
Simulation time 18825313 ps
CPU time 0.9 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 200096 kb
Host smart-30ad7556-7f0e-423e-9cb0-8ac60319cf8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993650749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.993650749
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2728661461
Short name T569
Test name
Test status
Simulation time 14643687 ps
CPU time 0.56 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:52 PM PDT 24
Peak memory 195152 kb
Host smart-eb8f148d-b327-4a47-ad38-a0cb72851ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728661461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2728661461
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2178108750
Short name T615
Test name
Test status
Simulation time 43951298 ps
CPU time 2.09 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:45 PM PDT 24
Peak memory 200304 kb
Host smart-d3f2e823-a1d8-43da-b2c4-325b81934c48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178108750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2178108750
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1615371907
Short name T543
Test name
Test status
Simulation time 173219174 ps
CPU time 1.5 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:51 PM PDT 24
Peak memory 200260 kb
Host smart-c604993c-a399-4f69-bff5-9fbdec4267fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615371907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1615371907
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1273868948
Short name T634
Test name
Test status
Simulation time 105036772 ps
CPU time 1.96 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:52 PM PDT 24
Peak memory 200284 kb
Host smart-c257b832-004f-4394-b139-73c0503f5725
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273868948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1273868948
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2518064685
Short name T579
Test name
Test status
Simulation time 73161833 ps
CPU time 1.85 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:54 PM PDT 24
Peak memory 200392 kb
Host smart-a6d6ef9b-f008-4e25-a07d-fadad9c1296e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518064685 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2518064685
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3497035078
Short name T110
Test name
Test status
Simulation time 101620746 ps
CPU time 0.84 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:51 PM PDT 24
Peak memory 200096 kb
Host smart-2e48b2d3-dc21-4136-903c-592fc4a40214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497035078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3497035078
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3969818048
Short name T572
Test name
Test status
Simulation time 58221351 ps
CPU time 0.65 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:52 PM PDT 24
Peak memory 195328 kb
Host smart-0c3bd4c1-e302-4442-b0bd-5d32ce5c8c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969818048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3969818048
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3933307314
Short name T121
Test name
Test status
Simulation time 84388519 ps
CPU time 1.7 seconds
Started Jul 13 06:06:51 PM PDT 24
Finished Jul 13 06:07:29 PM PDT 24
Peak memory 200260 kb
Host smart-f64126fd-7ddb-47f7-bd00-fd85d225a394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933307314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3933307314
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.726111245
Short name T594
Test name
Test status
Simulation time 173765780 ps
CPU time 2.14 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:45 PM PDT 24
Peak memory 200348 kb
Host smart-92983af3-9f28-4379-a6d3-9ae38d8aa5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726111245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.726111245
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1654933339
Short name T535
Test name
Test status
Simulation time 86530948 ps
CPU time 2.81 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:54 PM PDT 24
Peak memory 215772 kb
Host smart-95675b87-07b9-4c08-a5dd-73cbf9b20322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654933339 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1654933339
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3042810823
Short name T113
Test name
Test status
Simulation time 79196594 ps
CPU time 0.72 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:52 PM PDT 24
Peak memory 198244 kb
Host smart-9a89d34a-3296-4935-a781-363de2d399f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042810823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3042810823
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.767809197
Short name T603
Test name
Test status
Simulation time 33929065 ps
CPU time 0.58 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:44 PM PDT 24
Peak memory 195088 kb
Host smart-95212d96-4b1b-4efe-9750-d69959de6c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767809197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.767809197
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2832865814
Short name T627
Test name
Test status
Simulation time 269576105 ps
CPU time 1.66 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:07:59 PM PDT 24
Peak memory 200200 kb
Host smart-4ec6f44c-7274-47e5-8d6f-bb531f2aa91c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832865814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2832865814
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1818686961
Short name T555
Test name
Test status
Simulation time 139837208 ps
CPU time 3.41 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 200148 kb
Host smart-cbd8486e-b8cf-4d6f-8a46-013d5cbb48a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818686961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1818686961
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4101830059
Short name T132
Test name
Test status
Simulation time 157366026 ps
CPU time 2.8 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:52 PM PDT 24
Peak memory 200328 kb
Host smart-8d857481-4370-4faa-93e1-ad1dd6b0a56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101830059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4101830059
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1581303841
Short name T640
Test name
Test status
Simulation time 190125664190 ps
CPU time 612.82 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:18:10 PM PDT 24
Peak memory 216672 kb
Host smart-ec56ef56-910c-40da-b13c-53aff1498c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581303841 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1581303841
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.96476423
Short name T107
Test name
Test status
Simulation time 20426246 ps
CPU time 0.7 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:07:59 PM PDT 24
Peak memory 197640 kb
Host smart-68de302d-c752-4ab6-a317-bdd707dcc49e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96476423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.96476423
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3341670442
Short name T547
Test name
Test status
Simulation time 13904593 ps
CPU time 0.61 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:57 PM PDT 24
Peak memory 195260 kb
Host smart-5a3dfde5-e6f4-4f85-ae17-d70df8424093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341670442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3341670442
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2653092020
Short name T646
Test name
Test status
Simulation time 133320818 ps
CPU time 1.81 seconds
Started Jul 13 06:07:03 PM PDT 24
Finished Jul 13 06:08:07 PM PDT 24
Peak memory 200280 kb
Host smart-f6ab844e-c921-41bf-8a9d-69a80211f584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653092020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2653092020
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.845364826
Short name T566
Test name
Test status
Simulation time 178900497 ps
CPU time 2.47 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:54 PM PDT 24
Peak memory 200276 kb
Host smart-f349852b-183c-4f7a-8b9a-26e29a7321a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845364826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.845364826
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3682105906
Short name T64
Test name
Test status
Simulation time 66942545 ps
CPU time 1.78 seconds
Started Jul 13 06:07:04 PM PDT 24
Finished Jul 13 06:08:11 PM PDT 24
Peak memory 200308 kb
Host smart-8d03522a-8ce5-40e3-a6b7-299a83891847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682105906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3682105906
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.658971908
Short name T548
Test name
Test status
Simulation time 26508789 ps
CPU time 1.66 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:08:00 PM PDT 24
Peak memory 200200 kb
Host smart-051bb011-b619-4c1e-abfe-c7caceaa5010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658971908 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.658971908
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1084084846
Short name T614
Test name
Test status
Simulation time 55224487 ps
CPU time 0.62 seconds
Started Jul 13 06:07:02 PM PDT 24
Finished Jul 13 06:08:05 PM PDT 24
Peak memory 195120 kb
Host smart-092fb258-6817-457a-bce1-3e358c1103a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084084846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1084084846
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2446779161
Short name T601
Test name
Test status
Simulation time 64317374 ps
CPU time 1.62 seconds
Started Jul 13 06:07:04 PM PDT 24
Finished Jul 13 06:08:07 PM PDT 24
Peak memory 200308 kb
Host smart-b01daab7-7af4-4d44-a630-d39c531cc1b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446779161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2446779161
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.25423454
Short name T591
Test name
Test status
Simulation time 333205739 ps
CPU time 3.43 seconds
Started Jul 13 06:07:03 PM PDT 24
Finished Jul 13 06:08:09 PM PDT 24
Peak memory 200288 kb
Host smart-ace5f0eb-2455-495c-89f2-3367602925a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.25423454
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3800264683
Short name T632
Test name
Test status
Simulation time 207582988 ps
CPU time 1.8 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:08:00 PM PDT 24
Peak memory 200256 kb
Host smart-3d69baa2-b1ac-4f84-bb9c-90bc83040ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800264683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3800264683
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4234184501
Short name T544
Test name
Test status
Simulation time 65967699 ps
CPU time 1.97 seconds
Started Jul 13 06:07:05 PM PDT 24
Finished Jul 13 06:08:13 PM PDT 24
Peak memory 200336 kb
Host smart-dad50f2b-878f-4243-b35e-c6b2e0fb2d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234184501 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4234184501
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2616262820
Short name T575
Test name
Test status
Simulation time 68988885 ps
CPU time 0.78 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:07:59 PM PDT 24
Peak memory 199968 kb
Host smart-4fc71ce0-5119-43d1-a536-46d6d80cbddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616262820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2616262820
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.473771972
Short name T542
Test name
Test status
Simulation time 32774059 ps
CPU time 0.61 seconds
Started Jul 13 06:07:06 PM PDT 24
Finished Jul 13 06:08:12 PM PDT 24
Peak memory 193520 kb
Host smart-0ca8f6cd-b4fa-4bc1-8249-a511576eabb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473771972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.473771972
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.5973995
Short name T638
Test name
Test status
Simulation time 25533912 ps
CPU time 1.15 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:07:59 PM PDT 24
Peak memory 199988 kb
Host smart-cb5e414c-a2e7-4fc2-ab21-b829ef62561d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5973995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_o
utstanding.5973995
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.290665393
Short name T545
Test name
Test status
Simulation time 337848781 ps
CPU time 3.23 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:08:00 PM PDT 24
Peak memory 200284 kb
Host smart-48284f58-e0f6-4ecc-9748-ae006a94a457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290665393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.290665393
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.577120315
Short name T641
Test name
Test status
Simulation time 794303690 ps
CPU time 4.08 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:08:02 PM PDT 24
Peak memory 200228 kb
Host smart-60977d18-0622-4e90-8787-6db254963f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577120315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.577120315
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.682326062
Short name T556
Test name
Test status
Simulation time 118410277 ps
CPU time 2.26 seconds
Started Jul 13 06:07:04 PM PDT 24
Finished Jul 13 06:08:08 PM PDT 24
Peak memory 200360 kb
Host smart-ba7d8286-bda4-4904-95b7-79339d442431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682326062 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.682326062
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2798363042
Short name T616
Test name
Test status
Simulation time 23767389 ps
CPU time 0.84 seconds
Started Jul 13 06:07:06 PM PDT 24
Finished Jul 13 06:08:12 PM PDT 24
Peak memory 199908 kb
Host smart-1019f365-33e0-4a05-9e3f-3704f53c5640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798363042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2798363042
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2445927313
Short name T540
Test name
Test status
Simulation time 50365969 ps
CPU time 0.64 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:07:58 PM PDT 24
Peak memory 195128 kb
Host smart-ab496652-689c-4a6c-b86d-9d8ea0f4b073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445927313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2445927313
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2935696474
Short name T655
Test name
Test status
Simulation time 185164380 ps
CPU time 2.15 seconds
Started Jul 13 06:07:02 PM PDT 24
Finished Jul 13 06:08:07 PM PDT 24
Peak memory 200184 kb
Host smart-23150bdd-ff79-464a-bcab-0707f944c412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935696474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2935696474
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2650865299
Short name T649
Test name
Test status
Simulation time 331756993 ps
CPU time 3.01 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:08:01 PM PDT 24
Peak memory 200200 kb
Host smart-c96a6e06-d130-4317-8830-820608db51f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650865299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2650865299
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2187486933
Short name T551
Test name
Test status
Simulation time 400931061 ps
CPU time 2.21 seconds
Started Jul 13 06:07:04 PM PDT 24
Finished Jul 13 06:08:12 PM PDT 24
Peak memory 200296 kb
Host smart-60da9aad-2c1d-4080-ab17-b922a7469f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187486933 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2187486933
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1292720110
Short name T623
Test name
Test status
Simulation time 43986968 ps
CPU time 0.84 seconds
Started Jul 13 06:07:07 PM PDT 24
Finished Jul 13 06:08:12 PM PDT 24
Peak memory 199884 kb
Host smart-fe0e7d54-8c28-46d6-93fd-90be2a06debd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292720110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1292720110
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1131935109
Short name T608
Test name
Test status
Simulation time 117492273 ps
CPU time 0.63 seconds
Started Jul 13 06:07:04 PM PDT 24
Finished Jul 13 06:08:06 PM PDT 24
Peak memory 195300 kb
Host smart-138490cb-9e42-4659-b603-a479b58bd1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131935109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1131935109
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.142827589
Short name T630
Test name
Test status
Simulation time 27626970 ps
CPU time 1.18 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:08:00 PM PDT 24
Peak memory 199064 kb
Host smart-93897c15-b1d4-4ef7-b13d-6c3fef97f822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142827589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.142827589
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4051695557
Short name T639
Test name
Test status
Simulation time 29598007 ps
CPU time 1.51 seconds
Started Jul 13 06:07:02 PM PDT 24
Finished Jul 13 06:08:06 PM PDT 24
Peak memory 200288 kb
Host smart-c31fbba3-1fc3-4df7-98de-8341fd05f723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051695557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4051695557
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.542624870
Short name T534
Test name
Test status
Simulation time 104203844218 ps
CPU time 982.8 seconds
Started Jul 13 06:07:05 PM PDT 24
Finished Jul 13 06:24:34 PM PDT 24
Peak memory 216704 kb
Host smart-40cf2260-f486-40f8-a87a-b52c18d44ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542624870 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.542624870
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.212281816
Short name T106
Test name
Test status
Simulation time 40725215 ps
CPU time 0.92 seconds
Started Jul 13 06:07:03 PM PDT 24
Finished Jul 13 06:08:06 PM PDT 24
Peak memory 199992 kb
Host smart-b087f396-7644-4f6c-acec-99f9d29a7fff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212281816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.212281816
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.150727782
Short name T584
Test name
Test status
Simulation time 24763951 ps
CPU time 0.58 seconds
Started Jul 13 06:07:02 PM PDT 24
Finished Jul 13 06:08:04 PM PDT 24
Peak memory 195048 kb
Host smart-9a65e12c-7f4c-4906-8323-7444fdc46780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150727782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.150727782
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3022162723
Short name T651
Test name
Test status
Simulation time 38891931 ps
CPU time 1.11 seconds
Started Jul 13 06:07:03 PM PDT 24
Finished Jul 13 06:08:06 PM PDT 24
Peak memory 200136 kb
Host smart-60e5580a-85fb-439d-9dbd-887150cbe8f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022162723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3022162723
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1807478333
Short name T585
Test name
Test status
Simulation time 65063906 ps
CPU time 3.45 seconds
Started Jul 13 06:07:06 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 200280 kb
Host smart-40c1cc82-0812-4017-9313-07e5ed0ce2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807478333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1807478333
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2288813915
Short name T136
Test name
Test status
Simulation time 3562482334 ps
CPU time 3.97 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:18 PM PDT 24
Peak memory 200408 kb
Host smart-9e51d56e-e24c-4265-97a1-8af7e87d82f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288813915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2288813915
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.147155510
Short name T116
Test name
Test status
Simulation time 1962897420 ps
CPU time 6.28 seconds
Started Jul 13 06:06:41 PM PDT 24
Finished Jul 13 06:06:56 PM PDT 24
Peak memory 200532 kb
Host smart-be80bb0a-b7df-4136-8874-d8a01d0b6c3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147155510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.147155510
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2894618836
Short name T633
Test name
Test status
Simulation time 2122489676 ps
CPU time 5.87 seconds
Started Jul 13 06:06:40 PM PDT 24
Finished Jul 13 06:06:53 PM PDT 24
Peak memory 200344 kb
Host smart-3ca3db7e-5f3f-4655-9fd5-85b6e473c7f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894618836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2894618836
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1325338580
Short name T586
Test name
Test status
Simulation time 18633670 ps
CPU time 0.81 seconds
Started Jul 13 06:06:50 PM PDT 24
Finished Jul 13 06:07:27 PM PDT 24
Peak memory 199320 kb
Host smart-4aff3590-0289-4393-abb0-60d4b67d8596
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325338580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1325338580
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3820284103
Short name T599
Test name
Test status
Simulation time 342180866 ps
CPU time 2.45 seconds
Started Jul 13 06:06:48 PM PDT 24
Finished Jul 13 06:07:20 PM PDT 24
Peak memory 216588 kb
Host smart-b2d5369b-f824-4599-a9a2-b6357e93241e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820284103 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3820284103
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2932954866
Short name T104
Test name
Test status
Simulation time 46822238 ps
CPU time 0.84 seconds
Started Jul 13 06:06:50 PM PDT 24
Finished Jul 13 06:07:28 PM PDT 24
Peak memory 200116 kb
Host smart-91e63b89-4593-475c-8d1b-1b64d1cbde56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932954866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2932954866
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.99486398
Short name T618
Test name
Test status
Simulation time 50645052 ps
CPU time 0.6 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:09 PM PDT 24
Peak memory 195168 kb
Host smart-7f0aa3fa-1d9a-470e-8dc9-e5ef269a4083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99486398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.99486398
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2957643942
Short name T117
Test name
Test status
Simulation time 94055645 ps
CPU time 1.82 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:14 PM PDT 24
Peak memory 200324 kb
Host smart-e9a78dbb-3517-43ab-b77d-60deb37feca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957643942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2957643942
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3062564149
Short name T643
Test name
Test status
Simulation time 652893277 ps
CPU time 3.25 seconds
Started Jul 13 06:06:44 PM PDT 24
Finished Jul 13 06:07:03 PM PDT 24
Peak memory 200476 kb
Host smart-d3127da1-6ec6-4d52-bad0-9130b3bd006e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062564149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3062564149
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.406129991
Short name T134
Test name
Test status
Simulation time 237123266 ps
CPU time 4.38 seconds
Started Jul 13 06:06:33 PM PDT 24
Finished Jul 13 06:06:40 PM PDT 24
Peak memory 200328 kb
Host smart-e342ec18-81c1-48cd-b6de-399a5f616462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406129991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.406129991
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1312443920
Short name T636
Test name
Test status
Simulation time 56897896 ps
CPU time 0.58 seconds
Started Jul 13 06:07:02 PM PDT 24
Finished Jul 13 06:08:05 PM PDT 24
Peak memory 195172 kb
Host smart-855fc494-a1fb-42c6-b549-f096ef467e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312443920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1312443920
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3557501399
Short name T583
Test name
Test status
Simulation time 13680250 ps
CPU time 0.59 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:07:58 PM PDT 24
Peak memory 195164 kb
Host smart-338de3c6-1c38-4e10-b693-3dbf83867180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557501399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3557501399
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2605821606
Short name T650
Test name
Test status
Simulation time 41835970 ps
CPU time 0.61 seconds
Started Jul 13 06:07:01 PM PDT 24
Finished Jul 13 06:07:59 PM PDT 24
Peak memory 195248 kb
Host smart-f813a311-4248-4c95-9c59-99b3ee29ca85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605821606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2605821606
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1506740467
Short name T621
Test name
Test status
Simulation time 22151610 ps
CPU time 0.59 seconds
Started Jul 13 06:07:03 PM PDT 24
Finished Jul 13 06:08:06 PM PDT 24
Peak memory 195188 kb
Host smart-a93e3f86-2e15-4bce-9b38-7d6f9fe4b2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506740467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1506740467
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2635898123
Short name T558
Test name
Test status
Simulation time 13309636 ps
CPU time 0.6 seconds
Started Jul 13 06:07:12 PM PDT 24
Finished Jul 13 06:08:19 PM PDT 24
Peak memory 195100 kb
Host smart-9863fd7a-8888-49ad-89b6-1d2d0b4e009a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635898123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2635898123
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3179015493
Short name T559
Test name
Test status
Simulation time 57573360 ps
CPU time 0.61 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195196 kb
Host smart-6527ea9f-1df1-45b6-8643-3ab83c818acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179015493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3179015493
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1789273277
Short name T588
Test name
Test status
Simulation time 30164084 ps
CPU time 0.63 seconds
Started Jul 13 06:07:12 PM PDT 24
Finished Jul 13 06:08:19 PM PDT 24
Peak memory 195240 kb
Host smart-d3c493ad-df2b-4fce-af07-f8ac00be1f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789273277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1789273277
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2783496411
Short name T606
Test name
Test status
Simulation time 36193938 ps
CPU time 0.59 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195128 kb
Host smart-3991e54f-1ea6-4c60-a1e1-7c469e583895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783496411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2783496411
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2826142048
Short name T590
Test name
Test status
Simulation time 46275304 ps
CPU time 0.59 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195228 kb
Host smart-c141cf0d-da3f-48f4-98a6-958238898a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826142048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2826142048
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3054082614
Short name T644
Test name
Test status
Simulation time 57746502 ps
CPU time 0.61 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195224 kb
Host smart-1dc4164f-803b-419b-8026-f0020fa63882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054082614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3054082614
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1053655914
Short name T101
Test name
Test status
Simulation time 2053899003 ps
CPU time 6.37 seconds
Started Jul 13 06:06:43 PM PDT 24
Finished Jul 13 06:07:01 PM PDT 24
Peak memory 200204 kb
Host smart-0156bf43-4b63-4a30-9f96-04fb41f87f6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053655914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1053655914
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.562616536
Short name T115
Test name
Test status
Simulation time 215038711 ps
CPU time 9.52 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:18 PM PDT 24
Peak memory 200192 kb
Host smart-b83d3a27-a52f-4ec2-becd-03b89b3ea8c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562616536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.562616536
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1236687518
Short name T103
Test name
Test status
Simulation time 33023845 ps
CPU time 0.79 seconds
Started Jul 13 06:06:48 PM PDT 24
Finished Jul 13 06:07:19 PM PDT 24
Peak memory 199164 kb
Host smart-fa5b6f68-a7c5-4361-b758-1c448f0ef1d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236687518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1236687518
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.965102071
Short name T607
Test name
Test status
Simulation time 85943568 ps
CPU time 2.23 seconds
Started Jul 13 06:06:42 PM PDT 24
Finished Jul 13 06:06:54 PM PDT 24
Peak memory 200280 kb
Host smart-e0e80e45-af65-4ec3-ad38-01fdc4a856d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965102071 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.965102071
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1797694091
Short name T102
Test name
Test status
Simulation time 82251966 ps
CPU time 0.8 seconds
Started Jul 13 06:06:49 PM PDT 24
Finished Jul 13 06:07:23 PM PDT 24
Peak memory 199808 kb
Host smart-836077f3-d1ac-4e77-8b30-58f7c574bc5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797694091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1797694091
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2121650522
Short name T562
Test name
Test status
Simulation time 42159172 ps
CPU time 0.66 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:13 PM PDT 24
Peak memory 195088 kb
Host smart-24be7a41-cc55-4ab1-90b7-fce193206c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121650522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2121650522
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1032674486
Short name T118
Test name
Test status
Simulation time 298492429 ps
CPU time 2.29 seconds
Started Jul 13 06:06:40 PM PDT 24
Finished Jul 13 06:06:50 PM PDT 24
Peak memory 200268 kb
Host smart-abd5ca59-6064-42a3-8e27-d6a461ac90f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032674486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1032674486
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.262985744
Short name T605
Test name
Test status
Simulation time 29824780 ps
CPU time 1.47 seconds
Started Jul 13 06:06:43 PM PDT 24
Finished Jul 13 06:06:59 PM PDT 24
Peak memory 200256 kb
Host smart-e3ecf937-1070-4fc7-bb01-0f94814c0f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262985744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.262985744
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1389173957
Short name T654
Test name
Test status
Simulation time 90211614 ps
CPU time 1.83 seconds
Started Jul 13 06:06:41 PM PDT 24
Finished Jul 13 06:06:50 PM PDT 24
Peak memory 200352 kb
Host smart-17392d65-2f7d-4486-8871-d9781b7518d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389173957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1389173957
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.215418050
Short name T553
Test name
Test status
Simulation time 36384162 ps
CPU time 0.6 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195156 kb
Host smart-2ff48056-f1f3-4228-a976-94f339707a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215418050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.215418050
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3777411441
Short name T557
Test name
Test status
Simulation time 54606108 ps
CPU time 0.59 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195172 kb
Host smart-c70a19c6-3085-4dca-8478-39aa35659b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777411441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3777411441
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2138273278
Short name T659
Test name
Test status
Simulation time 43404148 ps
CPU time 0.57 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195164 kb
Host smart-61a99374-afdb-4573-9af3-00c241f0d0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138273278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2138273278
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3006062755
Short name T597
Test name
Test status
Simulation time 14243158 ps
CPU time 0.62 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195128 kb
Host smart-c7c5bebf-f772-4d68-90c6-b44c22c1f1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006062755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3006062755
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1332511734
Short name T549
Test name
Test status
Simulation time 14704337 ps
CPU time 0.61 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195256 kb
Host smart-06af32a7-d0c7-4f7b-9067-ef4f5349b546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332511734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1332511734
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.445265401
Short name T596
Test name
Test status
Simulation time 37395242 ps
CPU time 0.57 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195080 kb
Host smart-1207916f-89a5-48a2-8dac-92d76038c6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445265401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.445265401
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2859637623
Short name T625
Test name
Test status
Simulation time 28246113 ps
CPU time 0.57 seconds
Started Jul 13 06:07:11 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195048 kb
Host smart-aad21be0-7c61-466a-be37-f206676e6660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859637623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2859637623
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2737047795
Short name T629
Test name
Test status
Simulation time 15245396 ps
CPU time 0.6 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195572 kb
Host smart-f3cae54b-f7ee-4fd3-846e-b1742310560a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737047795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2737047795
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2613992919
Short name T546
Test name
Test status
Simulation time 34927819 ps
CPU time 0.59 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195276 kb
Host smart-a8276de8-3da9-45e3-9443-214df751df2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613992919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2613992919
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.643949622
Short name T612
Test name
Test status
Simulation time 33287219 ps
CPU time 0.61 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195056 kb
Host smart-ecee6e90-e83e-4cc9-98a2-5f46634e3ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643949622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.643949622
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4093998464
Short name T620
Test name
Test status
Simulation time 154484626 ps
CPU time 3.24 seconds
Started Jul 13 06:06:49 PM PDT 24
Finished Jul 13 06:07:25 PM PDT 24
Peak memory 200252 kb
Host smart-e695c998-dfa3-41a0-9482-2a229ed5a654
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093998464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4093998464
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1720122016
Short name T581
Test name
Test status
Simulation time 1463510556 ps
CPU time 11.04 seconds
Started Jul 13 06:06:42 PM PDT 24
Finished Jul 13 06:07:04 PM PDT 24
Peak memory 200256 kb
Host smart-eb23febc-6e24-49f5-8cc1-613f68cdf4f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720122016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1720122016
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2424112712
Short name T105
Test name
Test status
Simulation time 21497752 ps
CPU time 1.01 seconds
Started Jul 13 06:06:47 PM PDT 24
Finished Jul 13 06:07:15 PM PDT 24
Peak memory 200036 kb
Host smart-cf529528-fdee-4840-8645-2230de151ee7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424112712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2424112712
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2648007594
Short name T647
Test name
Test status
Simulation time 29951789 ps
CPU time 1.9 seconds
Started Jul 13 06:06:41 PM PDT 24
Finished Jul 13 06:06:50 PM PDT 24
Peak memory 200276 kb
Host smart-8b650335-0c26-4b4e-ba95-680ba963f0c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648007594 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2648007594
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1763038465
Short name T123
Test name
Test status
Simulation time 108017529 ps
CPU time 0.93 seconds
Started Jul 13 06:06:47 PM PDT 24
Finished Jul 13 06:07:13 PM PDT 24
Peak memory 200020 kb
Host smart-ce133551-29a6-4f04-8b7f-113ebd770904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763038465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1763038465
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2875644007
Short name T609
Test name
Test status
Simulation time 20448519 ps
CPU time 0.56 seconds
Started Jul 13 06:06:42 PM PDT 24
Finished Jul 13 06:06:53 PM PDT 24
Peak memory 195172 kb
Host smart-ea1fd8ac-ff8a-4b6e-9820-56d7aeec27af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875644007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2875644007
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.458383254
Short name T637
Test name
Test status
Simulation time 44292929 ps
CPU time 2.05 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:14 PM PDT 24
Peak memory 200324 kb
Host smart-06fb3b27-d925-4a40-a869-74f8cb5e5da3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458383254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.458383254
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1881754778
Short name T648
Test name
Test status
Simulation time 37199828 ps
CPU time 1.73 seconds
Started Jul 13 06:06:45 PM PDT 24
Finished Jul 13 06:07:06 PM PDT 24
Peak memory 200212 kb
Host smart-59485153-bc62-4138-a230-14b3cfa6ce65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881754778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1881754778
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2770760823
Short name T595
Test name
Test status
Simulation time 580081614 ps
CPU time 1.87 seconds
Started Jul 13 06:06:41 PM PDT 24
Finished Jul 13 06:06:52 PM PDT 24
Peak memory 200312 kb
Host smart-f352022c-67b7-4a81-9172-248f7d53cd27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770760823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2770760823
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.376178576
Short name T576
Test name
Test status
Simulation time 46803256 ps
CPU time 0.59 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195292 kb
Host smart-cb817492-2b5f-48a8-969d-d163f0eccf93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376178576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.376178576
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.4020283237
Short name T582
Test name
Test status
Simulation time 23460478 ps
CPU time 0.61 seconds
Started Jul 13 06:07:22 PM PDT 24
Finished Jul 13 06:08:35 PM PDT 24
Peak memory 195212 kb
Host smart-c06065c8-e4cb-49e9-8fd7-545336eb492f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020283237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4020283237
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3027302796
Short name T564
Test name
Test status
Simulation time 29569075 ps
CPU time 0.62 seconds
Started Jul 13 06:07:13 PM PDT 24
Finished Jul 13 06:08:19 PM PDT 24
Peak memory 195132 kb
Host smart-a92fe02a-8db0-48e7-8790-ebd69aee9f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027302796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3027302796
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1538358687
Short name T537
Test name
Test status
Simulation time 12817978 ps
CPU time 0.59 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195156 kb
Host smart-26d01a7c-20fd-4dc4-9ca9-5ad041bf5aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538358687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1538358687
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.271917327
Short name T592
Test name
Test status
Simulation time 14849041 ps
CPU time 0.63 seconds
Started Jul 13 06:07:11 PM PDT 24
Finished Jul 13 06:08:16 PM PDT 24
Peak memory 195160 kb
Host smart-c5d84183-0160-442f-9c83-c93cfddb7945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271917327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.271917327
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2622130332
Short name T580
Test name
Test status
Simulation time 24611740 ps
CPU time 0.56 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195036 kb
Host smart-239ee1f4-4212-405d-89b9-f49116bda1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622130332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2622130332
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.577484236
Short name T570
Test name
Test status
Simulation time 54369153 ps
CPU time 0.61 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195216 kb
Host smart-c0a010ab-7825-4e83-a069-53ca5bfe7ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577484236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.577484236
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1773601882
Short name T642
Test name
Test status
Simulation time 16521464 ps
CPU time 0.56 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195188 kb
Host smart-c4a7de11-09c9-4bfa-a7e9-487d808508cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773601882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1773601882
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.773896084
Short name T533
Test name
Test status
Simulation time 11998041 ps
CPU time 0.6 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195156 kb
Host smart-6be7ecc7-06f8-4dbd-8fd7-964541ab1786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773896084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.773896084
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2876600000
Short name T626
Test name
Test status
Simulation time 12018367 ps
CPU time 0.56 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:08:15 PM PDT 24
Peak memory 195148 kb
Host smart-5e7db12b-2835-4906-8989-11d5018849f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876600000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2876600000
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3891307483
Short name T532
Test name
Test status
Simulation time 108493588 ps
CPU time 1.67 seconds
Started Jul 13 06:06:41 PM PDT 24
Finished Jul 13 06:06:51 PM PDT 24
Peak memory 200368 kb
Host smart-be43ccf5-ca32-495e-a06d-2c8229bc780b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891307483 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3891307483
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1166983804
Short name T653
Test name
Test status
Simulation time 333969449 ps
CPU time 0.93 seconds
Started Jul 13 06:06:41 PM PDT 24
Finished Jul 13 06:06:51 PM PDT 24
Peak memory 200128 kb
Host smart-64fe9abf-391b-44df-85f3-ced203ece5e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166983804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1166983804
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.406179327
Short name T568
Test name
Test status
Simulation time 15869890 ps
CPU time 0.6 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:09 PM PDT 24
Peak memory 195200 kb
Host smart-a4d3464e-472b-4a3e-83c6-66634332b0e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406179327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.406179327
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4208462135
Short name T600
Test name
Test status
Simulation time 73144914 ps
CPU time 1.74 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:10 PM PDT 24
Peak memory 200236 kb
Host smart-f1b9e2d2-415d-42e6-8d2e-90c97484ee4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208462135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4208462135
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2560398911
Short name T602
Test name
Test status
Simulation time 65601908 ps
CPU time 1.66 seconds
Started Jul 13 06:06:46 PM PDT 24
Finished Jul 13 06:07:10 PM PDT 24
Peak memory 200264 kb
Host smart-2ca00a9e-1ce0-4f42-9c93-bc449e90069f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560398911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2560398911
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2708873396
Short name T624
Test name
Test status
Simulation time 226509404 ps
CPU time 3.81 seconds
Started Jul 13 06:06:48 PM PDT 24
Finished Jul 13 06:07:25 PM PDT 24
Peak memory 200272 kb
Host smart-93c9f14b-9cdd-4f1d-a786-6aefeac63ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708873396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2708873396
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2981430614
Short name T577
Test name
Test status
Simulation time 70847143 ps
CPU time 1.9 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:54 PM PDT 24
Peak memory 200292 kb
Host smart-9b0e9a3b-faf6-42d1-bcaa-70ba570a9600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981430614 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2981430614
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.808035201
Short name T656
Test name
Test status
Simulation time 136791116 ps
CPU time 0.96 seconds
Started Jul 13 06:06:59 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 200128 kb
Host smart-85547fa4-5b2c-4cae-9592-7b9c51ffb31f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808035201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.808035201
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1597320947
Short name T538
Test name
Test status
Simulation time 16504866 ps
CPU time 0.6 seconds
Started Jul 13 06:06:51 PM PDT 24
Finished Jul 13 06:07:28 PM PDT 24
Peak memory 195148 kb
Host smart-20685f36-2dfb-484b-ac17-bbd2e169395e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597320947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1597320947
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.420455893
Short name T652
Test name
Test status
Simulation time 26163959 ps
CPU time 1.13 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 198724 kb
Host smart-d59a1a35-7791-4cb5-8009-48546db8dc34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420455893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.420455893
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2515630667
Short name T552
Test name
Test status
Simulation time 109090209 ps
CPU time 1.93 seconds
Started Jul 13 06:06:51 PM PDT 24
Finished Jul 13 06:07:29 PM PDT 24
Peak memory 200224 kb
Host smart-76ac2f12-f9cd-425e-a6a4-e8d0426617b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515630667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2515630667
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1351726696
Short name T131
Test name
Test status
Simulation time 340000848 ps
CPU time 2.72 seconds
Started Jul 13 06:06:52 PM PDT 24
Finished Jul 13 06:07:32 PM PDT 24
Peak memory 200292 kb
Host smart-6e601d68-c641-4c10-896a-48c6dc201180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351726696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1351726696
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3388815659
Short name T589
Test name
Test status
Simulation time 108520148 ps
CPU time 2.6 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:08:00 PM PDT 24
Peak memory 200292 kb
Host smart-05123f5f-f76b-4e90-9628-d50d32742825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388815659 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3388815659
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3166809040
Short name T114
Test name
Test status
Simulation time 54169890 ps
CPU time 0.71 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:50 PM PDT 24
Peak memory 198368 kb
Host smart-9f3ad73e-6751-4971-87e0-25de91783d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166809040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3166809040
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4244445244
Short name T619
Test name
Test status
Simulation time 68798665 ps
CPU time 0.57 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:51 PM PDT 24
Peak memory 195236 kb
Host smart-778f3e3e-a263-4b09-8047-f4b69d914eb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244445244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4244445244
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3592061306
Short name T604
Test name
Test status
Simulation time 532726226 ps
CPU time 2.22 seconds
Started Jul 13 06:06:53 PM PDT 24
Finished Jul 13 06:07:38 PM PDT 24
Peak memory 200276 kb
Host smart-3731bd46-a942-4e86-8f2d-262d5cf06801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592061306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3592061306
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2854061301
Short name T613
Test name
Test status
Simulation time 408047807 ps
CPU time 1.94 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 200084 kb
Host smart-45c94d00-434a-491b-b009-2dc72579b8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854061301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2854061301
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3845292499
Short name T63
Test name
Test status
Simulation time 129672688 ps
CPU time 3.88 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:47 PM PDT 24
Peak memory 200176 kb
Host smart-1b553796-820c-46f6-a301-46c134b51f98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845292499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3845292499
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2799811438
Short name T563
Test name
Test status
Simulation time 140145481 ps
CPU time 1.95 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:45 PM PDT 24
Peak memory 200324 kb
Host smart-5a1c65ec-4917-469a-afe4-512afd36a4dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799811438 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2799811438
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1982772880
Short name T539
Test name
Test status
Simulation time 22846782 ps
CPU time 0.84 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:52 PM PDT 24
Peak memory 199848 kb
Host smart-68e00b62-df25-4fbf-90af-c4bbb218ba5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982772880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1982772880
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3473059748
Short name T554
Test name
Test status
Simulation time 56831833 ps
CPU time 0.63 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:51 PM PDT 24
Peak memory 195176 kb
Host smart-ef57243b-da22-4814-882b-2e4ae4f2f7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473059748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3473059748
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4206591700
Short name T658
Test name
Test status
Simulation time 41218630 ps
CPU time 1.09 seconds
Started Jul 13 06:06:51 PM PDT 24
Finished Jul 13 06:07:28 PM PDT 24
Peak memory 200040 kb
Host smart-436ee09a-e240-4fcc-8345-d0a39cd27586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206591700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.4206591700
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2469634868
Short name T536
Test name
Test status
Simulation time 120610855 ps
CPU time 1.34 seconds
Started Jul 13 06:06:58 PM PDT 24
Finished Jul 13 06:07:53 PM PDT 24
Peak memory 199972 kb
Host smart-dc7d7ed0-9388-4366-b0cf-5b2d20bf1f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469634868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2469634868
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2343138166
Short name T133
Test name
Test status
Simulation time 94344596 ps
CPU time 2.88 seconds
Started Jul 13 06:06:57 PM PDT 24
Finished Jul 13 06:07:54 PM PDT 24
Peak memory 200256 kb
Host smart-12add541-55b0-4632-b5fa-dcce4241984c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343138166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2343138166
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2092193971
Short name T628
Test name
Test status
Simulation time 43423040 ps
CPU time 1.22 seconds
Started Jul 13 06:06:55 PM PDT 24
Finished Jul 13 06:07:44 PM PDT 24
Peak memory 200188 kb
Host smart-a17e0c54-8edb-4b73-90a8-74234b0c074d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092193971 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2092193971
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1872896550
Short name T120
Test name
Test status
Simulation time 28362407 ps
CPU time 0.93 seconds
Started Jul 13 06:06:56 PM PDT 24
Finished Jul 13 06:07:44 PM PDT 24
Peak memory 200128 kb
Host smart-fc5df022-aa68-44cc-80f1-14ee5fded900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872896550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1872896550
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2622540988
Short name T573
Test name
Test status
Simulation time 51229277 ps
CPU time 0.62 seconds
Started Jul 13 06:06:49 PM PDT 24
Finished Jul 13 06:07:23 PM PDT 24
Peak memory 195316 kb
Host smart-a9d6cda3-21a2-488b-b26c-4cff10cef231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622540988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2622540988
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4225347126
Short name T119
Test name
Test status
Simulation time 116909755 ps
CPU time 2.33 seconds
Started Jul 13 06:06:53 PM PDT 24
Finished Jul 13 06:07:39 PM PDT 24
Peak memory 199992 kb
Host smart-2f6e123d-8345-450b-8775-b75f6159f049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225347126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4225347126
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1827218960
Short name T561
Test name
Test status
Simulation time 70600364 ps
CPU time 1.61 seconds
Started Jul 13 06:06:51 PM PDT 24
Finished Jul 13 06:07:29 PM PDT 24
Peak memory 200212 kb
Host smart-e134bca8-c2bc-40ab-b6ed-3f2ce1bf6d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827218960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1827218960
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.688935867
Short name T130
Test name
Test status
Simulation time 361129157 ps
CPU time 1.72 seconds
Started Jul 13 06:07:00 PM PDT 24
Finished Jul 13 06:07:59 PM PDT 24
Peak memory 200544 kb
Host smart-e53dad09-7fe3-4b83-9dbc-d84818bb0ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688935867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.688935867
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1886208303
Short name T297
Test name
Test status
Simulation time 44416084 ps
CPU time 0.59 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:08:32 PM PDT 24
Peak memory 197112 kb
Host smart-af17b6ed-c715-4a15-8d39-82f7c6634bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886208303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1886208303
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3070700261
Short name T212
Test name
Test status
Simulation time 1401178655 ps
CPU time 37.39 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:09:08 PM PDT 24
Peak memory 200276 kb
Host smart-e2787214-9273-4d24-8309-ffa31a5ccb0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070700261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3070700261
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1182242269
Short name T296
Test name
Test status
Simulation time 716734562 ps
CPU time 35.33 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:08:50 PM PDT 24
Peak memory 200316 kb
Host smart-52c9f39a-8a53-4391-adf3-1f92807d2e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182242269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1182242269
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1369949158
Short name T464
Test name
Test status
Simulation time 7874176611 ps
CPU time 1530.38 seconds
Started Jul 13 06:07:10 PM PDT 24
Finished Jul 13 06:33:45 PM PDT 24
Peak memory 769520 kb
Host smart-36bb611f-2682-48a0-aeec-d36c1233832e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369949158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1369949158
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1329954832
Short name T474
Test name
Test status
Simulation time 5486911250 ps
CPU time 68.93 seconds
Started Jul 13 06:07:14 PM PDT 24
Finished Jul 13 06:09:28 PM PDT 24
Peak memory 200368 kb
Host smart-a68cde7a-bbaf-4a12-be6d-6def558fbfa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329954832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1329954832
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1313854406
Short name T312
Test name
Test status
Simulation time 3146036925 ps
CPU time 158.24 seconds
Started Jul 13 06:07:12 PM PDT 24
Finished Jul 13 06:10:56 PM PDT 24
Peak memory 200360 kb
Host smart-ff305292-df48-4f2d-b24d-59fbf47e4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313854406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1313854406
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1862023067
Short name T54
Test name
Test status
Simulation time 85684696 ps
CPU time 1.01 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:08:30 PM PDT 24
Peak memory 219340 kb
Host smart-23e38d91-ad91-4e40-a29e-2d2db97f34d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862023067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1862023067
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.410693872
Short name T458
Test name
Test status
Simulation time 473453277 ps
CPU time 10.17 seconds
Started Jul 13 06:07:14 PM PDT 24
Finished Jul 13 06:08:30 PM PDT 24
Peak memory 200300 kb
Host smart-8c50d8cd-0778-4fff-ae80-8adaa3746405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410693872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.410693872
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2744056179
Short name T3
Test name
Test status
Simulation time 5687690835 ps
CPU time 48.87 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:09:03 PM PDT 24
Peak memory 200344 kb
Host smart-69db84f3-a030-483c-a0e8-7e0525de7e9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744056179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2744056179
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.414936415
Short name T11
Test name
Test status
Simulation time 233751795683 ps
CPU time 1962.28 seconds
Started Jul 13 06:07:08 PM PDT 24
Finished Jul 13 06:40:57 PM PDT 24
Peak memory 783848 kb
Host smart-bc9845de-68b2-4d17-933b-378b6f458be6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414936415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.414936415
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2513072065
Short name T341
Test name
Test status
Simulation time 15574578961 ps
CPU time 45.42 seconds
Started Jul 13 06:07:11 PM PDT 24
Finished Jul 13 06:09:00 PM PDT 24
Peak memory 200336 kb
Host smart-cd1258df-f89d-439b-8ced-88fefdba5a31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2513072065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2513072065
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2429073069
Short name T347
Test name
Test status
Simulation time 3800629882 ps
CPU time 56.96 seconds
Started Jul 13 06:07:11 PM PDT 24
Finished Jul 13 06:09:12 PM PDT 24
Peak memory 200372 kb
Host smart-d6bbb6bf-4bc2-46c3-a1ad-5a7ff9654a7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2429073069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2429073069
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.207633592
Short name T469
Test name
Test status
Simulation time 2281441129 ps
CPU time 78.18 seconds
Started Jul 13 06:07:12 PM PDT 24
Finished Jul 13 06:09:33 PM PDT 24
Peak memory 200344 kb
Host smart-affb41a7-f4a5-4c04-8474-9f6d30d2a6b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=207633592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.207633592
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3778970976
Short name T340
Test name
Test status
Simulation time 11193388101 ps
CPU time 629.34 seconds
Started Jul 13 06:07:09 PM PDT 24
Finished Jul 13 06:18:44 PM PDT 24
Peak memory 200340 kb
Host smart-5eee14fa-ed1c-4894-9563-be85f135eb5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3778970976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3778970976
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3314970674
Short name T390
Test name
Test status
Simulation time 183207694366 ps
CPU time 2549.91 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:51:01 PM PDT 24
Peak memory 215720 kb
Host smart-99e3d43a-1732-4a11-a697-9d411edf5f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3314970674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3314970674
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.62369677
Short name T38
Test name
Test status
Simulation time 16668407866 ps
CPU time 85.33 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:09:56 PM PDT 24
Peak memory 200292 kb
Host smart-c1c125a7-8634-497d-9719-bd78fdc96758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62369677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.62369677
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.958595013
Short name T318
Test name
Test status
Simulation time 53480964 ps
CPU time 0.62 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:08:26 PM PDT 24
Peak memory 195084 kb
Host smart-65206601-b8aa-4e9d-9dda-257b08f98d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958595013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.958595013
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3313879129
Short name T350
Test name
Test status
Simulation time 1479096584 ps
CPU time 41.43 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:09:11 PM PDT 24
Peak memory 200300 kb
Host smart-81c29dfc-032a-402b-962f-b84eb9f6501c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313879129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3313879129
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3363465488
Short name T287
Test name
Test status
Simulation time 101994161 ps
CPU time 1.92 seconds
Started Jul 13 06:07:16 PM PDT 24
Finished Jul 13 06:08:28 PM PDT 24
Peak memory 200300 kb
Host smart-957c1db0-6c24-406c-9473-bca4566a6934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363465488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3363465488
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.42891310
Short name T149
Test name
Test status
Simulation time 19038532545 ps
CPU time 804.2 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:21:54 PM PDT 24
Peak memory 701880 kb
Host smart-dd268e36-7727-4e6c-b569-0cd8b8ff0654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42891310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.42891310
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.549194062
Short name T408
Test name
Test status
Simulation time 395778296 ps
CPU time 5.4 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:08:31 PM PDT 24
Peak memory 200228 kb
Host smart-21a46c73-3e6f-439a-8d94-a8744a3cd1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549194062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.549194062
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1691930722
Short name T51
Test name
Test status
Simulation time 64210680 ps
CPU time 0.84 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:08:30 PM PDT 24
Peak memory 218292 kb
Host smart-8a8ef729-d2bf-48dc-a4f6-76487d947390
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691930722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1691930722
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2765317328
Short name T505
Test name
Test status
Simulation time 211396816 ps
CPU time 9.1 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:08:40 PM PDT 24
Peak memory 200296 kb
Host smart-fab20519-dc3f-4493-b5b9-d17ea5a0bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765317328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2765317328
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2429737981
Short name T338
Test name
Test status
Simulation time 7868345743 ps
CPU time 405.19 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:15:15 PM PDT 24
Peak memory 200380 kb
Host smart-f79706a9-6ff9-4f74-8c15-67d3d8752a5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429737981 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2429737981
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.770768466
Short name T69
Test name
Test status
Simulation time 112696808569 ps
CPU time 2026.81 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:42:17 PM PDT 24
Peak memory 778308 kb
Host smart-7026cee2-2bd8-493d-a9cf-129c59d3fcea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770768466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.770768466
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2661364177
Short name T40
Test name
Test status
Simulation time 6108400512 ps
CPU time 63.37 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:09:33 PM PDT 24
Peak memory 200348 kb
Host smart-92f2a10a-d3be-4efa-ada7-d8eed901671b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2661364177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2661364177
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.114303314
Short name T288
Test name
Test status
Simulation time 2399033374 ps
CPU time 98.88 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:10:10 PM PDT 24
Peak memory 200384 kb
Host smart-e9ead98a-db32-4724-a190-519595985cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=114303314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.114303314
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1285221964
Short name T422
Test name
Test status
Simulation time 6260986467 ps
CPU time 77.58 seconds
Started Jul 13 06:07:16 PM PDT 24
Finished Jul 13 06:09:43 PM PDT 24
Peak memory 200352 kb
Host smart-d3436112-e7f4-4d82-a64c-1288bf927079
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1285221964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1285221964
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3472365633
Short name T433
Test name
Test status
Simulation time 39536956589 ps
CPU time 537.47 seconds
Started Jul 13 06:07:16 PM PDT 24
Finished Jul 13 06:17:23 PM PDT 24
Peak memory 200380 kb
Host smart-fca8dbdc-c9d6-4e82-9c73-145e3c681bf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3472365633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3472365633
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2053403235
Short name T74
Test name
Test status
Simulation time 278128279328 ps
CPU time 2323.12 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:47:13 PM PDT 24
Peak memory 215812 kb
Host smart-5dc5b550-21c1-4287-a2a9-c66848b476ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2053403235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2053403235
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2060489915
Short name T159
Test name
Test status
Simulation time 45828887828 ps
CPU time 2336.46 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:47:27 PM PDT 24
Peak memory 215812 kb
Host smart-ec00c140-ef46-4f0e-b8e7-01d61af4c5f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060489915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2060489915
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1746321090
Short name T125
Test name
Test status
Simulation time 40677267104 ps
CPU time 104.57 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:10:16 PM PDT 24
Peak memory 200316 kb
Host smart-b06f4730-3ba3-4a2b-86b7-91e3cf1e8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746321090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1746321090
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3390445675
Short name T262
Test name
Test status
Simulation time 22313763 ps
CPU time 0.59 seconds
Started Jul 13 06:07:50 PM PDT 24
Finished Jul 13 06:09:07 PM PDT 24
Peak memory 196172 kb
Host smart-72e86d72-0477-43b5-9ef5-4cb594b7b1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390445675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3390445675
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2174929219
Short name T261
Test name
Test status
Simulation time 5230938533 ps
CPU time 76.07 seconds
Started Jul 13 06:07:45 PM PDT 24
Finished Jul 13 06:10:17 PM PDT 24
Peak memory 200608 kb
Host smart-1a508e2c-f7fc-4f1f-81e5-ad3b31aafc29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174929219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2174929219
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3815496647
Short name T411
Test name
Test status
Simulation time 924258665 ps
CPU time 48.05 seconds
Started Jul 13 06:07:46 PM PDT 24
Finished Jul 13 06:09:49 PM PDT 24
Peak memory 200600 kb
Host smart-645bd909-1fe6-46c4-b8dd-345b27317c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815496647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3815496647
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1501028273
Short name T337
Test name
Test status
Simulation time 15582340183 ps
CPU time 700.97 seconds
Started Jul 13 06:07:43 PM PDT 24
Finished Jul 13 06:20:41 PM PDT 24
Peak memory 686520 kb
Host smart-6aa00aca-10f6-4a58-ba21-a4c9743bd15c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501028273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1501028273
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2714506888
Short name T504
Test name
Test status
Simulation time 1303606830 ps
CPU time 19.74 seconds
Started Jul 13 06:07:44 PM PDT 24
Finished Jul 13 06:09:20 PM PDT 24
Peak memory 200280 kb
Host smart-4b7e8ddb-414b-4a4b-bb40-14522bce3708
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714506888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2714506888
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.274056497
Short name T303
Test name
Test status
Simulation time 51904750 ps
CPU time 3.08 seconds
Started Jul 13 06:07:43 PM PDT 24
Finished Jul 13 06:09:03 PM PDT 24
Peak memory 200196 kb
Host smart-555c766e-0978-42e1-86b7-c1d5a797f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274056497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.274056497
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.909983134
Short name T492
Test name
Test status
Simulation time 537718554 ps
CPU time 6.63 seconds
Started Jul 13 06:07:43 PM PDT 24
Finished Jul 13 06:09:06 PM PDT 24
Peak memory 200344 kb
Host smart-70414099-5ce5-49a3-b9bf-cea4d49bd4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909983134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.909983134
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2679625561
Short name T251
Test name
Test status
Simulation time 5962981215 ps
CPU time 105.23 seconds
Started Jul 13 06:07:45 PM PDT 24
Finished Jul 13 06:10:46 PM PDT 24
Peak memory 200544 kb
Host smart-599c4ef0-3024-4bc4-a028-b24a406605ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679625561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2679625561
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2700090746
Short name T185
Test name
Test status
Simulation time 27701827 ps
CPU time 0.56 seconds
Started Jul 13 06:07:49 PM PDT 24
Finished Jul 13 06:09:07 PM PDT 24
Peak memory 196188 kb
Host smart-db3d65c1-3532-4da7-ae41-610a143aac8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700090746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2700090746
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2701161647
Short name T294
Test name
Test status
Simulation time 4044987991 ps
CPU time 60.95 seconds
Started Jul 13 06:07:58 PM PDT 24
Finished Jul 13 06:10:14 PM PDT 24
Peak memory 200524 kb
Host smart-a83ec593-d10b-4c05-870b-d701495ef201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701161647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2701161647
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.613951361
Short name T432
Test name
Test status
Simulation time 87973889 ps
CPU time 2 seconds
Started Jul 13 06:07:52 PM PDT 24
Finished Jul 13 06:09:09 PM PDT 24
Peak memory 200264 kb
Host smart-a9783d32-0059-453e-8862-a084fecf5ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613951361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.613951361
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2368237793
Short name T509
Test name
Test status
Simulation time 1998166098 ps
CPU time 79.82 seconds
Started Jul 13 06:07:57 PM PDT 24
Finished Jul 13 06:10:32 PM PDT 24
Peak memory 357552 kb
Host smart-86909133-83b5-4024-91b9-bc954f38fe88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368237793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2368237793
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1210199601
Short name T391
Test name
Test status
Simulation time 412007139 ps
CPU time 23.21 seconds
Started Jul 13 06:07:50 PM PDT 24
Finished Jul 13 06:09:30 PM PDT 24
Peak memory 200216 kb
Host smart-679f17e0-c5d6-4df5-8cc1-19dcc5ae91a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210199601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1210199601
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1683279861
Short name T198
Test name
Test status
Simulation time 9255873137 ps
CPU time 136.44 seconds
Started Jul 13 06:07:50 PM PDT 24
Finished Jul 13 06:11:23 PM PDT 24
Peak memory 200264 kb
Host smart-42444b70-5407-46e3-a810-e8b4054c9dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683279861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1683279861
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3926892964
Short name T328
Test name
Test status
Simulation time 176385152 ps
CPU time 7.86 seconds
Started Jul 13 06:07:50 PM PDT 24
Finished Jul 13 06:09:14 PM PDT 24
Peak memory 200300 kb
Host smart-03fcf0e3-3417-4a58-ba85-fc705e01ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926892964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3926892964
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3743041891
Short name T8
Test name
Test status
Simulation time 20700567050 ps
CPU time 631.21 seconds
Started Jul 13 06:07:58 PM PDT 24
Finished Jul 13 06:19:44 PM PDT 24
Peak memory 480736 kb
Host smart-cfcb9c6e-1ad9-45ec-bbb4-9001c03c5cb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743041891 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3743041891
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.745000403
Short name T516
Test name
Test status
Simulation time 2721320898 ps
CPU time 77.13 seconds
Started Jul 13 06:07:53 PM PDT 24
Finished Jul 13 06:10:25 PM PDT 24
Peak memory 200272 kb
Host smart-752a2491-44d6-4f56-ad37-76227d0ee558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745000403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.745000403
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2733969740
Short name T415
Test name
Test status
Simulation time 15593209 ps
CPU time 0.61 seconds
Started Jul 13 06:08:00 PM PDT 24
Finished Jul 13 06:09:15 PM PDT 24
Peak memory 196848 kb
Host smart-09aa6b63-0a30-454b-b9f4-51a3baada886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733969740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2733969740
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1751021385
Short name T233
Test name
Test status
Simulation time 1060076735 ps
CPU time 62.14 seconds
Started Jul 13 06:07:49 PM PDT 24
Finished Jul 13 06:10:08 PM PDT 24
Peak memory 200220 kb
Host smart-5ba30b30-2d82-4a67-9dd9-3f840189214e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751021385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1751021385
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1228119261
Short name T522
Test name
Test status
Simulation time 2015510157 ps
CPU time 25.5 seconds
Started Jul 13 06:08:03 PM PDT 24
Finished Jul 13 06:09:43 PM PDT 24
Peak memory 200320 kb
Host smart-7de5bca0-d503-4723-be5f-e0a4eb6954f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228119261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1228119261
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2013491200
Short name T479
Test name
Test status
Simulation time 2640903284 ps
CPU time 432.37 seconds
Started Jul 13 06:07:49 PM PDT 24
Finished Jul 13 06:16:14 PM PDT 24
Peak memory 663076 kb
Host smart-f2919b64-9516-4070-96a4-a17ec9f6993c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013491200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2013491200
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2173237720
Short name T301
Test name
Test status
Simulation time 5684847151 ps
CPU time 50.12 seconds
Started Jul 13 06:07:59 PM PDT 24
Finished Jul 13 06:10:04 PM PDT 24
Peak memory 200396 kb
Host smart-9f50b6d7-b2ea-455e-bd7c-d8da1b4f2a62
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173237720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2173237720
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1678699872
Short name T306
Test name
Test status
Simulation time 3349069979 ps
CPU time 46.58 seconds
Started Jul 13 06:07:50 PM PDT 24
Finished Jul 13 06:09:53 PM PDT 24
Peak memory 200280 kb
Host smart-762b31c9-5803-4574-8c26-4f7f29b87b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678699872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1678699872
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.189423033
Short name T221
Test name
Test status
Simulation time 236670779 ps
CPU time 5.89 seconds
Started Jul 13 06:07:57 PM PDT 24
Finished Jul 13 06:09:18 PM PDT 24
Peak memory 200436 kb
Host smart-d88497bf-bc73-44e7-892a-418870a198ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189423033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.189423033
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3546468817
Short name T423
Test name
Test status
Simulation time 14581048869 ps
CPU time 807.6 seconds
Started Jul 13 06:08:00 PM PDT 24
Finished Jul 13 06:22:42 PM PDT 24
Peak memory 326144 kb
Host smart-2fdfc677-714a-46d0-9043-69af12ff978a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546468817 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3546468817
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1201632757
Short name T290
Test name
Test status
Simulation time 2155348223 ps
CPU time 49.08 seconds
Started Jul 13 06:08:00 PM PDT 24
Finished Jul 13 06:10:03 PM PDT 24
Peak memory 200324 kb
Host smart-cd031681-be0d-4586-be1a-261bd31af11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201632757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1201632757
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1282878506
Short name T179
Test name
Test status
Simulation time 195750675 ps
CPU time 6.02 seconds
Started Jul 13 06:07:59 PM PDT 24
Finished Jul 13 06:09:20 PM PDT 24
Peak memory 200188 kb
Host smart-01012ec2-57a1-4ebf-b131-5722f03e4280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282878506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1282878506
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4121535195
Short name T137
Test name
Test status
Simulation time 26993459209 ps
CPU time 87.69 seconds
Started Jul 13 06:08:00 PM PDT 24
Finished Jul 13 06:10:42 PM PDT 24
Peak memory 200268 kb
Host smart-74a62b7d-286e-4849-a519-3b6daa8ac558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121535195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4121535195
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3312536144
Short name T515
Test name
Test status
Simulation time 483030349 ps
CPU time 91.21 seconds
Started Jul 13 06:08:00 PM PDT 24
Finished Jul 13 06:10:46 PM PDT 24
Peak memory 552856 kb
Host smart-61a4e638-e713-421a-9115-95f47d5d9edd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312536144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3312536144
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3002434313
Short name T413
Test name
Test status
Simulation time 13987543284 ps
CPU time 43.68 seconds
Started Jul 13 06:08:02 PM PDT 24
Finished Jul 13 06:09:58 PM PDT 24
Peak memory 200404 kb
Host smart-2deaee04-6683-4a36-b597-151311517265
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002434313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3002434313
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1787876056
Short name T26
Test name
Test status
Simulation time 3015346402 ps
CPU time 41.98 seconds
Started Jul 13 06:08:03 PM PDT 24
Finished Jul 13 06:09:57 PM PDT 24
Peak memory 200380 kb
Host smart-7c9a08ca-b048-49ef-8e6b-72259b0a93ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787876056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1787876056
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1909364239
Short name T60
Test name
Test status
Simulation time 60610880 ps
CPU time 1.2 seconds
Started Jul 13 06:07:59 PM PDT 24
Finished Jul 13 06:09:15 PM PDT 24
Peak memory 200360 kb
Host smart-673f4376-979f-4738-a0bc-7a227c6f0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909364239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1909364239
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4123124722
Short name T327
Test name
Test status
Simulation time 38353352986 ps
CPU time 118.94 seconds
Started Jul 13 06:08:03 PM PDT 24
Finished Jul 13 06:11:17 PM PDT 24
Peak memory 200416 kb
Host smart-a3f85be0-79ff-43d1-9613-2390203748ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123124722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4123124722
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.701609686
Short name T430
Test name
Test status
Simulation time 16524401 ps
CPU time 0.57 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:09:26 PM PDT 24
Peak memory 195160 kb
Host smart-4ab653ab-5ced-4bd7-bb91-f800428bdd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701609686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.701609686
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2417720190
Short name T410
Test name
Test status
Simulation time 1621444139 ps
CPU time 90.06 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:10:55 PM PDT 24
Peak memory 200064 kb
Host smart-7dd8e44f-c65b-45b0-8f6a-bbda9d5336c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417720190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2417720190
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2116396025
Short name T141
Test name
Test status
Simulation time 21688035909 ps
CPU time 55.69 seconds
Started Jul 13 06:08:18 PM PDT 24
Finished Jul 13 06:10:28 PM PDT 24
Peak memory 208580 kb
Host smart-b3604310-55bf-486e-a61d-7358ca2232ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116396025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2116396025
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1911712448
Short name T419
Test name
Test status
Simulation time 3466899507 ps
CPU time 322.1 seconds
Started Jul 13 06:08:16 PM PDT 24
Finished Jul 13 06:14:54 PM PDT 24
Peak memory 655576 kb
Host smart-2b1788f0-3c50-4480-b21a-e086abcbf83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911712448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1911712448
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.575609276
Short name T157
Test name
Test status
Simulation time 6435189981 ps
CPU time 105.32 seconds
Started Jul 13 06:08:09 PM PDT 24
Finished Jul 13 06:11:06 PM PDT 24
Peak memory 200284 kb
Host smart-6fa0dc89-778b-4ab9-b5af-f51682953a4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575609276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.575609276
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.447315759
Short name T496
Test name
Test status
Simulation time 21555687460 ps
CPU time 38.04 seconds
Started Jul 13 06:08:14 PM PDT 24
Finished Jul 13 06:10:08 PM PDT 24
Peak memory 200324 kb
Host smart-18e4367a-5a62-41aa-b78f-1eaa552fb01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447315759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.447315759
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3208668144
Short name T194
Test name
Test status
Simulation time 601357198 ps
CPU time 7.2 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:09:33 PM PDT 24
Peak memory 200560 kb
Host smart-8b8cfe3f-6e60-450e-b5e3-01abd8a5409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208668144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3208668144
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3670158073
Short name T253
Test name
Test status
Simulation time 63326778475 ps
CPU time 1948.07 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:41:54 PM PDT 24
Peak memory 731340 kb
Host smart-cd371784-75e1-4965-8936-b96ddd30fa58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670158073 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3670158073
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1352820447
Short name T344
Test name
Test status
Simulation time 27333441231 ps
CPU time 119.65 seconds
Started Jul 13 06:08:17 PM PDT 24
Finished Jul 13 06:11:32 PM PDT 24
Peak memory 200160 kb
Host smart-5a62d036-c1af-4009-80c7-4ba5e54c3cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352820447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1352820447
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2809404119
Short name T220
Test name
Test status
Simulation time 11037092 ps
CPU time 0.58 seconds
Started Jul 13 06:08:11 PM PDT 24
Finished Jul 13 06:09:26 PM PDT 24
Peak memory 195116 kb
Host smart-60891c89-30b5-44cb-a36f-d7e794abb555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809404119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2809404119
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1722911298
Short name T359
Test name
Test status
Simulation time 3122253290 ps
CPU time 46.48 seconds
Started Jul 13 06:08:11 PM PDT 24
Finished Jul 13 06:10:12 PM PDT 24
Peak memory 200340 kb
Host smart-eab840d3-db75-477d-9e87-68871943a667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722911298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1722911298
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1444077855
Short name T156
Test name
Test status
Simulation time 19127880055 ps
CPU time 51.21 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:10:16 PM PDT 24
Peak memory 200468 kb
Host smart-77554925-7bf8-40f7-b8e3-edf070a79ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444077855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1444077855
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3060368712
Short name T382
Test name
Test status
Simulation time 14159451 ps
CPU time 0.71 seconds
Started Jul 13 06:08:11 PM PDT 24
Finished Jul 13 06:09:26 PM PDT 24
Peak memory 199480 kb
Host smart-d20d1d1f-b34d-4c3e-b070-d6146ef42e2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3060368712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3060368712
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1377074337
Short name T183
Test name
Test status
Simulation time 35248618123 ps
CPU time 113.48 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:11:19 PM PDT 24
Peak memory 200384 kb
Host smart-2c740b29-c8ec-4a77-bf88-775da633394c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377074337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1377074337
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1215383872
Short name T240
Test name
Test status
Simulation time 585488197 ps
CPU time 8.26 seconds
Started Jul 13 06:08:11 PM PDT 24
Finished Jul 13 06:09:34 PM PDT 24
Peak memory 200304 kb
Host smart-a8c64fed-a273-46f7-afff-4c3982f21dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215383872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1215383872
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3091183921
Short name T162
Test name
Test status
Simulation time 311690428 ps
CPU time 4.21 seconds
Started Jul 13 06:08:10 PM PDT 24
Finished Jul 13 06:09:30 PM PDT 24
Peak memory 200344 kb
Host smart-9d0bfd1a-48b9-4cbe-8303-3ceb23aa8ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091183921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3091183921
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.693760108
Short name T44
Test name
Test status
Simulation time 77167614377 ps
CPU time 561.16 seconds
Started Jul 13 06:08:13 PM PDT 24
Finished Jul 13 06:18:48 PM PDT 24
Peak memory 208540 kb
Host smart-e786e534-51b8-441f-b5a9-a023ecab02c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693760108 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.693760108
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2398735892
Short name T427
Test name
Test status
Simulation time 178532129 ps
CPU time 3.67 seconds
Started Jul 13 06:08:11 PM PDT 24
Finished Jul 13 06:09:29 PM PDT 24
Peak memory 200200 kb
Host smart-1632b704-19b8-47a0-a682-5ad6fe1b6bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398735892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2398735892
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3621267939
Short name T426
Test name
Test status
Simulation time 13550506 ps
CPU time 0.6 seconds
Started Jul 13 06:08:19 PM PDT 24
Finished Jul 13 06:09:36 PM PDT 24
Peak memory 196852 kb
Host smart-830c35b6-f9f2-436d-9a26-9f4ad7e069c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621267939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3621267939
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3044636779
Short name T271
Test name
Test status
Simulation time 2325183372 ps
CPU time 69.47 seconds
Started Jul 13 06:08:18 PM PDT 24
Finished Jul 13 06:10:42 PM PDT 24
Peak memory 200352 kb
Host smart-7099f460-4824-4286-a272-e5b9e12cb224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044636779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3044636779
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3238597140
Short name T358
Test name
Test status
Simulation time 5450266332 ps
CPU time 48.21 seconds
Started Jul 13 06:08:20 PM PDT 24
Finished Jul 13 06:10:24 PM PDT 24
Peak memory 200348 kb
Host smart-55b21b59-916f-4b09-92b9-c76ac9c0a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238597140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3238597140
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4034481928
Short name T250
Test name
Test status
Simulation time 28930309381 ps
CPU time 1330.3 seconds
Started Jul 13 06:08:19 PM PDT 24
Finished Jul 13 06:31:46 PM PDT 24
Peak memory 736844 kb
Host smart-b148501e-86af-4b38-9202-f614bfa79660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034481928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4034481928
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.492484803
Short name T76
Test name
Test status
Simulation time 20133908997 ps
CPU time 81.13 seconds
Started Jul 13 06:08:21 PM PDT 24
Finished Jul 13 06:10:57 PM PDT 24
Peak memory 200260 kb
Host smart-83fe02d6-fdf6-4dc8-bd84-061975402756
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492484803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.492484803
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.599311174
Short name T305
Test name
Test status
Simulation time 47483820785 ps
CPU time 227.48 seconds
Started Jul 13 06:08:18 PM PDT 24
Finished Jul 13 06:13:20 PM PDT 24
Peak memory 200076 kb
Host smart-8c599f31-783e-4e94-bfb7-665606570b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599311174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.599311174
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1531109596
Short name T310
Test name
Test status
Simulation time 355049795 ps
CPU time 6.45 seconds
Started Jul 13 06:08:17 PM PDT 24
Finished Jul 13 06:09:39 PM PDT 24
Peak memory 200312 kb
Host smart-f8792dd1-2218-4f1b-b5c2-db8aed33c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531109596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1531109596
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1004539642
Short name T80
Test name
Test status
Simulation time 235479549238 ps
CPU time 1612.54 seconds
Started Jul 13 06:08:18 PM PDT 24
Finished Jul 13 06:36:28 PM PDT 24
Peak memory 791848 kb
Host smart-e9e26870-a9f9-43a8-87e3-cbbaac4e89f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004539642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1004539642
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1364012945
Short name T222
Test name
Test status
Simulation time 32124287720 ps
CPU time 80.15 seconds
Started Jul 13 06:08:21 PM PDT 24
Finished Jul 13 06:10:56 PM PDT 24
Peak memory 200328 kb
Host smart-a4f14698-4323-422a-8ba2-29bc95e406a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364012945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1364012945
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2136134357
Short name T308
Test name
Test status
Simulation time 22308108 ps
CPU time 0.58 seconds
Started Jul 13 06:08:27 PM PDT 24
Finished Jul 13 06:09:43 PM PDT 24
Peak memory 195812 kb
Host smart-f0e21aa1-9d5e-44e0-a035-173f9bd8d915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136134357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2136134357
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1118129310
Short name T503
Test name
Test status
Simulation time 52444706 ps
CPU time 3.04 seconds
Started Jul 13 06:08:18 PM PDT 24
Finished Jul 13 06:09:38 PM PDT 24
Peak memory 200324 kb
Host smart-83267711-0a87-4bbc-ba4c-4b8bd56fcefc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118129310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1118129310
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1293568271
Short name T352
Test name
Test status
Simulation time 1640691554 ps
CPU time 22.1 seconds
Started Jul 13 06:08:27 PM PDT 24
Finished Jul 13 06:10:05 PM PDT 24
Peak memory 200304 kb
Host smart-6020224f-9fbc-4e30-91b1-3c0d6c749992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293568271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1293568271
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4285218513
Short name T90
Test name
Test status
Simulation time 7339312082 ps
CPU time 229.6 seconds
Started Jul 13 06:08:27 PM PDT 24
Finished Jul 13 06:13:32 PM PDT 24
Peak memory 367572 kb
Host smart-62716108-02e9-4969-a2d4-89d37de03725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285218513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4285218513
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.302394146
Short name T349
Test name
Test status
Simulation time 23056063524 ps
CPU time 186.6 seconds
Started Jul 13 06:08:27 PM PDT 24
Finished Jul 13 06:12:49 PM PDT 24
Peak memory 200364 kb
Host smart-efab155e-af3c-4bb7-9c69-da74f09d878a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302394146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.302394146
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.573416393
Short name T304
Test name
Test status
Simulation time 7750956865 ps
CPU time 108.1 seconds
Started Jul 13 06:08:19 PM PDT 24
Finished Jul 13 06:11:24 PM PDT 24
Peak memory 216680 kb
Host smart-d028e4eb-2a38-470a-8738-eaa15d32e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573416393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.573416393
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3635814928
Short name T455
Test name
Test status
Simulation time 391827725 ps
CPU time 6.31 seconds
Started Jul 13 06:08:21 PM PDT 24
Finished Jul 13 06:09:42 PM PDT 24
Peak memory 200224 kb
Host smart-8b78909c-28c8-4a71-ab07-a50f0d7122d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635814928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3635814928
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.237112338
Short name T96
Test name
Test status
Simulation time 18278843936 ps
CPU time 227.93 seconds
Started Jul 13 06:08:28 PM PDT 24
Finished Jul 13 06:13:31 PM PDT 24
Peak memory 200352 kb
Host smart-8dfd6e5f-65b6-4556-801d-6bf7ecd82c6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237112338 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.237112338
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3556329710
Short name T398
Test name
Test status
Simulation time 24118064731 ps
CPU time 80.17 seconds
Started Jul 13 06:08:25 PM PDT 24
Finished Jul 13 06:11:02 PM PDT 24
Peak memory 200420 kb
Host smart-ce92201b-1bdd-4f6c-a5ca-ff957a503b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556329710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3556329710
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3457677404
Short name T246
Test name
Test status
Simulation time 11355553 ps
CPU time 0.56 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:09:53 PM PDT 24
Peak memory 195084 kb
Host smart-441a0f21-8716-4377-8e30-681f2fee168d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457677404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3457677404
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2399228175
Short name T172
Test name
Test status
Simulation time 113444029 ps
CPU time 6.46 seconds
Started Jul 13 06:08:26 PM PDT 24
Finished Jul 13 06:09:49 PM PDT 24
Peak memory 199988 kb
Host smart-2318e233-5372-4c6f-bbd8-da8691534b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399228175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2399228175
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1570104842
Short name T440
Test name
Test status
Simulation time 17671641787 ps
CPU time 15.56 seconds
Started Jul 13 06:08:26 PM PDT 24
Finished Jul 13 06:09:58 PM PDT 24
Peak memory 200284 kb
Host smart-554a9239-0522-4e4a-9e3e-04d7f9be46cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570104842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1570104842
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2078754527
Short name T443
Test name
Test status
Simulation time 12987348713 ps
CPU time 561.48 seconds
Started Jul 13 06:08:28 PM PDT 24
Finished Jul 13 06:19:04 PM PDT 24
Peak memory 659676 kb
Host smart-7d83e2a9-6ff3-4ebc-89df-bb942caae7cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078754527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2078754527
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.825022551
Short name T265
Test name
Test status
Simulation time 7324582779 ps
CPU time 99.8 seconds
Started Jul 13 06:08:42 PM PDT 24
Finished Jul 13 06:11:39 PM PDT 24
Peak memory 200304 kb
Host smart-e549e84f-18f5-4980-b719-3000df94d74c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825022551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.825022551
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2827632016
Short name T447
Test name
Test status
Simulation time 10146918737 ps
CPU time 128.32 seconds
Started Jul 13 06:08:26 PM PDT 24
Finished Jul 13 06:11:51 PM PDT 24
Peak memory 216592 kb
Host smart-67e16379-5366-45fb-93f0-79f841e7e0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827632016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2827632016
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3695149436
Short name T28
Test name
Test status
Simulation time 3895529084 ps
CPU time 12.48 seconds
Started Jul 13 06:08:27 PM PDT 24
Finished Jul 13 06:09:55 PM PDT 24
Peak memory 200328 kb
Host smart-52070474-bb9d-47ae-b292-baae645fbf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695149436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3695149436
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.924125506
Short name T81
Test name
Test status
Simulation time 412283267669 ps
CPU time 1450.47 seconds
Started Jul 13 06:08:39 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 680016 kb
Host smart-0be92e64-224b-46fb-817f-bb0eaff608b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924125506 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.924125506
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1018155592
Short name T381
Test name
Test status
Simulation time 2958317807 ps
CPU time 25.97 seconds
Started Jul 13 06:08:36 PM PDT 24
Finished Jul 13 06:10:19 PM PDT 24
Peak memory 200336 kb
Host smart-8c326aae-11fe-416c-9343-4db44c0a31db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018155592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1018155592
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3543923108
Short name T188
Test name
Test status
Simulation time 12624492 ps
CPU time 0.57 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:09:53 PM PDT 24
Peak memory 195176 kb
Host smart-f43315c7-1dad-469e-8a00-47af19d216e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543923108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3543923108
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3152315273
Short name T302
Test name
Test status
Simulation time 2512408475 ps
CPU time 29.97 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:10:23 PM PDT 24
Peak memory 200352 kb
Host smart-f416d8d7-4456-4da8-a213-92ebdf33d866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3152315273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3152315273
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3961597196
Short name T45
Test name
Test status
Simulation time 4821542950 ps
CPU time 55.49 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:10:48 PM PDT 24
Peak memory 200356 kb
Host smart-eaf62fee-aff7-47e6-b397-b1f6507817a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961597196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3961597196
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.387278317
Short name T78
Test name
Test status
Simulation time 2095313401 ps
CPU time 386.21 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:16:19 PM PDT 24
Peak memory 672888 kb
Host smart-e2b41a57-b04d-4c4e-a1af-d83bea96a53d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387278317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.387278317
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2988974060
Short name T75
Test name
Test status
Simulation time 10753886971 ps
CPU time 199.85 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:13:13 PM PDT 24
Peak memory 200344 kb
Host smart-81e315d6-d8f6-48fd-8ade-0c94b5dda11a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988974060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2988974060
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1011510653
Short name T463
Test name
Test status
Simulation time 79727879599 ps
CPU time 181.9 seconds
Started Jul 13 06:08:40 PM PDT 24
Finished Jul 13 06:13:00 PM PDT 24
Peak memory 216716 kb
Host smart-ceb87c21-6969-48cd-8354-99cfa7dbde5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011510653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1011510653
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3930313162
Short name T36
Test name
Test status
Simulation time 93702915 ps
CPU time 4.36 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:09:57 PM PDT 24
Peak memory 200268 kb
Host smart-edbe661b-2caf-44cf-96b2-bf0084d6c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930313162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3930313162
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1693981817
Short name T388
Test name
Test status
Simulation time 24199501795 ps
CPU time 290.2 seconds
Started Jul 13 06:08:36 PM PDT 24
Finished Jul 13 06:14:43 PM PDT 24
Peak memory 200348 kb
Host smart-75448b8b-86fa-4600-93d2-5de80a9d1c21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693981817 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1693981817
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.431108247
Short name T34
Test name
Test status
Simulation time 2128075746 ps
CPU time 24.87 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:10:18 PM PDT 24
Peak memory 200248 kb
Host smart-acbc8d81-b723-4fac-a527-ed5a1a124fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431108247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.431108247
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.945735144
Short name T59
Test name
Test status
Simulation time 42101019 ps
CPU time 0.62 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:08:30 PM PDT 24
Peak memory 195120 kb
Host smart-55aaa9e1-0ef5-4bbd-b55f-2c70c20a6fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945735144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.945735144
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.769503325
Short name T468
Test name
Test status
Simulation time 10583143790 ps
CPU time 44.41 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:09:14 PM PDT 24
Peak memory 200340 kb
Host smart-19434a47-62c5-442b-ad9b-4510502136fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769503325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.769503325
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1177636411
Short name T470
Test name
Test status
Simulation time 8301692111 ps
CPU time 36.49 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:09:07 PM PDT 24
Peak memory 200372 kb
Host smart-1b2becfc-70d3-4117-a079-485b1b753560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177636411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1177636411
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2292350721
Short name T485
Test name
Test status
Simulation time 1280106638 ps
CPU time 211.27 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:12:02 PM PDT 24
Peak memory 481936 kb
Host smart-f79b6a9c-8fdc-4242-84e6-f8fa94e71a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292350721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2292350721
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.467807423
Short name T252
Test name
Test status
Simulation time 2557974036 ps
CPU time 124.01 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:10:35 PM PDT 24
Peak memory 200260 kb
Host smart-5db7488f-fd00-4ba4-a750-e7ab06a28996
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467807423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.467807423
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3662384962
Short name T226
Test name
Test status
Simulation time 52510695566 ps
CPU time 136.21 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:10:46 PM PDT 24
Peak memory 200364 kb
Host smart-a87d0cfd-86f3-4634-83c0-ff2092058cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662384962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3662384962
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4181121971
Short name T53
Test name
Test status
Simulation time 107353774 ps
CPU time 1.01 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:08:32 PM PDT 24
Peak memory 219392 kb
Host smart-0ed44029-3fb8-4701-924a-a9475b9c703c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181121971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4181121971
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3220501548
Short name T55
Test name
Test status
Simulation time 4796798083 ps
CPU time 5.04 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:08:35 PM PDT 24
Peak memory 200280 kb
Host smart-1a860c57-07f6-46df-9f1e-89a06641e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220501548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3220501548
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2858256543
Short name T12
Test name
Test status
Simulation time 39286236899 ps
CPU time 723.77 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:20:35 PM PDT 24
Peak memory 585612 kb
Host smart-a89a8051-43e7-47b9-9fdb-690a1c4717ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858256543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2858256543
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.384694735
Short name T394
Test name
Test status
Simulation time 8831058384 ps
CPU time 41.89 seconds
Started Jul 13 06:07:16 PM PDT 24
Finished Jul 13 06:09:08 PM PDT 24
Peak memory 200304 kb
Host smart-19b4b0d1-947c-44aa-bb21-90d4f46fcfdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=384694735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.384694735
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.581138362
Short name T313
Test name
Test status
Simulation time 2306285555 ps
CPU time 87.39 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:09:59 PM PDT 24
Peak memory 200244 kb
Host smart-b333ab7f-72d6-404e-9c5b-c75ff84b72e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=581138362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.581138362
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.917501430
Short name T215
Test name
Test status
Simulation time 31784033919 ps
CPU time 116.22 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:10:26 PM PDT 24
Peak memory 200344 kb
Host smart-287ec0e1-b694-4ada-a424-6f72c8dbdbc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=917501430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.917501430
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3125680197
Short name T317
Test name
Test status
Simulation time 36486184606 ps
CPU time 602.65 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:18:34 PM PDT 24
Peak memory 200284 kb
Host smart-4a6cc157-3e1b-49bb-993c-e4c1eb50fee3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3125680197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3125680197
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1015807962
Short name T254
Test name
Test status
Simulation time 229757596659 ps
CPU time 2346.86 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:47:37 PM PDT 24
Peak memory 215932 kb
Host smart-c29fe3bb-1ab6-40b0-8330-8139c26ec957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1015807962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1015807962
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2520931885
Short name T448
Test name
Test status
Simulation time 763994887020 ps
CPU time 2520.83 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:50:32 PM PDT 24
Peak memory 216496 kb
Host smart-ac190030-c67e-4afc-9f48-6254b878ec3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2520931885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2520931885
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2491811067
Short name T184
Test name
Test status
Simulation time 3003505495 ps
CPU time 103.52 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:10:14 PM PDT 24
Peak memory 200360 kb
Host smart-d09588c0-d8a7-48ba-81ab-a28b80a8c288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491811067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2491811067
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2495801101
Short name T196
Test name
Test status
Simulation time 20334037 ps
CPU time 0.59 seconds
Started Jul 13 06:08:39 PM PDT 24
Finished Jul 13 06:09:58 PM PDT 24
Peak memory 196864 kb
Host smart-983b8007-7e24-45df-8551-afee0351688d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495801101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2495801101
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3265814791
Short name T147
Test name
Test status
Simulation time 420687016 ps
CPU time 23.78 seconds
Started Jul 13 06:08:36 PM PDT 24
Finished Jul 13 06:10:16 PM PDT 24
Peak memory 200324 kb
Host smart-6ed44ef3-3eb5-40cf-9137-37f49864de01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265814791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3265814791
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1949335011
Short name T385
Test name
Test status
Simulation time 86004717 ps
CPU time 0.83 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:09:54 PM PDT 24
Peak memory 198968 kb
Host smart-a58130f7-f9cd-4685-9461-0d6736b17798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949335011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1949335011
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4238923872
Short name T236
Test name
Test status
Simulation time 3985894627 ps
CPU time 95.59 seconds
Started Jul 13 06:08:37 PM PDT 24
Finished Jul 13 06:11:28 PM PDT 24
Peak memory 547020 kb
Host smart-6e26400a-685e-4f21-995b-ea721c6b7216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238923872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4238923872
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3382919366
Short name T316
Test name
Test status
Simulation time 24205874733 ps
CPU time 75.5 seconds
Started Jul 13 06:08:40 PM PDT 24
Finished Jul 13 06:11:14 PM PDT 24
Peak memory 200260 kb
Host smart-880d2487-91d3-41ed-9c27-1ac31cd1ef4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382919366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3382919366
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2330374690
Short name T211
Test name
Test status
Simulation time 3854573626 ps
CPU time 209.09 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:13:22 PM PDT 24
Peak memory 200308 kb
Host smart-ba5a585b-25da-4709-8874-1aa151b00c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330374690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2330374690
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2896752060
Short name T506
Test name
Test status
Simulation time 4004243569 ps
CPU time 12.75 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:10:06 PM PDT 24
Peak memory 200376 kb
Host smart-f9442107-3d13-41ca-8b49-883adaa48127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896752060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2896752060
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2944937010
Short name T98
Test name
Test status
Simulation time 75954244771 ps
CPU time 1571.18 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:36:04 PM PDT 24
Peak memory 652404 kb
Host smart-cb971d27-7b18-465f-a5f5-6b800098c0b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944937010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2944937010
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3670828873
Short name T173
Test name
Test status
Simulation time 483816099 ps
CPU time 25.69 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:10:19 PM PDT 24
Peak memory 200232 kb
Host smart-ac9b02ab-4f6b-47da-b66d-c28ff7fe2ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670828873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3670828873
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1429878640
Short name T401
Test name
Test status
Simulation time 17430275 ps
CPU time 0.6 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:10:06 PM PDT 24
Peak memory 196860 kb
Host smart-ca899a1a-9b3f-4c48-bd0a-5c0570d581c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429878640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1429878640
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2031804969
Short name T282
Test name
Test status
Simulation time 286899340 ps
CPU time 16.93 seconds
Started Jul 13 06:08:40 PM PDT 24
Finished Jul 13 06:10:15 PM PDT 24
Peak memory 200284 kb
Host smart-4e776cff-3077-4d95-a0b4-a4617dde5356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031804969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2031804969
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3043756411
Short name T357
Test name
Test status
Simulation time 1625808891 ps
CPU time 9.08 seconds
Started Jul 13 06:08:50 PM PDT 24
Finished Jul 13 06:10:14 PM PDT 24
Peak memory 200304 kb
Host smart-9592f2e6-9ece-4686-aa1d-bb40eb2adc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043756411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3043756411
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1111978000
Short name T202
Test name
Test status
Simulation time 14024398815 ps
CPU time 960.29 seconds
Started Jul 13 06:08:38 PM PDT 24
Finished Jul 13 06:25:53 PM PDT 24
Peak memory 748592 kb
Host smart-a3c23244-98bc-4b08-8678-08656a42a4a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111978000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1111978000
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.827721346
Short name T217
Test name
Test status
Simulation time 4321005865 ps
CPU time 39.1 seconds
Started Jul 13 06:08:48 PM PDT 24
Finished Jul 13 06:10:44 PM PDT 24
Peak memory 200300 kb
Host smart-79fcda8e-bf03-42a9-90c2-ef12db79d05a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827721346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.827721346
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1972089451
Short name T476
Test name
Test status
Simulation time 8229469939 ps
CPU time 56.19 seconds
Started Jul 13 06:08:40 PM PDT 24
Finished Jul 13 06:10:54 PM PDT 24
Peak memory 200360 kb
Host smart-c25fd397-0ef9-4765-83ef-73861960df0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972089451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1972089451
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4242327072
Short name T62
Test name
Test status
Simulation time 434086309 ps
CPU time 2.28 seconds
Started Jul 13 06:08:40 PM PDT 24
Finished Jul 13 06:10:01 PM PDT 24
Peak memory 200328 kb
Host smart-9b18c85e-a023-4062-93c5-eefc8f06f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242327072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4242327072
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1897581057
Short name T494
Test name
Test status
Simulation time 6922964384 ps
CPU time 469.2 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:17:54 PM PDT 24
Peak memory 618328 kb
Host smart-37bba65e-b17f-4e19-abbb-b451cafa7111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897581057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1897581057
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1467008611
Short name T445
Test name
Test status
Simulation time 2457314646 ps
CPU time 37.16 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:10:42 PM PDT 24
Peak memory 200284 kb
Host smart-77e10a55-df4d-4eeb-ba00-ac2eea2bd95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467008611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1467008611
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1939275079
Short name T409
Test name
Test status
Simulation time 33414594 ps
CPU time 0.62 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:10:01 PM PDT 24
Peak memory 196888 kb
Host smart-3ff05b23-a31c-4acd-b3ba-65836d5440b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939275079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1939275079
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.88655641
Short name T520
Test name
Test status
Simulation time 40469913 ps
CPU time 2.55 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:10:07 PM PDT 24
Peak memory 200212 kb
Host smart-e9d533b6-a209-4aad-8ba8-a0b4d4505252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88655641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.88655641
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2319431890
Short name T314
Test name
Test status
Simulation time 3020165940 ps
CPU time 57.52 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:10:58 PM PDT 24
Peak memory 200388 kb
Host smart-32652d9d-ddc2-4ff1-b8d2-4ccc3a4b8c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319431890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2319431890
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2753553375
Short name T473
Test name
Test status
Simulation time 6863673144 ps
CPU time 305.84 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:15:10 PM PDT 24
Peak memory 594708 kb
Host smart-55b1f067-f60e-4ab3-922c-dc17e27c00cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753553375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2753553375
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.447068691
Short name T201
Test name
Test status
Simulation time 9106057036 ps
CPU time 139.24 seconds
Started Jul 13 06:08:44 PM PDT 24
Finished Jul 13 06:12:19 PM PDT 24
Peak memory 200364 kb
Host smart-5ceff1a5-a1bf-46d0-b9c6-21ebc9c58af9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447068691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.447068691
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2504742312
Short name T269
Test name
Test status
Simulation time 7354778046 ps
CPU time 133.28 seconds
Started Jul 13 06:08:49 PM PDT 24
Finished Jul 13 06:12:19 PM PDT 24
Peak memory 200356 kb
Host smart-d527535b-a0b0-4da0-bb94-4f8a94a661cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504742312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2504742312
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3603848543
Short name T402
Test name
Test status
Simulation time 737915732 ps
CPU time 12.56 seconds
Started Jul 13 06:08:48 PM PDT 24
Finished Jul 13 06:10:18 PM PDT 24
Peak memory 200312 kb
Host smart-06c94020-643d-4243-a6fd-e0194060af94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603848543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3603848543
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2121701512
Short name T471
Test name
Test status
Simulation time 7559805309 ps
CPU time 227.11 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:13:52 PM PDT 24
Peak memory 200352 kb
Host smart-a7fce32b-531d-4d04-af3f-64326445f83f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121701512 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2121701512
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1375457567
Short name T18
Test name
Test status
Simulation time 2244142922 ps
CPU time 24.76 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:10:29 PM PDT 24
Peak memory 200292 kb
Host smart-454fb3a1-1232-40c1-b3e5-2c356958ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375457567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1375457567
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2236178135
Short name T208
Test name
Test status
Simulation time 17318084 ps
CPU time 0.61 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:10:05 PM PDT 24
Peak memory 196208 kb
Host smart-f5dbfe95-d013-4586-b668-7a3e8337730e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236178135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2236178135
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.687289888
Short name T518
Test name
Test status
Simulation time 745256274 ps
CPU time 43.31 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:10:48 PM PDT 24
Peak memory 200320 kb
Host smart-e08e3d0c-3bed-486f-b775-052b1e8d921f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687289888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.687289888
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4219878768
Short name T239
Test name
Test status
Simulation time 2908272262 ps
CPU time 50.15 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:10:51 PM PDT 24
Peak memory 200292 kb
Host smart-c267c716-db3d-4951-ad99-bf2953373914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219878768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4219878768
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2267080775
Short name T37
Test name
Test status
Simulation time 3506756493 ps
CPU time 473.53 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:17:58 PM PDT 24
Peak memory 607292 kb
Host smart-b3d5066c-36d7-460d-8bf7-0fe50d7b00ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267080775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2267080775
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1905489988
Short name T380
Test name
Test status
Simulation time 1860496373 ps
CPU time 35.72 seconds
Started Jul 13 06:08:48 PM PDT 24
Finished Jul 13 06:10:41 PM PDT 24
Peak memory 200212 kb
Host smart-d9fc0804-51bd-4dc8-9f75-85462cb60bd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905489988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1905489988
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.396693276
Short name T462
Test name
Test status
Simulation time 1044403938 ps
CPU time 7.27 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:10:08 PM PDT 24
Peak memory 200308 kb
Host smart-2d78c67e-14c0-4e9f-b0ed-80f4f778f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396693276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.396693276
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2952894264
Short name T43
Test name
Test status
Simulation time 1098783962 ps
CPU time 13.51 seconds
Started Jul 13 06:08:44 PM PDT 24
Finished Jul 13 06:10:14 PM PDT 24
Peak memory 200468 kb
Host smart-eb2544c1-c414-43ce-a2fe-c17ef4134939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952894264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2952894264
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4146002600
Short name T489
Test name
Test status
Simulation time 94043775520 ps
CPU time 2724.81 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:55:30 PM PDT 24
Peak memory 815028 kb
Host smart-27b65414-77b6-42aa-802d-801d84f0fde5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146002600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4146002600
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3466994331
Short name T203
Test name
Test status
Simulation time 5923630302 ps
CPU time 81.14 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:11:21 PM PDT 24
Peak memory 200416 kb
Host smart-93a5b966-9a7d-4427-b3a3-3ac7805979a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466994331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3466994331
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3729805156
Short name T353
Test name
Test status
Simulation time 10931926 ps
CPU time 0.59 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:10:05 PM PDT 24
Peak memory 195156 kb
Host smart-3e844063-decf-41c1-b16c-5b1d23aed6e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729805156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3729805156
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3574150993
Short name T484
Test name
Test status
Simulation time 279793512 ps
CPU time 15.58 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:10:16 PM PDT 24
Peak memory 200224 kb
Host smart-374b7886-e86d-4137-bb15-76061888887f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574150993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3574150993
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2072396138
Short name T20
Test name
Test status
Simulation time 2702446169 ps
CPU time 37.88 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:10:38 PM PDT 24
Peak memory 200416 kb
Host smart-e418b8b9-c2b0-4016-95c9-aed24b16b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072396138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2072396138
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1563072970
Short name T61
Test name
Test status
Simulation time 4118788109 ps
CPU time 396.5 seconds
Started Jul 13 06:08:44 PM PDT 24
Finished Jul 13 06:16:37 PM PDT 24
Peak memory 520668 kb
Host smart-90584609-8a45-45fb-9105-5478778a85a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563072970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1563072970
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3482699391
Short name T161
Test name
Test status
Simulation time 6206816694 ps
CPU time 88.49 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:11:29 PM PDT 24
Peak memory 200280 kb
Host smart-9f13cdd2-6fde-4951-b843-86c72cac8e9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482699391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3482699391
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2540386701
Short name T491
Test name
Test status
Simulation time 9396171644 ps
CPU time 165.27 seconds
Started Jul 13 06:08:48 PM PDT 24
Finished Jul 13 06:12:50 PM PDT 24
Peak memory 200352 kb
Host smart-4ed1693a-4537-4c7b-baae-01a817b562e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540386701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2540386701
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1910265988
Short name T500
Test name
Test status
Simulation time 602227960 ps
CPU time 6.16 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:10:11 PM PDT 24
Peak memory 200324 kb
Host smart-947af8f2-109c-4b2d-8399-84569306ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910265988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1910265988
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2409879046
Short name T23
Test name
Test status
Simulation time 85540384091 ps
CPU time 2165.08 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 711408 kb
Host smart-b41c83a9-4cca-4175-9e6c-3c8a6b1c26a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409879046 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2409879046
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2184248574
Short name T529
Test name
Test status
Simulation time 7191782199 ps
CPU time 124.54 seconds
Started Jul 13 06:08:45 PM PDT 24
Finished Jul 13 06:12:05 PM PDT 24
Peak memory 200372 kb
Host smart-dd799d21-8412-4e0b-805d-46111d5f8f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184248574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2184248574
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2782312435
Short name T360
Test name
Test status
Simulation time 12777840 ps
CPU time 0.65 seconds
Started Jul 13 06:08:52 PM PDT 24
Finished Jul 13 06:10:11 PM PDT 24
Peak memory 195756 kb
Host smart-b1da8b3f-be0a-4f09-b364-cfbe01505735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782312435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2782312435
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2170480581
Short name T267
Test name
Test status
Simulation time 218725615 ps
CPU time 12.72 seconds
Started Jul 13 06:08:49 PM PDT 24
Finished Jul 13 06:10:18 PM PDT 24
Peak memory 200308 kb
Host smart-747ebda4-6f8c-47f6-a7ab-0f222e045e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170480581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2170480581
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4100794666
Short name T364
Test name
Test status
Simulation time 1145752756 ps
CPU time 20.86 seconds
Started Jul 13 06:08:48 PM PDT 24
Finished Jul 13 06:10:26 PM PDT 24
Peak memory 200300 kb
Host smart-c9a4bad6-d805-4bed-9bbc-007d28ac2a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100794666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4100794666
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1915507198
Short name T405
Test name
Test status
Simulation time 3415765039 ps
CPU time 515.91 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 466396 kb
Host smart-c802f480-8ea4-4278-8748-214817ff772c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915507198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1915507198
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2124559569
Short name T248
Test name
Test status
Simulation time 3246813863 ps
CPU time 45.77 seconds
Started Jul 13 06:08:51 PM PDT 24
Finished Jul 13 06:10:51 PM PDT 24
Peak memory 200364 kb
Host smart-048490a4-5666-4654-8e22-03ac10dc5a47
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124559569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2124559569
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2547303565
Short name T283
Test name
Test status
Simulation time 33709894899 ps
CPU time 159.18 seconds
Started Jul 13 06:08:47 PM PDT 24
Finished Jul 13 06:12:44 PM PDT 24
Peak memory 200360 kb
Host smart-a4ac6c51-e450-4390-b2d7-56340da4476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547303565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2547303565
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.380274937
Short name T87
Test name
Test status
Simulation time 108045862 ps
CPU time 5.05 seconds
Started Jul 13 06:08:46 PM PDT 24
Finished Jul 13 06:10:10 PM PDT 24
Peak memory 200296 kb
Host smart-02821a4d-4afb-4204-981f-ccfab6eebafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380274937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.380274937
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2803299318
Short name T270
Test name
Test status
Simulation time 64153776001 ps
CPU time 989.97 seconds
Started Jul 13 06:08:56 PM PDT 24
Finished Jul 13 06:26:43 PM PDT 24
Peak memory 516452 kb
Host smart-c9b2cbaf-3a5b-4dd7-8607-5402a37bca1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803299318 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2803299318
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1357177817
Short name T399
Test name
Test status
Simulation time 5392301415 ps
CPU time 70.11 seconds
Started Jul 13 06:08:58 PM PDT 24
Finished Jul 13 06:11:23 PM PDT 24
Peak memory 200280 kb
Host smart-bd801824-d30f-46e8-9c4e-88a270f5acf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357177817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1357177817
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2844611364
Short name T299
Test name
Test status
Simulation time 25548934 ps
CPU time 0.59 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:10:12 PM PDT 24
Peak memory 196232 kb
Host smart-cfb885c6-b987-4cc1-8a10-7136a006dde6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844611364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2844611364
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3586376717
Short name T190
Test name
Test status
Simulation time 438244667 ps
CPU time 14.11 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:10:25 PM PDT 24
Peak memory 200188 kb
Host smart-293b4473-862a-4823-a85d-62f95d3992d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586376717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3586376717
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1775567579
Short name T264
Test name
Test status
Simulation time 13681886 ps
CPU time 0.72 seconds
Started Jul 13 06:08:54 PM PDT 24
Finished Jul 13 06:10:12 PM PDT 24
Peak memory 196740 kb
Host smart-e965bf43-475f-411f-a28e-5f646d1dca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775567579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1775567579
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2222833718
Short name T279
Test name
Test status
Simulation time 5129680390 ps
CPU time 993.78 seconds
Started Jul 13 06:08:52 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 726068 kb
Host smart-72c6f3b4-177d-4f6f-af55-578d78696dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222833718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2222833718
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3725526428
Short name T291
Test name
Test status
Simulation time 15887058270 ps
CPU time 133.14 seconds
Started Jul 13 06:08:55 PM PDT 24
Finished Jul 13 06:12:26 PM PDT 24
Peak memory 200320 kb
Host smart-e8426c58-0f48-4bb9-85ff-fc79996bb6ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725526428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3725526428
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.746044868
Short name T501
Test name
Test status
Simulation time 9790513064 ps
CPU time 137.96 seconds
Started Jul 13 06:08:56 PM PDT 24
Finished Jul 13 06:12:31 PM PDT 24
Peak memory 216668 kb
Host smart-b7a9dea7-00bc-42eb-b9b9-5b8fd159e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746044868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.746044868
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.868746533
Short name T213
Test name
Test status
Simulation time 6715646131 ps
CPU time 7.01 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:10:18 PM PDT 24
Peak memory 200360 kb
Host smart-34f866f9-c286-49aa-9ad5-48c35ed22fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868746533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.868746533
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3795177149
Short name T85
Test name
Test status
Simulation time 305645291040 ps
CPU time 2084.47 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:44:56 PM PDT 24
Peak memory 725676 kb
Host smart-5393c81f-1d49-44f7-9cad-d5fcb097aa6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795177149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3795177149
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4237125278
Short name T480
Test name
Test status
Simulation time 1842619195 ps
CPU time 34.41 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:10:45 PM PDT 24
Peak memory 200308 kb
Host smart-6861046e-0c1d-4ec4-9308-ba0fbad960df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237125278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4237125278
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4261077224
Short name T365
Test name
Test status
Simulation time 14895384 ps
CPU time 0.62 seconds
Started Jul 13 06:08:59 PM PDT 24
Finished Jul 13 06:10:14 PM PDT 24
Peak memory 196112 kb
Host smart-164c3a6c-b6b3-410a-8c8a-0f994d7f857d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261077224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4261077224
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2709747803
Short name T24
Test name
Test status
Simulation time 1237893077 ps
CPU time 25.06 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:10:36 PM PDT 24
Peak memory 200200 kb
Host smart-1c04e986-9324-4772-b12c-944a3a0307f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709747803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2709747803
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3050309094
Short name T241
Test name
Test status
Simulation time 1338113868 ps
CPU time 11 seconds
Started Jul 13 06:08:55 PM PDT 24
Finished Jul 13 06:10:24 PM PDT 24
Peak memory 200220 kb
Host smart-0dbb657c-9bed-4d1f-8888-0440b9a0a6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050309094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3050309094
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1689317220
Short name T438
Test name
Test status
Simulation time 8301186713 ps
CPU time 801.56 seconds
Started Jul 13 06:08:54 PM PDT 24
Finished Jul 13 06:23:33 PM PDT 24
Peak memory 696780 kb
Host smart-4cad09e3-3b90-464c-8411-414b2bae0e7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689317220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1689317220
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1843914438
Short name T336
Test name
Test status
Simulation time 5653174914 ps
CPU time 98.43 seconds
Started Jul 13 06:08:56 PM PDT 24
Finished Jul 13 06:11:51 PM PDT 24
Peak memory 200336 kb
Host smart-f483bc89-1c87-42ca-af39-80987e5045c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843914438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1843914438
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3267044705
Short name T139
Test name
Test status
Simulation time 8478088933 ps
CPU time 160.42 seconds
Started Jul 13 06:08:53 PM PDT 24
Finished Jul 13 06:12:52 PM PDT 24
Peak memory 200496 kb
Host smart-8e3599c5-0b68-46c1-a53f-f74cfba8c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267044705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3267044705
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.702465484
Short name T154
Test name
Test status
Simulation time 710737956 ps
CPU time 8.68 seconds
Started Jul 13 06:08:55 PM PDT 24
Finished Jul 13 06:10:21 PM PDT 24
Peak memory 200296 kb
Host smart-f1d3a9a9-4f6f-435b-a0e3-01f4ce1a511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702465484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.702465484
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2588526977
Short name T84
Test name
Test status
Simulation time 13874414695 ps
CPU time 211.85 seconds
Started Jul 13 06:08:56 PM PDT 24
Finished Jul 13 06:13:45 PM PDT 24
Peak memory 237384 kb
Host smart-f9499420-3fa5-43de-a1a9-7ba57ad8f547
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588526977 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2588526977
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2823192059
Short name T487
Test name
Test status
Simulation time 3598882659 ps
CPU time 63.87 seconds
Started Jul 13 06:08:52 PM PDT 24
Finished Jul 13 06:11:10 PM PDT 24
Peak memory 200300 kb
Host smart-94cb8054-6982-465f-a125-dd30504659be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823192059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2823192059
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4051327623
Short name T182
Test name
Test status
Simulation time 41581126 ps
CPU time 0.58 seconds
Started Jul 13 06:09:04 PM PDT 24
Finished Jul 13 06:10:19 PM PDT 24
Peak memory 196180 kb
Host smart-db0136f1-e645-4de0-a0f7-a7b7cb362d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051327623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4051327623
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3591695052
Short name T16
Test name
Test status
Simulation time 617710466 ps
CPU time 36 seconds
Started Jul 13 06:08:59 PM PDT 24
Finished Jul 13 06:10:54 PM PDT 24
Peak memory 200260 kb
Host smart-e93dcbd3-6da7-4bc7-9a54-b7a8a49a38ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591695052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3591695052
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1932344772
Short name T441
Test name
Test status
Simulation time 21688717514 ps
CPU time 72.36 seconds
Started Jul 13 06:09:05 PM PDT 24
Finished Jul 13 06:11:31 PM PDT 24
Peak memory 216732 kb
Host smart-84314fca-8042-4c21-932e-ce79adb06d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932344772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1932344772
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1449209585
Short name T9
Test name
Test status
Simulation time 5676835370 ps
CPU time 443.86 seconds
Started Jul 13 06:08:59 PM PDT 24
Finished Jul 13 06:17:42 PM PDT 24
Peak memory 672620 kb
Host smart-15f2edfe-c68b-4454-bbd9-af644408df24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449209585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1449209585
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4119463898
Short name T392
Test name
Test status
Simulation time 5062142483 ps
CPU time 162.97 seconds
Started Jul 13 06:09:02 PM PDT 24
Finished Jul 13 06:13:01 PM PDT 24
Peak memory 200272 kb
Host smart-fcd08798-119d-48d8-ba54-70265b9cf42c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119463898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4119463898
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1106980023
Short name T268
Test name
Test status
Simulation time 1110423655 ps
CPU time 4.06 seconds
Started Jul 13 06:08:56 PM PDT 24
Finished Jul 13 06:10:17 PM PDT 24
Peak memory 200308 kb
Host smart-ab2d95f8-569e-4472-a63c-aac6311e5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106980023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1106980023
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3166931029
Short name T88
Test name
Test status
Simulation time 231963045 ps
CPU time 11.44 seconds
Started Jul 13 06:08:55 PM PDT 24
Finished Jul 13 06:10:24 PM PDT 24
Peak memory 200244 kb
Host smart-7f373965-43d6-4831-ae55-f8e219e1277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166931029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3166931029
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2412058935
Short name T322
Test name
Test status
Simulation time 64119408923 ps
CPU time 417.42 seconds
Started Jul 13 06:09:03 PM PDT 24
Finished Jul 13 06:17:16 PM PDT 24
Peak memory 208488 kb
Host smart-c66fd717-30b4-4c4d-a87a-cae5a0f83789
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412058935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2412058935
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4109421753
Short name T495
Test name
Test status
Simulation time 2484252771 ps
CPU time 28.09 seconds
Started Jul 13 06:09:03 PM PDT 24
Finished Jul 13 06:10:47 PM PDT 24
Peak memory 200420 kb
Host smart-b9e05665-1966-4b82-8d9e-fcda138a83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109421753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4109421753
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1563017400
Short name T207
Test name
Test status
Simulation time 76224688 ps
CPU time 0.57 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:10:26 PM PDT 24
Peak memory 196212 kb
Host smart-b28b6f83-993f-4bbc-b5c5-caa2f639bdf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563017400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1563017400
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.244669796
Short name T325
Test name
Test status
Simulation time 1200781772 ps
CPU time 71.59 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:11:36 PM PDT 24
Peak memory 200348 kb
Host smart-2b34cf97-5425-4d87-9577-c6623bcba775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244669796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.244669796
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1017763043
Short name T278
Test name
Test status
Simulation time 4640021106 ps
CPU time 49.77 seconds
Started Jul 13 06:09:05 PM PDT 24
Finished Jul 13 06:11:09 PM PDT 24
Peak memory 200360 kb
Host smart-6d21eb1b-761d-4fa0-abf0-dc904542cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017763043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1017763043
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1219997403
Short name T417
Test name
Test status
Simulation time 3290708510 ps
CPU time 458.92 seconds
Started Jul 13 06:09:09 PM PDT 24
Finished Jul 13 06:18:05 PM PDT 24
Peak memory 647652 kb
Host smart-1770481b-a010-4593-b426-4686359bbdf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219997403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1219997403
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.550533696
Short name T498
Test name
Test status
Simulation time 5835465638 ps
CPU time 20.6 seconds
Started Jul 13 06:09:05 PM PDT 24
Finished Jul 13 06:10:40 PM PDT 24
Peak memory 200360 kb
Host smart-33e00449-5e03-4faf-8747-5f930673fa11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550533696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.550533696
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.882909994
Short name T292
Test name
Test status
Simulation time 829643564 ps
CPU time 48.75 seconds
Started Jul 13 06:09:03 PM PDT 24
Finished Jul 13 06:11:07 PM PDT 24
Peak memory 200304 kb
Host smart-1b171b6d-841d-4954-8863-1f8cf1f7ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882909994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.882909994
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.680746291
Short name T73
Test name
Test status
Simulation time 444431109 ps
CPU time 4.31 seconds
Started Jul 13 06:09:02 PM PDT 24
Finished Jul 13 06:10:23 PM PDT 24
Peak memory 200296 kb
Host smart-c7471478-143b-4e30-9ac7-65a2236a1721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680746291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.680746291
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1439244409
Short name T99
Test name
Test status
Simulation time 20677914043 ps
CPU time 2332.74 seconds
Started Jul 13 06:09:04 PM PDT 24
Finished Jul 13 06:49:12 PM PDT 24
Peak memory 739520 kb
Host smart-493767da-2778-4b85-b013-041245cfe862
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439244409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1439244409
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1229428672
Short name T514
Test name
Test status
Simulation time 7692943338 ps
CPU time 47.85 seconds
Started Jul 13 06:09:04 PM PDT 24
Finished Jul 13 06:11:07 PM PDT 24
Peak memory 200304 kb
Host smart-85cb9372-0e4e-4e49-ba09-c1e72eec6eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229428672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1229428672
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1892068361
Short name T2
Test name
Test status
Simulation time 40816331 ps
CPU time 0.55 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:08:32 PM PDT 24
Peak memory 195872 kb
Host smart-3ce0860a-b4b8-4160-bc7d-8a96d12253c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892068361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1892068361
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2895701272
Short name T414
Test name
Test status
Simulation time 1492063607 ps
CPU time 43.51 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:09:15 PM PDT 24
Peak memory 200280 kb
Host smart-885698a8-328f-4a1a-8003-3f83ecbd05df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895701272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2895701272
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2168664982
Short name T326
Test name
Test status
Simulation time 4260194216 ps
CPU time 60.19 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:09:31 PM PDT 24
Peak memory 200324 kb
Host smart-86a09773-4541-44df-8b2c-c5b91ac46a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168664982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2168664982
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3296898954
Short name T170
Test name
Test status
Simulation time 3415378616 ps
CPU time 222.69 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:12:13 PM PDT 24
Peak memory 598124 kb
Host smart-f39d5a5c-4518-4ad2-88f1-b611685c5c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296898954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3296898954
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.261216239
Short name T418
Test name
Test status
Simulation time 15309971850 ps
CPU time 131.91 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:10:41 PM PDT 24
Peak memory 200284 kb
Host smart-2ff6a873-2c70-4353-8aa9-9717fbb128e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261216239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.261216239
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3905087081
Short name T355
Test name
Test status
Simulation time 1049824849 ps
CPU time 5.51 seconds
Started Jul 13 06:07:16 PM PDT 24
Finished Jul 13 06:08:31 PM PDT 24
Peak memory 200308 kb
Host smart-6df9677a-c6b8-410f-bf6b-cd40289015b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905087081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3905087081
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.3416204856
Short name T507
Test name
Test status
Simulation time 98601502 ps
CPU time 4.77 seconds
Started Jul 13 06:07:17 PM PDT 24
Finished Jul 13 06:08:34 PM PDT 24
Peak memory 200240 kb
Host smart-5fdaf757-61b7-4a14-86f1-cca325c7e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416204856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3416204856
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2183588565
Short name T493
Test name
Test status
Simulation time 381887071665 ps
CPU time 2711.07 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:53:42 PM PDT 24
Peak memory 781544 kb
Host smart-145c8feb-5718-4441-b935-f477184be26b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183588565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2183588565
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1952395945
Short name T71
Test name
Test status
Simulation time 129295847352 ps
CPU time 587.58 seconds
Started Jul 13 06:07:22 PM PDT 24
Finished Jul 13 06:18:22 PM PDT 24
Peak memory 472968 kb
Host smart-bf32a9e0-3a4d-4f6b-8874-8e1092c8858e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952395945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1952395945
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2196166593
Short name T93
Test name
Test status
Simulation time 23638762653 ps
CPU time 43.98 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:09:16 PM PDT 24
Peak memory 200392 kb
Host smart-83642d1f-87ae-4526-9a9a-b262dd0e8c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2196166593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2196166593
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1403011952
Short name T511
Test name
Test status
Simulation time 8327195356 ps
CPU time 64.17 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:09:36 PM PDT 24
Peak memory 200244 kb
Host smart-1e0c711e-9912-42fc-9d0a-c0d87e94c9c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1403011952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1403011952
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1511077914
Short name T371
Test name
Test status
Simulation time 9424554254 ps
CPU time 86.09 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:09:58 PM PDT 24
Peak memory 200444 kb
Host smart-a50f3268-4a24-4312-87ab-7398d1f6a81d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1511077914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1511077914
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2488800213
Short name T209
Test name
Test status
Simulation time 21593768258 ps
CPU time 556.97 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:17:49 PM PDT 24
Peak memory 200340 kb
Host smart-62ccba17-2608-48a2-af8e-84e7907865bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2488800213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2488800213
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2562599021
Short name T205
Test name
Test status
Simulation time 694920834252 ps
CPU time 2077.44 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:43:09 PM PDT 24
Peak memory 216412 kb
Host smart-478af4b0-73fe-4a55-8c78-8ebb02ee4b2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2562599021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2562599021
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2196069121
Short name T230
Test name
Test status
Simulation time 156247062061 ps
CPU time 2273.92 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:46:26 PM PDT 24
Peak memory 208796 kb
Host smart-8a41d577-3b71-45d2-bc16-028ed12583ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2196069121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2196069121
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3826212147
Short name T197
Test name
Test status
Simulation time 10267883304 ps
CPU time 138.66 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:10:49 PM PDT 24
Peak memory 200380 kb
Host smart-6761a99a-7acb-43f7-a0b3-c76794b10d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826212147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3826212147
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3676560844
Short name T48
Test name
Test status
Simulation time 40477516 ps
CPU time 0.56 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:10:26 PM PDT 24
Peak memory 195188 kb
Host smart-4f61332b-82bc-4421-9cb7-c1c87d1bcf8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676560844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3676560844
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.22864660
Short name T284
Test name
Test status
Simulation time 9740867505 ps
CPU time 116.09 seconds
Started Jul 13 06:09:09 PM PDT 24
Finished Jul 13 06:12:22 PM PDT 24
Peak memory 200376 kb
Host smart-56393def-856b-4ba4-b423-b45878b2f330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22864660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.22864660
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1616195475
Short name T421
Test name
Test status
Simulation time 8048606594 ps
CPU time 54.55 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:11:19 PM PDT 24
Peak memory 200412 kb
Host smart-539db089-5608-4be6-945d-32aabd965234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616195475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1616195475
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2805619896
Short name T465
Test name
Test status
Simulation time 20078132970 ps
CPU time 1095.64 seconds
Started Jul 13 06:09:04 PM PDT 24
Finished Jul 13 06:28:34 PM PDT 24
Peak memory 735700 kb
Host smart-2887d0c0-264d-4815-9fc5-a474b2f6e4fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805619896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2805619896
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1437981476
Short name T94
Test name
Test status
Simulation time 56144431421 ps
CPU time 246.32 seconds
Started Jul 13 06:09:04 PM PDT 24
Finished Jul 13 06:14:25 PM PDT 24
Peak memory 200288 kb
Host smart-a9e6226b-f039-4961-8076-4df39cc3c94b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437981476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1437981476
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1786665627
Short name T300
Test name
Test status
Simulation time 762082027 ps
CPU time 42.05 seconds
Started Jul 13 06:09:05 PM PDT 24
Finished Jul 13 06:11:01 PM PDT 24
Peak memory 200292 kb
Host smart-2d2bf8f9-3fea-4261-8870-d07f05ecf072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786665627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1786665627
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2161086035
Short name T79
Test name
Test status
Simulation time 1312758631 ps
CPU time 14.89 seconds
Started Jul 13 06:09:10 PM PDT 24
Finished Jul 13 06:10:41 PM PDT 24
Peak memory 200260 kb
Host smart-c44fd1a6-d93e-4b53-bf88-78d22f56cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161086035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2161086035
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2604426178
Short name T393
Test name
Test status
Simulation time 6067251304 ps
CPU time 322.92 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:15:48 PM PDT 24
Peak memory 200352 kb
Host smart-750d4ffa-90cb-4d35-819a-5856ea002f5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604426178 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2604426178
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2516853288
Short name T91
Test name
Test status
Simulation time 44397371745 ps
CPU time 121.47 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:12:26 PM PDT 24
Peak memory 200380 kb
Host smart-032cebc5-22bd-4e3a-8998-12589a7dc023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516853288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2516853288
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4086005841
Short name T428
Test name
Test status
Simulation time 13052727 ps
CPU time 0.61 seconds
Started Jul 13 06:09:06 PM PDT 24
Finished Jul 13 06:10:20 PM PDT 24
Peak memory 195184 kb
Host smart-48c9e0e3-4f1e-4e9c-a345-9effd70751e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086005841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4086005841
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1989883794
Short name T321
Test name
Test status
Simulation time 8152665391 ps
CPU time 89.88 seconds
Started Jul 13 06:09:04 PM PDT 24
Finished Jul 13 06:11:49 PM PDT 24
Peak memory 208812 kb
Host smart-3cd3cfca-7944-4ab5-a66e-c013a6a66e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989883794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1989883794
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1007870923
Short name T335
Test name
Test status
Simulation time 564503714 ps
CPU time 30.73 seconds
Started Jul 13 06:09:06 PM PDT 24
Finished Jul 13 06:10:55 PM PDT 24
Peak memory 200224 kb
Host smart-94e2ae33-3149-4a2c-963f-0d5fe2805569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007870923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1007870923
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1271242813
Short name T204
Test name
Test status
Simulation time 15838691884 ps
CPU time 681.88 seconds
Started Jul 13 06:09:05 PM PDT 24
Finished Jul 13 06:21:41 PM PDT 24
Peak memory 655952 kb
Host smart-a15178f8-6aa1-4608-a5c7-a74c675e37e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271242813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1271242813
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1429840176
Short name T490
Test name
Test status
Simulation time 18246690327 ps
CPU time 131.75 seconds
Started Jul 13 06:09:10 PM PDT 24
Finished Jul 13 06:12:38 PM PDT 24
Peak memory 200340 kb
Host smart-8d418607-ed2b-4fa7-a074-af5608e90154
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429840176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1429840176
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.744837382
Short name T460
Test name
Test status
Simulation time 1843127382 ps
CPU time 103.95 seconds
Started Jul 13 06:09:06 PM PDT 24
Finished Jul 13 06:12:09 PM PDT 24
Peak memory 200232 kb
Host smart-a38ad882-f6a3-44d8-9729-095078b32ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744837382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.744837382
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1693060651
Short name T384
Test name
Test status
Simulation time 5097240596 ps
CPU time 14.26 seconds
Started Jul 13 06:09:10 PM PDT 24
Finished Jul 13 06:10:40 PM PDT 24
Peak memory 200356 kb
Host smart-2ed7481e-1bf4-4ff3-888a-3f616ff6381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693060651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1693060651
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3564722030
Short name T25
Test name
Test status
Simulation time 13918888466 ps
CPU time 2049.48 seconds
Started Jul 13 06:09:06 PM PDT 24
Finished Jul 13 06:44:34 PM PDT 24
Peak memory 778360 kb
Host smart-9152d83c-bb3e-4a65-adda-148ee51e579b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564722030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3564722030
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1586536071
Short name T124
Test name
Test status
Simulation time 49043467737 ps
CPU time 81.86 seconds
Started Jul 13 06:09:14 PM PDT 24
Finished Jul 13 06:11:52 PM PDT 24
Peak memory 200236 kb
Host smart-a58548db-3bf7-43cb-a490-474c09f727d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586536071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1586536071
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2866244257
Short name T397
Test name
Test status
Simulation time 13528816 ps
CPU time 0.62 seconds
Started Jul 13 06:09:11 PM PDT 24
Finished Jul 13 06:10:27 PM PDT 24
Peak memory 196888 kb
Host smart-8e75ff0b-da78-44b3-be4b-e701580ae435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866244257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2866244257
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4113225169
Short name T214
Test name
Test status
Simulation time 1542868624 ps
CPU time 91.83 seconds
Started Jul 13 06:09:14 PM PDT 24
Finished Jul 13 06:12:02 PM PDT 24
Peak memory 200188 kb
Host smart-518f628d-76ed-4e31-b93a-073067684f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113225169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4113225169
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.190668513
Short name T286
Test name
Test status
Simulation time 5083575280 ps
CPU time 10.05 seconds
Started Jul 13 06:09:06 PM PDT 24
Finished Jul 13 06:10:29 PM PDT 24
Peak memory 200336 kb
Host smart-806e8c1c-78ff-41f0-814e-6e820a7c8894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190668513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.190668513
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2614374681
Short name T527
Test name
Test status
Simulation time 4219100567 ps
CPU time 776.84 seconds
Started Jul 13 06:09:07 PM PDT 24
Finished Jul 13 06:23:21 PM PDT 24
Peak memory 732504 kb
Host smart-6171f758-793b-45ac-96a7-07018c20cf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614374681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2614374681
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.588892468
Short name T165
Test name
Test status
Simulation time 18620382629 ps
CPU time 159.13 seconds
Started Jul 13 06:09:14 PM PDT 24
Finished Jul 13 06:13:09 PM PDT 24
Peak memory 200360 kb
Host smart-2004d9a4-61d8-4dd8-bc9a-f61f440db139
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588892468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.588892468
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1267174647
Short name T280
Test name
Test status
Simulation time 2014470739 ps
CPU time 35.86 seconds
Started Jul 13 06:09:05 PM PDT 24
Finished Jul 13 06:10:55 PM PDT 24
Peak memory 200196 kb
Host smart-721f3c50-eba5-4436-937d-b5d8c69d7230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267174647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1267174647
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2626097704
Short name T379
Test name
Test status
Simulation time 143192712 ps
CPU time 2.96 seconds
Started Jul 13 06:09:14 PM PDT 24
Finished Jul 13 06:10:33 PM PDT 24
Peak memory 200364 kb
Host smart-b53b8073-8641-4b69-b967-20eb3ced347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626097704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2626097704
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3050570158
Short name T488
Test name
Test status
Simulation time 4870390615 ps
CPU time 33.9 seconds
Started Jul 13 06:09:14 PM PDT 24
Finished Jul 13 06:11:04 PM PDT 24
Peak memory 200380 kb
Host smart-8d6f5b96-aeb2-4b92-983b-e40adb4f9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050570158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3050570158
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2873874434
Short name T218
Test name
Test status
Simulation time 12908534 ps
CPU time 0.62 seconds
Started Jul 13 06:09:11 PM PDT 24
Finished Jul 13 06:10:27 PM PDT 24
Peak memory 196212 kb
Host smart-ea407fd1-4fe8-4399-9965-d06bba08267f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873874434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2873874434
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1213675099
Short name T437
Test name
Test status
Simulation time 3887813982 ps
CPU time 59.62 seconds
Started Jul 13 06:09:10 PM PDT 24
Finished Jul 13 06:11:25 PM PDT 24
Peak memory 200320 kb
Host smart-266841ab-2286-4005-aaaf-b7c93b4263cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213675099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1213675099
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1434767436
Short name T258
Test name
Test status
Simulation time 4618900004 ps
CPU time 45.51 seconds
Started Jul 13 06:09:08 PM PDT 24
Finished Jul 13 06:11:11 PM PDT 24
Peak memory 200288 kb
Host smart-ee5027a9-e12a-4f3e-b1fc-139989ecb608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434767436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1434767436
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3104197927
Short name T152
Test name
Test status
Simulation time 1654604283 ps
CPU time 231.89 seconds
Started Jul 13 06:09:10 PM PDT 24
Finished Jul 13 06:14:18 PM PDT 24
Peak memory 620836 kb
Host smart-25c6ec7f-b480-4d57-b079-e8ea04d50b86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104197927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3104197927
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1481754752
Short name T362
Test name
Test status
Simulation time 1532152390 ps
CPU time 81.26 seconds
Started Jul 13 06:09:09 PM PDT 24
Finished Jul 13 06:11:47 PM PDT 24
Peak memory 200280 kb
Host smart-28c8f454-6d7d-4173-8945-6c1e264f6ff1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481754752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1481754752
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1392979826
Short name T259
Test name
Test status
Simulation time 3515194838 ps
CPU time 46.04 seconds
Started Jul 13 06:09:10 PM PDT 24
Finished Jul 13 06:11:12 PM PDT 24
Peak memory 200376 kb
Host smart-a9721870-fa7e-4f33-9fd7-ad157f4c9d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392979826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1392979826
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2878962569
Short name T181
Test name
Test status
Simulation time 451851551 ps
CPU time 3.86 seconds
Started Jul 13 06:09:09 PM PDT 24
Finished Jul 13 06:10:29 PM PDT 24
Peak memory 200280 kb
Host smart-5e34d965-093c-456a-a340-1dabae4bb820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878962569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2878962569
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2415869782
Short name T235
Test name
Test status
Simulation time 23442876774 ps
CPU time 3404.67 seconds
Started Jul 13 06:09:09 PM PDT 24
Finished Jul 13 07:07:11 PM PDT 24
Peak memory 798572 kb
Host smart-2ec0b56c-da91-4d0d-b809-cdab5b868b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415869782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2415869782
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1953988657
Short name T231
Test name
Test status
Simulation time 3900243005 ps
CPU time 72.33 seconds
Started Jul 13 06:09:12 PM PDT 24
Finished Jul 13 06:11:38 PM PDT 24
Peak memory 200284 kb
Host smart-ec31d0c3-5513-45b0-aacd-c6e252f35d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953988657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1953988657
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3493546834
Short name T281
Test name
Test status
Simulation time 40928584 ps
CPU time 0.59 seconds
Started Jul 13 06:09:19 PM PDT 24
Finished Jul 13 06:10:36 PM PDT 24
Peak memory 196140 kb
Host smart-e4e04417-93f2-4525-8e30-28cde2689fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493546834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3493546834
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2309770772
Short name T245
Test name
Test status
Simulation time 1108676257 ps
CPU time 62.02 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:11:38 PM PDT 24
Peak memory 200292 kb
Host smart-4206bdbe-ed27-41ef-8238-fc528b246b9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309770772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2309770772
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3138241254
Short name T153
Test name
Test status
Simulation time 5049962287 ps
CPU time 13 seconds
Started Jul 13 06:09:18 PM PDT 24
Finished Jul 13 06:10:49 PM PDT 24
Peak memory 200368 kb
Host smart-d4f66012-1535-4446-ab70-e3b51adb39de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138241254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3138241254
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3231718891
Short name T342
Test name
Test status
Simulation time 16253241559 ps
CPU time 751.44 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:23:08 PM PDT 24
Peak memory 702696 kb
Host smart-2584e510-15d3-493b-b3c0-f0d6497aafa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231718891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3231718891
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.608921205
Short name T329
Test name
Test status
Simulation time 2242323704 ps
CPU time 121.34 seconds
Started Jul 13 06:09:22 PM PDT 24
Finished Jul 13 06:12:39 PM PDT 24
Peak memory 200348 kb
Host smart-07a2a4e9-fc2b-4b37-a61d-cbd5c5467c98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608921205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.608921205
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.221220348
Short name T502
Test name
Test status
Simulation time 7215530021 ps
CPU time 128.18 seconds
Started Jul 13 06:09:19 PM PDT 24
Finished Jul 13 06:12:44 PM PDT 24
Peak memory 200364 kb
Host smart-11162539-710c-43fb-9fa9-15f61155ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221220348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.221220348
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.703541867
Short name T21
Test name
Test status
Simulation time 1750589514 ps
CPU time 10.75 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:10:47 PM PDT 24
Peak memory 200296 kb
Host smart-89591816-49c2-40e7-9d1c-b0a582837c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703541867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.703541867
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3413924034
Short name T189
Test name
Test status
Simulation time 61772501173 ps
CPU time 997.17 seconds
Started Jul 13 06:09:19 PM PDT 24
Finished Jul 13 06:27:13 PM PDT 24
Peak memory 637584 kb
Host smart-2088ac55-4c13-4a79-b4dc-fba963243d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413924034 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3413924034
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.455303622
Short name T449
Test name
Test status
Simulation time 9812957340 ps
CPU time 130.97 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:12:47 PM PDT 24
Peak memory 200352 kb
Host smart-ffe27423-5d71-4b78-826e-ca6fbc047cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455303622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.455303622
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3860633674
Short name T180
Test name
Test status
Simulation time 85662223 ps
CPU time 0.57 seconds
Started Jul 13 06:09:26 PM PDT 24
Finished Jul 13 06:10:42 PM PDT 24
Peak memory 195816 kb
Host smart-33df4410-e43e-432a-9831-4468aefacc5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860633674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3860633674
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2501603587
Short name T5
Test name
Test status
Simulation time 3916903660 ps
CPU time 108.11 seconds
Started Jul 13 06:09:21 PM PDT 24
Finished Jul 13 06:12:25 PM PDT 24
Peak memory 200360 kb
Host smart-c55e12db-cc73-4553-866d-d1bcf9e2cd5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501603587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2501603587
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.519897196
Short name T41
Test name
Test status
Simulation time 148994921 ps
CPU time 7.3 seconds
Started Jul 13 06:09:22 PM PDT 24
Finished Jul 13 06:10:44 PM PDT 24
Peak memory 200556 kb
Host smart-a950bf95-c3d9-4ee3-b0d0-04e480a77c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519897196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.519897196
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3449801137
Short name T193
Test name
Test status
Simulation time 20567842475 ps
CPU time 947.7 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:26:24 PM PDT 24
Peak memory 730636 kb
Host smart-ac774462-58a9-46d9-a42e-0114bd669e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449801137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3449801137
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1238767826
Short name T361
Test name
Test status
Simulation time 1867402240 ps
CPU time 100.19 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:12:17 PM PDT 24
Peak memory 200360 kb
Host smart-a5f7445b-be0e-49b3-8a89-14b8a83f7e4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238767826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1238767826
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.587246679
Short name T57
Test name
Test status
Simulation time 33965194801 ps
CPU time 209.4 seconds
Started Jul 13 06:09:22 PM PDT 24
Finished Jul 13 06:14:07 PM PDT 24
Peak memory 200436 kb
Host smart-14360d6f-2b15-4bf6-81ee-d43162fbc3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587246679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.587246679
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2493777874
Short name T513
Test name
Test status
Simulation time 217328803 ps
CPU time 9.6 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:10:46 PM PDT 24
Peak memory 200320 kb
Host smart-55e61316-aeaa-4a44-80d9-c5bafff48298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493777874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2493777874
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2282717162
Short name T219
Test name
Test status
Simulation time 1039563166 ps
CPU time 20.9 seconds
Started Jul 13 06:09:20 PM PDT 24
Finished Jul 13 06:10:57 PM PDT 24
Peak memory 200220 kb
Host smart-5ded0d9c-0c67-4d5a-bb44-9fddb95c0507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282717162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2282717162
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1933846136
Short name T148
Test name
Test status
Simulation time 46548069 ps
CPU time 0.57 seconds
Started Jul 13 06:09:29 PM PDT 24
Finished Jul 13 06:10:43 PM PDT 24
Peak memory 196216 kb
Host smart-3f45aa32-80ef-4ecc-9141-0b850adadbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933846136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1933846136
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1783522071
Short name T472
Test name
Test status
Simulation time 5783193436 ps
CPU time 85.3 seconds
Started Jul 13 06:09:28 PM PDT 24
Finished Jul 13 06:12:07 PM PDT 24
Peak memory 200304 kb
Host smart-aa15f23d-2d18-49cf-8964-2e220910659a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783522071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1783522071
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1761850413
Short name T77
Test name
Test status
Simulation time 5218503339 ps
CPU time 46.55 seconds
Started Jul 13 06:09:28 PM PDT 24
Finished Jul 13 06:11:28 PM PDT 24
Peak memory 200380 kb
Host smart-e9075e83-a60a-4cae-94d5-296df9e716b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761850413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1761850413
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3778799684
Short name T425
Test name
Test status
Simulation time 743098200 ps
CPU time 114.83 seconds
Started Jul 13 06:09:27 PM PDT 24
Finished Jul 13 06:12:36 PM PDT 24
Peak memory 579776 kb
Host smart-850784eb-e210-4997-9dc8-474650dc5977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778799684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3778799684
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3863117747
Short name T144
Test name
Test status
Simulation time 8220716973 ps
CPU time 105.67 seconds
Started Jul 13 06:09:28 PM PDT 24
Finished Jul 13 06:12:27 PM PDT 24
Peak memory 200280 kb
Host smart-1c2433f2-1482-4b0e-aac2-24f8be5abd5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863117747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3863117747
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.902001371
Short name T508
Test name
Test status
Simulation time 3544265189 ps
CPU time 52.84 seconds
Started Jul 13 06:09:27 PM PDT 24
Finished Jul 13 06:11:34 PM PDT 24
Peak memory 200404 kb
Host smart-7f083336-74e9-4972-bf5d-b80caf7315f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902001371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.902001371
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.840301579
Short name T42
Test name
Test status
Simulation time 93868938 ps
CPU time 2.03 seconds
Started Jul 13 06:09:27 PM PDT 24
Finished Jul 13 06:10:44 PM PDT 24
Peak memory 200232 kb
Host smart-1d49df76-8b23-47eb-8994-97e872a90856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840301579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.840301579
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1601224358
Short name T477
Test name
Test status
Simulation time 81370070330 ps
CPU time 708.51 seconds
Started Jul 13 06:09:27 PM PDT 24
Finished Jul 13 06:22:30 PM PDT 24
Peak memory 216792 kb
Host smart-383fdc5c-e491-4bb1-a083-ab2db1a36a00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601224358 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1601224358
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1868083543
Short name T512
Test name
Test status
Simulation time 12792719295 ps
CPU time 59.63 seconds
Started Jul 13 06:09:25 PM PDT 24
Finished Jul 13 06:11:41 PM PDT 24
Peak memory 200256 kb
Host smart-8afc1c29-2149-4e19-a780-8a0fdd76a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868083543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1868083543
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.259213126
Short name T346
Test name
Test status
Simulation time 34175365 ps
CPU time 0.57 seconds
Started Jul 13 06:09:36 PM PDT 24
Finished Jul 13 06:10:54 PM PDT 24
Peak memory 195960 kb
Host smart-c74ceaff-39d1-466b-bef8-7b2504f9c47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259213126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.259213126
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1498789551
Short name T309
Test name
Test status
Simulation time 2863021556 ps
CPU time 39.53 seconds
Started Jul 13 06:09:34 PM PDT 24
Finished Jul 13 06:11:30 PM PDT 24
Peak memory 200360 kb
Host smart-7c4329e0-a408-40f0-acb0-6717e51db3da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498789551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1498789551
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3272639963
Short name T434
Test name
Test status
Simulation time 1759113229 ps
CPU time 43.37 seconds
Started Jul 13 06:09:35 PM PDT 24
Finished Jul 13 06:11:34 PM PDT 24
Peak memory 200312 kb
Host smart-5972610c-fa1b-42a8-9ad7-25b0e4115c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272639963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3272639963
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2882100908
Short name T228
Test name
Test status
Simulation time 4018899132 ps
CPU time 774.79 seconds
Started Jul 13 06:09:35 PM PDT 24
Finished Jul 13 06:23:48 PM PDT 24
Peak memory 672916 kb
Host smart-cb571444-26d5-4810-9107-aa0fb7abd86f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2882100908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2882100908
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3740326125
Short name T439
Test name
Test status
Simulation time 2916668886 ps
CPU time 162.05 seconds
Started Jul 13 06:09:35 PM PDT 24
Finished Jul 13 06:13:35 PM PDT 24
Peak memory 200380 kb
Host smart-42a230cc-637c-4390-bc0b-234491291e51
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740326125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3740326125
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2995559735
Short name T138
Test name
Test status
Simulation time 2683344173 ps
CPU time 149.51 seconds
Started Jul 13 06:09:34 PM PDT 24
Finished Jul 13 06:13:20 PM PDT 24
Peak memory 200292 kb
Host smart-50790976-3350-41b7-a37e-816a130cb513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995559735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2995559735
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.341640016
Short name T145
Test name
Test status
Simulation time 88851689 ps
CPU time 4.26 seconds
Started Jul 13 06:09:27 PM PDT 24
Finished Jul 13 06:10:46 PM PDT 24
Peak memory 200320 kb
Host smart-e07a5cb4-a571-43d6-b18b-88249e93cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341640016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.341640016
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2054837175
Short name T86
Test name
Test status
Simulation time 86690588655 ps
CPU time 689.06 seconds
Started Jul 13 06:09:35 PM PDT 24
Finished Jul 13 06:22:19 PM PDT 24
Peak memory 488728 kb
Host smart-97c1ea46-02f4-4fb4-8223-051d597671e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054837175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2054837175
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.471724147
Short name T446
Test name
Test status
Simulation time 805446564 ps
CPU time 21.51 seconds
Started Jul 13 06:09:35 PM PDT 24
Finished Jul 13 06:11:12 PM PDT 24
Peak memory 200320 kb
Host smart-2cbb4bb1-d0b7-486d-a786-78373e34d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471724147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.471724147
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3586125980
Short name T257
Test name
Test status
Simulation time 12424003 ps
CPU time 0.58 seconds
Started Jul 13 06:09:44 PM PDT 24
Finished Jul 13 06:11:02 PM PDT 24
Peak memory 196828 kb
Host smart-b4a4e291-37d4-4752-9d23-0e54a0523158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586125980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3586125980
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2186701455
Short name T1
Test name
Test status
Simulation time 1524658716 ps
CPU time 23.35 seconds
Started Jul 13 06:09:44 PM PDT 24
Finished Jul 13 06:11:25 PM PDT 24
Peak memory 200248 kb
Host smart-28333501-075f-40ad-961a-7e191f989c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186701455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2186701455
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.371758343
Short name T343
Test name
Test status
Simulation time 452018441 ps
CPU time 6.14 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:11:08 PM PDT 24
Peak memory 200344 kb
Host smart-93731240-a4d7-4f84-a040-5ef0c8dd5d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371758343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.371758343
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2751425161
Short name T163
Test name
Test status
Simulation time 9043575816 ps
CPU time 605.8 seconds
Started Jul 13 06:09:47 PM PDT 24
Finished Jul 13 06:21:14 PM PDT 24
Peak memory 715044 kb
Host smart-30c40e6c-ff40-4198-9e97-758ecd1d0e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751425161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2751425161
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3190366834
Short name T260
Test name
Test status
Simulation time 2988621903 ps
CPU time 143.35 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:13:26 PM PDT 24
Peak memory 200596 kb
Host smart-04feab23-1418-4a66-8300-e43228a8f063
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190366834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3190366834
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.388760389
Short name T420
Test name
Test status
Simulation time 6835965550 ps
CPU time 118.84 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:13:01 PM PDT 24
Peak memory 200420 kb
Host smart-8fb7821e-4e52-4ca2-8b0e-18d3d0807473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388760389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.388760389
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2917274268
Short name T155
Test name
Test status
Simulation time 642695575 ps
CPU time 13 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:11:15 PM PDT 24
Peak memory 200296 kb
Host smart-14863f73-abea-43c6-b95b-afffbdfc436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917274268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2917274268
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.959122444
Short name T403
Test name
Test status
Simulation time 55241410743 ps
CPU time 958.1 seconds
Started Jul 13 06:09:48 PM PDT 24
Finished Jul 13 06:27:07 PM PDT 24
Peak memory 677104 kb
Host smart-71e07572-5c33-4320-9307-3476ac95b214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959122444 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.959122444
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.568626700
Short name T406
Test name
Test status
Simulation time 3416836391 ps
CPU time 48.36 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:11:51 PM PDT 24
Peak memory 200408 kb
Host smart-485be9f3-4ac3-4a8b-a10e-311a9b260ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568626700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.568626700
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1611257002
Short name T407
Test name
Test status
Simulation time 23562966 ps
CPU time 0.62 seconds
Started Jul 13 06:09:55 PM PDT 24
Finished Jul 13 06:11:16 PM PDT 24
Peak memory 196844 kb
Host smart-a4a44c5f-bab1-4af2-8992-1599cf3d703f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611257002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1611257002
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.161776875
Short name T7
Test name
Test status
Simulation time 2255889629 ps
CPU time 30.85 seconds
Started Jul 13 06:09:57 PM PDT 24
Finished Jul 13 06:11:47 PM PDT 24
Peak memory 200104 kb
Host smart-ff8d5daf-a7b7-4b7b-b9a3-9d44c91adbb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161776875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.161776875
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1187187887
Short name T256
Test name
Test status
Simulation time 48428682358 ps
CPU time 65.25 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:12:21 PM PDT 24
Peak memory 200416 kb
Host smart-48b4cdcf-409c-4292-8d60-b747f1494a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187187887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1187187887
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1054145655
Short name T525
Test name
Test status
Simulation time 4308192262 ps
CPU time 328.53 seconds
Started Jul 13 06:09:57 PM PDT 24
Finished Jul 13 06:16:45 PM PDT 24
Peak memory 642600 kb
Host smart-f13b10e3-a600-43de-88d1-1148202436ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054145655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1054145655
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.37329058
Short name T332
Test name
Test status
Simulation time 15134159677 ps
CPU time 187.02 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:14:23 PM PDT 24
Peak memory 200348 kb
Host smart-b13458bc-47e0-40f1-ba47-b97bc4bfbb0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.37329058
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.51637878
Short name T232
Test name
Test status
Simulation time 8974139250 ps
CPU time 39.44 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:11:42 PM PDT 24
Peak memory 200364 kb
Host smart-116237b1-59c7-45cb-9197-33397f74ac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51637878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.51637878
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1915180259
Short name T373
Test name
Test status
Simulation time 1089834218 ps
CPU time 3.97 seconds
Started Jul 13 06:09:45 PM PDT 24
Finished Jul 13 06:11:06 PM PDT 24
Peak memory 200236 kb
Host smart-f96012fb-eb2c-4928-af5d-5d5afa1ad2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915180259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1915180259
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1887059862
Short name T49
Test name
Test status
Simulation time 192198674428 ps
CPU time 528.67 seconds
Started Jul 13 06:09:55 PM PDT 24
Finished Jul 13 06:20:04 PM PDT 24
Peak memory 200320 kb
Host smart-a6e6badd-8799-4d85-b8a5-6c1f731f088f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887059862 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1887059862
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2249577486
Short name T126
Test name
Test status
Simulation time 60146527828 ps
CPU time 140.71 seconds
Started Jul 13 06:09:55 PM PDT 24
Finished Jul 13 06:13:36 PM PDT 24
Peak memory 200360 kb
Host smart-5c086af2-6d49-4b44-80b7-4d5c55dbbc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249577486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2249577486
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3421564789
Short name T456
Test name
Test status
Simulation time 23837112 ps
CPU time 0.6 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:08:40 PM PDT 24
Peak memory 196080 kb
Host smart-15641726-0985-456a-898c-4e74b3400175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421564789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3421564789
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3980132699
Short name T315
Test name
Test status
Simulation time 696089031 ps
CPU time 20.41 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:08:52 PM PDT 24
Peak memory 200276 kb
Host smart-d1352892-1ffa-49b7-af69-e1039859f143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980132699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3980132699
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1090642225
Short name T160
Test name
Test status
Simulation time 3595085956 ps
CPU time 47.9 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:09:19 PM PDT 24
Peak memory 200408 kb
Host smart-270465c2-da12-4d35-ad36-9ca9af18f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090642225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1090642225
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2581315434
Short name T431
Test name
Test status
Simulation time 23619961378 ps
CPU time 1098.32 seconds
Started Jul 13 06:07:18 PM PDT 24
Finished Jul 13 06:26:48 PM PDT 24
Peak memory 726316 kb
Host smart-ab584ef5-71dd-4ec1-b0f9-9d6398311c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2581315434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2581315434
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1440691830
Short name T331
Test name
Test status
Simulation time 25311337185 ps
CPU time 84.62 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:09:56 PM PDT 24
Peak memory 200304 kb
Host smart-b7577936-8766-4a8f-b661-df549e0b68c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440691830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1440691830
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2919313030
Short name T435
Test name
Test status
Simulation time 11553327682 ps
CPU time 25.63 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:08:57 PM PDT 24
Peak memory 200356 kb
Host smart-7e3e9126-7e35-43fe-b5ef-1507c1ec4013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919313030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2919313030
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4007817732
Short name T52
Test name
Test status
Simulation time 39049004 ps
CPU time 0.85 seconds
Started Jul 13 06:07:40 PM PDT 24
Finished Jul 13 06:08:55 PM PDT 24
Peak memory 218240 kb
Host smart-f1121018-bcd2-4e9b-9c3f-7abec8854c2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007817732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4007817732
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1832541018
Short name T263
Test name
Test status
Simulation time 280261911 ps
CPU time 1.55 seconds
Started Jul 13 06:07:20 PM PDT 24
Finished Jul 13 06:08:33 PM PDT 24
Peak memory 200356 kb
Host smart-7b2437bc-fa28-4a28-a9ff-32045627cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832541018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1832541018
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.193783953
Short name T523
Test name
Test status
Simulation time 8335103568 ps
CPU time 478.18 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:16:37 PM PDT 24
Peak memory 434452 kb
Host smart-c4ff719e-c3d8-4909-8fdc-43701edfe832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193783953 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.193783953
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2557627295
Short name T70
Test name
Test status
Simulation time 192673749449 ps
CPU time 4935.33 seconds
Started Jul 13 06:07:40 PM PDT 24
Finished Jul 13 07:31:10 PM PDT 24
Peak memory 776896 kb
Host smart-c2ea9be6-c39c-4f12-b4e1-42f4ccb471eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557627295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2557627295
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.581276007
Short name T164
Test name
Test status
Simulation time 16956520650 ps
CPU time 75.16 seconds
Started Jul 13 06:07:25 PM PDT 24
Finished Jul 13 06:09:51 PM PDT 24
Peak memory 200292 kb
Host smart-5bbe7c0a-dcc4-4d18-a98c-6119d7aebb57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=581276007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.581276007
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1038805566
Short name T307
Test name
Test status
Simulation time 74683244506 ps
CPU time 57.92 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:09:47 PM PDT 24
Peak memory 200344 kb
Host smart-77b0f5a6-9931-49bd-a0de-25c96eb776a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1038805566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1038805566
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1887349622
Short name T333
Test name
Test status
Simulation time 22150466767 ps
CPU time 85.66 seconds
Started Jul 13 06:07:39 PM PDT 24
Finished Jul 13 06:10:20 PM PDT 24
Peak memory 200192 kb
Host smart-6934d996-4434-4c23-9b2f-08f5be31ccf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1887349622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1887349622
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2998187413
Short name T526
Test name
Test status
Simulation time 42273362603 ps
CPU time 572.23 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:18:04 PM PDT 24
Peak memory 200340 kb
Host smart-32c9d026-cc54-4384-bfed-f7f650290cd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2998187413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2998187413
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2321297932
Short name T387
Test name
Test status
Simulation time 488137147339 ps
CPU time 2284.8 seconds
Started Jul 13 06:07:19 PM PDT 24
Finished Jul 13 06:46:36 PM PDT 24
Peak memory 215688 kb
Host smart-de99aba6-db32-4768-9189-197bfed1ac42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2321297932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2321297932
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.68801109
Short name T167
Test name
Test status
Simulation time 857480810174 ps
CPU time 2393.02 seconds
Started Jul 13 06:07:24 PM PDT 24
Finished Jul 13 06:48:29 PM PDT 24
Peak memory 216816 kb
Host smart-05427746-e183-44ea-9c75-2e5e0557781b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=68801109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.68801109
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3955264985
Short name T386
Test name
Test status
Simulation time 888642222 ps
CPU time 35.33 seconds
Started Jul 13 06:07:21 PM PDT 24
Finished Jul 13 06:09:09 PM PDT 24
Peak memory 200312 kb
Host smart-f1d08994-7989-48b5-93f1-8f94439356c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955264985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3955264985
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1340622477
Short name T275
Test name
Test status
Simulation time 28765921 ps
CPU time 0.61 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:11:16 PM PDT 24
Peak memory 196220 kb
Host smart-68d0079d-d3fb-4bad-be7e-60eccc2846e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340622477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1340622477
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3913508705
Short name T210
Test name
Test status
Simulation time 1873865028 ps
CPU time 109.24 seconds
Started Jul 13 06:09:53 PM PDT 24
Finished Jul 13 06:13:04 PM PDT 24
Peak memory 200336 kb
Host smart-b7ff9490-d0eb-44e7-ab05-dca2e2fff7b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913508705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3913508705
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2531432353
Short name T158
Test name
Test status
Simulation time 868379635 ps
CPU time 14.78 seconds
Started Jul 13 06:09:57 PM PDT 24
Finished Jul 13 06:11:31 PM PDT 24
Peak memory 200280 kb
Host smart-c473db17-a593-4a7f-b23d-182f8081dccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531432353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2531432353
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2772751016
Short name T467
Test name
Test status
Simulation time 22206072967 ps
CPU time 1196.17 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:31:12 PM PDT 24
Peak memory 724400 kb
Host smart-f86a50b1-f53a-4db8-b2b2-89133bc3478a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772751016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2772751016
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2793386179
Short name T150
Test name
Test status
Simulation time 27404624961 ps
CPU time 104.15 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:13:00 PM PDT 24
Peak memory 200336 kb
Host smart-5f87e348-1903-4a0d-aa42-17961ca9895c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793386179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2793386179
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.424511233
Short name T383
Test name
Test status
Simulation time 38542236303 ps
CPU time 127.65 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:13:23 PM PDT 24
Peak memory 200396 kb
Host smart-f2096547-8c24-47c2-86d6-1de78a183521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424511233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.424511233
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.978298111
Short name T531
Test name
Test status
Simulation time 3786255894 ps
CPU time 11.3 seconds
Started Jul 13 06:09:56 PM PDT 24
Finished Jul 13 06:11:28 PM PDT 24
Peak memory 200412 kb
Host smart-560288aa-2929-4538-816b-4e5faebbf294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978298111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.978298111
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2917628228
Short name T528
Test name
Test status
Simulation time 125901936909 ps
CPU time 2658.28 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:55:34 PM PDT 24
Peak memory 783464 kb
Host smart-b54fe52b-59f4-44d2-87f5-a4e1673c60e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917628228 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2917628228
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.204866286
Short name T416
Test name
Test status
Simulation time 173252225716 ps
CPU time 104.29 seconds
Started Jul 13 06:09:53 PM PDT 24
Finished Jul 13 06:12:59 PM PDT 24
Peak memory 200256 kb
Host smart-8f858bcf-59fa-4eab-96ae-63f0e206d118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204866286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.204866286
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.564647254
Short name T295
Test name
Test status
Simulation time 11111699 ps
CPU time 0.56 seconds
Started Jul 13 06:10:01 PM PDT 24
Finished Jul 13 06:11:25 PM PDT 24
Peak memory 195100 kb
Host smart-57dc6b2a-49b8-4da4-ab01-8e6948dab5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564647254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.564647254
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1248477520
Short name T424
Test name
Test status
Simulation time 10297161626 ps
CPU time 60.5 seconds
Started Jul 13 06:10:04 PM PDT 24
Finished Jul 13 06:12:25 PM PDT 24
Peak memory 200356 kb
Host smart-b4060181-d8a8-47e9-bde6-2e7994deb1fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248477520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1248477520
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2246243652
Short name T200
Test name
Test status
Simulation time 4134714869 ps
CPU time 71.94 seconds
Started Jul 13 06:10:01 PM PDT 24
Finished Jul 13 06:12:36 PM PDT 24
Peak memory 200316 kb
Host smart-d42a2ada-45ac-4dc8-b5fb-851a4ce6c9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246243652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2246243652
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1541849842
Short name T442
Test name
Test status
Simulation time 14896107580 ps
CPU time 1456.76 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:35:41 PM PDT 24
Peak memory 739616 kb
Host smart-8121780b-0331-4f2d-bdd5-05efe3efcb65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541849842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1541849842
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1879292648
Short name T277
Test name
Test status
Simulation time 1209991301 ps
CPU time 67.21 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:12:31 PM PDT 24
Peak memory 200276 kb
Host smart-9c5d10e9-201b-4a52-8fa5-079224e56a1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879292648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1879292648
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.858504700
Short name T375
Test name
Test status
Simulation time 13995506939 ps
CPU time 119.29 seconds
Started Jul 13 06:09:55 PM PDT 24
Finished Jul 13 06:13:15 PM PDT 24
Peak memory 216648 kb
Host smart-7669d346-5b1c-45ac-b851-331d9fb43578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858504700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.858504700
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.750233495
Short name T389
Test name
Test status
Simulation time 143568027 ps
CPU time 6.73 seconds
Started Jul 13 06:09:54 PM PDT 24
Finished Jul 13 06:11:22 PM PDT 24
Peak memory 200360 kb
Host smart-cb2cab5b-f641-4983-b0cd-f2f9ad5bc653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750233495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.750233495
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.305417287
Short name T97
Test name
Test status
Simulation time 59774136789 ps
CPU time 1065.14 seconds
Started Jul 13 06:10:00 PM PDT 24
Finished Jul 13 06:29:09 PM PDT 24
Peak memory 502688 kb
Host smart-ba49d608-fefe-427d-bf2b-672721eb96f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305417287 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.305417287
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2688019452
Short name T323
Test name
Test status
Simulation time 78378235270 ps
CPU time 96.89 seconds
Started Jul 13 06:10:04 PM PDT 24
Finished Jul 13 06:13:04 PM PDT 24
Peak memory 200380 kb
Host smart-f1fd2028-bbc6-45a4-9401-1ff33dcd85d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688019452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2688019452
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1921436961
Short name T372
Test name
Test status
Simulation time 45698756 ps
CPU time 0.59 seconds
Started Jul 13 06:10:04 PM PDT 24
Finished Jul 13 06:11:25 PM PDT 24
Peak memory 196124 kb
Host smart-9d759f17-bb1a-4df2-b7e6-d93de498f566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921436961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1921436961
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.4238747306
Short name T285
Test name
Test status
Simulation time 3053780334 ps
CPU time 85.2 seconds
Started Jul 13 06:10:01 PM PDT 24
Finished Jul 13 06:12:49 PM PDT 24
Peak memory 200396 kb
Host smart-5b43c026-e291-46fe-bca2-81137deda476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238747306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.4238747306
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3777737093
Short name T404
Test name
Test status
Simulation time 9844496699 ps
CPU time 55.62 seconds
Started Jul 13 06:10:04 PM PDT 24
Finished Jul 13 06:12:20 PM PDT 24
Peak memory 215896 kb
Host smart-60ecfe81-23eb-454d-bb1d-94427c28236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777737093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3777737093
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3833695382
Short name T499
Test name
Test status
Simulation time 6397991508 ps
CPU time 1151.74 seconds
Started Jul 13 06:10:04 PM PDT 24
Finished Jul 13 06:30:36 PM PDT 24
Peak memory 685960 kb
Host smart-de563b1d-3618-4fda-97cd-6f7551fafa91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833695382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3833695382
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3233832635
Short name T234
Test name
Test status
Simulation time 2790643232 ps
CPU time 158.61 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:14:03 PM PDT 24
Peak memory 200316 kb
Host smart-11faeec4-6e43-43e7-90e2-3a58c0a46759
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233832635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3233832635
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1986092402
Short name T151
Test name
Test status
Simulation time 12170112389 ps
CPU time 13.7 seconds
Started Jul 13 06:10:00 PM PDT 24
Finished Jul 13 06:11:37 PM PDT 24
Peak memory 200356 kb
Host smart-40b3d856-ca34-47db-aab7-e630ed57ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986092402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1986092402
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4038108039
Short name T436
Test name
Test status
Simulation time 537050465 ps
CPU time 8.91 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:11:33 PM PDT 24
Peak memory 200468 kb
Host smart-793b2acf-5794-450a-bd48-af9e8af1fb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038108039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4038108039
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3032179820
Short name T334
Test name
Test status
Simulation time 956877250 ps
CPU time 17.47 seconds
Started Jul 13 06:10:00 PM PDT 24
Finished Jul 13 06:11:41 PM PDT 24
Peak memory 200308 kb
Host smart-fb219979-9ac1-499b-8261-1d36b92cd32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032179820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3032179820
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3549363602
Short name T249
Test name
Test status
Simulation time 14426995 ps
CPU time 0.6 seconds
Started Jul 13 06:10:16 PM PDT 24
Finished Jul 13 06:11:37 PM PDT 24
Peak memory 195956 kb
Host smart-b8149606-a781-42aa-bd51-f0c5f543ad64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549363602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3549363602
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2557120129
Short name T324
Test name
Test status
Simulation time 1110048199 ps
CPU time 39.84 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:12:04 PM PDT 24
Peak memory 200284 kb
Host smart-3c7d58c5-cf5a-4369-bc3b-ef3d87cad3a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557120129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2557120129
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2228612363
Short name T351
Test name
Test status
Simulation time 621208001 ps
CPU time 34.03 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:11:58 PM PDT 24
Peak memory 200280 kb
Host smart-9bd98e85-6a64-45c4-a32a-d1eddf9150ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228612363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2228612363
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2571593224
Short name T192
Test name
Test status
Simulation time 4165033305 ps
CPU time 167.36 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:14:11 PM PDT 24
Peak memory 482988 kb
Host smart-677143b6-e13f-4839-9162-5dfc23e8caa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571593224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2571593224
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.146910758
Short name T517
Test name
Test status
Simulation time 27155228300 ps
CPU time 95.58 seconds
Started Jul 13 06:10:13 PM PDT 24
Finished Jul 13 06:13:10 PM PDT 24
Peak memory 200284 kb
Host smart-2b367d8d-b0c0-4499-b7d5-792d34420f9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146910758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.146910758
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1817428375
Short name T166
Test name
Test status
Simulation time 2478677935 ps
CPU time 140.88 seconds
Started Jul 13 06:10:05 PM PDT 24
Finished Jul 13 06:13:48 PM PDT 24
Peak memory 200348 kb
Host smart-9b66e61a-1399-4b8a-b2f7-adb2be745fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817428375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1817428375
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.4234413059
Short name T466
Test name
Test status
Simulation time 53135055 ps
CPU time 2.2 seconds
Started Jul 13 06:10:02 PM PDT 24
Finished Jul 13 06:11:26 PM PDT 24
Peak memory 200320 kb
Host smart-c126922e-a5a1-4b1c-9d74-309016d8bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234413059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.4234413059
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3109669292
Short name T216
Test name
Test status
Simulation time 607426507460 ps
CPU time 4149.41 seconds
Started Jul 13 06:10:16 PM PDT 24
Finished Jul 13 07:20:46 PM PDT 24
Peak memory 798544 kb
Host smart-4a5e7b14-4812-4b75-b28f-33aaeb974bdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109669292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3109669292
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.674465118
Short name T66
Test name
Test status
Simulation time 2641981785 ps
CPU time 73.38 seconds
Started Jul 13 06:10:13 PM PDT 24
Finished Jul 13 06:12:48 PM PDT 24
Peak memory 200256 kb
Host smart-be8e0f92-f6f8-4395-a189-cb18d9a83972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674465118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.674465118
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1464646177
Short name T354
Test name
Test status
Simulation time 48324601 ps
CPU time 0.62 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:11:48 PM PDT 24
Peak memory 196896 kb
Host smart-59d2a5ca-85c3-4e3a-bc16-94223c65b314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464646177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1464646177
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2220975676
Short name T171
Test name
Test status
Simulation time 360208348 ps
CPU time 8.01 seconds
Started Jul 13 06:10:15 PM PDT 24
Finished Jul 13 06:11:44 PM PDT 24
Peak memory 200284 kb
Host smart-299fcaa0-b89e-4be1-afa2-20162698b023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220975676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2220975676
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4141343554
Short name T243
Test name
Test status
Simulation time 632266467 ps
CPU time 12.28 seconds
Started Jul 13 06:10:16 PM PDT 24
Finished Jul 13 06:11:49 PM PDT 24
Peak memory 200308 kb
Host smart-49eea58f-7945-406b-985a-114de7882ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141343554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4141343554
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1145118787
Short name T376
Test name
Test status
Simulation time 2049475377 ps
CPU time 52.47 seconds
Started Jul 13 06:10:15 PM PDT 24
Finished Jul 13 06:12:28 PM PDT 24
Peak memory 309652 kb
Host smart-19b938f8-bf16-494e-835c-10c649aee160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145118787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1145118787
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.598436187
Short name T320
Test name
Test status
Simulation time 3060165532 ps
CPU time 39.9 seconds
Started Jul 13 06:10:14 PM PDT 24
Finished Jul 13 06:12:15 PM PDT 24
Peak memory 200336 kb
Host smart-6bae1ecc-5659-43c3-a3f0-7ee94f4061a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598436187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.598436187
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.220506608
Short name T227
Test name
Test status
Simulation time 3168855272 ps
CPU time 160.58 seconds
Started Jul 13 06:10:14 PM PDT 24
Finished Jul 13 06:14:16 PM PDT 24
Peak memory 200368 kb
Host smart-57b6b143-e3c4-4dc3-a0df-3ff1207e1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220506608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.220506608
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1532950064
Short name T486
Test name
Test status
Simulation time 2287075663 ps
CPU time 10.09 seconds
Started Jul 13 06:10:15 PM PDT 24
Finished Jul 13 06:11:46 PM PDT 24
Peak memory 200384 kb
Host smart-5aebfed6-d061-4b2c-a05e-ae4d2bc63b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532950064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1532950064
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1062377535
Short name T83
Test name
Test status
Simulation time 108446345237 ps
CPU time 118.79 seconds
Started Jul 13 06:10:26 PM PDT 24
Finished Jul 13 06:13:46 PM PDT 24
Peak memory 200336 kb
Host smart-6b732b9a-9b5f-444c-b419-ca08a7150a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062377535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1062377535
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.845247940
Short name T29
Test name
Test status
Simulation time 1202373873 ps
CPU time 3.25 seconds
Started Jul 13 06:10:15 PM PDT 24
Finished Jul 13 06:11:39 PM PDT 24
Peak memory 200232 kb
Host smart-694a7ae1-3f09-4029-b934-63205668f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845247940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.845247940
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2438676037
Short name T374
Test name
Test status
Simulation time 12104051 ps
CPU time 0.59 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:11:48 PM PDT 24
Peak memory 195132 kb
Host smart-cad9b363-a953-485b-a89a-7ba26a192582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438676037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2438676037
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1529334781
Short name T293
Test name
Test status
Simulation time 230429050 ps
CPU time 13.4 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:12:00 PM PDT 24
Peak memory 200260 kb
Host smart-77724a78-1e1e-48a2-a1d9-0b5ffd3bc643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529334781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1529334781
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2009482964
Short name T451
Test name
Test status
Simulation time 412888543 ps
CPU time 10.82 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:11:58 PM PDT 24
Peak memory 200280 kb
Host smart-6adeb21b-a6f5-4d75-a313-7ccc1a39c071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009482964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2009482964
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1364282160
Short name T30
Test name
Test status
Simulation time 12011664634 ps
CPU time 1155.13 seconds
Started Jul 13 06:10:26 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 721160 kb
Host smart-af346fc5-e065-4ffe-bdd4-cdf40683e38b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364282160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1364282160
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1844714797
Short name T368
Test name
Test status
Simulation time 669008308 ps
CPU time 36.45 seconds
Started Jul 13 06:10:27 PM PDT 24
Finished Jul 13 06:12:25 PM PDT 24
Peak memory 200288 kb
Host smart-5aeab1d8-cf35-4911-b3f3-d4a0e9af48be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844714797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1844714797
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1103784994
Short name T367
Test name
Test status
Simulation time 49349161736 ps
CPU time 211.42 seconds
Started Jul 13 06:10:26 PM PDT 24
Finished Jul 13 06:15:19 PM PDT 24
Peak memory 208592 kb
Host smart-04a47165-a2f1-4be4-95fa-7d558e00093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103784994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1103784994
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4026475304
Short name T32
Test name
Test status
Simulation time 1555311715 ps
CPU time 13.01 seconds
Started Jul 13 06:10:26 PM PDT 24
Finished Jul 13 06:12:00 PM PDT 24
Peak memory 200312 kb
Host smart-8170b7df-938e-4710-b7cb-fe27b27d0ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026475304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4026475304
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1476455249
Short name T475
Test name
Test status
Simulation time 63278062087 ps
CPU time 187.53 seconds
Started Jul 13 06:10:27 PM PDT 24
Finished Jul 13 06:14:57 PM PDT 24
Peak memory 209768 kb
Host smart-7148cc8e-70c4-4965-bda3-db851045d73f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476455249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1476455249
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3836531354
Short name T266
Test name
Test status
Simulation time 28594813785 ps
CPU time 87.07 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:13:14 PM PDT 24
Peak memory 200336 kb
Host smart-56c386c5-db92-4582-b225-07ecd2208db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836531354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3836531354
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.99462708
Short name T178
Test name
Test status
Simulation time 12831457 ps
CPU time 0.6 seconds
Started Jul 13 06:10:33 PM PDT 24
Finished Jul 13 06:11:57 PM PDT 24
Peak memory 196444 kb
Host smart-cfd9d85d-8a86-49c6-910e-752c8eb24bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99462708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.99462708
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3156872711
Short name T461
Test name
Test status
Simulation time 1188309895 ps
CPU time 67.78 seconds
Started Jul 13 06:10:26 PM PDT 24
Finished Jul 13 06:12:56 PM PDT 24
Peak memory 200284 kb
Host smart-1e4efb8e-e904-44dc-ab6e-88b3a57175b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156872711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3156872711
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3262930498
Short name T206
Test name
Test status
Simulation time 133745176 ps
CPU time 3.56 seconds
Started Jul 13 06:10:26 PM PDT 24
Finished Jul 13 06:11:51 PM PDT 24
Peak memory 200236 kb
Host smart-58fd1cbb-73bb-4ce5-a59d-08f10e24667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262930498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3262930498
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1071300835
Short name T224
Test name
Test status
Simulation time 10592040635 ps
CPU time 300.29 seconds
Started Jul 13 06:10:27 PM PDT 24
Finished Jul 13 06:16:50 PM PDT 24
Peak memory 445944 kb
Host smart-dacef0f3-3f62-4b5e-93ea-120132a3b3d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071300835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1071300835
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3120909330
Short name T377
Test name
Test status
Simulation time 14572007946 ps
CPU time 193 seconds
Started Jul 13 06:10:33 PM PDT 24
Finished Jul 13 06:15:09 PM PDT 24
Peak memory 200360 kb
Host smart-e0be3a34-c562-4ba5-9232-2743bc19324a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120909330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3120909330
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1005553313
Short name T56
Test name
Test status
Simulation time 4915576694 ps
CPU time 21.91 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:12:09 PM PDT 24
Peak memory 200360 kb
Host smart-cb55d97c-76ce-4980-b380-b33b4187fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005553313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1005553313
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3258252340
Short name T510
Test name
Test status
Simulation time 2081920716 ps
CPU time 7.04 seconds
Started Jul 13 06:10:25 PM PDT 24
Finished Jul 13 06:11:54 PM PDT 24
Peak memory 200300 kb
Host smart-7189cbb1-f437-46ab-bd32-09944da5f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258252340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3258252340
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.63829640
Short name T187
Test name
Test status
Simulation time 64601759832 ps
CPU time 2290.67 seconds
Started Jul 13 06:10:34 PM PDT 24
Finished Jul 13 06:50:08 PM PDT 24
Peak memory 820776 kb
Host smart-2b7e0c57-5983-45e6-9134-6631939235a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63829640 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.63829640
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2918590093
Short name T229
Test name
Test status
Simulation time 6113054538 ps
CPU time 74.42 seconds
Started Jul 13 06:10:39 PM PDT 24
Finished Jul 13 06:13:19 PM PDT 24
Peak memory 200332 kb
Host smart-9100a0d4-90f7-4479-addd-af5fb70a32f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918590093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2918590093
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1486508488
Short name T242
Test name
Test status
Simulation time 18816096 ps
CPU time 0.56 seconds
Started Jul 13 06:10:43 PM PDT 24
Finished Jul 13 06:12:06 PM PDT 24
Peak memory 195080 kb
Host smart-1291c89b-8fe8-4d4d-9908-45344960b846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486508488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1486508488
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3502331149
Short name T174
Test name
Test status
Simulation time 900974434 ps
CPU time 48.64 seconds
Started Jul 13 06:10:37 PM PDT 24
Finished Jul 13 06:12:51 PM PDT 24
Peak memory 200284 kb
Host smart-ca290c4a-bb11-4542-b787-8b698d545013
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502331149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3502331149
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2737922735
Short name T143
Test name
Test status
Simulation time 5466728693 ps
CPU time 48.53 seconds
Started Jul 13 06:10:32 PM PDT 24
Finished Jul 13 06:12:44 PM PDT 24
Peak memory 200320 kb
Host smart-dbd78f98-7856-42f1-b800-6a2ed94a34c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737922735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2737922735
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.288112712
Short name T39
Test name
Test status
Simulation time 7125453477 ps
CPU time 337.24 seconds
Started Jul 13 06:10:38 PM PDT 24
Finished Jul 13 06:17:41 PM PDT 24
Peak memory 669156 kb
Host smart-cf6f5611-d5af-4d48-925e-99ae1960df31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288112712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.288112712
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1376224735
Short name T481
Test name
Test status
Simulation time 23679136 ps
CPU time 0.7 seconds
Started Jul 13 06:10:33 PM PDT 24
Finished Jul 13 06:11:57 PM PDT 24
Peak memory 196676 kb
Host smart-1c42617d-676d-4fec-924d-740783f46329
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376224735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1376224735
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1470741859
Short name T452
Test name
Test status
Simulation time 3699555086 ps
CPU time 101.81 seconds
Started Jul 13 06:10:39 PM PDT 24
Finished Jul 13 06:13:46 PM PDT 24
Peak memory 200380 kb
Host smart-c2af799d-65b6-4be5-9669-661a5bd61f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470741859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1470741859
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3807788259
Short name T177
Test name
Test status
Simulation time 1111270242 ps
CPU time 11.7 seconds
Started Jul 13 06:10:38 PM PDT 24
Finished Jul 13 06:12:16 PM PDT 24
Peak memory 200320 kb
Host smart-9e20c121-7e5c-4046-b5bb-86ed553257d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807788259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3807788259
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3733621503
Short name T142
Test name
Test status
Simulation time 34290965531 ps
CPU time 1220.21 seconds
Started Jul 13 06:10:32 PM PDT 24
Finished Jul 13 06:32:16 PM PDT 24
Peak memory 675948 kb
Host smart-efb29cd3-2948-410e-83d0-3ec9ba4285cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733621503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3733621503
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.68922450
Short name T363
Test name
Test status
Simulation time 546248564 ps
CPU time 20.48 seconds
Started Jul 13 06:10:33 PM PDT 24
Finished Jul 13 06:12:17 PM PDT 24
Peak memory 200072 kb
Host smart-b79fddb5-9b9e-4cc8-a29f-e623fec2aeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68922450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.68922450
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2513850302
Short name T378
Test name
Test status
Simulation time 103422610 ps
CPU time 0.56 seconds
Started Jul 13 06:10:42 PM PDT 24
Finished Jul 13 06:12:06 PM PDT 24
Peak memory 196160 kb
Host smart-d6b45ce4-8710-4675-89f3-6cd71efe9a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513850302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2513850302
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.390506086
Short name T482
Test name
Test status
Simulation time 4949192171 ps
CPU time 74.64 seconds
Started Jul 13 06:10:42 PM PDT 24
Finished Jul 13 06:13:20 PM PDT 24
Peak memory 200444 kb
Host smart-64421e9b-0983-413d-8f80-99285dd5bb1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390506086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.390506086
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3868959308
Short name T247
Test name
Test status
Simulation time 2637245771 ps
CPU time 52.73 seconds
Started Jul 13 06:10:44 PM PDT 24
Finished Jul 13 06:12:58 PM PDT 24
Peak memory 200392 kb
Host smart-8422edbf-c9ac-443f-82fa-39e2b43fa58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868959308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3868959308
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1867792696
Short name T225
Test name
Test status
Simulation time 973464586 ps
CPU time 51.46 seconds
Started Jul 13 06:10:42 PM PDT 24
Finished Jul 13 06:12:57 PM PDT 24
Peak memory 259112 kb
Host smart-ecdc501d-8176-4bff-b275-44623a9dd614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867792696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1867792696
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1226233472
Short name T195
Test name
Test status
Simulation time 14488184698 ps
CPU time 196.12 seconds
Started Jul 13 06:10:42 PM PDT 24
Finished Jul 13 06:15:21 PM PDT 24
Peak memory 200312 kb
Host smart-2e92f82f-d9ad-4d7d-8421-ca8ffc161a2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226233472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1226233472
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3727582428
Short name T244
Test name
Test status
Simulation time 35172402808 ps
CPU time 93.75 seconds
Started Jul 13 06:10:41 PM PDT 24
Finished Jul 13 06:13:38 PM PDT 24
Peak memory 200372 kb
Host smart-62781209-261f-4881-8d94-aa31f14cda46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727582428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3727582428
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3123254799
Short name T497
Test name
Test status
Simulation time 2725014977 ps
CPU time 17.75 seconds
Started Jul 13 06:10:43 PM PDT 24
Finished Jul 13 06:12:23 PM PDT 24
Peak memory 200372 kb
Host smart-c4e19f0e-ef71-42f6-a683-df7e417b6878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123254799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3123254799
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2887244662
Short name T276
Test name
Test status
Simulation time 374482404700 ps
CPU time 3375 seconds
Started Jul 13 06:10:43 PM PDT 24
Finished Jul 13 07:08:21 PM PDT 24
Peak memory 759896 kb
Host smart-95794276-fd06-49b0-8c65-a5c25315ceb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887244662 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2887244662
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.474640457
Short name T524
Test name
Test status
Simulation time 29551760840 ps
CPU time 93 seconds
Started Jul 13 06:10:41 PM PDT 24
Finished Jul 13 06:13:37 PM PDT 24
Peak memory 200260 kb
Host smart-d9690131-8a97-46bc-9001-f12fa266dc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474640457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.474640457
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4108232953
Short name T366
Test name
Test status
Simulation time 46505090 ps
CPU time 0.58 seconds
Started Jul 13 06:10:52 PM PDT 24
Finished Jul 13 06:12:13 PM PDT 24
Peak memory 196860 kb
Host smart-3f474cf1-0927-4da4-93a1-b51b121103cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108232953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4108232953
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2148148151
Short name T169
Test name
Test status
Simulation time 171401173 ps
CPU time 2.5 seconds
Started Jul 13 06:10:41 PM PDT 24
Finished Jul 13 06:12:07 PM PDT 24
Peak memory 200280 kb
Host smart-f4409384-7dc8-4917-9748-3d15aab20ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148148151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2148148151
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4222166431
Short name T370
Test name
Test status
Simulation time 727165286 ps
CPU time 9.12 seconds
Started Jul 13 06:10:42 PM PDT 24
Finished Jul 13 06:12:14 PM PDT 24
Peak memory 200300 kb
Host smart-d526e5d0-45ef-4a32-be52-7a858a9f7687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222166431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4222166431
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2329059246
Short name T530
Test name
Test status
Simulation time 3138624755 ps
CPU time 135.73 seconds
Started Jul 13 06:10:44 PM PDT 24
Finished Jul 13 06:14:21 PM PDT 24
Peak memory 440196 kb
Host smart-f822e82b-92e7-4897-88be-84cece29cd2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2329059246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2329059246
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3471721040
Short name T339
Test name
Test status
Simulation time 6793426912 ps
CPU time 174.5 seconds
Started Jul 13 06:10:43 PM PDT 24
Finished Jul 13 06:15:00 PM PDT 24
Peak memory 200264 kb
Host smart-1207b3a2-9e06-4b4d-ae2e-e0dbc43137e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471721040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3471721040
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3145507233
Short name T255
Test name
Test status
Simulation time 41354069602 ps
CPU time 181.95 seconds
Started Jul 13 06:10:42 PM PDT 24
Finished Jul 13 06:15:07 PM PDT 24
Peak memory 200360 kb
Host smart-b93128ff-58c3-483a-a816-54d866ed0c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145507233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3145507233
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4193471358
Short name T454
Test name
Test status
Simulation time 1716801504 ps
CPU time 2.8 seconds
Started Jul 13 06:10:41 PM PDT 24
Finished Jul 13 06:12:08 PM PDT 24
Peak memory 200320 kb
Host smart-8f257455-4af8-4ed3-9c32-55cabc77f85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193471358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4193471358
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2126377290
Short name T457
Test name
Test status
Simulation time 15734400141 ps
CPU time 285.9 seconds
Started Jul 13 06:10:51 PM PDT 24
Finished Jul 13 06:16:58 PM PDT 24
Peak memory 200356 kb
Host smart-b434ebd7-e2e9-461a-8fc9-1b307572ed3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126377290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2126377290
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3454335764
Short name T396
Test name
Test status
Simulation time 4742058712 ps
CPU time 36.76 seconds
Started Jul 13 06:10:51 PM PDT 24
Finished Jul 13 06:12:49 PM PDT 24
Peak memory 200332 kb
Host smart-48f7f344-c558-4cb7-a707-30d5311a3be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454335764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3454335764
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1593615212
Short name T412
Test name
Test status
Simulation time 12584564 ps
CPU time 0.58 seconds
Started Jul 13 06:07:25 PM PDT 24
Finished Jul 13 06:08:37 PM PDT 24
Peak memory 196212 kb
Host smart-bf37ad4c-00aa-4da9-a0a7-9f3e323b3925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593615212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1593615212
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.458235919
Short name T274
Test name
Test status
Simulation time 268928626 ps
CPU time 7.74 seconds
Started Jul 13 06:07:25 PM PDT 24
Finished Jul 13 06:08:44 PM PDT 24
Peak memory 200292 kb
Host smart-b7abdd05-0fd3-4d29-b2fd-33d6e124969b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458235919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.458235919
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3627731745
Short name T58
Test name
Test status
Simulation time 427007666 ps
CPU time 5.99 seconds
Started Jul 13 06:07:25 PM PDT 24
Finished Jul 13 06:08:42 PM PDT 24
Peak memory 200140 kb
Host smart-1d05a424-3741-4c7a-b3a1-c549ee8412cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627731745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3627731745
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1113647626
Short name T400
Test name
Test status
Simulation time 8001996860 ps
CPU time 1500.54 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:33:40 PM PDT 24
Peak memory 761552 kb
Host smart-1263f7c9-8c3a-4880-a4e8-87dc1c187500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113647626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1113647626
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.326654194
Short name T27
Test name
Test status
Simulation time 2255682364 ps
CPU time 34.35 seconds
Started Jul 13 06:07:25 PM PDT 24
Finished Jul 13 06:09:10 PM PDT 24
Peak memory 200336 kb
Host smart-8060cdb2-c891-49ee-a5b4-80b439fc0b14
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326654194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.326654194
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2113566732
Short name T273
Test name
Test status
Simulation time 1842733322 ps
CPU time 99.5 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:10:19 PM PDT 24
Peak memory 200304 kb
Host smart-2b07b915-b326-432b-aa00-a343546e9684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113566732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2113566732
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2695121072
Short name T483
Test name
Test status
Simulation time 198911946 ps
CPU time 4.78 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:08:44 PM PDT 24
Peak memory 200300 kb
Host smart-eeb870cd-c082-4440-9a35-bf8d46925201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695121072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2695121072
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3776243646
Short name T199
Test name
Test status
Simulation time 288903354833 ps
CPU time 2847.49 seconds
Started Jul 13 06:07:24 PM PDT 24
Finished Jul 13 06:56:03 PM PDT 24
Peak memory 776616 kb
Host smart-a94cce1a-efbb-4f44-91c3-52db31271b33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776243646 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3776243646
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1827963141
Short name T72
Test name
Test status
Simulation time 33408497914 ps
CPU time 279.14 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:13:31 PM PDT 24
Peak memory 225156 kb
Host smart-6d8829fa-0175-41eb-84c1-f00b4c519920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827963141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1827963141
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.767637992
Short name T521
Test name
Test status
Simulation time 8222042636 ps
CPU time 106.32 seconds
Started Jul 13 06:07:27 PM PDT 24
Finished Jul 13 06:10:26 PM PDT 24
Peak memory 200348 kb
Host smart-b707017d-6363-42b6-ae42-dad7707d315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767637992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.767637992
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.746246942
Short name T176
Test name
Test status
Simulation time 15422256 ps
CPU time 0.57 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:08:40 PM PDT 24
Peak memory 196276 kb
Host smart-6c0a9b0d-ee4e-4a3b-b834-5984e7ab8a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746246942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.746246942
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.111477980
Short name T191
Test name
Test status
Simulation time 11999340174 ps
CPU time 96.01 seconds
Started Jul 13 06:07:39 PM PDT 24
Finished Jul 13 06:10:30 PM PDT 24
Peak memory 200372 kb
Host smart-958ba08d-0383-4790-9ae2-68628dbf6443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111477980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.111477980
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.531237529
Short name T319
Test name
Test status
Simulation time 5103674201 ps
CPU time 25.83 seconds
Started Jul 13 06:07:40 PM PDT 24
Finished Jul 13 06:09:20 PM PDT 24
Peak memory 200332 kb
Host smart-c1387bd2-6e8d-43da-943d-252a61c02532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531237529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.531237529
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1594311080
Short name T146
Test name
Test status
Simulation time 2752804361 ps
CPU time 477.64 seconds
Started Jul 13 06:07:27 PM PDT 24
Finished Jul 13 06:16:37 PM PDT 24
Peak memory 664640 kb
Host smart-2fd96124-8ab6-4075-9c8f-9fc271394000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594311080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1594311080
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4250949407
Short name T223
Test name
Test status
Simulation time 8558680717 ps
CPU time 114.94 seconds
Started Jul 13 06:07:40 PM PDT 24
Finished Jul 13 06:10:49 PM PDT 24
Peak memory 200300 kb
Host smart-70e87e1f-3235-4f27-92cf-4cd51ec34344
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250949407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4250949407
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1600939088
Short name T459
Test name
Test status
Simulation time 3397278225 ps
CPU time 77.98 seconds
Started Jul 13 06:07:40 PM PDT 24
Finished Jul 13 06:10:12 PM PDT 24
Peak memory 200316 kb
Host smart-742c5985-8dfb-497a-8db7-380c124bdc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600939088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1600939088
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.703090765
Short name T311
Test name
Test status
Simulation time 479195429 ps
CPU time 4.61 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:08:57 PM PDT 24
Peak memory 200296 kb
Host smart-0c674254-269f-4252-ba60-cad61f0e1212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703090765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.703090765
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.981803889
Short name T450
Test name
Test status
Simulation time 107863399500 ps
CPU time 516.12 seconds
Started Jul 13 06:07:25 PM PDT 24
Finished Jul 13 06:17:12 PM PDT 24
Peak memory 215812 kb
Host smart-60e8b209-c443-41aa-bf90-4e2dba74e6d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981803889 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.981803889
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.528191796
Short name T429
Test name
Test status
Simulation time 4483437672 ps
CPU time 111.65 seconds
Started Jul 13 06:07:26 PM PDT 24
Finished Jul 13 06:10:31 PM PDT 24
Peak memory 200316 kb
Host smart-7dbdf5a1-c0c4-463b-9c6a-c8af0c206820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528191796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.528191796
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2469713134
Short name T92
Test name
Test status
Simulation time 14230882 ps
CPU time 0.58 seconds
Started Jul 13 06:07:37 PM PDT 24
Finished Jul 13 06:08:54 PM PDT 24
Peak memory 195860 kb
Host smart-0ef31980-da15-439c-b353-371c6cfbbadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469713134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2469713134
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1818896460
Short name T345
Test name
Test status
Simulation time 5619158686 ps
CPU time 64.36 seconds
Started Jul 13 06:07:33 PM PDT 24
Finished Jul 13 06:09:54 PM PDT 24
Peak memory 200328 kb
Host smart-ca4725ad-12c1-448c-895c-96d1ddcdd75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818896460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1818896460
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3618347874
Short name T35
Test name
Test status
Simulation time 2113442097 ps
CPU time 55.06 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:09:44 PM PDT 24
Peak memory 200232 kb
Host smart-71efcf5c-36a1-45a2-84a4-fb22509debe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618347874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3618347874
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1398940933
Short name T330
Test name
Test status
Simulation time 9602603378 ps
CPU time 1907.25 seconds
Started Jul 13 06:07:24 PM PDT 24
Finished Jul 13 06:40:23 PM PDT 24
Peak memory 787936 kb
Host smart-988911b5-e5cb-4b5b-986e-5e072a553033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398940933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1398940933
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1282471933
Short name T356
Test name
Test status
Simulation time 1767228064 ps
CPU time 94.92 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:10:27 PM PDT 24
Peak memory 200280 kb
Host smart-5231a6c8-3d38-4379-8363-e1992e988f92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282471933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1282471933
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3205513752
Short name T453
Test name
Test status
Simulation time 11977815955 ps
CPU time 153.01 seconds
Started Jul 13 06:07:40 PM PDT 24
Finished Jul 13 06:11:27 PM PDT 24
Peak memory 216532 kb
Host smart-15739c00-a4fd-4038-b107-90c048f7184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205513752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3205513752
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4144207577
Short name T89
Test name
Test status
Simulation time 474217160 ps
CPU time 5.82 seconds
Started Jul 13 06:07:39 PM PDT 24
Finished Jul 13 06:09:00 PM PDT 24
Peak memory 200268 kb
Host smart-5a26bf70-db09-45d9-b67f-1138a06f2ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144207577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4144207577
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.5418366
Short name T82
Test name
Test status
Simulation time 56823055 ps
CPU time 0.61 seconds
Started Jul 13 06:07:38 PM PDT 24
Finished Jul 13 06:08:55 PM PDT 24
Peak memory 196032 kb
Host smart-26227e7d-02aa-4f41-b774-7e793b5845dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5418366 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.5418366
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.4293361006
Short name T13
Test name
Test status
Simulation time 18211057962 ps
CPU time 276.46 seconds
Started Jul 13 06:07:36 PM PDT 24
Finished Jul 13 06:13:30 PM PDT 24
Peak memory 216540 kb
Host smart-973593c3-0ec4-4f0c-9154-cbe80c1ead4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293361006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.4293361006
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.484233761
Short name T127
Test name
Test status
Simulation time 31511937957 ps
CPU time 123.7 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:10:56 PM PDT 24
Peak memory 200396 kb
Host smart-ca502736-b750-43ba-880c-1a92be5996a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484233761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.484233761
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3138321348
Short name T478
Test name
Test status
Simulation time 38296228 ps
CPU time 0.56 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:08:50 PM PDT 24
Peak memory 195956 kb
Host smart-7e6b2130-ac7b-4aff-bb3e-85cfeee26674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138321348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3138321348
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1933220568
Short name T348
Test name
Test status
Simulation time 1391622080 ps
CPU time 31.63 seconds
Started Jul 13 06:07:41 PM PDT 24
Finished Jul 13 06:09:26 PM PDT 24
Peak memory 200252 kb
Host smart-bde9bd2b-210c-4864-8808-ca5c816fec3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933220568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1933220568
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2650500669
Short name T237
Test name
Test status
Simulation time 3197362277 ps
CPU time 57.47 seconds
Started Jul 13 06:07:37 PM PDT 24
Finished Jul 13 06:09:51 PM PDT 24
Peak memory 200376 kb
Host smart-5f756d47-26e2-4b85-9113-7c3e45e9df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650500669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2650500669
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3784345314
Short name T238
Test name
Test status
Simulation time 2987552870 ps
CPU time 469.18 seconds
Started Jul 13 06:07:35 PM PDT 24
Finished Jul 13 06:16:42 PM PDT 24
Peak memory 498780 kb
Host smart-65a3df17-d8c7-4c0f-91bb-c03987a8a8cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784345314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3784345314
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3306173933
Short name T175
Test name
Test status
Simulation time 60763592078 ps
CPU time 184.99 seconds
Started Jul 13 06:07:33 PM PDT 24
Finished Jul 13 06:11:54 PM PDT 24
Peak memory 200408 kb
Host smart-e128388e-57fd-489e-a2a2-f5591f13c050
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306173933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3306173933
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.757449648
Short name T19
Test name
Test status
Simulation time 4847008700 ps
CPU time 108.43 seconds
Started Jul 13 06:07:37 PM PDT 24
Finished Jul 13 06:10:42 PM PDT 24
Peak memory 200372 kb
Host smart-7b52ea36-40ce-4c8c-b07d-4ae78ba4a5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757449648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.757449648
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2132935629
Short name T168
Test name
Test status
Simulation time 878927453 ps
CPU time 5.13 seconds
Started Jul 13 06:07:35 PM PDT 24
Finished Jul 13 06:08:58 PM PDT 24
Peak memory 200264 kb
Host smart-8e30edc9-b83b-4091-a0c3-4363b764f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132935629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2132935629
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3058613557
Short name T289
Test name
Test status
Simulation time 243996350525 ps
CPU time 1752.06 seconds
Started Jul 13 06:07:32 PM PDT 24
Finished Jul 13 06:38:01 PM PDT 24
Peak memory 712080 kb
Host smart-ab6ad03d-acc8-431f-bf93-6dc8571b2146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058613557 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3058613557
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1374136728
Short name T67
Test name
Test status
Simulation time 58727172106 ps
CPU time 3341.74 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 07:04:34 PM PDT 24
Peak memory 783784 kb
Host smart-9f974ae1-57d6-461a-b1d4-6c8f0a080ba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374136728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1374136728
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2989793210
Short name T369
Test name
Test status
Simulation time 952408250 ps
CPU time 43.16 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:09:33 PM PDT 24
Peak memory 200264 kb
Host smart-88e988b3-4bbe-47f9-b651-63f91e98ee16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989793210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2989793210
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2153746375
Short name T395
Test name
Test status
Simulation time 21729923 ps
CPU time 0.58 seconds
Started Jul 13 06:07:49 PM PDT 24
Finished Jul 13 06:09:02 PM PDT 24
Peak memory 196216 kb
Host smart-313b1b0e-de2a-4c0d-8ebd-fed056f2d258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153746375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2153746375
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2257947367
Short name T519
Test name
Test status
Simulation time 1908136288 ps
CPU time 27.13 seconds
Started Jul 13 06:07:48 PM PDT 24
Finished Jul 13 06:09:29 PM PDT 24
Peak memory 200324 kb
Host smart-7d4997f9-3918-4feb-b9ea-17cb23869ffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257947367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2257947367
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1656267670
Short name T46
Test name
Test status
Simulation time 4300472092 ps
CPU time 29.43 seconds
Started Jul 13 06:07:42 PM PDT 24
Finished Jul 13 06:09:29 PM PDT 24
Peak memory 200360 kb
Host smart-ac419801-9e90-4ac2-9ee2-49ff8c4ce723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656267670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1656267670
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4126340412
Short name T95
Test name
Test status
Simulation time 2185631124 ps
CPU time 389.15 seconds
Started Jul 13 06:07:42 PM PDT 24
Finished Jul 13 06:15:29 PM PDT 24
Peak memory 677160 kb
Host smart-91e88b31-9be5-4000-ba5b-c69b884d6151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126340412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4126340412
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3650344679
Short name T272
Test name
Test status
Simulation time 6088819657 ps
CPU time 28.3 seconds
Started Jul 13 06:07:41 PM PDT 24
Finished Jul 13 06:09:27 PM PDT 24
Peak memory 200280 kb
Host smart-23eb16d3-a483-4599-9ba1-682deb45b3f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650344679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3650344679
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.118386332
Short name T33
Test name
Test status
Simulation time 6747274261 ps
CPU time 90.95 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:10:23 PM PDT 24
Peak memory 200364 kb
Host smart-e1d0094a-9e34-45b1-8274-9675645fb188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118386332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.118386332
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3674135918
Short name T444
Test name
Test status
Simulation time 3188900170 ps
CPU time 10.13 seconds
Started Jul 13 06:07:34 PM PDT 24
Finished Jul 13 06:09:02 PM PDT 24
Peak memory 200308 kb
Host smart-21e2c0f3-9d28-4ea6-ae46-7e0827e4b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674135918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3674135918
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1068643839
Short name T186
Test name
Test status
Simulation time 64881245 ps
CPU time 1.5 seconds
Started Jul 13 06:07:49 PM PDT 24
Finished Jul 13 06:09:03 PM PDT 24
Peak memory 200304 kb
Host smart-5ffa337c-0d85-41fe-b76f-6b44845d6cf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068643839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1068643839
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.434857752
Short name T68
Test name
Test status
Simulation time 141870811401 ps
CPU time 1688.2 seconds
Started Jul 13 06:07:42 PM PDT 24
Finished Jul 13 06:37:08 PM PDT 24
Peak memory 224980 kb
Host smart-baebda67-6bb0-483c-b57f-87897f79fc70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434857752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.434857752
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.952143293
Short name T298
Test name
Test status
Simulation time 2121788786 ps
CPU time 19.07 seconds
Started Jul 13 06:07:49 PM PDT 24
Finished Jul 13 06:09:21 PM PDT 24
Peak memory 200288 kb
Host smart-4115d4ef-d5b6-4a08-9527-9522e7b776a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952143293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.952143293
Directory /workspace/9.hmac_wipe_secret/latest
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