Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18130595	1			T2	581		T7	42392		T4	1930
all_values[1]	18130595	1			T2	581		T7	42392		T4	1930
all_values[2]	18130595	1			T2	581		T7	42392		T4	1930

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329891

1

T7

4528

T4

198

T5

5311

auto[1]

54061894

1

T2

1743

T7

122648

T4

5592

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46421615

1

T2

1479

T7

97094

T4

5292

auto[1]

7970170

1

T2

264

T7

30082

T4

498

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	120159	1			T7	2998		T5	2633		T55	230
all_values[0]	auto[0]	auto[1]	359	1			T5	7		T55	2		T30	2
all_values[0]	auto[1]	auto[0]	17989948	1			T2	576		T7	39387		T4	1911
all_values[0]	auto[1]	auto[1]	20129	1			T2	5		T7	7		T4	19
all_values[1]	auto[0]	auto[0]	89334	1			T5	2474		T8	41		T120	285
all_values[1]	auto[0]	auto[1]	220	1			T5	3		T58	4		T9	4
all_values[1]	auto[1]	auto[0]	18040656	1			T2	581		T7	42392		T4	1930
all_values[1]	auto[1]	auto[1]	385	1			T5	3		T8	2		T6	4
all_values[2]	auto[0]	auto[0]	68672	1			T7	775		T4	198		T5	190
all_values[2]	auto[0]	auto[1]	51147	1			T7	755		T5	4		T58	2
all_values[2]	auto[1]	auto[0]	10112846	1			T2	322		T7	11542		T4	1253
all_values[2]	auto[1]	auto[1]	7897930	1			T2	259		T7	29320		T4	479