Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147414

1

T2

4

T7

52

T4

594

auto[1]

140966

1

T2

12

T7

28

T4

910

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	108852	1			T7	23		T4	612		T5	1632
len_1026_2046	6312	1			T7	13		T4	33		T5	35
len_514_1022	3463	1			T2	4		T4	20		T5	37
len_2_510	5178	1			T4	24		T5	15		T8	3
len_2056	177	1			T5	2		T17	1		T132	3
len_2048	356	1			T4	2		T5	1		T17	4
len_2040	305	1			T5	1		T9	2		T76	3
len_1032	187	1			T5	2		T17	2		T133	3
len_1024	1745	1			T4	2		T5	1		T6	1
len_1016	271	1			T5	8		T134	1		T135	4
len_520	189	1			T17	1		T135	2		T9	4
len_512	683	1			T4	2		T5	6		T17	5
len_504	239	1			T5	3		T136	2		T9	8
len_8	1030	1			T2	1		T5	10		T18	14
len_0	15203	1			T2	3		T7	4		T4	57

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

122

1

T4

1

T58

1

T137

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	56346	1			T7	17		T4	265		T5	894
auto[0]	len_1026_2046	2944	1			T7	9		T4	11		T5	27
auto[0]	len_514_1022	2474	1			T2	1		T4	9		T5	15
auto[0]	len_2_510	2185	1			T4	7		T5	6		T6	73
auto[0]	len_2056	99	1			T5	2		T17	1		T132	3
auto[0]	len_2048	197	1			T4	1		T5	1		T17	1
auto[0]	len_2040	221	1			T5	1		T76	3		T37	2
auto[0]	len_1032	105	1			T5	2		T17	1		T9	1
auto[0]	len_1024	252	1			T4	2		T6	1		T55	1
auto[0]	len_1016	143	1			T5	3		T134	1		T135	2
auto[0]	len_520	103	1			T17	1		T9	3		T76	1
auto[0]	len_512	245	1			T4	1		T5	3		T17	3
auto[0]	len_504	109	1			T5	1		T9	3		T76	2
auto[0]	len_8	20	1			T2	1		T134	1		T36	1
auto[0]	len_0	8264	1			T4	1		T5	612		T8	144
auto[1]	len_2050_plus	52506	1			T7	6		T4	347		T5	738
auto[1]	len_1026_2046	3368	1			T7	4		T4	22		T5	8
auto[1]	len_514_1022	989	1			T2	3		T4	11		T5	22
auto[1]	len_2_510	2993	1			T4	17		T5	9		T8	3
auto[1]	len_2056	78	1			T77	3		T11	1		T138	5
auto[1]	len_2048	159	1			T4	1		T17	3		T22	1
auto[1]	len_2040	84	1			T9	2		T37	2		T132	1
auto[1]	len_1032	82	1			T17	1		T133	3		T9	1
auto[1]	len_1024	1493	1			T5	1		T55	1		T58	1
auto[1]	len_1016	128	1			T5	5		T135	2		T10	2
auto[1]	len_520	86	1			T135	2		T9	1		T37	1
auto[1]	len_512	438	1			T4	1		T5	3		T17	2
auto[1]	len_504	130	1			T5	2		T136	2		T9	5
auto[1]	len_8	1010	1			T5	10		T18	14		T22	12
auto[1]	len_0	6939	1			T2	3		T7	4		T4	56

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

70

1

T139

2

T140

2

T141

1

auto[1]

len_upper

52

1

T4

1

T58

1

T137

2