Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4638533 1 T2 78 T7 2914 T4 708
auto[1] 2980285 1 T2 115 T7 4359 T4 2396


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2929050 1 T2 29 T7 3912 T4 1400
auto[1] 4689768 1 T2 164 T7 3361 T4 1704


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3366139 1 T2 29 T7 6122 T4 1295
auto[1] 4252679 1 T2 164 T7 1151 T4 1809


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4705238 1 T2 103 T7 3555 T4 1098
auto[1] 2913580 1 T2 90 T7 3718 T4 2006


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6867123 1 T2 190 T7 7173 T4 2789
fifo_depth[1] 117389 1 T2 1 T7 89 T4 60
fifo_depth[2] 89421 1 T7 10 T4 75 T5 183
fifo_depth[3] 71624 1 T7 1 T4 28 T5 45
fifo_depth[4] 67763 1 T2 1 T4 61 T5 44
fifo_depth[5] 53459 1 T4 23 T5 6 T8 3
fifo_depth[6] 43983 1 T2 1 T4 24 T5 5
fifo_depth[7] 28989 1 T4 10 T5 3 T8 2


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 751695 1 T2 3 T7 100 T4 315
auto[1] 6867123 1 T2 190 T7 7173 T4 2789


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7601898 1 T2 193 T7 7273 T4 3104
auto[1] 16920 1 T8 38 T6 338 T19 69


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 30809 1 T7 33 T4 74 T5 67
auto[0] auto[0] auto[0] auto[0] auto[1] 36087 1 T4 61 T5 44 T6 503
auto[0] auto[0] auto[0] auto[1] auto[0] 29237 1 T4 3 T5 82 T8 328
auto[0] auto[0] auto[0] auto[1] auto[1] 42593 1 T2 3 T7 34 T4 7
auto[0] auto[0] auto[1] auto[0] auto[0] 132882 1 T4 14 T5 7 T6 931
auto[0] auto[0] auto[1] auto[0] auto[1] 27301 1 T7 13 T5 27 T6 145
auto[0] auto[0] auto[1] auto[1] auto[0] 30235 1 T7 19 T4 13 T5 47
auto[0] auto[0] auto[1] auto[1] auto[1] 47787 1 T5 64 T6 3 T55 2
auto[0] auto[1] auto[0] auto[0] auto[0] 52653 1 T5 31 T8 452 T6 457
auto[0] auto[1] auto[0] auto[0] auto[1] 47540 1 T5 35 T6 543 T18 266
auto[0] auto[1] auto[0] auto[1] auto[0] 43540 1 T4 19 T5 41 T6 77
auto[0] auto[1] auto[0] auto[1] auto[1] 42682 1 T4 60 T5 48 T6 1714
auto[0] auto[1] auto[1] auto[0] auto[0] 50307 1 T7 1 T5 6 T18 519
auto[0] auto[1] auto[1] auto[0] auto[1] 41812 1 T5 123 T8 7 T6 7
auto[0] auto[1] auto[1] auto[1] auto[0] 59938 1 T4 40 T5 14 T23 30
auto[0] auto[1] auto[1] auto[1] auto[1] 36292 1 T4 24 T5 112 T17 5
auto[1] auto[0] auto[0] auto[0] auto[0] 169279 1 T7 1254 T4 169 T5 3125
auto[1] auto[0] auto[0] auto[0] auto[1] 173481 1 T2 2 T7 368 T4 97
auto[1] auto[0] auto[0] auto[1] auto[0] 174096 1 T7 2 T4 36 T5 3558
auto[1] auto[0] auto[0] auto[1] auto[1] 192403 1 T2 9 T7 1961 T4 51
auto[1] auto[0] auto[1] auto[0] auto[0] 1742264 1 T7 469 T4 250 T5 2281
auto[1] auto[0] auto[1] auto[0] auto[1] 184534 1 T2 15 T7 473 T5 2374
auto[1] auto[0] auto[1] auto[1] auto[0] 176255 1 T7 1068 T4 63 T5 2722
auto[1] auto[0] auto[1] auto[1] auto[1] 176896 1 T7 428 T4 457 T5 3033
auto[1] auto[1] auto[0] auto[0] auto[0] 493180 1 T2 1 T7 257 T4 13
auto[1] auto[1] auto[0] auto[0] auto[1] 457536 1 T2 13 T7 2 T5 5725
auto[1] auto[1] auto[0] auto[1] auto[0] 469584 1 T4 253 T5 6474 T8 121
auto[1] auto[1] auto[0] auto[1] auto[1] 474350 1 T2 1 T7 1 T4 557
auto[1] auto[1] auto[1] auto[0] auto[0] 530512 1 T7 43 T4 16 T5 1163
auto[1] auto[1] auto[1] auto[0] auto[1] 468356 1 T2 47 T7 1 T4 14
auto[1] auto[1] auto[1] auto[1] auto[0] 520467 1 T2 102 T7 409 T4 135
auto[1] auto[1] auto[1] auto[1] auto[1] 463930 1 T7 437 T4 678 T5 7277


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 199192 1 T7 1287 T4 243 T5 3192
auto[0] auto[0] auto[0] auto[0] auto[1] 207995 1 T2 2 T7 368 T4 158
auto[0] auto[0] auto[0] auto[1] auto[0] 203172 1 T7 2 T4 39 T5 3640
auto[0] auto[0] auto[0] auto[1] auto[1] 232426 1 T2 12 T7 1995 T4 58
auto[0] auto[0] auto[1] auto[0] auto[0] 1874538 1 T7 469 T4 264 T5 2288
auto[0] auto[0] auto[1] auto[0] auto[1] 211178 1 T2 15 T7 486 T5 2401
auto[0] auto[0] auto[1] auto[1] auto[0] 204623 1 T7 1087 T4 76 T5 2769
auto[0] auto[0] auto[1] auto[1] auto[1] 222211 1 T7 428 T4 457 T5 3097
auto[0] auto[1] auto[0] auto[0] auto[0] 544763 1 T2 1 T7 257 T4 13
auto[0] auto[1] auto[0] auto[0] auto[1] 504299 1 T2 13 T7 2 T5 5760
auto[0] auto[1] auto[0] auto[1] auto[0] 512474 1 T4 272 T5 6515 T8 121
auto[0] auto[1] auto[0] auto[1] auto[1] 515773 1 T2 1 T7 1 T4 617
auto[0] auto[1] auto[1] auto[0] auto[0] 579840 1 T7 44 T4 16 T5 1169
auto[0] auto[1] auto[1] auto[0] auto[1] 509941 1 T2 47 T7 1 T4 14
auto[0] auto[1] auto[1] auto[1] auto[0] 579363 1 T2 102 T7 409 T4 175
auto[0] auto[1] auto[1] auto[1] auto[1] 500110 1 T7 437 T4 702 T5 7389
auto[1] auto[0] auto[0] auto[0] auto[0] 896 1 T6 39 T54 9 T144 13
auto[1] auto[0] auto[0] auto[0] auto[1] 1573 1 T6 218 T145 101 T54 6
auto[1] auto[0] auto[0] auto[1] auto[0] 161 1 T6 20 T145 4 T54 2
auto[1] auto[0] auto[0] auto[1] auto[1] 2570 1 T8 31 T6 3 T54 9
auto[1] auto[0] auto[1] auto[0] auto[0] 608 1 T19 66 T145 13 T146 29
auto[1] auto[0] auto[1] auto[0] auto[1] 657 1 T19 2 T145 5 T54 10
auto[1] auto[0] auto[1] auto[1] auto[0] 1867 1 T6 6 T145 69 T54 6
auto[1] auto[0] auto[1] auto[1] auto[1] 2472 1 T54 4 T146 1 T147 1
auto[1] auto[1] auto[0] auto[0] auto[0] 1070 1 T8 7 T6 8 T145 69
auto[1] auto[1] auto[0] auto[0] auto[1] 777 1 T6 11 T19 1 T54 4
auto[1] auto[1] auto[0] auto[1] auto[0] 650 1 T145 32 T146 198 T148 160
auto[1] auto[1] auto[0] auto[1] auto[1] 1259 1 T6 33 T145 14 T144 132
auto[1] auto[1] auto[1] auto[0] auto[0] 979 1 T145 34 T146 51 T13 20
auto[1] auto[1] auto[1] auto[0] auto[1] 227 1 T149 32 T150 2 T151 20
auto[1] auto[1] auto[1] auto[1] auto[0] 1042 1 T145 46 T146 7 T150 7
auto[1] auto[1] auto[1] auto[1] auto[1] 112 1 T54 7 T146 9 T150 1


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 169279 1 T7 1254 T4 169 T5 3125
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 173481 1 T2 2 T7 368 T4 97
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 174096 1 T7 2 T4 36 T5 3558
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 192403 1 T2 9 T7 1961 T4 51
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1742264 1 T7 469 T4 250 T5 2281
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 184534 1 T2 15 T7 473 T5 2374
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 176255 1 T7 1068 T4 63 T5 2722
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 176896 1 T7 428 T4 457 T5 3033
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 493180 1 T2 1 T7 257 T4 13
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 457536 1 T2 13 T7 2 T5 5725
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 469584 1 T4 253 T5 6474 T8 121
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 474350 1 T2 1 T7 1 T4 557
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 530512 1 T7 43 T4 16 T5 1163
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 468356 1 T2 47 T7 1 T4 14
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 520467 1 T2 102 T7 409 T4 135
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 463930 1 T7 437 T4 678 T5 7277
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3107 1 T7 32 T4 8 T5 42
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3358 1 T4 10 T5 33 T17 2
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3387 1 T4 1 T5 52 T8 5
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3653 1 T2 1 T7 33 T5 25
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 38403 1 T4 2 T5 2 T6 22
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3850 1 T7 10 T5 19 T27 8
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3329 1 T7 13 T5 32 T6 47
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3222 1 T5 35 T142 42 T31 15
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6648 1 T5 14 T8 2 T6 2
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6722 1 T5 22 T18 38 T22 107
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 7101 1 T4 3 T5 20 T6 31
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5848 1 T4 12 T5 21 T6 40
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8172 1 T7 1 T5 5 T18 70
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6933 1 T5 83 T27 17 T23 73
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7336 1 T4 1 T5 7 T23 3
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6320 1 T4 23 T5 83 T17 3
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2435 1 T7 1 T4 13 T5 14
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2657 1 T4 8 T5 10 T27 7
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2753 1 T4 2 T5 19 T8 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2863 1 T7 1 T5 6 T8 14
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 24252 1 T4 12 T5 4 T6 2
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3013 1 T7 3 T5 7 T27 5
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2846 1 T7 5 T4 1 T5 8
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2665 1 T5 11 T142 12 T31 14
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5497 1 T5 9 T6 4 T18 129
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5595 1 T5 12 T18 38 T22 115
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5894 1 T4 2 T5 14 T6 22
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4854 1 T4 16 T5 10 T6 35
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6592 1 T5 1 T18 84 T23 50
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5978 1 T5 32 T8 1 T6 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6353 1 T4 20 T5 3 T23 5
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5174 1 T4 1 T5 23 T17 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1871 1 T4 8 T5 3 T6 3
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2124 1 T4 9 T5 1 T31 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2068 1 T5 6 T8 2 T6 2
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2191 1 T5 3 T6 77 T28 10
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 17466 1 T6 22 T134 3799 T58 6
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2323 1 T5 1 T6 3 T27 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2146 1 T7 1 T4 1 T5 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1978 1 T5 2 T142 1 T31 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5003 1 T5 2 T6 2 T18 121
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4931 1 T5 1 T6 1 T18 43
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 5053 1 T4 2 T5 3 T6 6
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4200 1 T4 7 T5 9 T6 28
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5388 1 T18 75 T23 59 T31 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5126 1 T5 8 T27 3 T23 76
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5523 1 T4 1 T5 2 T23 4
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4233 1 T5 3 T17 1 T22 59
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2154 1 T4 15 T5 4 T6 28
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2326 1 T4 8 T58 8 T152 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2155 1 T5 5 T8 2 T28 24
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2594 1 T2 1 T4 4 T8 16
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 13112 1 T5 1 T6 2 T134 2955
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2574 1 T6 2 T31 1 T58 17
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2324 1 T4 6 T5 6 T6 37
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2347 1 T5 16 T135 1 T58 29
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4737 1 T5 3 T8 8 T6 4
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4705 1 T6 2 T18 34 T22 93
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4905 1 T4 2 T5 1 T6 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4034 1 T4 9 T5 4 T6 10
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4947 1 T18 72 T23 52 T31 2
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4881 1 T6 2 T27 1 T23 69
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5914 1 T4 17 T5 2 T23 7
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4054 1 T5 2 T22 61 T23 58
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1454 1 T4 5 T5 2 T58 3
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1778 1 T4 11 T58 2 T132 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1605 1 T8 2 T6 1 T28 14
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1897 1 T6 36 T28 7 T58 6
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9290 1 T6 22 T134 2262 T58 4
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1825 1 T6 1 T9 5 T41 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1728 1 T6 11 T28 22 T135 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1819 1 T55 1 T135 4 T58 9
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4035 1 T5 1 T6 2 T18 108
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3953 1 T6 1 T18 36 T22 114
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4122 1 T4 2 T5 2 T18 31
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3455 1 T4 5 T5 1 T6 3
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4129 1 T18 63 T23 44 T135 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4179 1 T8 1 T23 59 T58 11
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4714 1 T23 5 T58 9 T137 17
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3476 1 T22 51 T23 43 T58 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1215 1 T4 9 T5 1 T6 2
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1506 1 T4 5 T9 2 T35 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1453 1 T8 2 T6 3 T28 13
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1725 1 T2 1 T8 14 T6 17
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6525 1 T134 1710 T58 5 T9 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1546 1 T6 6 T58 1 T152 1
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1507 1 T6 8 T28 22 T37 3
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1622 1 T135 1 T58 9 T152 3
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3286 1 T5 1 T6 5 T18 110
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3321 1 T6 1 T18 31 T22 90
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3447 1 T4 4 T5 1 T6 2
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2857 1 T4 5 T5 1 T18 8
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3310 1 T18 63 T23 35 T135 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3271 1 T8 1 T6 1 T23 42
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 4462 1 T4 1 T23 2 T58 8
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2930 1 T5 1 T22 37 T23 29
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 883 1 T4 5 T6 2 T58 2
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 952 1 T4 4 T9 2 T132 3
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1040 1 T8 2 T6 1 T28 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1227 1 T6 32 T28 3 T152 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 3911 1 T6 22 T134 1040 T58 4
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 952 1 T6 2 T152 1 T9 2
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 940 1 T6 6 T28 11 T19 38
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1203 1 T58 9 T37 1 T77 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2295 1 T5 1 T6 2 T18 69
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2222 1 T6 17 T18 18 T22 62
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2264 1 T4 1 T18 15 T22 1
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2042 1 T5 2 T6 46 T18 5
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2374 1 T18 51 T23 26 T135 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1948 1 T6 1 T23 22 T58 9
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2765 1 T23 2 T58 7 T137 18
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1971 1 T22 31 T23 10 T153 2

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