Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18130595	1			T2	581		T7	42392		T4	1930
all_pins[1]	18130595	1			T2	581		T7	42392		T4	1930
all_pins[2]	18130595	1			T2	581		T7	42392		T4	1930

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46472446	1			T2	1479		T7	97849		T4	5292
values[0x1]	7919339	1			T2	264		T7	29327		T4	498
transitions[0x0=>0x1]	7919160	1			T2	264		T7	29327		T4	498
transitions[0x1=>0x0]	7919171	1			T2	264		T7	29327		T4	498

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18109598	1			T2	576		T7	42385		T4	1911
all_pins[0]	values[0x1]	20997	1			T2	5		T7	7		T4	19
all_pins[0]	transitions[0x0=>0x1]	20917	1			T2	5		T7	7		T4	19
all_pins[0]	transitions[0x1=>0x0]	7897861	1			T2	259		T7	29320		T4	479
all_pins[1]	values[0x0]	18130183	1			T2	581		T7	42392		T4	1930
all_pins[1]	values[0x1]	412	1			T5	3		T8	2		T6	5
all_pins[1]	transitions[0x0=>0x1]	366	1			T5	3		T8	2		T6	5
all_pins[1]	transitions[0x1=>0x0]	20951	1			T2	5		T7	7		T4	19
all_pins[2]	values[0x0]	10232665	1			T2	322		T7	13072		T4	1451
all_pins[2]	values[0x1]	7897930	1			T2	259		T7	29320		T4	479
all_pins[2]	transitions[0x0=>0x1]	7897877	1			T2	259		T7	29320		T4	479
all_pins[2]	transitions[0x1=>0x0]	359	1			T5	2		T8	2		T6	5