Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1041 1 T5 18 T58 17 T9 17
all_values[1] 1041 1 T5 18 T58 17 T9 17
all_values[2] 1041 1 T5 18 T58 17 T9 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1596 1 T5 29 T58 22 T9 25
auto[1] 1527 1 T5 25 T58 29 T9 26


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1148 1 T5 26 T58 18 T9 13
auto[1] 1975 1 T5 28 T58 33 T9 38


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1803 1 T5 37 T58 27 T9 26
auto[1] 1320 1 T5 17 T58 24 T9 25


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 196 1 T5 6 T58 1 T9 1
all_values[0] auto[0] auto[0] auto[1] 90 1 T5 2 T58 1 T9 3
all_values[0] auto[0] auto[1] auto[0] 205 1 T5 4 T58 7 T9 4
all_values[0] auto[0] auto[1] auto[1] 108 1 T5 1 T58 1 T9 1
all_values[0] auto[1] auto[0] auto[1] 235 1 T5 2 T58 4 T9 2
all_values[0] auto[1] auto[1] auto[1] 207 1 T5 3 T58 3 T9 6
all_values[1] auto[0] auto[0] auto[0] 184 1 T5 4 T58 5 T9 2
all_values[1] auto[0] auto[0] auto[1] 124 1 T5 3 T58 2 T9 2
all_values[1] auto[0] auto[1] auto[0] 149 1 T5 4 T58 1 T9 1
all_values[1] auto[0] auto[1] auto[1] 134 1 T5 1 T58 2 T9 4
all_values[1] auto[1] auto[0] auto[1] 229 1 T5 4 T58 5 T9 4
all_values[1] auto[1] auto[1] auto[1] 221 1 T5 2 T58 2 T9 4
all_values[2] auto[0] auto[0] auto[0] 233 1 T5 3 T58 1 T9 3
all_values[2] auto[0] auto[0] auto[1] 97 1 T5 2 T9 3 T37 1
all_values[2] auto[0] auto[1] auto[0] 181 1 T5 5 T58 3 T9 2
all_values[2] auto[0] auto[1] auto[1] 102 1 T5 2 T58 3 T68 1
all_values[2] auto[1] auto[0] auto[1] 208 1 T5 3 T58 3 T9 5
all_values[2] auto[1] auto[1] auto[1] 220 1 T5 3 T58 7 T9 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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