Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4502	1			T2	4		T7	8		T4	4
sha2_none	4377	1			T7	4		T4	3		T5	79
sha2_512	7665	1			T2	3		T7	6		T4	6
sha2_384	7564	1			T2	2		T7	10		T4	4
sha2_256	6453	1			T2	1		T7	10		T4	8

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19149

1

T2

6

T7

13

T4

10

auto[1]

11804

1

T2

4

T7

25

T4

15

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11582

1

T2

5

T7

19

T4

15

auto[1]

19371

1

T2

5

T7

19

T4

10

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16135

1

T2

7

T7

13

T4

12

disabled

14818

1

T2

3

T7

25

T4

13

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4766	1			T2	3		T7	13		T4	2
key_none	7969	1			T2	1		T7	6		T4	4
key_1024	4453	1			T2	4		T7	4		T4	2
key_512	3947	1			T7	4		T4	3		T5	52
key_384	3491	1			T2	1		T7	5		T4	5
key_256	3270	1			T7	3		T4	3		T5	54
key_128	2978	1			T2	1		T7	3		T4	6

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19328

1

T2

3

T7

20

T4

14

auto[1]

11625

1

T2

7

T7

18

T4

11

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30786

1

T2

10

T7

34

T4

25

disabled

167

1

T7

4

T5

4

T6

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1673

1

T2

1

T7

3

T4

2

enabled

auto[0]

auto[0]

auto[1]

1673

1

T2

1

T7

1

T5

29

enabled

auto[0]

auto[1]

auto[0]

1611

1

T7

1

T4

2

T5

27

enabled

auto[0]

auto[1]

auto[1]

1655

1

T2

1

T7

2

T4

3

enabled

auto[1]

auto[0]

auto[0]

4317

1

T7

2

T4

1

T5

15

enabled

auto[1]

auto[0]

auto[1]

1660

1

T2

2

T4

1

T5

34

enabled

auto[1]

auto[1]

auto[0]

1909

1

T2

2

T7

2

T4

2

enabled

auto[1]

auto[1]

auto[1]

1637

1

T7

2

T4

1

T5

21

disabled

auto[0]

auto[0]

auto[0]

1268

1

T7

2

T4

4

T5

22

disabled

auto[0]

auto[0]

auto[1]

1228

1

T2

1

T7

1

T4

1

disabled

auto[0]

auto[1]

auto[0]

1237

1

T7

1

T4

1

T5

18

disabled

auto[0]

auto[1]

auto[1]

1237

1

T2

1

T7

8

T4

2

disabled

auto[1]

auto[0]

auto[0]

6069

1

T7

2

T4

1

T5

16

disabled

auto[1]

auto[0]

auto[1]

1261

1

T2

1

T7

2

T5

25

disabled

auto[1]

auto[1]

auto[0]

1244

1

T7

7

T4

1

T5

17

disabled

auto[1]

auto[1]

auto[1]

1274

1

T7

2

T4

3

T5

22

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16067

1

T2

7

T7

12

T4

12

enabled

disabled

68

1

T7

1

T5

2

T27

1

disabled

disabled

99

1

T7

3

T5

2

T6

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14719

1

T2

3

T7

22

T4

13

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1125	1			T2	1		T7	4		T5	12
key_invalid	sha2_none	925	1			T7	1		T5	20		T8	1
key_invalid	sha2_512	870	1			T2	1		T7	1		T4	1
key_invalid	sha2_384	876	1			T2	1		T7	4		T5	21
key_invalid	sha2_256	857	1			T7	3		T4	1		T5	13
key_none	sha2_invalid	610	1			T4	1		T5	14		T8	1
key_none	sha2_none	591	1			T7	1		T5	13		T8	1
key_none	sha2_512	2535	1			T2	1		T7	2		T5	9
key_none	sha2_384	2602	1			T7	2		T4	1		T5	7
key_none	sha2_256	1578	1			T7	1		T4	2		T5	13
key_1024	sha2_invalid	521	1			T2	1		T5	11		T6	1
key_1024	sha2_none	578	1			T7	1		T4	1		T5	11
key_1024	sha2_512	1760	1			T2	1		T7	1		T4	1
key_1024	sha2_384	922	1			T2	1		T7	1		T5	7
key_512	sha2_invalid	593	1			T7	3		T4	1		T5	15
key_512	sha2_none	567	1			T4	1		T5	11		T6	3
key_512	sha2_512	594	1			T5	9		T6	4		T17	2
key_512	sha2_384	1251	1			T7	1		T4	1		T5	8
key_512	sha2_256	884	1			T5	8		T6	3		T17	1
key_384	sha2_invalid	535	1			T2	1		T5	7		T6	3
key_384	sha2_none	567	1			T5	7		T8	1		T6	3
key_384	sha2_512	636	1			T7	1		T4	2		T5	10
key_384	sha2_384	628	1			T4	1		T5	4		T8	2
key_384	sha2_256	1092	1			T7	4		T4	2		T5	8
key_256	sha2_invalid	567	1			T4	1		T5	9		T8	1
key_256	sha2_none	590	1			T7	1		T4	1		T5	9
key_256	sha2_512	637	1			T5	10		T6	2		T17	1
key_256	sha2_384	658	1			T7	2		T4	1		T5	14
key_256	sha2_256	768	1			T5	9		T8	1		T6	4
key_128	sha2_invalid	535	1			T2	1		T7	1		T4	1
key_128	sha2_none	541	1			T5	7		T8	1		T6	2
key_128	sha2_512	617	1			T7	1		T4	2		T5	7
key_128	sha2_384	614	1			T5	14		T6	7		T18	3
key_128	sha2_256	624	1			T7	1		T4	3		T5	13

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

638

1

T2

1

T7

1

T5

11

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1125	1			T2	1		T7	4		T5	12
key_invalid	sha2_none	925	1			T7	1		T5	20		T8	1
key_invalid	sha2_512	870	1			T2	1		T7	1		T4	1
key_invalid	sha2_384	876	1			T2	1		T7	4		T5	21
key_invalid	sha2_256	857	1			T7	3		T4	1		T5	13
key_none	sha2_invalid	610	1			T4	1		T5	14		T8	1
key_none	sha2_none	591	1			T7	1		T5	13		T8	1
key_none	sha2_512	2535	1			T2	1		T7	2		T5	9
key_none	sha2_384	2602	1			T7	2		T4	1		T5	7
key_none	sha2_256	1578	1			T7	1		T4	2		T5	13
key_1024	sha2_invalid	521	1			T2	1		T5	11		T6	1
key_1024	sha2_none	578	1			T7	1		T4	1		T5	11
key_1024	sha2_512	1760	1			T2	1		T7	1		T4	1
key_1024	sha2_384	922	1			T2	1		T7	1		T5	7
key_1024	sha2_256	638	1			T2	1		T7	1		T5	11
key_512	sha2_invalid	593	1			T7	3		T4	1		T5	15
key_512	sha2_none	567	1			T4	1		T5	11		T6	3
key_512	sha2_512	594	1			T5	9		T6	4		T17	2
key_512	sha2_384	1251	1			T7	1		T4	1		T5	8
key_512	sha2_256	884	1			T5	8		T6	3		T17	1
key_384	sha2_invalid	535	1			T2	1		T5	7		T6	3
key_384	sha2_none	567	1			T5	7		T8	1		T6	3
key_384	sha2_512	636	1			T7	1		T4	2		T5	10
key_384	sha2_384	628	1			T4	1		T5	4		T8	2
key_384	sha2_256	1092	1			T7	4		T4	2		T5	8
key_256	sha2_invalid	567	1			T4	1		T5	9		T8	1
key_256	sha2_none	590	1			T7	1		T4	1		T5	9
key_256	sha2_512	637	1			T5	10		T6	2		T17	1
key_256	sha2_384	658	1			T7	2		T4	1		T5	14
key_256	sha2_256	768	1			T5	9		T8	1		T6	4
key_128	sha2_invalid	535	1			T2	1		T7	1		T4	1
key_128	sha2_none	541	1			T5	7		T8	1		T6	2
key_128	sha2_512	617	1			T7	1		T4	2		T5	7
key_128	sha2_384	614	1			T5	14		T6	7		T18	3
key_128	sha2_256	624	1			T7	1		T4	3		T5	13