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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 658
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T73 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2338610229 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:01 PM PDT 24 303136419 ps
T111 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4060820251 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:53 PM PDT 24 14469498 ps
T74 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.670766699 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:50 PM PDT 24 47988743 ps
T532 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3115211404 Jul 14 06:30:53 PM PDT 24 Jul 14 06:30:56 PM PDT 24 14996875 ps
T533 /workspace/coverage/cover_reg_top/19.hmac_intr_test.909792370 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:57 PM PDT 24 27302838 ps
T534 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3021214024 Jul 14 06:30:47 PM PDT 24 Jul 14 06:30:48 PM PDT 24 124447168 ps
T112 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.231737620 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:49 PM PDT 24 21371501 ps
T113 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.44637148 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:51 PM PDT 24 150942028 ps
T99 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3077074806 Jul 14 06:30:44 PM PDT 24 Jul 14 06:31:01 PM PDT 24 1645980290 ps
T535 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1109883348 Jul 14 06:31:04 PM PDT 24 Jul 14 06:31:06 PM PDT 24 17173954 ps
T536 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.928085951 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:47 PM PDT 24 119305906 ps
T537 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2937345441 Jul 14 06:30:35 PM PDT 24 Jul 14 06:30:37 PM PDT 24 51582977 ps
T538 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3624181846 Jul 14 06:30:54 PM PDT 24 Jul 14 06:31:00 PM PDT 24 699803250 ps
T539 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3406449432 Jul 14 06:30:53 PM PDT 24 Jul 14 06:30:57 PM PDT 24 58533411 ps
T94 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3726508175 Jul 14 06:30:42 PM PDT 24 Jul 14 06:30:46 PM PDT 24 462325708 ps
T540 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2739745547 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:53 PM PDT 24 36510546 ps
T541 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2864324069 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:54 PM PDT 24 54846367 ps
T123 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2890566123 Jul 14 06:30:34 PM PDT 24 Jul 14 06:30:36 PM PDT 24 417166526 ps
T131 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3941022196 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:54 PM PDT 24 62078343 ps
T114 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2903160517 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:54 PM PDT 24 23180226 ps
T542 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2125862407 Jul 14 06:30:36 PM PDT 24 Jul 14 06:30:41 PM PDT 24 3052195529 ps
T543 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2713810884 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:45 PM PDT 24 100432723 ps
T115 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2455513689 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:55 PM PDT 24 311098404 ps
T544 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.63202008 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:50 PM PDT 24 206339750 ps
T95 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2174062671 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:49 PM PDT 24 59780659 ps
T545 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3508405467 Jul 14 06:30:44 PM PDT 24 Jul 14 06:30:48 PM PDT 24 177309569 ps
T116 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3776012651 Jul 14 06:30:56 PM PDT 24 Jul 14 06:30:59 PM PDT 24 24705149 ps
T127 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2394550117 Jul 14 06:30:35 PM PDT 24 Jul 14 06:30:37 PM PDT 24 687911833 ps
T546 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1632521108 Jul 14 06:30:55 PM PDT 24 Jul 14 06:30:59 PM PDT 24 68435088 ps
T117 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1273591959 Jul 14 06:30:43 PM PDT 24 Jul 14 06:30:45 PM PDT 24 134379669 ps
T118 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4000681149 Jul 14 06:30:47 PM PDT 24 Jul 14 06:30:49 PM PDT 24 342723409 ps
T119 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3979768526 Jul 14 06:30:50 PM PDT 24 Jul 14 06:30:52 PM PDT 24 18786347 ps
T547 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1981082441 Jul 14 06:30:54 PM PDT 24 Jul 14 06:31:01 PM PDT 24 688807384 ps
T96 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.520062350 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:53 PM PDT 24 118726359 ps
T548 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3478677864 Jul 14 06:30:50 PM PDT 24 Jul 14 06:30:54 PM PDT 24 60245900 ps
T124 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2468955588 Jul 14 06:30:46 PM PDT 24 Jul 14 06:30:48 PM PDT 24 92302025 ps
T549 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1990963163 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:54 PM PDT 24 21901357 ps
T550 /workspace/coverage/cover_reg_top/12.hmac_intr_test.4062997165 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:53 PM PDT 24 16097292 ps
T551 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2853296594 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:51 PM PDT 24 69110641 ps
T552 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3652163211 Jul 14 06:30:49 PM PDT 24 Jul 14 06:30:52 PM PDT 24 66054304 ps
T97 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3086939600 Jul 14 06:30:44 PM PDT 24 Jul 14 06:30:45 PM PDT 24 57425370 ps
T553 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2875553936 Jul 14 06:30:59 PM PDT 24 Jul 14 06:31:01 PM PDT 24 25187965 ps
T554 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1967414950 Jul 14 06:31:00 PM PDT 24 Jul 14 06:31:04 PM PDT 24 100568408 ps
T129 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.349061178 Jul 14 06:30:50 PM PDT 24 Jul 14 06:30:53 PM PDT 24 177985147 ps
T555 /workspace/coverage/cover_reg_top/17.hmac_intr_test.389124019 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:57 PM PDT 24 11741793 ps
T556 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2896022474 Jul 14 06:30:38 PM PDT 24 Jul 14 06:30:39 PM PDT 24 12079872 ps
T557 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3722131523 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:01 PM PDT 24 330868217 ps
T98 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2687806693 Jul 14 06:30:46 PM PDT 24 Jul 14 06:30:47 PM PDT 24 15489880 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2395329601 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:43 PM PDT 24 23340839 ps
T558 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.814969648 Jul 14 06:30:49 PM PDT 24 Jul 14 06:30:52 PM PDT 24 361601708 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1476672504 Jul 14 06:30:47 PM PDT 24 Jul 14 06:34:42 PM PDT 24 100581844613 ps
T560 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.648225542 Jul 14 06:30:42 PM PDT 24 Jul 14 06:30:47 PM PDT 24 108742182 ps
T126 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1553618409 Jul 14 06:30:42 PM PDT 24 Jul 14 06:30:48 PM PDT 24 1021310471 ps
T130 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2038351739 Jul 14 06:31:02 PM PDT 24 Jul 14 06:31:05 PM PDT 24 195396369 ps
T561 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2005759758 Jul 14 06:30:36 PM PDT 24 Jul 14 06:30:38 PM PDT 24 52489914 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3816368808 Jul 14 06:30:34 PM PDT 24 Jul 14 06:30:36 PM PDT 24 69540034 ps
T563 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3989360432 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:01 PM PDT 24 19249066 ps
T564 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.20829899 Jul 14 06:30:46 PM PDT 24 Jul 14 06:33:31 PM PDT 24 45313336437 ps
T565 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.569255053 Jul 14 06:30:34 PM PDT 24 Jul 14 06:30:39 PM PDT 24 282025860 ps
T128 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3858072339 Jul 14 06:30:47 PM PDT 24 Jul 14 06:30:52 PM PDT 24 263101672 ps
T566 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.78919230 Jul 14 06:30:45 PM PDT 24 Jul 14 06:30:49 PM PDT 24 244397289 ps
T567 /workspace/coverage/cover_reg_top/16.hmac_intr_test.420239002 Jul 14 06:30:55 PM PDT 24 Jul 14 06:30:58 PM PDT 24 14590732 ps
T568 /workspace/coverage/cover_reg_top/33.hmac_intr_test.30731144 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:00 PM PDT 24 23659686 ps
T569 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1626008335 Jul 14 06:31:02 PM PDT 24 Jul 14 06:31:06 PM PDT 24 322631957 ps
T570 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2473329488 Jul 14 06:30:39 PM PDT 24 Jul 14 06:30:42 PM PDT 24 111570376 ps
T571 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3408664459 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:57 PM PDT 24 51526806 ps
T572 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2426330206 Jul 14 06:30:35 PM PDT 24 Jul 14 06:30:36 PM PDT 24 42485030 ps
T573 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2081844674 Jul 14 06:30:49 PM PDT 24 Jul 14 06:30:52 PM PDT 24 85119506 ps
T574 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3295064349 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:55 PM PDT 24 44292356 ps
T575 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2411430575 Jul 14 06:30:38 PM PDT 24 Jul 14 06:49:03 PM PDT 24 181499953386 ps
T576 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.174164704 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:44 PM PDT 24 1002597543 ps
T577 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3955140130 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:50 PM PDT 24 38250993 ps
T578 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1271436742 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:46 PM PDT 24 146590301 ps
T579 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2952554263 Jul 14 06:30:42 PM PDT 24 Jul 14 06:30:44 PM PDT 24 36723601 ps
T580 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3900619453 Jul 14 06:31:01 PM PDT 24 Jul 14 06:31:04 PM PDT 24 14686127 ps
T581 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3092211780 Jul 14 06:31:03 PM PDT 24 Jul 14 06:31:05 PM PDT 24 13816589 ps
T582 /workspace/coverage/cover_reg_top/43.hmac_intr_test.546149749 Jul 14 06:30:59 PM PDT 24 Jul 14 06:31:02 PM PDT 24 56264898 ps
T583 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4120696099 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:44 PM PDT 24 130982016 ps
T584 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.224593552 Jul 14 06:30:53 PM PDT 24 Jul 14 06:30:59 PM PDT 24 190792435 ps
T585 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1719375886 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:01 PM PDT 24 16415912 ps
T586 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4035086415 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:42 PM PDT 24 84941332 ps
T587 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3045217143 Jul 14 06:31:00 PM PDT 24 Jul 14 06:31:03 PM PDT 24 39483592 ps
T588 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2099690159 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:00 PM PDT 24 22320010 ps
T589 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1915265153 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:43 PM PDT 24 31728248 ps
T590 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4020468990 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:42 PM PDT 24 39754881 ps
T100 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.354057981 Jul 14 06:30:36 PM PDT 24 Jul 14 06:30:37 PM PDT 24 25524426 ps
T591 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2389487644 Jul 14 06:30:59 PM PDT 24 Jul 14 06:31:02 PM PDT 24 34486225 ps
T592 /workspace/coverage/cover_reg_top/39.hmac_intr_test.788360916 Jul 14 06:30:57 PM PDT 24 Jul 14 06:30:59 PM PDT 24 59320175 ps
T125 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.158506963 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:01 PM PDT 24 154009763 ps
T593 /workspace/coverage/cover_reg_top/48.hmac_intr_test.729323372 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:01 PM PDT 24 22644334 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.855746424 Jul 14 06:30:35 PM PDT 24 Jul 14 06:30:36 PM PDT 24 31466937 ps
T594 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1974878067 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:44 PM PDT 24 173249021 ps
T595 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.906067297 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:00 PM PDT 24 38361787 ps
T596 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.346948313 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:56 PM PDT 24 75126227 ps
T597 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1720593225 Jul 14 06:30:39 PM PDT 24 Jul 14 06:30:41 PM PDT 24 233244825 ps
T598 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1560865764 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:58 PM PDT 24 628155152 ps
T599 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.950340581 Jul 14 06:30:50 PM PDT 24 Jul 14 06:30:51 PM PDT 24 37424483 ps
T121 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2163053461 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:45 PM PDT 24 185536216 ps
T600 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.524346261 Jul 14 06:30:37 PM PDT 24 Jul 14 06:30:54 PM PDT 24 13057207531 ps
T601 /workspace/coverage/cover_reg_top/10.hmac_intr_test.259050374 Jul 14 06:30:46 PM PDT 24 Jul 14 06:30:47 PM PDT 24 14411976 ps
T602 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3526571276 Jul 14 06:31:02 PM PDT 24 Jul 14 06:31:04 PM PDT 24 33974150 ps
T603 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2313944497 Jul 14 06:30:37 PM PDT 24 Jul 14 06:30:39 PM PDT 24 69844587 ps
T604 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.400423805 Jul 14 06:30:48 PM PDT 24 Jul 14 06:30:50 PM PDT 24 49545236 ps
T605 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4037812162 Jul 14 06:30:55 PM PDT 24 Jul 14 06:30:58 PM PDT 24 72959125 ps
T606 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3937551567 Jul 14 06:30:34 PM PDT 24 Jul 14 06:30:46 PM PDT 24 961902115 ps
T607 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.186069597 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:01 PM PDT 24 658972544 ps
T608 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.7444321 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:57 PM PDT 24 236044307 ps
T609 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4160133753 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:43 PM PDT 24 173761277 ps
T610 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2688701043 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:57 PM PDT 24 45677560 ps
T122 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4064965916 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:01 PM PDT 24 261718344 ps
T611 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3012985521 Jul 14 06:30:55 PM PDT 24 Jul 14 06:30:58 PM PDT 24 34919742 ps
T612 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4177543601 Jul 14 06:31:00 PM PDT 24 Jul 14 06:31:03 PM PDT 24 13597169 ps
T613 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2790741059 Jul 14 06:30:54 PM PDT 24 Jul 14 06:31:00 PM PDT 24 196533665 ps
T614 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.172718388 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:51 PM PDT 24 532250840 ps
T615 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1853047391 Jul 14 06:30:42 PM PDT 24 Jul 14 06:30:46 PM PDT 24 168120067 ps
T616 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1294594315 Jul 14 06:30:39 PM PDT 24 Jul 14 06:30:40 PM PDT 24 17591648 ps
T617 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3693103220 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:45 PM PDT 24 177369244 ps
T618 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1556204813 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:57 PM PDT 24 123769733 ps
T619 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2882361186 Jul 14 06:30:57 PM PDT 24 Jul 14 06:30:59 PM PDT 24 54777255 ps
T620 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1717323596 Jul 14 06:31:00 PM PDT 24 Jul 14 06:31:03 PM PDT 24 11303390 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3868959760 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:59 PM PDT 24 198929271 ps
T622 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3203070093 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:42 PM PDT 24 15729369 ps
T623 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1361832299 Jul 14 06:30:58 PM PDT 24 Jul 14 06:30:59 PM PDT 24 31912864 ps
T624 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1629016124 Jul 14 06:31:05 PM PDT 24 Jul 14 06:31:08 PM PDT 24 21595531 ps
T625 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3821888987 Jul 14 06:31:02 PM PDT 24 Jul 14 06:31:04 PM PDT 24 42611182 ps
T626 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3582082884 Jul 14 06:30:58 PM PDT 24 Jul 14 06:31:00 PM PDT 24 278282429 ps
T627 /workspace/coverage/cover_reg_top/11.hmac_intr_test.225749260 Jul 14 06:30:47 PM PDT 24 Jul 14 06:30:48 PM PDT 24 43159352 ps
T628 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2900582105 Jul 14 06:30:39 PM PDT 24 Jul 14 06:30:46 PM PDT 24 2121392167 ps
T629 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3290631221 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:42 PM PDT 24 16701672 ps
T630 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2930015991 Jul 14 06:30:59 PM PDT 24 Jul 14 06:31:01 PM PDT 24 17818199 ps
T631 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3098565872 Jul 14 06:31:04 PM PDT 24 Jul 14 06:31:06 PM PDT 24 29350593 ps
T632 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1791558597 Jul 14 06:30:54 PM PDT 24 Jul 14 06:30:59 PM PDT 24 88017904 ps
T633 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3642211987 Jul 14 06:30:38 PM PDT 24 Jul 14 06:30:43 PM PDT 24 435475013 ps
T634 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.421705033 Jul 14 06:30:37 PM PDT 24 Jul 14 06:30:40 PM PDT 24 157502555 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1482486608 Jul 14 06:30:42 PM PDT 24 Jul 14 06:30:45 PM PDT 24 44926490 ps
T636 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.301777619 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:02 PM PDT 24 240711042 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.68869332 Jul 14 06:30:39 PM PDT 24 Jul 14 06:30:43 PM PDT 24 195847854 ps
T638 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1394808605 Jul 14 06:30:59 PM PDT 24 Jul 14 06:31:01 PM PDT 24 14986618 ps
T639 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3490610073 Jul 14 06:31:02 PM PDT 24 Jul 14 06:31:06 PM PDT 24 161365566 ps
T640 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3865912527 Jul 14 06:31:01 PM PDT 24 Jul 14 06:31:04 PM PDT 24 14057071 ps
T641 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1274969843 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:53 PM PDT 24 113194233 ps
T642 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2275415708 Jul 14 06:30:41 PM PDT 24 Jul 14 06:30:43 PM PDT 24 14012213 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2975048375 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:42 PM PDT 24 82594633 ps
T644 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.214804502 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:45 PM PDT 24 51654528 ps
T645 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1319377978 Jul 14 06:30:55 PM PDT 24 Jul 14 06:31:00 PM PDT 24 191412713 ps
T646 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1831553027 Jul 14 06:30:55 PM PDT 24 Jul 14 06:30:59 PM PDT 24 94244583 ps
T647 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3268635620 Jul 14 06:30:59 PM PDT 24 Jul 14 06:31:02 PM PDT 24 23599584 ps
T648 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3349598699 Jul 14 06:30:53 PM PDT 24 Jul 14 06:30:56 PM PDT 24 18803424 ps
T649 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3462974647 Jul 14 06:30:34 PM PDT 24 Jul 14 06:30:40 PM PDT 24 118635580 ps
T650 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1247078490 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:54 PM PDT 24 15470443 ps
T651 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2185524411 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:56 PM PDT 24 199753428 ps
T652 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1188450776 Jul 14 06:30:51 PM PDT 24 Jul 14 06:30:54 PM PDT 24 601964059 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1807771819 Jul 14 06:30:45 PM PDT 24 Jul 14 06:30:46 PM PDT 24 205535278 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1957134710 Jul 14 06:30:55 PM PDT 24 Jul 14 06:30:58 PM PDT 24 30248390 ps
T655 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1845113420 Jul 14 06:30:40 PM PDT 24 Jul 14 06:30:44 PM PDT 24 157973027 ps
T656 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3898653464 Jul 14 06:31:00 PM PDT 24 Jul 14 06:31:03 PM PDT 24 26343264 ps
T657 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.15271300 Jul 14 06:30:43 PM PDT 24 Jul 14 06:31:30 PM PDT 24 8682506994 ps
T658 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1474103570 Jul 14 06:30:52 PM PDT 24 Jul 14 06:30:54 PM PDT 24 39733751 ps

Test location /workspace/coverage/default/40.hmac_stress_all.3011121937
Short name T6
Test name
Test status
Simulation time 7903157702 ps
CPU time 563.07 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:41:54 PM PDT 24
Peak memory 576224 kb
Host smart-c6f98ea9-4fcc-4923-bbe2-71295c753997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011121937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3011121937
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.4138656805
Short name T9
Test name
Test status
Simulation time 352622555723 ps
CPU time 1367.11 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 693408 kb
Host smart-57441f83-462e-4941-a11c-524e7e0f1870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138656805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.4138656805
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3086298021
Short name T23
Test name
Test status
Simulation time 30736070278 ps
CPU time 1194.36 seconds
Started Jul 14 06:31:29 PM PDT 24
Finished Jul 14 06:51:25 PM PDT 24
Peak memory 743132 kb
Host smart-8d2f59b1-e68e-4391-bcd5-eac688394dfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086298021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3086298021
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1438322095
Short name T25
Test name
Test status
Simulation time 41429272424 ps
CPU time 2681.41 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 07:15:48 PM PDT 24
Peak memory 726516 kb
Host smart-49e66897-cb2a-48a3-b25c-2796e1988497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438322095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1438322095
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2875474434
Short name T72
Test name
Test status
Simulation time 588981797 ps
CPU time 4.31 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 200248 kb
Host smart-41798287-eca4-4deb-842a-db33b6bb85ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875474434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2875474434
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2605033260
Short name T5
Test name
Test status
Simulation time 256423464191 ps
CPU time 1721.72 seconds
Started Jul 14 06:32:04 PM PDT 24
Finished Jul 14 07:00:46 PM PDT 24
Peak memory 680564 kb
Host smart-22a1cb1b-fc1b-40a6-a9b9-d591c919ab1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605033260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2605033260
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2470265472
Short name T59
Test name
Test status
Simulation time 84896646 ps
CPU time 0.96 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 06:31:20 PM PDT 24
Peak memory 218392 kb
Host smart-70917ac1-b62b-48aa-a36b-abf622e54933
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470265472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2470265472
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3494051309
Short name T32
Test name
Test status
Simulation time 795662357 ps
CPU time 47.04 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:32:03 PM PDT 24
Peak memory 200196 kb
Host smart-46b70ab0-676c-4ee1-84ba-285e3067b0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494051309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3494051309
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2074525645
Short name T58
Test name
Test status
Simulation time 436989761012 ps
CPU time 629.9 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 06:41:50 PM PDT 24
Peak memory 697508 kb
Host smart-58a70559-112c-402e-93eb-2df6d7a707d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074525645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2074525645
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3390353906
Short name T146
Test name
Test status
Simulation time 30894158046 ps
CPU time 1095.68 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:49:33 PM PDT 24
Peak memory 642684 kb
Host smart-8794b4aa-a5c6-4d78-9a5e-9bdfcd2ce850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390353906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3390353906
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1553618409
Short name T126
Test name
Test status
Simulation time 1021310471 ps
CPU time 4.36 seconds
Started Jul 14 06:30:42 PM PDT 24
Finished Jul 14 06:30:48 PM PDT 24
Peak memory 200300 kb
Host smart-1a7cd308-b35e-4252-9f5c-6fbb0652d496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553618409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1553618409
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2174062671
Short name T95
Test name
Test status
Simulation time 59780659 ps
CPU time 0.92 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:49 PM PDT 24
Peak memory 200148 kb
Host smart-23c997e0-aa9a-4f71-a271-818043d3912c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174062671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2174062671
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1191301081
Short name T199
Test name
Test status
Simulation time 21533326 ps
CPU time 0.57 seconds
Started Jul 14 06:31:41 PM PDT 24
Finished Jul 14 06:31:44 PM PDT 24
Peak memory 195152 kb
Host smart-8a440f6f-df0f-45c9-9b28-5f5f0f4a5097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191301081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1191301081
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2196280604
Short name T53
Test name
Test status
Simulation time 7276170109 ps
CPU time 115.58 seconds
Started Jul 14 06:32:03 PM PDT 24
Finished Jul 14 06:33:59 PM PDT 24
Peak memory 208616 kb
Host smart-0bf05b16-f377-4631-8412-c7b62dd46f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196280604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2196280604
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1378855010
Short name T223
Test name
Test status
Simulation time 60560127220 ps
CPU time 755.5 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:43:46 PM PDT 24
Peak memory 200264 kb
Host smart-8074b105-c148-4cf3-bcfe-412c654b4554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1378855010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1378855010
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2055601361
Short name T15
Test name
Test status
Simulation time 289088018134 ps
CPU time 1356.16 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:53:43 PM PDT 24
Peak memory 602696 kb
Host smart-ee68391c-c671-4b12-805d-6b8d133c127e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055601361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2055601361
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3462974647
Short name T649
Test name
Test status
Simulation time 118635580 ps
CPU time 5.47 seconds
Started Jul 14 06:30:34 PM PDT 24
Finished Jul 14 06:30:40 PM PDT 24
Peak memory 200096 kb
Host smart-5739c3f3-a16e-4f93-886a-dc88e33277a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462974647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3462974647
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3937551567
Short name T606
Test name
Test status
Simulation time 961902115 ps
CPU time 11.49 seconds
Started Jul 14 06:30:34 PM PDT 24
Finished Jul 14 06:30:46 PM PDT 24
Peak memory 200296 kb
Host smart-8bc34aea-2f43-4e7e-a9ec-486a82805637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937551567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3937551567
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3816368808
Short name T562
Test name
Test status
Simulation time 69540034 ps
CPU time 0.99 seconds
Started Jul 14 06:30:34 PM PDT 24
Finished Jul 14 06:30:36 PM PDT 24
Peak memory 200128 kb
Host smart-d9c02dc2-3768-4774-8652-ca51f11178a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816368808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3816368808
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2411430575
Short name T575
Test name
Test status
Simulation time 181499953386 ps
CPU time 1104.21 seconds
Started Jul 14 06:30:38 PM PDT 24
Finished Jul 14 06:49:03 PM PDT 24
Peak memory 224960 kb
Host smart-dc05693c-a895-46e2-9672-497c349fed70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411430575 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2411430575
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.855746424
Short name T101
Test name
Test status
Simulation time 31466937 ps
CPU time 0.8 seconds
Started Jul 14 06:30:35 PM PDT 24
Finished Jul 14 06:30:36 PM PDT 24
Peak memory 199908 kb
Host smart-da9ea1f5-477f-4443-8d2f-02e7c997e4e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855746424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.855746424
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3030350771
Short name T528
Test name
Test status
Simulation time 119487391 ps
CPU time 0.61 seconds
Started Jul 14 06:30:33 PM PDT 24
Finished Jul 14 06:30:34 PM PDT 24
Peak memory 195264 kb
Host smart-d003e284-f02c-4068-a05c-842dc1bc4222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030350771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3030350771
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2313944497
Short name T603
Test name
Test status
Simulation time 69844587 ps
CPU time 1.1 seconds
Started Jul 14 06:30:37 PM PDT 24
Finished Jul 14 06:30:39 PM PDT 24
Peak memory 200260 kb
Host smart-a0f770ad-c269-4083-a648-e4b791c55dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313944497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2313944497
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2125862407
Short name T542
Test name
Test status
Simulation time 3052195529 ps
CPU time 3.62 seconds
Started Jul 14 06:30:36 PM PDT 24
Finished Jul 14 06:30:41 PM PDT 24
Peak memory 200356 kb
Host smart-2850fd2a-8b0e-4f05-88ce-450ec524e3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125862407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2125862407
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3642211987
Short name T633
Test name
Test status
Simulation time 435475013 ps
CPU time 4.56 seconds
Started Jul 14 06:30:38 PM PDT 24
Finished Jul 14 06:30:43 PM PDT 24
Peak memory 200264 kb
Host smart-bb97500b-f475-45cb-b2f7-c9b74098364b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642211987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3642211987
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3138337110
Short name T92
Test name
Test status
Simulation time 698403892 ps
CPU time 3.17 seconds
Started Jul 14 06:30:35 PM PDT 24
Finished Jul 14 06:30:39 PM PDT 24
Peak memory 199260 kb
Host smart-15486eda-a76c-4283-af03-4b95192f537e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138337110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3138337110
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.524346261
Short name T600
Test name
Test status
Simulation time 13057207531 ps
CPU time 16.4 seconds
Started Jul 14 06:30:37 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 199776 kb
Host smart-28f02cc6-19ea-4a89-bae3-59bc73be87dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524346261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.524346261
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1919403398
Short name T93
Test name
Test status
Simulation time 41931699 ps
CPU time 1.06 seconds
Started Jul 14 06:30:36 PM PDT 24
Finished Jul 14 06:30:38 PM PDT 24
Peak memory 199780 kb
Host smart-ccb89eba-8c95-40fb-89ac-eadf7dd2df72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919403398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1919403398
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1720593225
Short name T597
Test name
Test status
Simulation time 233244825 ps
CPU time 1.31 seconds
Started Jul 14 06:30:39 PM PDT 24
Finished Jul 14 06:30:41 PM PDT 24
Peak memory 200368 kb
Host smart-c2223ddb-48ce-4fae-bc5f-50721deff1dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720593225 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1720593225
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2005759758
Short name T561
Test name
Test status
Simulation time 52489914 ps
CPU time 0.95 seconds
Started Jul 14 06:30:36 PM PDT 24
Finished Jul 14 06:30:38 PM PDT 24
Peak memory 200088 kb
Host smart-26d0489e-82d9-4d28-ac82-7e7ac87ebf49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005759758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2005759758
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1294594315
Short name T616
Test name
Test status
Simulation time 17591648 ps
CPU time 0.59 seconds
Started Jul 14 06:30:39 PM PDT 24
Finished Jul 14 06:30:40 PM PDT 24
Peak memory 195280 kb
Host smart-d920b476-3f25-4aa6-b228-d1360567185f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294594315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1294594315
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.421705033
Short name T634
Test name
Test status
Simulation time 157502555 ps
CPU time 1.9 seconds
Started Jul 14 06:30:37 PM PDT 24
Finished Jul 14 06:30:40 PM PDT 24
Peak memory 200360 kb
Host smart-e52ffcfc-c7ab-4e83-9d69-7368aa915e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421705033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.421705033
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2937345441
Short name T537
Test name
Test status
Simulation time 51582977 ps
CPU time 1.37 seconds
Started Jul 14 06:30:35 PM PDT 24
Finished Jul 14 06:30:37 PM PDT 24
Peak memory 200248 kb
Host smart-4d29e3fe-cb91-44f9-bb63-7804168ebbde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937345441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2937345441
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2890566123
Short name T123
Test name
Test status
Simulation time 417166526 ps
CPU time 1.96 seconds
Started Jul 14 06:30:34 PM PDT 24
Finished Jul 14 06:30:36 PM PDT 24
Peak memory 200356 kb
Host smart-05a38e32-5f11-4d07-ae08-d7cc2f24d936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890566123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2890566123
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.400423805
Short name T604
Test name
Test status
Simulation time 49545236 ps
CPU time 1.67 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:50 PM PDT 24
Peak memory 200276 kb
Host smart-509eab76-7540-489e-bc52-031f924d61e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400423805 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.400423805
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2687806693
Short name T98
Test name
Test status
Simulation time 15489880 ps
CPU time 0.71 seconds
Started Jul 14 06:30:46 PM PDT 24
Finished Jul 14 06:30:47 PM PDT 24
Peak memory 198248 kb
Host smart-13fc2449-ca77-4845-a415-38f919c8ad7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687806693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2687806693
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.259050374
Short name T601
Test name
Test status
Simulation time 14411976 ps
CPU time 0.61 seconds
Started Jul 14 06:30:46 PM PDT 24
Finished Jul 14 06:30:47 PM PDT 24
Peak memory 195192 kb
Host smart-4b9d67ee-4b56-4131-b40f-5b681837d0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259050374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.259050374
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3955140130
Short name T577
Test name
Test status
Simulation time 38250993 ps
CPU time 1.68 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:50 PM PDT 24
Peak memory 199412 kb
Host smart-68113650-7cb8-4cb8-b127-8e87ff833af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955140130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3955140130
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3478677864
Short name T548
Test name
Test status
Simulation time 60245900 ps
CPU time 3.3 seconds
Started Jul 14 06:30:50 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 200264 kb
Host smart-45d2a810-798f-4576-a55c-c9624d4c2414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478677864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3478677864
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2468955588
Short name T124
Test name
Test status
Simulation time 92302025 ps
CPU time 1.79 seconds
Started Jul 14 06:30:46 PM PDT 24
Finished Jul 14 06:30:48 PM PDT 24
Peak memory 200300 kb
Host smart-a3efb88c-2320-4a3e-9018-5b1c99c9c57e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468955588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2468955588
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.814969648
Short name T558
Test name
Test status
Simulation time 361601708 ps
CPU time 2.71 seconds
Started Jul 14 06:30:49 PM PDT 24
Finished Jul 14 06:30:52 PM PDT 24
Peak memory 200344 kb
Host smart-3102b52c-bb1e-4a97-a214-6584a4e13a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814969648 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.814969648
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.231737620
Short name T112
Test name
Test status
Simulation time 21371501 ps
CPU time 0.71 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:49 PM PDT 24
Peak memory 198124 kb
Host smart-bd34d0c4-5237-4a0e-b438-eaead9661aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231737620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.231737620
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.225749260
Short name T627
Test name
Test status
Simulation time 43159352 ps
CPU time 0.62 seconds
Started Jul 14 06:30:47 PM PDT 24
Finished Jul 14 06:30:48 PM PDT 24
Peak memory 195228 kb
Host smart-079a1d11-4396-49f1-9ac1-9d5cd2c7aa1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225749260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.225749260
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4000681149
Short name T118
Test name
Test status
Simulation time 342723409 ps
CPU time 2.07 seconds
Started Jul 14 06:30:47 PM PDT 24
Finished Jul 14 06:30:49 PM PDT 24
Peak memory 200376 kb
Host smart-d026e5eb-5206-48a4-a5a5-db30721fa719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000681149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4000681149
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.78919230
Short name T566
Test name
Test status
Simulation time 244397289 ps
CPU time 3.39 seconds
Started Jul 14 06:30:45 PM PDT 24
Finished Jul 14 06:30:49 PM PDT 24
Peak memory 200296 kb
Host smart-e388d15e-603a-43bc-829d-cd6960800491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78919230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.78919230
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.349061178
Short name T129
Test name
Test status
Simulation time 177985147 ps
CPU time 3.11 seconds
Started Jul 14 06:30:50 PM PDT 24
Finished Jul 14 06:30:53 PM PDT 24
Peak memory 200260 kb
Host smart-782a5b7b-da6d-4072-805b-7e66ea253d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349061178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.349061178
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.20829899
Short name T564
Test name
Test status
Simulation time 45313336437 ps
CPU time 164.51 seconds
Started Jul 14 06:30:46 PM PDT 24
Finished Jul 14 06:33:31 PM PDT 24
Peak memory 216828 kb
Host smart-0e0622b9-7dcf-4282-9ace-444866254021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20829899 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.20829899
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.63202008
Short name T544
Test name
Test status
Simulation time 206339750 ps
CPU time 0.82 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:50 PM PDT 24
Peak memory 199832 kb
Host smart-bcded786-161d-44d1-828f-d1edd528c9b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63202008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.63202008
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.4062997165
Short name T550
Test name
Test status
Simulation time 16097292 ps
CPU time 0.57 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:53 PM PDT 24
Peak memory 195188 kb
Host smart-4960c069-fc34-4a4b-84bd-8565ba3d6250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062997165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.4062997165
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1274969843
Short name T641
Test name
Test status
Simulation time 113194233 ps
CPU time 1.14 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:53 PM PDT 24
Peak memory 199920 kb
Host smart-8d68936c-a625-43ef-9ed3-a134549d9869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274969843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1274969843
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1188450776
Short name T652
Test name
Test status
Simulation time 601964059 ps
CPU time 1.83 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 200164 kb
Host smart-76eed9eb-70df-4ed8-8ea7-2990e373a12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188450776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1188450776
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1990963163
Short name T549
Test name
Test status
Simulation time 21901357 ps
CPU time 1.37 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 200380 kb
Host smart-ef60a17c-574a-4840-a69e-622857240d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990963163 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1990963163
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1556204813
Short name T618
Test name
Test status
Simulation time 123769733 ps
CPU time 0.93 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 199704 kb
Host smart-af7b935a-4653-4271-a3cf-e0a7329e20af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556204813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1556204813
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2864324069
Short name T541
Test name
Test status
Simulation time 54846367 ps
CPU time 0.65 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 195224 kb
Host smart-96199e76-8b84-4f66-b57b-6d374a0e920c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864324069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2864324069
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3295064349
Short name T574
Test name
Test status
Simulation time 44292356 ps
CPU time 2.02 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:55 PM PDT 24
Peak memory 200328 kb
Host smart-b4f858d9-b1a0-4da7-8fdc-6edc68cd43f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295064349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3295064349
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.301777619
Short name T636
Test name
Test status
Simulation time 240711042 ps
CPU time 4.5 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:02 PM PDT 24
Peak memory 200308 kb
Host smart-31f3c243-7b95-47e7-9006-93f798d25262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301777619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.301777619
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4064965916
Short name T122
Test name
Test status
Simulation time 261718344 ps
CPU time 4.1 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200336 kb
Host smart-cf813267-2050-40ea-a623-5dbff8264540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064965916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4064965916
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.906067297
Short name T595
Test name
Test status
Simulation time 38361787 ps
CPU time 2.4 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 208568 kb
Host smart-f2bf71d4-a6cc-476b-9141-bbc3a898de37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906067297 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.906067297
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3408664459
Short name T571
Test name
Test status
Simulation time 51526806 ps
CPU time 0.82 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 199528 kb
Host smart-89c5374b-edde-4031-ab47-7a7e0b19cb80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408664459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3408664459
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1474103570
Short name T658
Test name
Test status
Simulation time 39733751 ps
CPU time 0.61 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 195280 kb
Host smart-bb2ce257-aa1a-4e1a-88cc-6a0e779ff41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474103570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1474103570
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1560865764
Short name T598
Test name
Test status
Simulation time 628155152 ps
CPU time 1.24 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:58 PM PDT 24
Peak memory 198796 kb
Host smart-ed16a95e-96f2-4cc3-aaba-fd15c0f8cf41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560865764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1560865764
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.346948313
Short name T596
Test name
Test status
Simulation time 75126227 ps
CPU time 3.9 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:56 PM PDT 24
Peak memory 200328 kb
Host smart-ded66b3a-ee19-4c41-b081-cc11d67674c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346948313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.346948313
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3941022196
Short name T131
Test name
Test status
Simulation time 62078343 ps
CPU time 1.71 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 200328 kb
Host smart-bdc27068-7ab9-421b-8f41-3d142d7a6368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941022196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3941022196
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1319377978
Short name T645
Test name
Test status
Simulation time 191412713 ps
CPU time 2.11 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 200344 kb
Host smart-c5862c69-8274-4776-9143-8d2a8a987e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319377978 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1319377978
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2688701043
Short name T610
Test name
Test status
Simulation time 45677560 ps
CPU time 0.7 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 197880 kb
Host smart-088f8511-c129-435a-af34-d9a5944cdaee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688701043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2688701043
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3526571276
Short name T602
Test name
Test status
Simulation time 33974150 ps
CPU time 0.61 seconds
Started Jul 14 06:31:02 PM PDT 24
Finished Jul 14 06:31:04 PM PDT 24
Peak memory 195268 kb
Host smart-16447014-0a9d-48d5-acde-905fa42e01d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526571276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3526571276
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3776012651
Short name T116
Test name
Test status
Simulation time 24705149 ps
CPU time 1.06 seconds
Started Jul 14 06:30:56 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 198840 kb
Host smart-2fa76df5-9a19-45d1-862e-d3473fe8d976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776012651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3776012651
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.186069597
Short name T607
Test name
Test status
Simulation time 658972544 ps
CPU time 3.65 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200312 kb
Host smart-13a6186f-cb44-4572-8d2e-b8cef745db04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186069597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.186069597
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2790741059
Short name T613
Test name
Test status
Simulation time 196533665 ps
CPU time 3.21 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 200352 kb
Host smart-0cb3383e-fef6-45fa-a580-0500102560b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790741059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2790741059
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1632521108
Short name T546
Test name
Test status
Simulation time 68435088 ps
CPU time 1.85 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 200276 kb
Host smart-dac98c72-d424-4c4a-a779-801b70d73ac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632521108 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1632521108
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1831553027
Short name T646
Test name
Test status
Simulation time 94244583 ps
CPU time 0.8 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 199952 kb
Host smart-b18d832c-1412-462a-af4c-19f9a4fbd0fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831553027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1831553027
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.420239002
Short name T567
Test name
Test status
Simulation time 14590732 ps
CPU time 0.62 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:30:58 PM PDT 24
Peak memory 195212 kb
Host smart-fbd1f938-c52f-425d-9962-cd0630a260bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420239002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.420239002
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3582082884
Short name T626
Test name
Test status
Simulation time 278282429 ps
CPU time 1.28 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 200008 kb
Host smart-5f47d38c-b753-48f0-9fe8-13dcf6d8ca14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582082884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3582082884
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3406449432
Short name T539
Test name
Test status
Simulation time 58533411 ps
CPU time 1.64 seconds
Started Jul 14 06:30:53 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 200320 kb
Host smart-a4f287f8-da7a-4dbd-a14e-2a04271e6d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406449432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3406449432
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2338610229
Short name T73
Test name
Test status
Simulation time 303136419 ps
CPU time 3.12 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200340 kb
Host smart-4a97d461-025c-4146-b90c-07ca1af09422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338610229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2338610229
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3722131523
Short name T557
Test name
Test status
Simulation time 330868217 ps
CPU time 2.36 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200408 kb
Host smart-fe1b4f06-d11f-4494-ae2a-c5364ea17b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722131523 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3722131523
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3012985521
Short name T611
Test name
Test status
Simulation time 34919742 ps
CPU time 0.76 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:30:58 PM PDT 24
Peak memory 198440 kb
Host smart-25d914a0-5d3b-408f-9129-a7ccbea4d6a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012985521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3012985521
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.389124019
Short name T555
Test name
Test status
Simulation time 11741793 ps
CPU time 0.57 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 195320 kb
Host smart-abdac934-81a6-49ac-ab63-6f4b279985ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389124019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.389124019
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3490610073
Short name T639
Test name
Test status
Simulation time 161365566 ps
CPU time 2 seconds
Started Jul 14 06:31:02 PM PDT 24
Finished Jul 14 06:31:06 PM PDT 24
Peak memory 200260 kb
Host smart-23a2e53c-8c66-4398-a1a0-fa25dc7bdba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490610073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3490610073
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3868959760
Short name T621
Test name
Test status
Simulation time 198929271 ps
CPU time 3.03 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 200248 kb
Host smart-5b89bbe1-68ba-4ae8-92bc-756e64ebd635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868959760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3868959760
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.158506963
Short name T125
Test name
Test status
Simulation time 154009763 ps
CPU time 3.33 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200220 kb
Host smart-2795f64e-c67a-4963-8f32-0d0a47adcd92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158506963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.158506963
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1967414950
Short name T554
Test name
Test status
Simulation time 100568408 ps
CPU time 1.72 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:31:04 PM PDT 24
Peak memory 200248 kb
Host smart-4f5b7581-38e9-4a0a-b492-65705d2ffdb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967414950 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1967414950
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4060820251
Short name T111
Test name
Test status
Simulation time 14469498 ps
CPU time 0.8 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:53 PM PDT 24
Peak memory 199736 kb
Host smart-0e1d1cf4-ae92-42dd-8a9a-5f38abea0e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060820251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4060820251
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1957134710
Short name T654
Test name
Test status
Simulation time 30248390 ps
CPU time 0.67 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:30:58 PM PDT 24
Peak memory 195188 kb
Host smart-8bc90882-2670-46e8-9585-c29fa11297e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957134710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1957134710
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1791558597
Short name T632
Test name
Test status
Simulation time 88017904 ps
CPU time 1.86 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 200296 kb
Host smart-fb4344d2-38b2-4796-a57f-aeb35f26f6ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791558597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1791558597
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1981082441
Short name T547
Test name
Test status
Simulation time 688807384 ps
CPU time 3.72 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200304 kb
Host smart-2b84ce06-dcf2-4532-afa4-f1d99f822425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981082441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1981082441
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2038351739
Short name T130
Test name
Test status
Simulation time 195396369 ps
CPU time 1.98 seconds
Started Jul 14 06:31:02 PM PDT 24
Finished Jul 14 06:31:05 PM PDT 24
Peak memory 200160 kb
Host smart-f6d60fb3-2a28-44b2-9552-889163e3b8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038351739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2038351739
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.224593552
Short name T584
Test name
Test status
Simulation time 190792435 ps
CPU time 3.27 seconds
Started Jul 14 06:30:53 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 200480 kb
Host smart-c29338a3-cb6d-4fe3-a954-da796224c246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224593552 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.224593552
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3349598699
Short name T648
Test name
Test status
Simulation time 18803424 ps
CPU time 0.95 seconds
Started Jul 14 06:30:53 PM PDT 24
Finished Jul 14 06:30:56 PM PDT 24
Peak memory 200116 kb
Host smart-86f7c0fb-5169-4833-a47d-cef776b8c9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349598699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3349598699
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.909792370
Short name T533
Test name
Test status
Simulation time 27302838 ps
CPU time 0.59 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 195184 kb
Host smart-813b8d96-fc81-438f-be8b-3ee737b2ed9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909792370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.909792370
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2903160517
Short name T114
Test name
Test status
Simulation time 23180226 ps
CPU time 1.12 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 200024 kb
Host smart-126f8585-adec-4d74-812f-1ba18821ccbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903160517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2903160517
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3624181846
Short name T538
Test name
Test status
Simulation time 699803250 ps
CPU time 3.42 seconds
Started Jul 14 06:30:54 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 200352 kb
Host smart-34d371fc-0f90-4210-9ece-ceb2d70e64d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624181846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3624181846
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1626008335
Short name T569
Test name
Test status
Simulation time 322631957 ps
CPU time 2.92 seconds
Started Jul 14 06:31:02 PM PDT 24
Finished Jul 14 06:31:06 PM PDT 24
Peak memory 200056 kb
Host smart-a3b69c6e-3d87-427c-9b32-0bd0e10b2db4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626008335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1626008335
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3726508175
Short name T94
Test name
Test status
Simulation time 462325708 ps
CPU time 3.08 seconds
Started Jul 14 06:30:42 PM PDT 24
Finished Jul 14 06:30:46 PM PDT 24
Peak memory 200288 kb
Host smart-ba5b1b1b-52cd-494a-840d-5df1e89a8c1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726508175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3726508175
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2900582105
Short name T628
Test name
Test status
Simulation time 2121392167 ps
CPU time 6.26 seconds
Started Jul 14 06:30:39 PM PDT 24
Finished Jul 14 06:30:46 PM PDT 24
Peak memory 200340 kb
Host smart-a3c98265-f2c4-497d-b4a6-1bcda33472ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900582105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2900582105
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.354057981
Short name T100
Test name
Test status
Simulation time 25524426 ps
CPU time 0.83 seconds
Started Jul 14 06:30:36 PM PDT 24
Finished Jul 14 06:30:37 PM PDT 24
Peak memory 199908 kb
Host smart-d563dec6-4eb3-4554-a302-5b40516a7f59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354057981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.354057981
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.174164704
Short name T576
Test name
Test status
Simulation time 1002597543 ps
CPU time 1.55 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:44 PM PDT 24
Peak memory 200372 kb
Host smart-9b353b92-f2f1-4114-8199-f3cd47c96ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174164704 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.174164704
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2896022474
Short name T556
Test name
Test status
Simulation time 12079872 ps
CPU time 0.74 seconds
Started Jul 14 06:30:38 PM PDT 24
Finished Jul 14 06:30:39 PM PDT 24
Peak memory 197984 kb
Host smart-48769bc4-3151-431e-981d-1dd65c4049a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896022474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2896022474
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2426330206
Short name T572
Test name
Test status
Simulation time 42485030 ps
CPU time 0.6 seconds
Started Jul 14 06:30:35 PM PDT 24
Finished Jul 14 06:30:36 PM PDT 24
Peak memory 195320 kb
Host smart-351e9293-87d1-4fb0-9b1c-db84f75dd43a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426330206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2426330206
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1482486608
Short name T635
Test name
Test status
Simulation time 44926490 ps
CPU time 2.11 seconds
Started Jul 14 06:30:42 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 200296 kb
Host smart-09dab14a-050d-4f91-bd14-12275d556539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482486608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1482486608
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.569255053
Short name T565
Test name
Test status
Simulation time 282025860 ps
CPU time 4.29 seconds
Started Jul 14 06:30:34 PM PDT 24
Finished Jul 14 06:30:39 PM PDT 24
Peak memory 200296 kb
Host smart-779ab7f9-321e-45d7-be96-5c60ca730aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569255053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.569255053
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2394550117
Short name T127
Test name
Test status
Simulation time 687911833 ps
CPU time 1.86 seconds
Started Jul 14 06:30:35 PM PDT 24
Finished Jul 14 06:30:37 PM PDT 24
Peak memory 200344 kb
Host smart-32c5dc99-fafe-4ab7-8751-72d806b19fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394550117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2394550117
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3115211404
Short name T532
Test name
Test status
Simulation time 14996875 ps
CPU time 0.66 seconds
Started Jul 14 06:30:53 PM PDT 24
Finished Jul 14 06:30:56 PM PDT 24
Peak memory 195288 kb
Host smart-ae73ed20-0f80-4c4e-8cc9-b937eb189b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115211404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3115211404
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1247078490
Short name T650
Test name
Test status
Simulation time 15470443 ps
CPU time 0.61 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:54 PM PDT 24
Peak memory 195100 kb
Host smart-7342b271-dbfd-4167-acf3-277dd08d0977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247078490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1247078490
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4037812162
Short name T605
Test name
Test status
Simulation time 72959125 ps
CPU time 0.65 seconds
Started Jul 14 06:30:55 PM PDT 24
Finished Jul 14 06:30:58 PM PDT 24
Peak memory 195308 kb
Host smart-1bb87905-162c-4239-a0d6-e59c1a465c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037812162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4037812162
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3821888987
Short name T625
Test name
Test status
Simulation time 42611182 ps
CPU time 0.58 seconds
Started Jul 14 06:31:02 PM PDT 24
Finished Jul 14 06:31:04 PM PDT 24
Peak memory 195248 kb
Host smart-54892d53-a747-4e20-9b47-66ec3990af9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821888987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3821888987
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3098565872
Short name T631
Test name
Test status
Simulation time 29350593 ps
CPU time 0.63 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:06 PM PDT 24
Peak memory 195304 kb
Host smart-3d9148ae-4caf-4753-99f7-4d2fbde43de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098565872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3098565872
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2930015991
Short name T630
Test name
Test status
Simulation time 17818199 ps
CPU time 0.66 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 195308 kb
Host smart-73c2707a-ff99-4dab-9448-2d0dbd63cba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930015991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2930015991
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2099690159
Short name T588
Test name
Test status
Simulation time 22320010 ps
CPU time 0.61 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 195216 kb
Host smart-d83f13f6-da48-441e-8bcf-3bdfc66ca073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099690159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2099690159
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1109883348
Short name T535
Test name
Test status
Simulation time 17173954 ps
CPU time 0.61 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:06 PM PDT 24
Peak memory 195300 kb
Host smart-b0844c86-3745-4ef8-9e6c-2aaaa5169b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109883348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1109883348
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1719375886
Short name T585
Test name
Test status
Simulation time 16415912 ps
CPU time 0.57 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 195176 kb
Host smart-fc3e9f87-2e23-435f-b6b7-54e7a09f20bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719375886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1719375886
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2875553936
Short name T553
Test name
Test status
Simulation time 25187965 ps
CPU time 0.62 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 195180 kb
Host smart-9c14ed04-4e53-4b5a-9ad0-df9e372f6f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875553936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2875553936
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.172718388
Short name T614
Test name
Test status
Simulation time 532250840 ps
CPU time 8.56 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:51 PM PDT 24
Peak memory 200312 kb
Host smart-b438359b-8ee4-401b-8f43-0ab2918e0ffc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172718388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.172718388
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.928085951
Short name T536
Test name
Test status
Simulation time 119305906 ps
CPU time 5.31 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:47 PM PDT 24
Peak memory 200292 kb
Host smart-980be1f5-c89d-4bf6-ab9b-9a6cab8f8312
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928085951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.928085951
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1807771819
Short name T653
Test name
Test status
Simulation time 205535278 ps
CPU time 0.74 seconds
Started Jul 14 06:30:45 PM PDT 24
Finished Jul 14 06:30:46 PM PDT 24
Peak memory 198056 kb
Host smart-77a6b1de-8afc-4b5c-b918-226ad7874dad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807771819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1807771819
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3652163211
Short name T552
Test name
Test status
Simulation time 66054304 ps
CPU time 1.86 seconds
Started Jul 14 06:30:49 PM PDT 24
Finished Jul 14 06:30:52 PM PDT 24
Peak memory 200368 kb
Host smart-ffcd8e43-b2ee-41fb-b718-426b880c91a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652163211 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3652163211
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2975048375
Short name T643
Test name
Test status
Simulation time 82594633 ps
CPU time 0.8 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:42 PM PDT 24
Peak memory 199520 kb
Host smart-d616be96-2bb0-4b84-b608-32a16165e060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975048375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2975048375
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3290631221
Short name T629
Test name
Test status
Simulation time 16701672 ps
CPU time 0.62 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:42 PM PDT 24
Peak memory 195256 kb
Host smart-74f3310f-ea00-4b1a-896f-6a7b33172e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290631221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3290631221
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4120696099
Short name T583
Test name
Test status
Simulation time 130982016 ps
CPU time 1.62 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:44 PM PDT 24
Peak memory 200180 kb
Host smart-e65b1bc9-c09f-4a15-bfd8-cd814f26a808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120696099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4120696099
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2473329488
Short name T570
Test name
Test status
Simulation time 111570376 ps
CPU time 2.31 seconds
Started Jul 14 06:30:39 PM PDT 24
Finished Jul 14 06:30:42 PM PDT 24
Peak memory 200324 kb
Host smart-103b9827-d5a6-4b51-84ca-24795bfe8877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473329488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2473329488
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2163053461
Short name T121
Test name
Test status
Simulation time 185536216 ps
CPU time 3.17 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 200320 kb
Host smart-a4ff4da4-2a08-4907-9e33-95d3a759ae15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163053461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2163053461
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3045217143
Short name T587
Test name
Test status
Simulation time 39483592 ps
CPU time 0.67 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:31:03 PM PDT 24
Peak memory 195388 kb
Host smart-b2d549d9-85da-453d-8e07-480505c8c723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045217143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3045217143
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2389487644
Short name T591
Test name
Test status
Simulation time 34486225 ps
CPU time 0.67 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:02 PM PDT 24
Peak memory 195224 kb
Host smart-8ae926c8-8908-43d2-b34d-cb39ce19888c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389487644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2389487644
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3865912527
Short name T640
Test name
Test status
Simulation time 14057071 ps
CPU time 0.64 seconds
Started Jul 14 06:31:01 PM PDT 24
Finished Jul 14 06:31:04 PM PDT 24
Peak memory 195140 kb
Host smart-99882a5d-1607-4b62-919d-cdd8c7051edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865912527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3865912527
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.30731144
Short name T568
Test name
Test status
Simulation time 23659686 ps
CPU time 0.6 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 195176 kb
Host smart-01974324-fcf6-4b40-8b2a-10eb779e8181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30731144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.30731144
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1624588979
Short name T529
Test name
Test status
Simulation time 26186239 ps
CPU time 0.59 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:00 PM PDT 24
Peak memory 195248 kb
Host smart-81128050-543d-4792-8bf0-fa3530e25088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624588979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1624588979
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1361832299
Short name T623
Test name
Test status
Simulation time 31912864 ps
CPU time 0.6 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 195180 kb
Host smart-3da15c05-02f0-4a12-a668-4abcc8558599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361832299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1361832299
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3092211780
Short name T581
Test name
Test status
Simulation time 13816589 ps
CPU time 0.66 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:31:05 PM PDT 24
Peak memory 195088 kb
Host smart-4edbe91a-5f85-4c66-ba29-1d2858147069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092211780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3092211780
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2351028746
Short name T531
Test name
Test status
Simulation time 13604599 ps
CPU time 0.63 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:02 PM PDT 24
Peak memory 195164 kb
Host smart-55778a21-c7a5-49aa-88f8-258a235d5c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351028746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2351028746
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3268635620
Short name T647
Test name
Test status
Simulation time 23599584 ps
CPU time 0.62 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:02 PM PDT 24
Peak memory 195320 kb
Host smart-baee021b-898b-438a-aef1-06b2adf9f4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268635620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3268635620
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.788360916
Short name T592
Test name
Test status
Simulation time 59320175 ps
CPU time 0.64 seconds
Started Jul 14 06:30:57 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 195212 kb
Host smart-d364379e-216b-4797-922a-8db4e6915d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788360916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.788360916
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.68869332
Short name T637
Test name
Test status
Simulation time 195847854 ps
CPU time 3.39 seconds
Started Jul 14 06:30:39 PM PDT 24
Finished Jul 14 06:30:43 PM PDT 24
Peak memory 200316 kb
Host smart-f21ef6c6-37d5-497f-9550-df1b35862109
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68869332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.68869332
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3077074806
Short name T99
Test name
Test status
Simulation time 1645980290 ps
CPU time 16.73 seconds
Started Jul 14 06:30:44 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 200324 kb
Host smart-8503a6c6-3e76-4e1f-9b2d-81c372bbb552
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077074806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3077074806
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2395329601
Short name T102
Test name
Test status
Simulation time 23340839 ps
CPU time 0.76 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:43 PM PDT 24
Peak memory 198640 kb
Host smart-c2bc85d4-be45-4132-af7a-2715e4d85296
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395329601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2395329601
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1974878067
Short name T594
Test name
Test status
Simulation time 173249021 ps
CPU time 2.39 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:44 PM PDT 24
Peak memory 200380 kb
Host smart-0b83be93-c416-4733-8d7a-30043f32480a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974878067 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1974878067
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3086939600
Short name T97
Test name
Test status
Simulation time 57425370 ps
CPU time 0.89 seconds
Started Jul 14 06:30:44 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 199952 kb
Host smart-d9417bb4-f04c-4631-af58-139e2a59fe50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086939600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3086939600
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3203070093
Short name T622
Test name
Test status
Simulation time 15729369 ps
CPU time 0.7 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:42 PM PDT 24
Peak memory 195312 kb
Host smart-f0b14ce7-db70-443a-9f53-6019af698472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203070093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3203070093
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2853296594
Short name T551
Test name
Test status
Simulation time 69110641 ps
CPU time 1.71 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:51 PM PDT 24
Peak memory 200288 kb
Host smart-51461893-6fb5-43a7-950e-4d2462b81f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853296594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2853296594
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1271436742
Short name T578
Test name
Test status
Simulation time 146590301 ps
CPU time 2.88 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:46 PM PDT 24
Peak memory 200356 kb
Host smart-882dec5f-2047-4ac0-a3ca-b132e04740d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271436742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1271436742
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3693103220
Short name T617
Test name
Test status
Simulation time 177369244 ps
CPU time 3.03 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 200304 kb
Host smart-34327d83-fd54-4e94-8b01-49cd1cda64d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693103220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3693103220
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3989360432
Short name T563
Test name
Test status
Simulation time 19249066 ps
CPU time 0.65 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 195272 kb
Host smart-dcce2bb4-cbb1-4ea9-94e3-683ebb596db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989360432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3989360432
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1394808605
Short name T638
Test name
Test status
Simulation time 14986618 ps
CPU time 0.61 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 195268 kb
Host smart-c2fdffec-1af8-49f2-b6b6-0effd40450f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394808605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1394808605
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1717323596
Short name T620
Test name
Test status
Simulation time 11303390 ps
CPU time 0.62 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:31:03 PM PDT 24
Peak memory 195160 kb
Host smart-cd2db5e0-ab0f-4294-8db0-a157d7acd1af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717323596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1717323596
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.546149749
Short name T582
Test name
Test status
Simulation time 56264898 ps
CPU time 0.64 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:02 PM PDT 24
Peak memory 195256 kb
Host smart-13a5c7cd-402e-4496-9f99-30527c64c127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546149749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.546149749
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1629016124
Short name T624
Test name
Test status
Simulation time 21595531 ps
CPU time 0.6 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:08 PM PDT 24
Peak memory 195192 kb
Host smart-bb907638-0fe8-41d0-b25e-926c3f3923f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629016124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1629016124
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3900619453
Short name T580
Test name
Test status
Simulation time 14686127 ps
CPU time 0.65 seconds
Started Jul 14 06:31:01 PM PDT 24
Finished Jul 14 06:31:04 PM PDT 24
Peak memory 195172 kb
Host smart-4fc0e526-96e5-49af-8965-9bb30f51c8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900619453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3900619453
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3898653464
Short name T656
Test name
Test status
Simulation time 26343264 ps
CPU time 0.55 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:31:03 PM PDT 24
Peak memory 195364 kb
Host smart-e2f4b337-aac1-4889-a18d-2d878dcf54ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898653464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3898653464
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2882361186
Short name T619
Test name
Test status
Simulation time 54777255 ps
CPU time 0.59 seconds
Started Jul 14 06:30:57 PM PDT 24
Finished Jul 14 06:30:59 PM PDT 24
Peak memory 195252 kb
Host smart-5ba2e126-7f4f-402f-bf6e-c6aad2bbd82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882361186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2882361186
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.729323372
Short name T593
Test name
Test status
Simulation time 22644334 ps
CPU time 0.58 seconds
Started Jul 14 06:30:58 PM PDT 24
Finished Jul 14 06:31:01 PM PDT 24
Peak memory 195268 kb
Host smart-e2e510ae-1aca-4ce9-bf67-a03c03a184d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729323372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.729323372
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4177543601
Short name T612
Test name
Test status
Simulation time 13597169 ps
CPU time 0.61 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:31:03 PM PDT 24
Peak memory 195336 kb
Host smart-7f88818c-03ed-40da-a2ff-5cc257f960c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177543601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4177543601
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.15271300
Short name T657
Test name
Test status
Simulation time 8682506994 ps
CPU time 46.11 seconds
Started Jul 14 06:30:43 PM PDT 24
Finished Jul 14 06:31:30 PM PDT 24
Peak memory 215976 kb
Host smart-c027beb2-212e-4e96-bd0b-f30661df1663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15271300 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.15271300
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4020468990
Short name T590
Test name
Test status
Simulation time 39754881 ps
CPU time 0.97 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:42 PM PDT 24
Peak memory 199700 kb
Host smart-bff3777d-7db8-4383-a0ee-9de293e3695b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020468990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.4020468990
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2275415708
Short name T642
Test name
Test status
Simulation time 14012213 ps
CPU time 0.58 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:43 PM PDT 24
Peak memory 195152 kb
Host smart-b3aed3b5-2474-4eb1-b542-a053e9be894c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275415708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2275415708
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1273591959
Short name T117
Test name
Test status
Simulation time 134379669 ps
CPU time 1.16 seconds
Started Jul 14 06:30:43 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 198808 kb
Host smart-e8635e7a-6c7a-4131-b43e-6252ed381112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273591959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1273591959
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4160133753
Short name T609
Test name
Test status
Simulation time 173761277 ps
CPU time 1.33 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:43 PM PDT 24
Peak memory 200272 kb
Host smart-3259dc96-4790-415f-832a-3a01e2cfacfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160133753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4160133753
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2713810884
Short name T543
Test name
Test status
Simulation time 100432723 ps
CPU time 1.75 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 200284 kb
Host smart-f2e94b48-05cf-4c23-a69e-62c7e54aa89d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713810884 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2713810884
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4035086415
Short name T586
Test name
Test status
Simulation time 84941332 ps
CPU time 0.84 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:42 PM PDT 24
Peak memory 200080 kb
Host smart-48eb964c-4f2e-459a-903c-cc0e9a88f93d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035086415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4035086415
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1915265153
Short name T589
Test name
Test status
Simulation time 31728248 ps
CPU time 0.58 seconds
Started Jul 14 06:30:41 PM PDT 24
Finished Jul 14 06:30:43 PM PDT 24
Peak memory 195200 kb
Host smart-81d2074d-e6b0-431c-a3f2-7595a7d510ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915265153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1915265153
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.214804502
Short name T644
Test name
Test status
Simulation time 51654528 ps
CPU time 2.12 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:45 PM PDT 24
Peak memory 200252 kb
Host smart-a3a5476f-0fe4-40f7-b4df-cf69918d48a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214804502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.214804502
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3508405467
Short name T545
Test name
Test status
Simulation time 177309569 ps
CPU time 3.18 seconds
Started Jul 14 06:30:44 PM PDT 24
Finished Jul 14 06:30:48 PM PDT 24
Peak memory 200300 kb
Host smart-86ec31ba-b230-43a7-bf8f-465e5d66e183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508405467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3508405467
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1853047391
Short name T615
Test name
Test status
Simulation time 168120067 ps
CPU time 1.93 seconds
Started Jul 14 06:30:42 PM PDT 24
Finished Jul 14 06:30:46 PM PDT 24
Peak memory 200320 kb
Host smart-1b60eac9-0e8e-4c7d-9b3a-42e272a75252
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853047391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1853047391
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.950340581
Short name T599
Test name
Test status
Simulation time 37424483 ps
CPU time 1.24 seconds
Started Jul 14 06:30:50 PM PDT 24
Finished Jul 14 06:30:51 PM PDT 24
Peak memory 200096 kb
Host smart-2a218305-e67a-42f8-a3a5-760eac9b2b9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950340581 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.950340581
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3979768526
Short name T119
Test name
Test status
Simulation time 18786347 ps
CPU time 0.78 seconds
Started Jul 14 06:30:50 PM PDT 24
Finished Jul 14 06:30:52 PM PDT 24
Peak memory 198144 kb
Host smart-2ad9781d-9db9-4d60-a9ff-2db13289a271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979768526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3979768526
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2952554263
Short name T579
Test name
Test status
Simulation time 36723601 ps
CPU time 0.59 seconds
Started Jul 14 06:30:42 PM PDT 24
Finished Jul 14 06:30:44 PM PDT 24
Peak memory 195108 kb
Host smart-625a4d0e-4a26-4c5f-ac02-20d5f2cfc0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952554263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2952554263
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2081844674
Short name T573
Test name
Test status
Simulation time 85119506 ps
CPU time 2.13 seconds
Started Jul 14 06:30:49 PM PDT 24
Finished Jul 14 06:30:52 PM PDT 24
Peak memory 200304 kb
Host smart-8c708603-effe-449d-8571-64e216758c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081844674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2081844674
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.648225542
Short name T560
Test name
Test status
Simulation time 108742182 ps
CPU time 3.63 seconds
Started Jul 14 06:30:42 PM PDT 24
Finished Jul 14 06:30:47 PM PDT 24
Peak memory 200304 kb
Host smart-812fc85f-f1ee-42c1-87f0-f8e7d87fa9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648225542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.648225542
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1845113420
Short name T655
Test name
Test status
Simulation time 157973027 ps
CPU time 3.05 seconds
Started Jul 14 06:30:40 PM PDT 24
Finished Jul 14 06:30:44 PM PDT 24
Peak memory 200312 kb
Host smart-51dcd8f3-871c-42b8-a8ad-37f46f9ad892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845113420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1845113420
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1476672504
Short name T559
Test name
Test status
Simulation time 100581844613 ps
CPU time 234.77 seconds
Started Jul 14 06:30:47 PM PDT 24
Finished Jul 14 06:34:42 PM PDT 24
Peak memory 216792 kb
Host smart-b058179d-6741-4090-b05e-f1318652818f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476672504 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1476672504
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2739745547
Short name T540
Test name
Test status
Simulation time 36510546 ps
CPU time 0.59 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:53 PM PDT 24
Peak memory 195200 kb
Host smart-57a583de-31a1-423c-a607-693da157ccc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739745547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2739745547
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.44637148
Short name T113
Test name
Test status
Simulation time 150942028 ps
CPU time 2.49 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:51 PM PDT 24
Peak memory 198996 kb
Host smart-3ca22c6b-8eed-46dd-8fdd-260ff0fc6211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44637148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_o
utstanding.44637148
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.7444321
Short name T608
Test name
Test status
Simulation time 236044307 ps
CPU time 3.37 seconds
Started Jul 14 06:30:52 PM PDT 24
Finished Jul 14 06:30:57 PM PDT 24
Peak memory 200292 kb
Host smart-fd2c8ad2-52eb-44ca-bcaa-5b27f594c395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7444321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.7444321
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.670766699
Short name T74
Test name
Test status
Simulation time 47988743 ps
CPU time 1.83 seconds
Started Jul 14 06:30:48 PM PDT 24
Finished Jul 14 06:30:50 PM PDT 24
Peak memory 200364 kb
Host smart-b0c1596d-e1bd-4528-8331-6d8cdb41826c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670766699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.670766699
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2060105871
Short name T530
Test name
Test status
Simulation time 147498713102 ps
CPU time 246.87 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:34:59 PM PDT 24
Peak memory 216244 kb
Host smart-4127ae85-dafe-435d-a0dd-158e49c54a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060105871 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2060105871
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.520062350
Short name T96
Test name
Test status
Simulation time 118726359 ps
CPU time 0.97 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:53 PM PDT 24
Peak memory 200132 kb
Host smart-d19dd074-6ca0-4600-a600-b1eb5126af85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520062350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.520062350
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3021214024
Short name T534
Test name
Test status
Simulation time 124447168 ps
CPU time 0.6 seconds
Started Jul 14 06:30:47 PM PDT 24
Finished Jul 14 06:30:48 PM PDT 24
Peak memory 195192 kb
Host smart-c7cfbc40-2200-493f-bb29-4b4999dbdc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021214024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3021214024
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2455513689
Short name T115
Test name
Test status
Simulation time 311098404 ps
CPU time 2.54 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:55 PM PDT 24
Peak memory 200340 kb
Host smart-a1985623-02df-477a-9d2f-b0a0c0f3de12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455513689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2455513689
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2185524411
Short name T651
Test name
Test status
Simulation time 199753428 ps
CPU time 3.75 seconds
Started Jul 14 06:30:51 PM PDT 24
Finished Jul 14 06:30:56 PM PDT 24
Peak memory 200240 kb
Host smart-35afe217-5ef3-4719-99b2-6ea8e75c0903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185524411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2185524411
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3858072339
Short name T128
Test name
Test status
Simulation time 263101672 ps
CPU time 4.26 seconds
Started Jul 14 06:30:47 PM PDT 24
Finished Jul 14 06:30:52 PM PDT 24
Peak memory 200288 kb
Host smart-65437519-55a7-4803-98cb-c9748cb91801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858072339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3858072339
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2684567816
Short name T510
Test name
Test status
Simulation time 36935154 ps
CPU time 0.6 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:08 PM PDT 24
Peak memory 196780 kb
Host smart-e8080bf2-8206-4cb1-9ec9-7ed59692d924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684567816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2684567816
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3813700858
Short name T335
Test name
Test status
Simulation time 1477334160 ps
CPU time 82.42 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:32:27 PM PDT 24
Peak memory 200220 kb
Host smart-54749db2-79ef-4fb3-a52c-17ac038cb005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813700858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3813700858
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2053215949
Short name T364
Test name
Test status
Simulation time 1200839838 ps
CPU time 18.96 seconds
Started Jul 14 06:30:59 PM PDT 24
Finished Jul 14 06:31:20 PM PDT 24
Peak memory 200348 kb
Host smart-1ce1e75c-e47e-475a-8e36-fa89a9137af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053215949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2053215949
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1108333903
Short name T258
Test name
Test status
Simulation time 447532448 ps
CPU time 57.34 seconds
Started Jul 14 06:31:07 PM PDT 24
Finished Jul 14 06:32:06 PM PDT 24
Peak memory 314852 kb
Host smart-a194bbe6-ab7d-4697-b181-56453790c393
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108333903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1108333903
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3174192984
Short name T181
Test name
Test status
Simulation time 1322808361 ps
CPU time 18.81 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:31:24 PM PDT 24
Peak memory 200124 kb
Host smart-d834fd15-8782-499f-95df-10225161fadd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174192984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3174192984
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.444889479
Short name T378
Test name
Test status
Simulation time 10934397070 ps
CPU time 82.58 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200688 kb
Host smart-80d2926b-46e9-43e7-be3f-46b266a34827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444889479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.444889479
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2175456791
Short name T63
Test name
Test status
Simulation time 206467103 ps
CPU time 0.85 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 06:31:03 PM PDT 24
Peak memory 218460 kb
Host smart-a1c465dd-8d75-46a1-b140-2b812022f7e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175456791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2175456791
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3697703205
Short name T481
Test name
Test status
Simulation time 145280745 ps
CPU time 6.99 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:14 PM PDT 24
Peak memory 200332 kb
Host smart-0d583563-57e2-4458-85e3-c75c424167e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697703205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3697703205
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.336311433
Short name T276
Test name
Test status
Simulation time 471073164072 ps
CPU time 3152.49 seconds
Started Jul 14 06:31:00 PM PDT 24
Finished Jul 14 07:23:35 PM PDT 24
Peak memory 833432 kb
Host smart-67642a3e-8dac-4e92-8b5b-cbcb1b62e0f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336311433 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.336311433
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3625556307
Short name T300
Test name
Test status
Simulation time 1999078515 ps
CPU time 65.87 seconds
Started Jul 14 06:31:07 PM PDT 24
Finished Jul 14 06:32:14 PM PDT 24
Peak memory 200280 kb
Host smart-77e38601-744f-45eb-a5ec-a8ce2025ee73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3625556307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3625556307
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1463885656
Short name T42
Test name
Test status
Simulation time 6537035315 ps
CPU time 108.74 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:32:55 PM PDT 24
Peak memory 200268 kb
Host smart-7dba91e9-7a0e-422b-b655-36b3e6965a4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1463885656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1463885656
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.4019343879
Short name T206
Test name
Test status
Simulation time 6666784165 ps
CPU time 80.41 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200304 kb
Host smart-3c3f0df4-0b21-4713-9f75-e22117869b08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4019343879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.4019343879
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2055229823
Short name T237
Test name
Test status
Simulation time 422132572873 ps
CPU time 2635.5 seconds
Started Jul 14 06:31:01 PM PDT 24
Finished Jul 14 07:14:59 PM PDT 24
Peak memory 216724 kb
Host smart-523934de-8f71-483f-bd9c-7ada30c596ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2055229823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2055229823
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.18855369
Short name T277
Test name
Test status
Simulation time 544295606778 ps
CPU time 2295.19 seconds
Started Jul 14 06:31:01 PM PDT 24
Finished Jul 14 07:09:19 PM PDT 24
Peak memory 215764 kb
Host smart-48b3ef5c-729c-4399-af6b-67bc9843cc94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=18855369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.18855369
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2271819314
Short name T310
Test name
Test status
Simulation time 5158891235 ps
CPU time 97.38 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:32:44 PM PDT 24
Peak memory 200420 kb
Host smart-6e970cd5-fb79-49b0-96af-03be38901e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271819314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2271819314
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3687933640
Short name T212
Test name
Test status
Simulation time 23913411 ps
CPU time 0.59 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:08 PM PDT 24
Peak memory 196184 kb
Host smart-82303908-1004-4b07-9451-8a6c51dfa7ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687933640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3687933640
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.88193242
Short name T474
Test name
Test status
Simulation time 8303071886 ps
CPU time 48.29 seconds
Started Jul 14 06:31:08 PM PDT 24
Finished Jul 14 06:31:58 PM PDT 24
Peak memory 200376 kb
Host smart-dfc10f0b-c1a4-40a3-85f4-c46eb85a878f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88193242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.88193242
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2062860231
Short name T372
Test name
Test status
Simulation time 6235725358 ps
CPU time 28.01 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:31:32 PM PDT 24
Peak memory 200380 kb
Host smart-23bc00a1-e92c-4f81-a55e-c0e85a1104b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062860231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2062860231
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3440413975
Short name T133
Test name
Test status
Simulation time 5767995903 ps
CPU time 534.66 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:40:02 PM PDT 24
Peak memory 622592 kb
Host smart-5fdda3fc-fe6d-43d3-9be7-374771c44c62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440413975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3440413975
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1180657877
Short name T189
Test name
Test status
Simulation time 18717858614 ps
CPU time 23.99 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:31 PM PDT 24
Peak memory 200336 kb
Host smart-a9917703-a6a9-4747-9572-e1100c34bfa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180657877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1180657877
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2860348438
Short name T463
Test name
Test status
Simulation time 841514216 ps
CPU time 11.75 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:19 PM PDT 24
Peak memory 200216 kb
Host smart-2d39f568-2182-40f2-beae-11d573f12547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860348438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2860348438
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.766984167
Short name T62
Test name
Test status
Simulation time 127495816 ps
CPU time 0.84 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:07 PM PDT 24
Peak memory 218192 kb
Host smart-e1e0d3f5-8745-40b2-9378-d55893b9ba42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766984167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.766984167
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.4052975764
Short name T282
Test name
Test status
Simulation time 20129275 ps
CPU time 0.99 seconds
Started Jul 14 06:31:06 PM PDT 24
Finished Jul 14 06:31:09 PM PDT 24
Peak memory 200088 kb
Host smart-3717e28e-33e4-4d5f-92f7-4a8cecbb23f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052975764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4052975764
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1090332956
Short name T350
Test name
Test status
Simulation time 77263994163 ps
CPU time 2788.91 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 07:17:36 PM PDT 24
Peak memory 788392 kb
Host smart-4491b9b6-92bb-4edf-90ff-de07d4497fd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090332956 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1090332956
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.478575594
Short name T29
Test name
Test status
Simulation time 71940242254 ps
CPU time 2368.67 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 07:10:39 PM PDT 24
Peak memory 798368 kb
Host smart-0a06f0c7-2b47-437c-a14c-fcf24b177c80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478575594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.478575594
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.250887473
Short name T256
Test name
Test status
Simulation time 19602514399 ps
CPU time 45.29 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:31:55 PM PDT 24
Peak memory 200336 kb
Host smart-331d6a7c-06b0-4e62-8f98-e145f325ba84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=250887473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.250887473
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2103323634
Short name T327
Test name
Test status
Simulation time 18237822011 ps
CPU time 114.62 seconds
Started Jul 14 06:31:06 PM PDT 24
Finished Jul 14 06:33:03 PM PDT 24
Peak memory 200396 kb
Host smart-bcb463a0-042e-4681-b22f-ed3e8d803741
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2103323634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2103323634
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1968959314
Short name T469
Test name
Test status
Simulation time 27110544108 ps
CPU time 82.45 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:32:28 PM PDT 24
Peak memory 200372 kb
Host smart-b17b1214-1db5-4fc2-9303-edaf37ad31c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1968959314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1968959314
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2354420283
Short name T196
Test name
Test status
Simulation time 51353607987 ps
CPU time 631.63 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:41:42 PM PDT 24
Peak memory 200336 kb
Host smart-2632a1c2-a679-48be-a9e7-7e281562a695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2354420283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2354420283
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3534608215
Short name T408
Test name
Test status
Simulation time 39271132069 ps
CPU time 2018.58 seconds
Started Jul 14 06:31:06 PM PDT 24
Finished Jul 14 07:04:47 PM PDT 24
Peak memory 216764 kb
Host smart-2ea1096e-a469-4f3d-a9e4-730fd2751f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3534608215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3534608215
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2370900927
Short name T173
Test name
Test status
Simulation time 211439892305 ps
CPU time 2542.21 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 215952 kb
Host smart-50a8ff84-0f4a-445a-8b91-beac20d935ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2370900927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2370900927
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3042653124
Short name T307
Test name
Test status
Simulation time 7272946831 ps
CPU time 32.18 seconds
Started Jul 14 06:31:06 PM PDT 24
Finished Jul 14 06:31:40 PM PDT 24
Peak memory 200348 kb
Host smart-bd982fdb-851a-4cda-a56e-3eeb600ef1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042653124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3042653124
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2533672191
Short name T240
Test name
Test status
Simulation time 49891892 ps
CPU time 0.6 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:31:37 PM PDT 24
Peak memory 195128 kb
Host smart-b44354e5-1027-4fc9-9439-80dfe6d1bfc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533672191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2533672191
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1889606055
Short name T244
Test name
Test status
Simulation time 1352872752 ps
CPU time 84.03 seconds
Started Jul 14 06:31:22 PM PDT 24
Finished Jul 14 06:32:50 PM PDT 24
Peak memory 200360 kb
Host smart-028fa9c5-e059-4ccd-9d68-a530a560fb8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889606055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1889606055
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1884610276
Short name T425
Test name
Test status
Simulation time 1528383446 ps
CPU time 19.19 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:31:44 PM PDT 24
Peak memory 200184 kb
Host smart-8fe0b029-43a5-4e59-9e63-9b7324bab918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884610276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1884610276
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2423450026
Short name T399
Test name
Test status
Simulation time 10907522259 ps
CPU time 509.09 seconds
Started Jul 14 06:31:28 PM PDT 24
Finished Jul 14 06:39:59 PM PDT 24
Peak memory 627008 kb
Host smart-2a397bc1-9bb7-414d-99f4-850a41480300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423450026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2423450026
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.177908364
Short name T52
Test name
Test status
Simulation time 33779961329 ps
CPU time 155.19 seconds
Started Jul 14 06:31:20 PM PDT 24
Finished Jul 14 06:33:59 PM PDT 24
Peak memory 200340 kb
Host smart-3c8901fe-aa40-4131-a92c-3599fc6a46f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177908364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.177908364
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1919553587
Short name T484
Test name
Test status
Simulation time 78870673 ps
CPU time 0.66 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:31:25 PM PDT 24
Peak memory 196804 kb
Host smart-c37783ab-3664-4236-a6e2-d1135dd75bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919553587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1919553587
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1432754818
Short name T177
Test name
Test status
Simulation time 786615581 ps
CPU time 5.82 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:31:31 PM PDT 24
Peak memory 200308 kb
Host smart-8e420cbc-1e9e-4ddb-95a0-77acd7012432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432754818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1432754818
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1377801100
Short name T77
Test name
Test status
Simulation time 328649329891 ps
CPU time 993.38 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:48:07 PM PDT 24
Peak memory 200384 kb
Host smart-a2dd60f7-f1b4-4f61-ae0a-2d48dc88658d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377801100 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1377801100
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2622486453
Short name T39
Test name
Test status
Simulation time 3217090402 ps
CPU time 57.41 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:32:22 PM PDT 24
Peak memory 200340 kb
Host smart-b280bfd5-0580-4ff4-a8be-a95e439b50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622486453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2622486453
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.967952960
Short name T328
Test name
Test status
Simulation time 29719250 ps
CPU time 0.59 seconds
Started Jul 14 06:31:41 PM PDT 24
Finished Jul 14 06:31:44 PM PDT 24
Peak memory 196100 kb
Host smart-c106d2b0-862b-49bf-8f1a-5990b8911a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967952960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.967952960
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.474421578
Short name T216
Test name
Test status
Simulation time 2488536956 ps
CPU time 52.71 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:32:17 PM PDT 24
Peak memory 200348 kb
Host smart-f3a91e90-be87-4ad3-8136-8ac4e084c0c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474421578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.474421578
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.676334163
Short name T346
Test name
Test status
Simulation time 163891050 ps
CPU time 2.17 seconds
Started Jul 14 06:31:22 PM PDT 24
Finished Jul 14 06:31:27 PM PDT 24
Peak memory 200220 kb
Host smart-cb7f5546-3b45-4ce8-b6ca-f791b469b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676334163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.676334163
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.357533007
Short name T523
Test name
Test status
Simulation time 2649929339 ps
CPU time 471.73 seconds
Started Jul 14 06:31:20 PM PDT 24
Finished Jul 14 06:39:15 PM PDT 24
Peak memory 693960 kb
Host smart-0095a550-97a9-4737-a1de-c927d528241f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357533007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.357533007
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2065430321
Short name T453
Test name
Test status
Simulation time 13006833309 ps
CPU time 178.82 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:34:30 PM PDT 24
Peak memory 200304 kb
Host smart-4a970464-6b51-4ab0-869f-2f09fd1b1d6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065430321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2065430321
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2999346675
Short name T373
Test name
Test status
Simulation time 4947619529 ps
CPU time 59.4 seconds
Started Jul 14 06:31:23 PM PDT 24
Finished Jul 14 06:32:26 PM PDT 24
Peak memory 200356 kb
Host smart-6cf66b3a-4081-4dbc-aa95-90aa5822fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999346675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2999346675
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1554141234
Short name T336
Test name
Test status
Simulation time 247596779 ps
CPU time 10.55 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:31:35 PM PDT 24
Peak memory 200300 kb
Host smart-2b4ca73a-7011-4fe4-801b-a93e7108034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554141234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1554141234
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3653147428
Short name T468
Test name
Test status
Simulation time 1609442696 ps
CPU time 12.48 seconds
Started Jul 14 06:31:23 PM PDT 24
Finished Jul 14 06:31:39 PM PDT 24
Peak memory 200272 kb
Host smart-3c578dc2-e7eb-4ebe-9151-50256d654bba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653147428 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3653147428
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2813572181
Short name T248
Test name
Test status
Simulation time 8000423614 ps
CPU time 15.34 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:31:48 PM PDT 24
Peak memory 200376 kb
Host smart-cfc9c9f3-274c-4af5-9d5b-f23d2b382ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813572181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2813572181
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1761471663
Short name T426
Test name
Test status
Simulation time 28345902 ps
CPU time 0.66 seconds
Started Jul 14 06:31:29 PM PDT 24
Finished Jul 14 06:31:31 PM PDT 24
Peak memory 196216 kb
Host smart-8606dae9-79e0-4f5c-89fb-b7a84c66c700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761471663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1761471663
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1919799124
Short name T446
Test name
Test status
Simulation time 2385620835 ps
CPU time 33.59 seconds
Started Jul 14 06:31:36 PM PDT 24
Finished Jul 14 06:32:11 PM PDT 24
Peak memory 200356 kb
Host smart-808b5317-4178-4af3-868f-1f26c665c691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919799124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1919799124
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_error.1977508194
Short name T174
Test name
Test status
Simulation time 2791114036 ps
CPU time 77.81 seconds
Started Jul 14 06:31:40 PM PDT 24
Finished Jul 14 06:33:01 PM PDT 24
Peak memory 200332 kb
Host smart-709fbc5f-b22d-4f5a-8e31-a3d5ca23121d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977508194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1977508194
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.873961734
Short name T170
Test name
Test status
Simulation time 30509680213 ps
CPU time 118.34 seconds
Started Jul 14 06:31:29 PM PDT 24
Finished Jul 14 06:33:28 PM PDT 24
Peak memory 200352 kb
Host smart-9ed4dc0c-ed02-45f0-91bc-56597fd3c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873961734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.873961734
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.229450320
Short name T293
Test name
Test status
Simulation time 2616477979 ps
CPU time 11.64 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:31:36 PM PDT 24
Peak memory 200380 kb
Host smart-d82be5a2-43cc-40e4-9173-38605ff797d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229450320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.229450320
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1088769463
Short name T389
Test name
Test status
Simulation time 66551886670 ps
CPU time 423.23 seconds
Started Jul 14 06:31:28 PM PDT 24
Finished Jul 14 06:38:33 PM PDT 24
Peak memory 200364 kb
Host smart-ae57da26-c67e-4bd1-8345-473641d53828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088769463 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1088769463
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.253946020
Short name T313
Test name
Test status
Simulation time 11088570207 ps
CPU time 141.9 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:33:56 PM PDT 24
Peak memory 200352 kb
Host smart-36ccb30b-e112-4027-ac35-91442cbb6384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253946020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.253946020
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2353905078
Short name T266
Test name
Test status
Simulation time 367394523 ps
CPU time 20.12 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:32:02 PM PDT 24
Peak memory 200248 kb
Host smart-bda6929f-1749-4260-a804-feed15470093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353905078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2353905078
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3607994815
Short name T500
Test name
Test status
Simulation time 1351642934 ps
CPU time 22.11 seconds
Started Jul 14 06:31:24 PM PDT 24
Finished Jul 14 06:31:49 PM PDT 24
Peak memory 200324 kb
Host smart-83f989e6-b5e3-45e7-933a-dc00c0c5221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607994815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3607994815
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.402500653
Short name T40
Test name
Test status
Simulation time 12031494529 ps
CPU time 367.37 seconds
Started Jul 14 06:31:27 PM PDT 24
Finished Jul 14 06:37:36 PM PDT 24
Peak memory 654920 kb
Host smart-c441e332-de30-4112-a3a9-0c465afa6976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402500653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.402500653
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1630682230
Short name T333
Test name
Test status
Simulation time 6685205687 ps
CPU time 29.3 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:32:09 PM PDT 24
Peak memory 200020 kb
Host smart-c3f330eb-ed37-4a4a-8548-3d27f59be4fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630682230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1630682230
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4001217968
Short name T461
Test name
Test status
Simulation time 8557031037 ps
CPU time 121.19 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:33:41 PM PDT 24
Peak memory 200052 kb
Host smart-f1defab9-861c-416d-8914-0452fd02cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001217968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4001217968
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.248488681
Short name T17
Test name
Test status
Simulation time 652491165 ps
CPU time 11.99 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:31:45 PM PDT 24
Peak memory 200268 kb
Host smart-594753ac-e5e5-4efb-a5af-52afa47aeed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248488681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.248488681
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2633197879
Short name T516
Test name
Test status
Simulation time 23644019258 ps
CPU time 1488.23 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 752972 kb
Host smart-51190cf3-9442-417e-b1c7-cf06c9065c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633197879 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2633197879
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2147537832
Short name T482
Test name
Test status
Simulation time 4775127112 ps
CPU time 64.53 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:32:38 PM PDT 24
Peak memory 200424 kb
Host smart-443626b7-ca9f-4169-9997-a1a00ea547af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147537832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2147537832
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2620869111
Short name T265
Test name
Test status
Simulation time 53463777 ps
CPU time 0.58 seconds
Started Jul 14 06:31:34 PM PDT 24
Finished Jul 14 06:31:35 PM PDT 24
Peak memory 195152 kb
Host smart-a7132d49-0d3a-44d1-88ab-31c86bdf3cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620869111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2620869111
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1779519124
Short name T485
Test name
Test status
Simulation time 1020511708 ps
CPU time 60.12 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:32:33 PM PDT 24
Peak memory 200296 kb
Host smart-70426315-cf58-4f6f-9ae2-06c37947f9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779519124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1779519124
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3916912297
Short name T429
Test name
Test status
Simulation time 3819488951 ps
CPU time 66.51 seconds
Started Jul 14 06:31:25 PM PDT 24
Finished Jul 14 06:32:34 PM PDT 24
Peak memory 200388 kb
Host smart-3cabbbdf-d082-484c-a398-bdf5eb232404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916912297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3916912297
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4256287502
Short name T358
Test name
Test status
Simulation time 11514305440 ps
CPU time 367.08 seconds
Started Jul 14 06:31:27 PM PDT 24
Finished Jul 14 06:37:36 PM PDT 24
Peak memory 434548 kb
Host smart-1be97088-cfd9-4a3d-ad07-417da593876d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256287502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4256287502
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3713192091
Short name T156
Test name
Test status
Simulation time 5889999205 ps
CPU time 54.58 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:32:27 PM PDT 24
Peak memory 200296 kb
Host smart-c1a769d7-0aae-4146-aaed-77171d53266c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713192091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3713192091
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1983025315
Short name T398
Test name
Test status
Simulation time 3316940560 ps
CPU time 41.21 seconds
Started Jul 14 06:31:41 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200316 kb
Host smart-b2bc6111-3a80-4b37-b446-b2e839330fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983025315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1983025315
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3595972206
Short name T76
Test name
Test status
Simulation time 673912488 ps
CPU time 11.15 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:31:43 PM PDT 24
Peak memory 200296 kb
Host smart-36b58c57-611f-4b2e-afb1-033fdd75abc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595972206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3595972206
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2766336720
Short name T402
Test name
Test status
Simulation time 29732927050 ps
CPU time 280.79 seconds
Started Jul 14 06:31:30 PM PDT 24
Finished Jul 14 06:36:12 PM PDT 24
Peak memory 200388 kb
Host smart-d0d5303f-2bd6-4570-9f13-133a0b9cde86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766336720 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2766336720
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4093829661
Short name T35
Test name
Test status
Simulation time 3134181933 ps
CPU time 57.09 seconds
Started Jul 14 06:31:25 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200420 kb
Host smart-57a3c70f-5dba-4e56-a24a-927cca9a6008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093829661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4093829661
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1741746819
Short name T168
Test name
Test status
Simulation time 30073709 ps
CPU time 0.58 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:31:36 PM PDT 24
Peak memory 195112 kb
Host smart-82c981a7-7162-45b6-aa0a-c897dcfbaa1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741746819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1741746819
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2782231003
Short name T476
Test name
Test status
Simulation time 6981968073 ps
CPU time 89.48 seconds
Started Jul 14 06:31:36 PM PDT 24
Finished Jul 14 06:33:07 PM PDT 24
Peak memory 200376 kb
Host smart-d2da8f6e-2d11-407b-a73f-940611303de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782231003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2782231003
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3247087865
Short name T8
Test name
Test status
Simulation time 1091933357 ps
CPU time 19.53 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 200320 kb
Host smart-9aad9831-8cbe-44de-8498-952a26c0c50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247087865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3247087865
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1500432299
Short name T393
Test name
Test status
Simulation time 4445388714 ps
CPU time 538.45 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:40:44 PM PDT 24
Peak memory 501748 kb
Host smart-e866e300-53f6-4947-b603-be616b956fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500432299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1500432299
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1800859473
Short name T201
Test name
Test status
Simulation time 1252496683 ps
CPU time 16.15 seconds
Started Jul 14 06:31:25 PM PDT 24
Finished Jul 14 06:31:44 PM PDT 24
Peak memory 200224 kb
Host smart-035d6fea-63db-4f78-994d-9733dc88170d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800859473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1800859473
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.213574299
Short name T221
Test name
Test status
Simulation time 4357885703 ps
CPU time 61.71 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:32:47 PM PDT 24
Peak memory 200424 kb
Host smart-62aa22aa-9fd7-4a91-87c5-f1d530514ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213574299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.213574299
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1670616819
Short name T132
Test name
Test status
Simulation time 374458299 ps
CPU time 15.08 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:31:47 PM PDT 24
Peak memory 200304 kb
Host smart-4c452761-c716-4131-ba25-0cb6358954d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670616819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1670616819
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1551029178
Short name T85
Test name
Test status
Simulation time 33058071839 ps
CPU time 814.38 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:45:15 PM PDT 24
Peak memory 508272 kb
Host smart-1a612596-f03c-4523-88bb-b4e21095eaf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551029178 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1551029178
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3807794510
Short name T366
Test name
Test status
Simulation time 1062404572 ps
CPU time 19.76 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 200348 kb
Host smart-fe5c0503-1293-4734-837d-c1075bed3cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807794510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3807794510
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3787230559
Short name T205
Test name
Test status
Simulation time 28798351 ps
CPU time 0.57 seconds
Started Jul 14 06:31:44 PM PDT 24
Finished Jul 14 06:31:47 PM PDT 24
Peak memory 195116 kb
Host smart-4d55f488-5e16-4ac2-b1a4-1cc833ea0a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787230559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3787230559
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4152650203
Short name T359
Test name
Test status
Simulation time 250854069 ps
CPU time 14.59 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:31:51 PM PDT 24
Peak memory 200232 kb
Host smart-1ca45d2f-4b1b-49ea-99a2-be0b0f1663e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152650203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4152650203
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.191516476
Short name T318
Test name
Test status
Simulation time 1820121371 ps
CPU time 20.7 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:32:00 PM PDT 24
Peak memory 200292 kb
Host smart-ae8f60fe-94c4-4ad5-b588-0276f68213c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191516476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.191516476
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4259126152
Short name T143
Test name
Test status
Simulation time 4925467817 ps
CPU time 780.44 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:44:37 PM PDT 24
Peak memory 672396 kb
Host smart-d3c1cfd2-7198-44c6-ab2d-f8c7426ee59a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259126152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4259126152
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3459353758
Short name T191
Test name
Test status
Simulation time 65121375800 ps
CPU time 177.95 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:34:43 PM PDT 24
Peak memory 200292 kb
Host smart-d303a07f-6660-40eb-85b2-eee02e945c42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459353758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3459353758
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3920756160
Short name T250
Test name
Test status
Simulation time 31013810713 ps
CPU time 129.55 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:33:54 PM PDT 24
Peak memory 200352 kb
Host smart-77613a7f-c41a-4f3d-b83a-ac1f16bf950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920756160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3920756160
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4004919966
Short name T2
Test name
Test status
Simulation time 138845095 ps
CPU time 3.28 seconds
Started Jul 14 06:31:36 PM PDT 24
Finished Jul 14 06:31:41 PM PDT 24
Peak memory 200304 kb
Host smart-d589a1ba-f20c-4c32-855b-5143817ba724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004919966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4004919966
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1599410881
Short name T145
Test name
Test status
Simulation time 21604513761 ps
CPU time 2611.53 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 07:15:16 PM PDT 24
Peak memory 745624 kb
Host smart-106fc0c8-f8f1-4c57-9e63-e634258b2933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599410881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1599410881
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3399982951
Short name T413
Test name
Test status
Simulation time 15694488415 ps
CPU time 72.58 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:32:53 PM PDT 24
Peak memory 200368 kb
Host smart-a62a1760-9045-4cd0-90b6-e9ef71f3b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399982951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3399982951
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.669771609
Short name T1
Test name
Test status
Simulation time 15878788 ps
CPU time 0.61 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:31:34 PM PDT 24
Peak memory 196188 kb
Host smart-d06beae5-6ee0-4bc4-9901-eda77249a1b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669771609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.669771609
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1904179878
Short name T154
Test name
Test status
Simulation time 375374314 ps
CPU time 5.27 seconds
Started Jul 14 06:31:36 PM PDT 24
Finished Jul 14 06:31:43 PM PDT 24
Peak memory 200292 kb
Host smart-25534ac4-0069-4066-8f96-b8bc5be83e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904179878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1904179878
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2562600741
Short name T367
Test name
Test status
Simulation time 457683502 ps
CPU time 2.45 seconds
Started Jul 14 06:31:34 PM PDT 24
Finished Jul 14 06:31:38 PM PDT 24
Peak memory 200316 kb
Host smart-e0ba30e0-c80d-45d9-b0bb-63c2aea2d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562600741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2562600741
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.762063962
Short name T22
Test name
Test status
Simulation time 21955261165 ps
CPU time 962.04 seconds
Started Jul 14 06:31:36 PM PDT 24
Finished Jul 14 06:47:40 PM PDT 24
Peak memory 757596 kb
Host smart-3125e4e8-d103-410b-b6f2-aa452861a35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762063962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.762063962
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.147213254
Short name T160
Test name
Test status
Simulation time 48297048964 ps
CPU time 131.78 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:33:45 PM PDT 24
Peak memory 200356 kb
Host smart-6f49ed38-d7a3-4e2c-9e3f-ebac6cef10a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147213254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.147213254
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.45411671
Short name T403
Test name
Test status
Simulation time 10847687581 ps
CPU time 160.68 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:34:20 PM PDT 24
Peak memory 209704 kb
Host smart-c9efe818-c927-4eea-b714-116ef6463b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45411671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.45411671
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.743639593
Short name T138
Test name
Test status
Simulation time 2273944477 ps
CPU time 12.63 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 200416 kb
Host smart-6329edb2-38f2-4663-8948-8c80b422f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743639593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.743639593
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2001731193
Short name T475
Test name
Test status
Simulation time 155235164605 ps
CPU time 1645.59 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 767032 kb
Host smart-c0429ebb-ec3c-4a0d-8d1e-5f4ca7c5ee9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001731193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2001731193
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.36860711
Short name T324
Test name
Test status
Simulation time 2408098087 ps
CPU time 125.36 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:33:46 PM PDT 24
Peak memory 200324 kb
Host smart-e59b7a22-3970-4e3f-83ed-91dc7ad80802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36860711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.36860711
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1164472599
Short name T401
Test name
Test status
Simulation time 14113690 ps
CPU time 0.63 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:31:41 PM PDT 24
Peak memory 196868 kb
Host smart-6e1b1d39-c8a1-4265-b286-6c3dd3635adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164472599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1164472599
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3893435088
Short name T12
Test name
Test status
Simulation time 1858685312 ps
CPU time 50.85 seconds
Started Jul 14 06:31:34 PM PDT 24
Finished Jul 14 06:32:26 PM PDT 24
Peak memory 200320 kb
Host smart-fa8ba891-2f96-44c7-9c4d-2a4910449854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893435088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3893435088
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2143393013
Short name T151
Test name
Test status
Simulation time 1339021636 ps
CPU time 68.38 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:32:42 PM PDT 24
Peak memory 200232 kb
Host smart-e3138b1a-b4a7-4181-9468-ff41fee88ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143393013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2143393013
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.151111280
Short name T496
Test name
Test status
Simulation time 11539938201 ps
CPU time 498.33 seconds
Started Jul 14 06:31:34 PM PDT 24
Finished Jul 14 06:39:53 PM PDT 24
Peak memory 718432 kb
Host smart-61e2a764-041c-45b4-8d5d-f64fa455721a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151111280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.151111280
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1747424928
Short name T7
Test name
Test status
Simulation time 38456311980 ps
CPU time 247.59 seconds
Started Jul 14 06:31:34 PM PDT 24
Finished Jul 14 06:35:43 PM PDT 24
Peak memory 200360 kb
Host smart-78ee61c9-f72a-4636-89ae-b17d9058b5c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747424928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1747424928
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1018606877
Short name T301
Test name
Test status
Simulation time 1044694349 ps
CPU time 56.65 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:32:28 PM PDT 24
Peak memory 200320 kb
Host smart-ad672ce8-7d5c-4ccc-8823-f8bac801c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018606877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1018606877
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.546950664
Short name T202
Test name
Test status
Simulation time 994642606 ps
CPU time 11.15 seconds
Started Jul 14 06:31:32 PM PDT 24
Finished Jul 14 06:31:45 PM PDT 24
Peak memory 200328 kb
Host smart-6942d0e4-3760-4f54-836f-05365f149bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546950664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.546950664
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4030964652
Short name T391
Test name
Test status
Simulation time 14095637178 ps
CPU time 1240.24 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:52:20 PM PDT 24
Peak memory 709960 kb
Host smart-32292237-621e-4ab6-b6bb-2c9ee7bac479
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030964652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4030964652
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.111832039
Short name T51
Test name
Test status
Simulation time 4517038034 ps
CPU time 77.47 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:32:52 PM PDT 24
Peak memory 200400 kb
Host smart-55663cfc-9ac0-4150-85bd-f99a1c8f0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111832039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.111832039
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2302442416
Short name T491
Test name
Test status
Simulation time 197978773 ps
CPU time 0.56 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:31:37 PM PDT 24
Peak memory 196152 kb
Host smart-1cd88b75-2744-420a-99d6-21a825c4210f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302442416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2302442416
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.301928371
Short name T50
Test name
Test status
Simulation time 476767897 ps
CPU time 27.83 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:32:07 PM PDT 24
Peak memory 200204 kb
Host smart-01169e44-f107-4497-afc2-85c8332f6e3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301928371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.301928371
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1428893684
Short name T148
Test name
Test status
Simulation time 766518747 ps
CPU time 39.69 seconds
Started Jul 14 06:31:48 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 200308 kb
Host smart-5464eb94-34ec-4c63-8992-6b86fb63eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428893684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1428893684
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3821142523
Short name T432
Test name
Test status
Simulation time 5503694276 ps
CPU time 992.05 seconds
Started Jul 14 06:31:40 PM PDT 24
Finished Jul 14 06:48:15 PM PDT 24
Peak memory 718388 kb
Host smart-74d0bf9d-419c-41c9-9555-1d9bd70c8299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821142523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3821142523
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1900854871
Short name T285
Test name
Test status
Simulation time 27445031688 ps
CPU time 154.64 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:34:25 PM PDT 24
Peak memory 200332 kb
Host smart-2d894387-c14a-40ef-bdd5-5e6d5a214822
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900854871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1900854871
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3821821719
Short name T376
Test name
Test status
Simulation time 23437406274 ps
CPU time 209.89 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:35:04 PM PDT 24
Peak memory 216580 kb
Host smart-69fec684-e78d-402a-84ef-11fb9e0fb9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821821719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3821821719
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1728518361
Short name T473
Test name
Test status
Simulation time 1112276852 ps
CPU time 11.67 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:31:51 PM PDT 24
Peak memory 200348 kb
Host smart-d0b85c3b-00cf-46e4-a254-bc486fcdcda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728518361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1728518361
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2917878327
Short name T69
Test name
Test status
Simulation time 34905410942 ps
CPU time 446.82 seconds
Started Jul 14 06:31:40 PM PDT 24
Finished Jul 14 06:39:09 PM PDT 24
Peak memory 216708 kb
Host smart-2a73c2e0-4a9a-435d-b1b8-4bc801ec812d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917878327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2917878327
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1666553497
Short name T317
Test name
Test status
Simulation time 13056981267 ps
CPU time 40.25 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:32:24 PM PDT 24
Peak memory 200304 kb
Host smart-ea7f9fae-6156-4f89-97bf-939812e3fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666553497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1666553497
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1906982698
Short name T311
Test name
Test status
Simulation time 13275261 ps
CPU time 0.61 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:06 PM PDT 24
Peak memory 196216 kb
Host smart-c7b326a7-b1f5-4bb9-b7d0-70ae72e52ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906982698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1906982698
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3233691484
Short name T357
Test name
Test status
Simulation time 172180928 ps
CPU time 4.81 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:11 PM PDT 24
Peak memory 200272 kb
Host smart-1d9b3b3c-755c-40fe-bb88-8c64a2988089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233691484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3233691484
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4241764217
Short name T515
Test name
Test status
Simulation time 3304701479 ps
CPU time 48.89 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:56 PM PDT 24
Peak memory 200476 kb
Host smart-8dc81fbb-6575-4927-a65f-d4d7f8712b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241764217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4241764217
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1127387336
Short name T166
Test name
Test status
Simulation time 4452073128 ps
CPU time 885.37 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:45:50 PM PDT 24
Peak memory 753328 kb
Host smart-88975a6f-503b-4a79-8b52-71ba9c9e5fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127387336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1127387336
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2073225995
Short name T521
Test name
Test status
Simulation time 7970785227 ps
CPU time 76.11 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:32:22 PM PDT 24
Peak memory 200196 kb
Host smart-f23c7415-cabc-4fab-a057-d19d4fc3eaf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073225995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2073225995
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1898216574
Short name T459
Test name
Test status
Simulation time 4835627223 ps
CPU time 96.58 seconds
Started Jul 14 06:31:06 PM PDT 24
Finished Jul 14 06:32:45 PM PDT 24
Peak memory 200356 kb
Host smart-7d539e3c-f3ef-4fde-9bab-b81d0ecef3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898216574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1898216574
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2080884587
Short name T60
Test name
Test status
Simulation time 59482935 ps
CPU time 0.9 seconds
Started Jul 14 06:31:06 PM PDT 24
Finished Jul 14 06:31:09 PM PDT 24
Peak memory 218248 kb
Host smart-40ea6651-0a24-4f49-b4c0-f96924c08774
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080884587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2080884587
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1345632941
Short name T254
Test name
Test status
Simulation time 80041369 ps
CPU time 3.71 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:09 PM PDT 24
Peak memory 200316 kb
Host smart-ab1a0989-04a4-4b41-a792-313e533247f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345632941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1345632941
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2699634414
Short name T479
Test name
Test status
Simulation time 7691329029 ps
CPU time 1155.59 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:50:22 PM PDT 24
Peak memory 764336 kb
Host smart-8198cf50-7e9f-4381-9d1b-3d58c3142c3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699634414 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2699634414
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3790646533
Short name T410
Test name
Test status
Simulation time 10925948594 ps
CPU time 43.25 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 06:31:49 PM PDT 24
Peak memory 200276 kb
Host smart-ed6f3fce-39a2-4a3d-8c7a-d73c86a773ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3790646533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3790646533
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.668973577
Short name T421
Test name
Test status
Simulation time 10483324417 ps
CPU time 65.94 seconds
Started Jul 14 06:31:03 PM PDT 24
Finished Jul 14 06:32:11 PM PDT 24
Peak memory 200352 kb
Host smart-a689c591-b3c1-46b3-a78f-b53ca809e5aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=668973577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.668973577
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1436578934
Short name T175
Test name
Test status
Simulation time 15898490232 ps
CPU time 125.79 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:33:16 PM PDT 24
Peak memory 200340 kb
Host smart-d61170a3-0f58-490f-86d3-57e8bc36d764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1436578934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1436578934
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3071450410
Short name T36
Test name
Test status
Simulation time 10093401135 ps
CPU time 561.38 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:40:32 PM PDT 24
Peak memory 200376 kb
Host smart-ae1dff17-8d4c-41e1-b702-5430ff842189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3071450410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3071450410
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3318363345
Short name T323
Test name
Test status
Simulation time 213439806437 ps
CPU time 2601.65 seconds
Started Jul 14 06:31:04 PM PDT 24
Finished Jul 14 07:14:29 PM PDT 24
Peak memory 215872 kb
Host smart-bab93774-800a-4d68-9f54-ff06c32883dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3318363345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3318363345
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.4257513890
Short name T200
Test name
Test status
Simulation time 174023742174 ps
CPU time 2346.34 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 07:10:21 PM PDT 24
Peak memory 208508 kb
Host smart-9a3dd1af-1a41-4fc7-9c0a-efb0111c5998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4257513890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.4257513890
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3075465451
Short name T211
Test name
Test status
Simulation time 4068387749 ps
CPU time 50.87 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:59 PM PDT 24
Peak memory 200264 kb
Host smart-18c0c95c-fa52-4c66-adde-a65fc882aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075465451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3075465451
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1524076918
Short name T3
Test name
Test status
Simulation time 11550589 ps
CPU time 0.6 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:31:46 PM PDT 24
Peak memory 195112 kb
Host smart-cbc50ba5-4b4a-41ba-a2b7-889a2d268051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524076918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1524076918
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1188453861
Short name T332
Test name
Test status
Simulation time 154185114 ps
CPU time 9.12 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:31:51 PM PDT 24
Peak memory 200316 kb
Host smart-95bbe23e-a7f2-40b8-8acf-ed21df90d13c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188453861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1188453861
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1487491321
Short name T261
Test name
Test status
Simulation time 327948115 ps
CPU time 8.33 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:31:45 PM PDT 24
Peak memory 200412 kb
Host smart-ee094f37-9973-411f-9efa-2bbbfefb0a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487491321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1487491321
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.99223696
Short name T493
Test name
Test status
Simulation time 2966190173 ps
CPU time 265.5 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:36:13 PM PDT 24
Peak memory 600716 kb
Host smart-4be7931b-e528-4cb9-b37a-16af90588b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99223696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.99223696
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1031813391
Short name T165
Test name
Test status
Simulation time 4429742843 ps
CPU time 105.86 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:33:32 PM PDT 24
Peak memory 200368 kb
Host smart-e2b52a13-06f7-4087-a3dd-05927fa402ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031813391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1031813391
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1129030824
Short name T457
Test name
Test status
Simulation time 1844415355 ps
CPU time 105.98 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:33:35 PM PDT 24
Peak memory 200340 kb
Host smart-6b674fa9-3095-456c-b55e-8b19500d1183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129030824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1129030824
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3950867471
Short name T438
Test name
Test status
Simulation time 757773391 ps
CPU time 2.58 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:31:44 PM PDT 24
Peak memory 200332 kb
Host smart-c5751889-038d-47b4-ac86-5d856fb23318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950867471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3950867471
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3794478896
Short name T498
Test name
Test status
Simulation time 128652191106 ps
CPU time 3569.84 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 07:31:10 PM PDT 24
Peak memory 812108 kb
Host smart-f2b1fc74-eaf0-4ddc-adda-589216b47d0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794478896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3794478896
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4229817986
Short name T442
Test name
Test status
Simulation time 273528575 ps
CPU time 3.7 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:31:50 PM PDT 24
Peak memory 200256 kb
Host smart-c4007811-db71-4a9d-9966-0b1d4799b7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229817986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4229817986
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2674032965
Short name T291
Test name
Test status
Simulation time 16754490 ps
CPU time 0.61 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:31:37 PM PDT 24
Peak memory 196116 kb
Host smart-053e439e-91bb-420f-bbb3-dda07fa9b092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674032965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2674032965
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1244898945
Short name T443
Test name
Test status
Simulation time 5146434635 ps
CPU time 79.36 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:33:01 PM PDT 24
Peak memory 200348 kb
Host smart-c9269a24-d06c-4c0f-8d18-d184125c1d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244898945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1244898945
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2459626431
Short name T103
Test name
Test status
Simulation time 19076321524 ps
CPU time 63.08 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:32:38 PM PDT 24
Peak memory 200356 kb
Host smart-e4b76e7f-0251-4064-8ac2-e05d0192de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459626431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2459626431
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2151947213
Short name T179
Test name
Test status
Simulation time 17636004724 ps
CPU time 771.93 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:44:37 PM PDT 24
Peak memory 686084 kb
Host smart-ed04dc63-f59e-40a0-bf82-04cb75f00374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151947213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2151947213
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3126628376
Short name T171
Test name
Test status
Simulation time 6346667251 ps
CPU time 93.05 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:33:15 PM PDT 24
Peak memory 200388 kb
Host smart-cf4a4f30-43d4-455e-9f3b-ee446ad2d037
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126628376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3126628376
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4071189640
Short name T506
Test name
Test status
Simulation time 4207187033 ps
CPU time 57.87 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:32:43 PM PDT 24
Peak memory 200312 kb
Host smart-30942f17-dcee-4251-8337-11b003b97607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071189640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4071189640
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.718979833
Short name T288
Test name
Test status
Simulation time 580502462 ps
CPU time 12.55 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 200184 kb
Host smart-b4fd0e92-efda-4bfa-8b10-23302f7576c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718979833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.718979833
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1295842606
Short name T79
Test name
Test status
Simulation time 246756141980 ps
CPU time 940.85 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:47:17 PM PDT 24
Peak memory 208604 kb
Host smart-fb63d26e-68d6-4a2b-956f-801ab3a1b6ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295842606 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1295842606
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2582727382
Short name T434
Test name
Test status
Simulation time 1812744749 ps
CPU time 33.11 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:32:15 PM PDT 24
Peak memory 200352 kb
Host smart-985ef3ff-8915-40c5-a0d1-6a2cc47a9cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582727382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2582727382
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1934219206
Short name T390
Test name
Test status
Simulation time 12622084 ps
CPU time 0.6 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:31:45 PM PDT 24
Peak memory 196192 kb
Host smart-70d5e46d-d905-4076-9795-2af9aaae99f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934219206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1934219206
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3640680741
Short name T513
Test name
Test status
Simulation time 391646433 ps
CPU time 20.61 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:32:03 PM PDT 24
Peak memory 200236 kb
Host smart-4e3d3c76-bd96-4fa0-812d-106a844fd5f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640680741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3640680741
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4235881322
Short name T255
Test name
Test status
Simulation time 2970088173 ps
CPU time 54.38 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:32:36 PM PDT 24
Peak memory 200296 kb
Host smart-f9e7547d-d6c4-40b5-8670-2e9b0e8c36b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235881322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4235881322
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3251099879
Short name T18
Test name
Test status
Simulation time 5155432234 ps
CPU time 1013.92 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:48:36 PM PDT 24
Peak memory 738000 kb
Host smart-338fa1b0-7012-4795-9df1-49a41bd466f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251099879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3251099879
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3080751761
Short name T440
Test name
Test status
Simulation time 17276688814 ps
CPU time 39.77 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200348 kb
Host smart-5d63fac5-8be0-4d18-ae53-937957eef7be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080751761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3080751761
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3648738414
Short name T238
Test name
Test status
Simulation time 3511340045 ps
CPU time 49.13 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:32:38 PM PDT 24
Peak memory 200368 kb
Host smart-c63f37db-c49c-463a-bba9-445a2a04977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648738414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3648738414
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1841600789
Short name T480
Test name
Test status
Simulation time 1763692662 ps
CPU time 9.27 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:31:50 PM PDT 24
Peak memory 200364 kb
Host smart-476189c8-0145-4133-97a9-54f1c4d0b46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841600789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1841600789
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.83804172
Short name T419
Test name
Test status
Simulation time 332686937100 ps
CPU time 1381.82 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:54:42 PM PDT 24
Peak memory 620236 kb
Host smart-f407b33f-4680-445b-bc49-127c4f503cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83804172 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.83804172
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3458036673
Short name T251
Test name
Test status
Simulation time 2077646962 ps
CPU time 63.14 seconds
Started Jul 14 06:31:37 PM PDT 24
Finished Jul 14 06:32:43 PM PDT 24
Peak memory 200196 kb
Host smart-179dc436-0dc5-4262-863f-0957490100fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458036673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3458036673
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4238073077
Short name T320
Test name
Test status
Simulation time 12598026 ps
CPU time 0.59 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:31:51 PM PDT 24
Peak memory 195160 kb
Host smart-bd7ac8cb-65f7-4500-9122-e6ef677007be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238073077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4238073077
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2694632326
Short name T467
Test name
Test status
Simulation time 3778356847 ps
CPU time 49.7 seconds
Started Jul 14 06:31:40 PM PDT 24
Finished Jul 14 06:32:32 PM PDT 24
Peak memory 200360 kb
Host smart-ba2297b6-1e7b-4b21-a185-a38f6efc377d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694632326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2694632326
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.182409207
Short name T360
Test name
Test status
Simulation time 2482273758 ps
CPU time 34.5 seconds
Started Jul 14 06:31:35 PM PDT 24
Finished Jul 14 06:32:11 PM PDT 24
Peak memory 200432 kb
Host smart-be29060b-2686-45c4-84d6-b9fc2f766742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182409207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.182409207
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.921921143
Short name T471
Test name
Test status
Simulation time 1229332300 ps
CPU time 153.06 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:34:23 PM PDT 24
Peak memory 333416 kb
Host smart-6b01ed7b-336b-4ec0-bcd4-2f53c078d27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921921143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.921921143
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.386700766
Short name T227
Test name
Test status
Simulation time 18905919559 ps
CPU time 212.93 seconds
Started Jul 14 06:31:48 PM PDT 24
Finished Jul 14 06:35:24 PM PDT 24
Peak memory 200320 kb
Host smart-72a4a886-19fe-43b2-98b8-e9e4b4131c88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386700766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.386700766
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4013476973
Short name T404
Test name
Test status
Simulation time 3607555243 ps
CPU time 64.71 seconds
Started Jul 14 06:31:38 PM PDT 24
Finished Jul 14 06:32:46 PM PDT 24
Peak memory 200284 kb
Host smart-1ef01147-2310-423d-9a08-291a3112024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013476973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4013476973
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1278128291
Short name T246
Test name
Test status
Simulation time 405036307 ps
CPU time 16.05 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:32:01 PM PDT 24
Peak memory 200364 kb
Host smart-3630b056-a2da-4b76-b7a5-c064e9c50410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278128291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1278128291
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4239696444
Short name T37
Test name
Test status
Simulation time 69227291746 ps
CPU time 2640.1 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 07:15:49 PM PDT 24
Peak memory 776084 kb
Host smart-269d6a47-dab8-4726-b792-2b49ec06d5f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239696444 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4239696444
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2588963514
Short name T159
Test name
Test status
Simulation time 1507260212 ps
CPU time 13.95 seconds
Started Jul 14 06:31:48 PM PDT 24
Finished Jul 14 06:32:05 PM PDT 24
Peak memory 200496 kb
Host smart-8475b25d-dc59-4c64-9530-fc7ed99d4cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588963514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2588963514
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.571597239
Short name T47
Test name
Test status
Simulation time 16574356 ps
CPU time 0.62 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:31:50 PM PDT 24
Peak memory 196208 kb
Host smart-8f9a81c6-b397-4bfb-b1ee-c9dc783c092e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571597239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.571597239
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1500046202
Short name T231
Test name
Test status
Simulation time 2842137809 ps
CPU time 41.13 seconds
Started Jul 14 06:31:44 PM PDT 24
Finished Jul 14 06:32:28 PM PDT 24
Peak memory 200312 kb
Host smart-576e25c5-9a80-43d4-9b63-a1161cf4566a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500046202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1500046202
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3894220639
Short name T306
Test name
Test status
Simulation time 140826114 ps
CPU time 3.68 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:31:54 PM PDT 24
Peak memory 200296 kb
Host smart-7eee8256-49f1-4eee-823f-7d39ceaa5684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894220639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3894220639
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3682248992
Short name T478
Test name
Test status
Simulation time 14578110134 ps
CPU time 544.96 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:40:50 PM PDT 24
Peak memory 623300 kb
Host smart-3274be5c-d479-4d05-a7e2-c8366e7ebaed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682248992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3682248992
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1286545856
Short name T492
Test name
Test status
Simulation time 7605505399 ps
CPU time 131.54 seconds
Started Jul 14 06:31:48 PM PDT 24
Finished Jul 14 06:34:02 PM PDT 24
Peak memory 200316 kb
Host smart-b51a2e3e-7fea-4260-b902-4b0b6f13c11f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286545856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1286545856
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2495059128
Short name T407
Test name
Test status
Simulation time 14008694311 ps
CPU time 87.77 seconds
Started Jul 14 06:31:39 PM PDT 24
Finished Jul 14 06:33:10 PM PDT 24
Peak memory 200584 kb
Host smart-1e71dd1f-1a8a-4531-83e8-7ab1b0466825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495059128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2495059128
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.124427508
Short name T339
Test name
Test status
Simulation time 204510083 ps
CPU time 10.21 seconds
Started Jul 14 06:31:41 PM PDT 24
Finished Jul 14 06:31:54 PM PDT 24
Peak memory 200312 kb
Host smart-6ea43cd7-8b71-43d6-adc7-097021ccc984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124427508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.124427508
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.739418084
Short name T13
Test name
Test status
Simulation time 24870544632 ps
CPU time 653.13 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:42:41 PM PDT 24
Peak memory 216744 kb
Host smart-0795737e-9cf1-4d45-b781-b5b072fd5da2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739418084 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.739418084
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.276021756
Short name T82
Test name
Test status
Simulation time 12807528575 ps
CPU time 60.35 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:32:45 PM PDT 24
Peak memory 200388 kb
Host smart-a9307ce2-4509-41e5-a14b-e8c969637317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276021756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.276021756
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4144873216
Short name T455
Test name
Test status
Simulation time 40080426 ps
CPU time 0.65 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 196188 kb
Host smart-1404fc5e-cade-43cc-99ef-505de64e996b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144873216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4144873216
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3576309590
Short name T439
Test name
Test status
Simulation time 1032944151 ps
CPU time 56.25 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:32:48 PM PDT 24
Peak memory 200228 kb
Host smart-2a66e2d1-2882-4140-89f8-adbc904afcff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576309590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3576309590
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.809320133
Short name T19
Test name
Test status
Simulation time 1152037078 ps
CPU time 15.14 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:32:04 PM PDT 24
Peak memory 200308 kb
Host smart-120e8330-4604-4687-aab8-00d14a9a0779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809320133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.809320133
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.522072756
Short name T153
Test name
Test status
Simulation time 7595331416 ps
CPU time 731.75 seconds
Started Jul 14 06:31:44 PM PDT 24
Finished Jul 14 06:43:59 PM PDT 24
Peak memory 669688 kb
Host smart-b10045ca-7c2c-4e31-b9fd-2c61710afdc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522072756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.522072756
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.880350509
Short name T162
Test name
Test status
Simulation time 4087052634 ps
CPU time 35.2 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:32:24 PM PDT 24
Peak memory 200324 kb
Host smart-1d2e9838-ee14-4626-a813-981d94bbc936
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880350509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.880350509
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2842700166
Short name T375
Test name
Test status
Simulation time 8788801752 ps
CPU time 124.38 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:33:53 PM PDT 24
Peak memory 200420 kb
Host smart-b2848592-009f-47ac-b64c-22e8516ca205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842700166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2842700166
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.363974256
Short name T505
Test name
Test status
Simulation time 2436593557 ps
CPU time 7.12 seconds
Started Jul 14 06:31:43 PM PDT 24
Finished Jul 14 06:31:53 PM PDT 24
Peak memory 200328 kb
Host smart-da8aec87-dd1e-4d59-aecf-279b905990a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363974256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.363974256
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3584659611
Short name T68
Test name
Test status
Simulation time 23472259755 ps
CPU time 956.26 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:47:45 PM PDT 24
Peak memory 725616 kb
Host smart-26039079-46a8-4c2b-bc57-e0fc17c3d91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584659611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3584659611
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.400114915
Short name T343
Test name
Test status
Simulation time 2581082756 ps
CPU time 37.55 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:32:28 PM PDT 24
Peak memory 200400 kb
Host smart-a9091878-9ea1-4884-bdc8-1191da82cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400114915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.400114915
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.299153577
Short name T315
Test name
Test status
Simulation time 10739790 ps
CPU time 0.6 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 195112 kb
Host smart-59aa9ffa-7ee0-487b-97ef-f69df9238c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299153577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.299153577
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2672950154
Short name T430
Test name
Test status
Simulation time 2190468686 ps
CPU time 31.29 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:32:23 PM PDT 24
Peak memory 200296 kb
Host smart-974f62cb-3504-49ca-9b54-8c23269d2818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672950154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2672950154
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3856669247
Short name T445
Test name
Test status
Simulation time 3236724286 ps
CPU time 12.5 seconds
Started Jul 14 06:31:50 PM PDT 24
Finished Jul 14 06:32:04 PM PDT 24
Peak memory 200348 kb
Host smart-9ab14fd8-327f-4de0-ac4d-f4ff4f814930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856669247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3856669247
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4126910952
Short name T522
Test name
Test status
Simulation time 10842302717 ps
CPU time 1515.33 seconds
Started Jul 14 06:31:51 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 743956 kb
Host smart-765c59fc-0a58-4f07-a10a-a84b810dd991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126910952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4126910952
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2299376967
Short name T43
Test name
Test status
Simulation time 7309896244 ps
CPU time 90.78 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:33:15 PM PDT 24
Peak memory 200320 kb
Host smart-28459d0c-451d-42ca-812e-13a6adbda4a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299376967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2299376967
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1805383909
Short name T267
Test name
Test status
Simulation time 924012040 ps
CPU time 49.42 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:32:37 PM PDT 24
Peak memory 200332 kb
Host smart-520883c1-7e52-4ef5-9c8e-90c1fefc7e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805383909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1805383909
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2507944950
Short name T383
Test name
Test status
Simulation time 40037119 ps
CPU time 1.25 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:31:50 PM PDT 24
Peak memory 200344 kb
Host smart-a4c732cf-0129-4998-955a-0893ea609e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507944950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2507944950
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3177381831
Short name T137
Test name
Test status
Simulation time 12264228372 ps
CPU time 849.24 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:45:59 PM PDT 24
Peak memory 673336 kb
Host smart-888a9695-ef35-4454-adca-b21ede21cd39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177381831 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3177381831
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1728208051
Short name T104
Test name
Test status
Simulation time 3710564475 ps
CPU time 46.76 seconds
Started Jul 14 06:31:40 PM PDT 24
Finished Jul 14 06:32:30 PM PDT 24
Peak memory 200364 kb
Host smart-bc335aa9-7763-4aca-b164-59eec94b8270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728208051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1728208051
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1256646032
Short name T418
Test name
Test status
Simulation time 12451150 ps
CPU time 0.59 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:31:52 PM PDT 24
Peak memory 195168 kb
Host smart-91797008-14c3-4f15-a89f-f4e345e78f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256646032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1256646032
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2695228011
Short name T140
Test name
Test status
Simulation time 1342333945 ps
CPU time 35.99 seconds
Started Jul 14 06:31:40 PM PDT 24
Finished Jul 14 06:32:18 PM PDT 24
Peak memory 200264 kb
Host smart-0bc6d1d9-fc06-456c-a874-527556d89e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695228011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2695228011
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.4092685506
Short name T368
Test name
Test status
Simulation time 448508728 ps
CPU time 23.36 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:32:15 PM PDT 24
Peak memory 200356 kb
Host smart-ec7ed059-b920-4116-aca7-759437cb39de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092685506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4092685506
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3592409933
Short name T334
Test name
Test status
Simulation time 4770276132 ps
CPU time 741.59 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:44:09 PM PDT 24
Peak memory 662900 kb
Host smart-dd87692f-7424-4a3e-b3fe-da0d6e0e9801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592409933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3592409933
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3235987305
Short name T377
Test name
Test status
Simulation time 31361439181 ps
CPU time 96.67 seconds
Started Jul 14 06:31:48 PM PDT 24
Finished Jul 14 06:33:28 PM PDT 24
Peak memory 200316 kb
Host smart-5b05d881-70f6-4901-8896-725bb6eeb08b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235987305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3235987305
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3367327963
Short name T452
Test name
Test status
Simulation time 39491070923 ps
CPU time 166.6 seconds
Started Jul 14 06:31:42 PM PDT 24
Finished Jul 14 06:34:31 PM PDT 24
Peak memory 200348 kb
Host smart-33cc824b-f19c-4634-a5db-19d26b2fa0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367327963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3367327963
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2734959506
Short name T296
Test name
Test status
Simulation time 1227818434 ps
CPU time 10.08 seconds
Started Jul 14 06:31:57 PM PDT 24
Finished Jul 14 06:32:07 PM PDT 24
Peak memory 200304 kb
Host smart-cd6f4491-0395-44e2-8f7b-7596fb65de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734959506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2734959506
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2230890344
Short name T81
Test name
Test status
Simulation time 178363097032 ps
CPU time 2497.88 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 07:13:26 PM PDT 24
Peak memory 753568 kb
Host smart-0cac64ad-edeb-49d6-be23-adc6faa6ac4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230890344 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2230890344
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.9011090
Short name T193
Test name
Test status
Simulation time 3510341796 ps
CPU time 36.07 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:32:24 PM PDT 24
Peak memory 200392 kb
Host smart-ed4ba8f0-abc7-4ca7-9845-a1cd6f7ccc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9011090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.9011090
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2612349605
Short name T499
Test name
Test status
Simulation time 69507049 ps
CPU time 0.63 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:31:51 PM PDT 24
Peak memory 196796 kb
Host smart-887ec191-22b5-4cb8-b574-38af9660fbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612349605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2612349605
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2032278990
Short name T326
Test name
Test status
Simulation time 1507615222 ps
CPU time 46.2 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:32:34 PM PDT 24
Peak memory 200308 kb
Host smart-cf5443f2-fd4b-4b1b-9ebb-c5c9e3c4960a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032278990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2032278990
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3059145195
Short name T379
Test name
Test status
Simulation time 107011266 ps
CPU time 4.63 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:31:54 PM PDT 24
Peak memory 200236 kb
Host smart-02bad4b1-effa-42e6-bf7a-aa9b3cb144d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059145195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3059145195
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3615649990
Short name T520
Test name
Test status
Simulation time 11389343953 ps
CPU time 760.58 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:44:31 PM PDT 24
Peak memory 738504 kb
Host smart-382b19f3-e6fb-4721-b863-7633ddc77a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615649990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3615649990
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1423349505
Short name T340
Test name
Test status
Simulation time 3190855302 ps
CPU time 43.63 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:32:34 PM PDT 24
Peak memory 200280 kb
Host smart-73e3bd13-dbc5-41d3-a94a-7256267f25d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423349505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1423349505
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3400487630
Short name T508
Test name
Test status
Simulation time 1473232496 ps
CPU time 7.62 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:31:56 PM PDT 24
Peak memory 200300 kb
Host smart-4df80832-56e6-4666-944a-0016dfa5cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400487630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3400487630
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.966922851
Short name T257
Test name
Test status
Simulation time 819453640 ps
CPU time 13.63 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:32:02 PM PDT 24
Peak memory 200288 kb
Host smart-2b252f18-6fec-4b57-bde5-4e62aeeb41dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966922851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.966922851
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1676769401
Short name T80
Test name
Test status
Simulation time 16320867379 ps
CPU time 207.55 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:35:17 PM PDT 24
Peak memory 200340 kb
Host smart-35d92279-535c-46d9-ab3e-6eb8afaef1f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676769401 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1676769401
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.128238556
Short name T302
Test name
Test status
Simulation time 9230002464 ps
CPU time 44.06 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:32:36 PM PDT 24
Peak memory 200356 kb
Host smart-34d38460-44e3-495d-bd0f-e782861224b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128238556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.128238556
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2086430975
Short name T45
Test name
Test status
Simulation time 49612798 ps
CPU time 0.65 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:31:50 PM PDT 24
Peak memory 196096 kb
Host smart-90fc132a-25b4-45f6-8e55-d8753b9ac2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086430975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2086430975
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3077252554
Short name T120
Test name
Test status
Simulation time 717787007 ps
CPU time 39.83 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:32:30 PM PDT 24
Peak memory 200288 kb
Host smart-a444a0bd-f69f-44a1-bb1b-7cd2b95114e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077252554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3077252554
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2899936682
Short name T395
Test name
Test status
Simulation time 676166535 ps
CPU time 3.47 seconds
Started Jul 14 06:31:51 PM PDT 24
Finished Jul 14 06:31:56 PM PDT 24
Peak memory 200248 kb
Host smart-78c4fb71-deee-4abc-a3e7-ab8140f62f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899936682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2899936682
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2663604579
Short name T91
Test name
Test status
Simulation time 2047342561 ps
CPU time 371.9 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:38:01 PM PDT 24
Peak memory 600972 kb
Host smart-ec72bd3c-d9a8-4e6c-a3aa-73127292d5eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663604579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2663604579
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3740005774
Short name T330
Test name
Test status
Simulation time 32327594583 ps
CPU time 101.37 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:33:30 PM PDT 24
Peak memory 200348 kb
Host smart-a3e2f97b-d1f9-43f6-b2a3-7d10e116f1d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740005774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3740005774
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4032777604
Short name T448
Test name
Test status
Simulation time 4244288298 ps
CPU time 78.04 seconds
Started Jul 14 06:31:47 PM PDT 24
Finished Jul 14 06:33:09 PM PDT 24
Peak memory 200332 kb
Host smart-e29f0541-1f6b-4f15-b76d-413716cc75cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032777604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4032777604
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2220971625
Short name T264
Test name
Test status
Simulation time 1555707498 ps
CPU time 15.9 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:32:05 PM PDT 24
Peak memory 200332 kb
Host smart-bd0c8c95-f3cc-4a61-83af-4b0675e5eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220971625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2220971625
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3511113168
Short name T150
Test name
Test status
Simulation time 26987568386 ps
CPU time 1331.37 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 704492 kb
Host smart-5c28d46c-4582-4447-87d7-f724d53b9529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511113168 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3511113168
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1943237785
Short name T185
Test name
Test status
Simulation time 35122531829 ps
CPU time 88.6 seconds
Started Jul 14 06:31:49 PM PDT 24
Finished Jul 14 06:33:20 PM PDT 24
Peak memory 200400 kb
Host smart-ee06ebf9-508b-4218-88eb-c7941356761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943237785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1943237785
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1112997152
Short name T249
Test name
Test status
Simulation time 19400325 ps
CPU time 0.62 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:31:11 PM PDT 24
Peak memory 195828 kb
Host smart-54b355c3-97a9-4272-baee-302a27a379a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112997152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1112997152
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.427341914
Short name T195
Test name
Test status
Simulation time 12297030465 ps
CPU time 48.63 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:32:03 PM PDT 24
Peak memory 200572 kb
Host smart-9583e08d-f9d8-4350-9c1f-9e0c7593d035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427341914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.427341914
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.205315929
Short name T371
Test name
Test status
Simulation time 5152577220 ps
CPU time 957.13 seconds
Started Jul 14 06:31:08 PM PDT 24
Finished Jul 14 06:47:06 PM PDT 24
Peak memory 716384 kb
Host smart-32e157f3-6dd3-416b-ba75-cb42005ecebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205315929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.205315929
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.130970350
Short name T213
Test name
Test status
Simulation time 29612392252 ps
CPU time 93.25 seconds
Started Jul 14 06:31:14 PM PDT 24
Finished Jul 14 06:32:49 PM PDT 24
Peak memory 200304 kb
Host smart-be6b63e3-fe21-44da-bf5b-d71c20790ace
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130970350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.130970350
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1503868400
Short name T450
Test name
Test status
Simulation time 2879060497 ps
CPU time 168.62 seconds
Started Jul 14 06:31:10 PM PDT 24
Finished Jul 14 06:33:59 PM PDT 24
Peak memory 200272 kb
Host smart-9141b6a6-602a-4092-97a5-a24936641364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503868400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1503868400
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.846009290
Short name T204
Test name
Test status
Simulation time 803235341 ps
CPU time 7.74 seconds
Started Jul 14 06:31:05 PM PDT 24
Finished Jul 14 06:31:15 PM PDT 24
Peak memory 200280 kb
Host smart-75509faf-0e71-41bc-bc71-eb7034c1e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846009290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.846009290
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.298686991
Short name T263
Test name
Test status
Simulation time 10053112164 ps
CPU time 191.11 seconds
Started Jul 14 06:31:10 PM PDT 24
Finished Jul 14 06:34:23 PM PDT 24
Peak memory 208492 kb
Host smart-9564054d-ffa6-416b-a733-dbbedd82ef0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298686991 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.298686991
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3615932182
Short name T194
Test name
Test status
Simulation time 2435238860 ps
CPU time 45.29 seconds
Started Jul 14 06:31:08 PM PDT 24
Finished Jul 14 06:31:54 PM PDT 24
Peak memory 200368 kb
Host smart-4a2a972d-c277-42cf-8367-ad6e820482f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3615932182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3615932182
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3581941091
Short name T456
Test name
Test status
Simulation time 1840632839 ps
CPU time 60.25 seconds
Started Jul 14 06:31:13 PM PDT 24
Finished Jul 14 06:32:15 PM PDT 24
Peak memory 200488 kb
Host smart-9dc3db34-61aa-4149-b7db-1b799972a222
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3581941091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3581941091
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1237284745
Short name T167
Test name
Test status
Simulation time 25213182525 ps
CPU time 77.09 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 200352 kb
Host smart-490927eb-7454-4bfd-a8f0-366f006dc5d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1237284745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1237284745
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1836774991
Short name T370
Test name
Test status
Simulation time 125148194969 ps
CPU time 576.86 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:40:55 PM PDT 24
Peak memory 200352 kb
Host smart-7921e222-fd24-4763-82c6-4ee090212397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1836774991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1836774991
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.351098015
Short name T134
Test name
Test status
Simulation time 160424874499 ps
CPU time 2200.29 seconds
Started Jul 14 06:31:10 PM PDT 24
Finished Jul 14 07:07:52 PM PDT 24
Peak memory 215972 kb
Host smart-f045a106-237b-4b8d-9360-510d21d5b618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=351098015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.351098015
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3297129663
Short name T519
Test name
Test status
Simulation time 784879107935 ps
CPU time 2246.36 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 07:08:36 PM PDT 24
Peak memory 216500 kb
Host smart-4dbb1f0d-b740-4a4b-b4f7-802027925209
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3297129663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3297129663
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4200870869
Short name T260
Test name
Test status
Simulation time 1914309256 ps
CPU time 19.64 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:31:37 PM PDT 24
Peak memory 200328 kb
Host smart-2a5e1610-b549-4fe0-8018-117ca0b33113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200870869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4200870869
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1898599606
Short name T278
Test name
Test status
Simulation time 14692632 ps
CPU time 0.6 seconds
Started Jul 14 06:31:56 PM PDT 24
Finished Jul 14 06:31:57 PM PDT 24
Peak memory 195148 kb
Host smart-d0e9c5fa-a614-423d-8068-2f24a749e7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898599606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1898599606
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2674808713
Short name T345
Test name
Test status
Simulation time 12911797172 ps
CPU time 61.15 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:32:50 PM PDT 24
Peak memory 200364 kb
Host smart-7a37366d-ef73-455d-ad94-ce779a3af3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674808713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2674808713
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2350299975
Short name T509
Test name
Test status
Simulation time 809144767 ps
CPU time 45.39 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:32:35 PM PDT 24
Peak memory 200320 kb
Host smart-d90f13be-701f-4817-9945-ad249cdce0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350299975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2350299975
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3394951919
Short name T397
Test name
Test status
Simulation time 3090834425 ps
CPU time 620.2 seconds
Started Jul 14 06:31:51 PM PDT 24
Finished Jul 14 06:42:13 PM PDT 24
Peak memory 657568 kb
Host smart-9db0383d-e16b-45e0-832a-0a436ec41c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394951919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3394951919
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4115484223
Short name T268
Test name
Test status
Simulation time 23374317460 ps
CPU time 51.19 seconds
Started Jul 14 06:31:45 PM PDT 24
Finished Jul 14 06:32:39 PM PDT 24
Peak memory 200312 kb
Host smart-55375839-d5d3-445b-abae-a162e3719c3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115484223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4115484223
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2019148774
Short name T67
Test name
Test status
Simulation time 8478376156 ps
CPU time 156.01 seconds
Started Jul 14 06:31:48 PM PDT 24
Finished Jul 14 06:34:27 PM PDT 24
Peak memory 208612 kb
Host smart-a62b37c0-d7ba-4eb1-8638-01fcff9597a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019148774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2019148774
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1889970540
Short name T232
Test name
Test status
Simulation time 673141247 ps
CPU time 6.97 seconds
Started Jul 14 06:31:46 PM PDT 24
Finished Jul 14 06:31:56 PM PDT 24
Peak memory 200184 kb
Host smart-ba21b42d-9701-4bad-8793-8a556eb01f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889970540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1889970540
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2331966227
Short name T354
Test name
Test status
Simulation time 82576991762 ps
CPU time 1091.46 seconds
Started Jul 14 06:31:52 PM PDT 24
Finished Jul 14 06:50:04 PM PDT 24
Peak memory 200252 kb
Host smart-d2103e22-be4e-4410-9ba7-1c7e37a96cb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331966227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2331966227
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3111587587
Short name T192
Test name
Test status
Simulation time 12912448138 ps
CPU time 99.5 seconds
Started Jul 14 06:31:56 PM PDT 24
Finished Jul 14 06:33:36 PM PDT 24
Peak memory 200364 kb
Host smart-b4189218-fbcf-4436-9364-e56d5973b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111587587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3111587587
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3499777331
Short name T57
Test name
Test status
Simulation time 24629568 ps
CPU time 0.62 seconds
Started Jul 14 06:32:02 PM PDT 24
Finished Jul 14 06:32:04 PM PDT 24
Peak memory 195128 kb
Host smart-63815096-652a-42f1-a7a2-0fffa3e9b300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499777331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3499777331
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2620945686
Short name T152
Test name
Test status
Simulation time 4465700670 ps
CPU time 56.71 seconds
Started Jul 14 06:31:58 PM PDT 24
Finished Jul 14 06:32:56 PM PDT 24
Peak memory 200420 kb
Host smart-0ed7df5e-8a88-4b08-b9ad-b273877fe375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620945686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2620945686
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2995061423
Short name T229
Test name
Test status
Simulation time 9071471149 ps
CPU time 1067.81 seconds
Started Jul 14 06:32:00 PM PDT 24
Finished Jul 14 06:49:48 PM PDT 24
Peak memory 739976 kb
Host smart-be89de26-53ee-49c2-b837-e93b64b5c07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995061423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2995061423
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.155643055
Short name T190
Test name
Test status
Simulation time 18510469342 ps
CPU time 166.86 seconds
Started Jul 14 06:31:59 PM PDT 24
Finished Jul 14 06:34:47 PM PDT 24
Peak memory 200340 kb
Host smart-b3987de9-3c44-4173-a3f4-532d4c06be96
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155643055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.155643055
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1022260881
Short name T280
Test name
Test status
Simulation time 6161814513 ps
CPU time 28.57 seconds
Started Jul 14 06:31:58 PM PDT 24
Finished Jul 14 06:32:26 PM PDT 24
Peak memory 200424 kb
Host smart-3356b9da-d5ad-4d50-909a-6f4ed95885ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022260881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1022260881
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1623425589
Short name T210
Test name
Test status
Simulation time 1618191976 ps
CPU time 11.19 seconds
Started Jul 14 06:31:54 PM PDT 24
Finished Jul 14 06:32:05 PM PDT 24
Peak memory 200312 kb
Host smart-bff8f739-b696-41d6-9a2f-6d4ab42d1c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623425589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1623425589
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.60235334
Short name T374
Test name
Test status
Simulation time 108864443099 ps
CPU time 986.02 seconds
Started Jul 14 06:31:59 PM PDT 24
Finished Jul 14 06:48:26 PM PDT 24
Peak memory 208616 kb
Host smart-b6f528c9-5a5e-408e-8c4b-a862ef09848c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60235334 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.60235334
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2247420641
Short name T84
Test name
Test status
Simulation time 4328510878 ps
CPU time 30.57 seconds
Started Jul 14 06:32:00 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 200412 kb
Host smart-9e2ec54e-c3a9-43b8-803d-0c1cc9e97ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247420641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2247420641
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2655309590
Short name T329
Test name
Test status
Simulation time 25914154 ps
CPU time 0.57 seconds
Started Jul 14 06:32:06 PM PDT 24
Finished Jul 14 06:32:07 PM PDT 24
Peak memory 195764 kb
Host smart-36b0773f-0321-482e-9f0d-b796f149ab63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655309590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2655309590
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4220375102
Short name T141
Test name
Test status
Simulation time 2329679228 ps
CPU time 62.27 seconds
Started Jul 14 06:31:59 PM PDT 24
Finished Jul 14 06:33:02 PM PDT 24
Peak memory 200268 kb
Host smart-59f720f0-9eb2-4655-b4ef-8f1376830362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220375102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4220375102
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1440606139
Short name T158
Test name
Test status
Simulation time 131684121 ps
CPU time 1.63 seconds
Started Jul 14 06:32:00 PM PDT 24
Finished Jul 14 06:32:02 PM PDT 24
Peak memory 200280 kb
Host smart-72b303ed-5526-40c3-b214-9e0211371a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440606139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1440606139
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3437270648
Short name T245
Test name
Test status
Simulation time 11441255172 ps
CPU time 520.59 seconds
Started Jul 14 06:31:58 PM PDT 24
Finished Jul 14 06:40:39 PM PDT 24
Peak memory 657548 kb
Host smart-ef8d69c6-ca8f-4a3f-a5c5-2b72cd5edf44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437270648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3437270648
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3873159783
Short name T305
Test name
Test status
Simulation time 5278308162 ps
CPU time 137.57 seconds
Started Jul 14 06:32:00 PM PDT 24
Finished Jul 14 06:34:18 PM PDT 24
Peak memory 200376 kb
Host smart-a00f4ec8-6981-48cf-9c90-83589d5627c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873159783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3873159783
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1117940069
Short name T66
Test name
Test status
Simulation time 89634192 ps
CPU time 0.83 seconds
Started Jul 14 06:32:02 PM PDT 24
Finished Jul 14 06:32:04 PM PDT 24
Peak memory 197988 kb
Host smart-00dbaf52-7eea-4a9d-a4ec-f2ff81da7147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117940069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1117940069
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.395905313
Short name T349
Test name
Test status
Simulation time 1284259735 ps
CPU time 14.08 seconds
Started Jul 14 06:32:01 PM PDT 24
Finished Jul 14 06:32:15 PM PDT 24
Peak memory 200328 kb
Host smart-eb578324-8c04-4a3c-9369-1948de414cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395905313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.395905313
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.580509477
Short name T271
Test name
Test status
Simulation time 2683786543 ps
CPU time 50.56 seconds
Started Jul 14 06:32:00 PM PDT 24
Finished Jul 14 06:32:51 PM PDT 24
Peak memory 200364 kb
Host smart-3e12b278-80bb-4781-9473-53dd619dca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580509477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.580509477
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2066521342
Short name T289
Test name
Test status
Simulation time 40247896 ps
CPU time 0.56 seconds
Started Jul 14 06:32:13 PM PDT 24
Finished Jul 14 06:32:14 PM PDT 24
Peak memory 195844 kb
Host smart-3b9e1dea-8378-4c66-968b-ad433ce4568d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066521342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2066521342
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.832583374
Short name T88
Test name
Test status
Simulation time 324923892 ps
CPU time 18.53 seconds
Started Jul 14 06:32:03 PM PDT 24
Finished Jul 14 06:32:22 PM PDT 24
Peak memory 200320 kb
Host smart-a259e05f-2e70-4b51-a18c-50e42715ca79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832583374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.832583374
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2432013831
Short name T436
Test name
Test status
Simulation time 2063842560 ps
CPU time 13.15 seconds
Started Jul 14 06:32:04 PM PDT 24
Finished Jul 14 06:32:18 PM PDT 24
Peak memory 200276 kb
Host smart-2596adbc-3562-4f83-9f2c-d225cc6f686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432013831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2432013831
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1609708682
Short name T441
Test name
Test status
Simulation time 6724877475 ps
CPU time 1260.5 seconds
Started Jul 14 06:32:05 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 742228 kb
Host smart-f9fbd457-0dcf-4e11-8ce6-684561fbeeb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1609708682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1609708682
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1572451174
Short name T225
Test name
Test status
Simulation time 9522947294 ps
CPU time 121.27 seconds
Started Jul 14 06:32:10 PM PDT 24
Finished Jul 14 06:34:13 PM PDT 24
Peak memory 200280 kb
Host smart-4aeae9d2-be47-47b1-a75d-fd5251e49a2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572451174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1572451174
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.539039674
Short name T155
Test name
Test status
Simulation time 7141205973 ps
CPU time 9.16 seconds
Started Jul 14 06:32:04 PM PDT 24
Finished Jul 14 06:32:14 PM PDT 24
Peak memory 200212 kb
Host smart-929778d5-d471-4a82-8d70-24c45ce0445c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539039674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.539039674
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1750583639
Short name T488
Test name
Test status
Simulation time 4222440444 ps
CPU time 12.09 seconds
Started Jul 14 06:32:03 PM PDT 24
Finished Jul 14 06:32:16 PM PDT 24
Peak memory 200380 kb
Host smart-7c528d1a-2e6d-4530-b315-e3015817b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750583639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1750583639
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4122357318
Short name T78
Test name
Test status
Simulation time 77964778084 ps
CPU time 2044.02 seconds
Started Jul 14 06:32:10 PM PDT 24
Finished Jul 14 07:06:15 PM PDT 24
Peak memory 761568 kb
Host smart-689c0d5d-a864-46a0-afc9-9f2ad859688e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122357318 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4122357318
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.55796561
Short name T352
Test name
Test status
Simulation time 748493288 ps
CPU time 13.26 seconds
Started Jul 14 06:32:09 PM PDT 24
Finished Jul 14 06:32:24 PM PDT 24
Peak memory 200268 kb
Host smart-d08f4734-28ce-4c03-82ba-75989d9645aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55796561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.55796561
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.4273881681
Short name T309
Test name
Test status
Simulation time 49424756 ps
CPU time 0.6 seconds
Started Jul 14 06:32:14 PM PDT 24
Finished Jul 14 06:32:16 PM PDT 24
Peak memory 195200 kb
Host smart-820c11a6-7d56-4396-80b3-214966ce93df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273881681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4273881681
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2283010055
Short name T286
Test name
Test status
Simulation time 2990809811 ps
CPU time 39.06 seconds
Started Jul 14 06:32:11 PM PDT 24
Finished Jul 14 06:32:51 PM PDT 24
Peak memory 200364 kb
Host smart-a6ec0de0-fd2f-458b-9f0b-be7e385d6b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283010055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2283010055
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.560699474
Short name T219
Test name
Test status
Simulation time 1457693459 ps
CPU time 19 seconds
Started Jul 14 06:32:11 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 200304 kb
Host smart-87c03108-59f3-4bc7-b8bd-8df636ab5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560699474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.560699474
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2324337873
Short name T274
Test name
Test status
Simulation time 911081324 ps
CPU time 140.44 seconds
Started Jul 14 06:32:10 PM PDT 24
Finished Jul 14 06:34:31 PM PDT 24
Peak memory 585312 kb
Host smart-205c97bf-1120-4a87-9fad-87f81d933462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324337873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2324337873
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1818074415
Short name T338
Test name
Test status
Simulation time 9713672052 ps
CPU time 81.81 seconds
Started Jul 14 06:32:09 PM PDT 24
Finished Jul 14 06:33:32 PM PDT 24
Peak memory 200392 kb
Host smart-36bb9f58-2b1c-40ce-bde0-d9a4a4f3291d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818074415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1818074415
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4194374136
Short name T518
Test name
Test status
Simulation time 37436727342 ps
CPU time 145.02 seconds
Started Jul 14 06:32:11 PM PDT 24
Finished Jul 14 06:34:37 PM PDT 24
Peak memory 216776 kb
Host smart-a33b9814-87f6-4e1d-896f-a8a21b3c4078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194374136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4194374136
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.279269412
Short name T110
Test name
Test status
Simulation time 995587980 ps
CPU time 16.74 seconds
Started Jul 14 06:32:11 PM PDT 24
Finished Jul 14 06:32:29 PM PDT 24
Peak memory 200316 kb
Host smart-e13826d1-091a-42c3-81f8-04e39ea741ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279269412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.279269412
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2297659685
Short name T38
Test name
Test status
Simulation time 33646306523 ps
CPU time 1318.73 seconds
Started Jul 14 06:32:14 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 741324 kb
Host smart-fc437b73-f200-4bc0-a0dc-22fe7bf014af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297659685 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2297659685
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2825044296
Short name T415
Test name
Test status
Simulation time 4331653877 ps
CPU time 58.52 seconds
Started Jul 14 06:32:14 PM PDT 24
Finished Jul 14 06:33:14 PM PDT 24
Peak memory 199496 kb
Host smart-88cd67e5-3da1-4c8d-9a0f-111a87eaa7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825044296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2825044296
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2021420527
Short name T308
Test name
Test status
Simulation time 12666436 ps
CPU time 0.58 seconds
Started Jul 14 06:32:16 PM PDT 24
Finished Jul 14 06:32:17 PM PDT 24
Peak memory 195848 kb
Host smart-45d175d0-8cd2-4242-b456-f573b1de3c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021420527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2021420527
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2944687860
Short name T217
Test name
Test status
Simulation time 582065387 ps
CPU time 33.14 seconds
Started Jul 14 06:32:15 PM PDT 24
Finished Jul 14 06:32:49 PM PDT 24
Peak memory 200272 kb
Host smart-dda858a9-13e4-42be-9449-5b6e67b3efa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944687860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2944687860
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1794136071
Short name T341
Test name
Test status
Simulation time 1812241011 ps
CPU time 47.03 seconds
Started Jul 14 06:32:15 PM PDT 24
Finished Jul 14 06:33:03 PM PDT 24
Peak memory 200232 kb
Host smart-de64b2c2-053a-4af7-9b6d-efbb26662709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794136071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1794136071
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1560008609
Short name T487
Test name
Test status
Simulation time 3769677398 ps
CPU time 775.76 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 06:45:15 PM PDT 24
Peak memory 756832 kb
Host smart-2c38132c-e59a-46ec-bb85-bbad4636493b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560008609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1560008609
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.388880163
Short name T504
Test name
Test status
Simulation time 2143828135 ps
CPU time 118.43 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 06:34:17 PM PDT 24
Peak memory 200300 kb
Host smart-edd7f685-3538-40ce-9b16-3bfd2e1a3457
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388880163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.388880163
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.240211234
Short name T28
Test name
Test status
Simulation time 813581222 ps
CPU time 23.66 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 06:32:43 PM PDT 24
Peak memory 200264 kb
Host smart-5ebe4c55-81d6-44c8-85bb-5ba92f5a3d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240211234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.240211234
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1410773283
Short name T454
Test name
Test status
Simulation time 766553639 ps
CPU time 5.82 seconds
Started Jul 14 06:32:15 PM PDT 24
Finished Jul 14 06:32:22 PM PDT 24
Peak memory 200296 kb
Host smart-4ca2a802-e829-4bba-8ef1-eb4280ca0861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410773283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1410773283
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.18284234
Short name T337
Test name
Test status
Simulation time 153499783371 ps
CPU time 1105.79 seconds
Started Jul 14 06:32:16 PM PDT 24
Finished Jul 14 06:50:43 PM PDT 24
Peak memory 677700 kb
Host smart-256a5ab4-6d38-493f-9ae3-083336b3a1bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284234 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.18284234
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3892725199
Short name T279
Test name
Test status
Simulation time 5598300713 ps
CPU time 83.57 seconds
Started Jul 14 06:32:15 PM PDT 24
Finished Jul 14 06:33:40 PM PDT 24
Peak memory 200340 kb
Host smart-840024ef-94a8-4022-8f2a-fc676046825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892725199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3892725199
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3707681317
Short name T412
Test name
Test status
Simulation time 11362443 ps
CPU time 0.56 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 06:32:19 PM PDT 24
Peak memory 195164 kb
Host smart-abb81522-9a1d-4fd1-b586-06ed721c0dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707681317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3707681317
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.317230060
Short name T298
Test name
Test status
Simulation time 166323838 ps
CPU time 2.76 seconds
Started Jul 14 06:32:18 PM PDT 24
Finished Jul 14 06:32:23 PM PDT 24
Peak memory 200300 kb
Host smart-e769b1fd-18fd-444e-9076-f0c4acadcb1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317230060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.317230060
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2584126444
Short name T4
Test name
Test status
Simulation time 7130388711 ps
CPU time 31.54 seconds
Started Jul 14 06:32:18 PM PDT 24
Finished Jul 14 06:32:52 PM PDT 24
Peak memory 208620 kb
Host smart-672d8122-acb6-495a-b81e-91844a0ff7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584126444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2584126444
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2908255616
Short name T105
Test name
Test status
Simulation time 19702171935 ps
CPU time 790.1 seconds
Started Jul 14 06:32:15 PM PDT 24
Finished Jul 14 06:45:27 PM PDT 24
Peak memory 694692 kb
Host smart-381dab0c-a07e-45f3-bf6f-77b5aee32667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908255616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2908255616
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.898666651
Short name T208
Test name
Test status
Simulation time 46024659081 ps
CPU time 131.71 seconds
Started Jul 14 06:32:16 PM PDT 24
Finished Jul 14 06:34:28 PM PDT 24
Peak memory 200304 kb
Host smart-7177e874-7467-4bef-9132-750fd917b450
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898666651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.898666651
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_smoke.1474044270
Short name T385
Test name
Test status
Simulation time 454867709 ps
CPU time 4.07 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 06:32:24 PM PDT 24
Peak memory 200340 kb
Host smart-41b2959c-c7e8-4dec-b071-5b42076d1912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474044270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1474044270
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2767789636
Short name T33
Test name
Test status
Simulation time 52386804191 ps
CPU time 2014.01 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 780268 kb
Host smart-da8d83a4-0122-4299-aaf9-b7a732d7aba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767789636 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2767789636
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.791133865
Short name T514
Test name
Test status
Simulation time 16930358973 ps
CPU time 21.27 seconds
Started Jul 14 06:32:14 PM PDT 24
Finished Jul 14 06:32:37 PM PDT 24
Peak memory 200388 kb
Host smart-5ce217bf-4929-478c-ae96-12f7858579bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791133865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.791133865
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.88779738
Short name T422
Test name
Test status
Simulation time 10458580 ps
CPU time 0.56 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:32:24 PM PDT 24
Peak memory 195164 kb
Host smart-44ba4f9b-16ce-447d-9043-459b7c2aeaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88779738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.88779738
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1732833858
Short name T417
Test name
Test status
Simulation time 2913412267 ps
CPU time 85.06 seconds
Started Jul 14 06:32:24 PM PDT 24
Finished Jul 14 06:33:52 PM PDT 24
Peak memory 200436 kb
Host smart-7bb7429b-60b6-4ecf-b5de-c5fc155ea37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732833858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1732833858
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1961212679
Short name T365
Test name
Test status
Simulation time 7656955297 ps
CPU time 24.91 seconds
Started Jul 14 06:32:21 PM PDT 24
Finished Jul 14 06:32:47 PM PDT 24
Peak memory 200368 kb
Host smart-c85c5d36-ba9a-4190-b888-5694cf63de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961212679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1961212679
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3400376244
Short name T89
Test name
Test status
Simulation time 7315176379 ps
CPU time 320.25 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:37:45 PM PDT 24
Peak memory 688172 kb
Host smart-7bff41d4-440a-4fb1-96e6-1716e4e261bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400376244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3400376244
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1191266200
Short name T348
Test name
Test status
Simulation time 2080983626 ps
CPU time 20.3 seconds
Started Jul 14 06:32:23 PM PDT 24
Finished Jul 14 06:32:45 PM PDT 24
Peak memory 200304 kb
Host smart-4577d46a-c787-4690-80b8-7b7dff523695
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191266200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1191266200
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2239507244
Short name T405
Test name
Test status
Simulation time 2979198280 ps
CPU time 57.4 seconds
Started Jul 14 06:32:23 PM PDT 24
Finished Jul 14 06:33:23 PM PDT 24
Peak memory 200384 kb
Host smart-35720852-b9cd-46b2-9fb2-f0d22cc80da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239507244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2239507244
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2686229810
Short name T234
Test name
Test status
Simulation time 722963944 ps
CPU time 5.31 seconds
Started Jul 14 06:32:17 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200280 kb
Host smart-c8f90bf8-4477-47bc-976c-81706786b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686229810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2686229810
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2256073011
Short name T489
Test name
Test status
Simulation time 86300556872 ps
CPU time 2154.8 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 07:08:18 PM PDT 24
Peak memory 749808 kb
Host smart-fb58f0e5-8a80-4e35-9412-59a41532db37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256073011 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2256073011
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3189231793
Short name T90
Test name
Test status
Simulation time 16096419511 ps
CPU time 50.43 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:33:15 PM PDT 24
Peak memory 200272 kb
Host smart-7b071bf4-7469-45da-80e7-5a5e365d0fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189231793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3189231793
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3209202709
Short name T48
Test name
Test status
Simulation time 34813823 ps
CPU time 0.59 seconds
Started Jul 14 06:32:23 PM PDT 24
Finished Jul 14 06:32:26 PM PDT 24
Peak memory 196200 kb
Host smart-5b367de5-46a7-4aa3-86aa-ec9a77629228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209202709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3209202709
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3329881130
Short name T444
Test name
Test status
Simulation time 1433423819 ps
CPU time 6.33 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 200236 kb
Host smart-8d149240-bb6b-48d8-baa2-7e04ab74556d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329881130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3329881130
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.459441190
Short name T147
Test name
Test status
Simulation time 1813959704 ps
CPU time 48.13 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:33:12 PM PDT 24
Peak memory 200264 kb
Host smart-4c0da2ee-e19f-430e-a833-49de0e6e38d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459441190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.459441190
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1878469882
Short name T394
Test name
Test status
Simulation time 8090222249 ps
CPU time 343.57 seconds
Started Jul 14 06:32:23 PM PDT 24
Finished Jul 14 06:38:09 PM PDT 24
Peak memory 671732 kb
Host smart-2baf0aa1-4881-47ab-8f23-eee91515c732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878469882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1878469882
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.602213796
Short name T184
Test name
Test status
Simulation time 9834142056 ps
CPU time 113.86 seconds
Started Jul 14 06:32:24 PM PDT 24
Finished Jul 14 06:34:20 PM PDT 24
Peak memory 200376 kb
Host smart-bb8d3997-8872-49df-aef6-b892c8cfd967
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602213796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.602213796
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3050383847
Short name T71
Test name
Test status
Simulation time 5651241509 ps
CPU time 69.92 seconds
Started Jul 14 06:32:24 PM PDT 24
Finished Jul 14 06:33:36 PM PDT 24
Peak memory 200248 kb
Host smart-77842d35-00e4-4618-b096-1bd7ebc95655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050383847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3050383847
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1891024983
Short name T49
Test name
Test status
Simulation time 6887511965 ps
CPU time 8.97 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:32:32 PM PDT 24
Peak memory 200364 kb
Host smart-36332b66-23f1-4278-9d23-2137c3833bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891024983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1891024983
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.112794059
Short name T203
Test name
Test status
Simulation time 1169014649 ps
CPU time 67.33 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:33:32 PM PDT 24
Peak memory 200188 kb
Host smart-bd00a3d7-dd13-4b10-8ab4-1cdc8b2427f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112794059 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.112794059
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2478046354
Short name T369
Test name
Test status
Simulation time 1541719340 ps
CPU time 14.84 seconds
Started Jul 14 06:32:22 PM PDT 24
Finished Jul 14 06:32:39 PM PDT 24
Peak memory 200312 kb
Host smart-b4fcc4db-2925-4f26-8a99-2b6d44ea07a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478046354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2478046354
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2011026562
Short name T527
Test name
Test status
Simulation time 18439293 ps
CPU time 0.61 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:32:32 PM PDT 24
Peak memory 195888 kb
Host smart-43505210-c501-4e6e-900a-2acefeb9c998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011026562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2011026562
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2730683787
Short name T347
Test name
Test status
Simulation time 6164462392 ps
CPU time 85.85 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:33:56 PM PDT 24
Peak memory 200492 kb
Host smart-fa3d8465-ca7c-49a0-8924-864961cad934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730683787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2730683787
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1791095571
Short name T380
Test name
Test status
Simulation time 3811448570 ps
CPU time 59.51 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:33:30 PM PDT 24
Peak memory 200376 kb
Host smart-6d945d49-ff1f-4676-a75e-2644ddd1878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791095571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1791095571
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3894287665
Short name T406
Test name
Test status
Simulation time 767916271 ps
CPU time 83.32 seconds
Started Jul 14 06:32:31 PM PDT 24
Finished Jul 14 06:33:55 PM PDT 24
Peak memory 254536 kb
Host smart-b8bf7f44-625e-4f03-90f4-9f30f768f850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894287665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3894287665
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.484313600
Short name T253
Test name
Test status
Simulation time 6391782337 ps
CPU time 54.31 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:33:25 PM PDT 24
Peak memory 200332 kb
Host smart-b37dc40d-f91a-4349-ad9b-5a259b99a7be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484313600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.484313600
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.489848561
Short name T107
Test name
Test status
Simulation time 939496309 ps
CPU time 54.08 seconds
Started Jul 14 06:32:23 PM PDT 24
Finished Jul 14 06:33:20 PM PDT 24
Peak memory 200356 kb
Host smart-40b9fadb-62f0-4e32-909c-3f4ef7f05601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489848561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.489848561
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1344675550
Short name T46
Test name
Test status
Simulation time 4033320407 ps
CPU time 11.66 seconds
Started Jul 14 06:32:24 PM PDT 24
Finished Jul 14 06:32:38 PM PDT 24
Peak memory 200288 kb
Host smart-546edad1-f641-46f6-ad58-813c15bd0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344675550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1344675550
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3357975356
Short name T470
Test name
Test status
Simulation time 19754234117 ps
CPU time 3189.02 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 07:25:39 PM PDT 24
Peak memory 792068 kb
Host smart-68a60a57-7591-4d9f-9e95-f8dd4a4f25ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357975356 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3357975356
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.634000649
Short name T83
Test name
Test status
Simulation time 776973554 ps
CPU time 42.95 seconds
Started Jul 14 06:32:27 PM PDT 24
Finished Jul 14 06:33:11 PM PDT 24
Peak memory 200296 kb
Host smart-757e38a1-9773-40e9-b169-8675517228c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634000649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.634000649
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3806755276
Short name T447
Test name
Test status
Simulation time 22141271 ps
CPU time 0.61 seconds
Started Jul 14 06:31:11 PM PDT 24
Finished Jul 14 06:31:13 PM PDT 24
Peak memory 195572 kb
Host smart-d21a6524-2b70-431e-b827-12fea404779f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806755276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3806755276
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.433223812
Short name T55
Test name
Test status
Simulation time 1139080130 ps
CPU time 64.94 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:32:15 PM PDT 24
Peak memory 200280 kb
Host smart-4eaa4410-b185-4923-b430-fe636068cf48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433223812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.433223812
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1032987781
Short name T252
Test name
Test status
Simulation time 10010901851 ps
CPU time 17.65 seconds
Started Jul 14 06:31:14 PM PDT 24
Finished Jul 14 06:31:33 PM PDT 24
Peak memory 200388 kb
Host smart-11039a1e-29eb-4436-8ea2-358d32d3eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032987781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1032987781
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2117917167
Short name T220
Test name
Test status
Simulation time 17934258787 ps
CPU time 807.42 seconds
Started Jul 14 06:31:13 PM PDT 24
Finished Jul 14 06:44:42 PM PDT 24
Peak memory 721640 kb
Host smart-19e57558-d1c4-499a-9d72-c7c52acbe773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117917167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2117917167
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3319471514
Short name T507
Test name
Test status
Simulation time 20865207097 ps
CPU time 135.37 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:33:29 PM PDT 24
Peak memory 200244 kb
Host smart-a9d26c81-e23c-4cc3-8882-921d5ad8e728
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319471514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3319471514
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3003479565
Short name T87
Test name
Test status
Simulation time 119776597169 ps
CPU time 182.48 seconds
Started Jul 14 06:31:14 PM PDT 24
Finished Jul 14 06:34:18 PM PDT 24
Peak memory 208564 kb
Host smart-76bbd40f-54d7-4274-9db2-822edeb57697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003479565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3003479565
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.426003480
Short name T61
Test name
Test status
Simulation time 167254398 ps
CPU time 0.81 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:31:14 PM PDT 24
Peak memory 218380 kb
Host smart-2197c62d-aafe-4d14-802c-4992c3225cf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426003480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.426003480
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1568679427
Short name T262
Test name
Test status
Simulation time 321545381 ps
CPU time 11.45 seconds
Started Jul 14 06:31:10 PM PDT 24
Finished Jul 14 06:31:22 PM PDT 24
Peak memory 200320 kb
Host smart-b7af1d53-a50c-4159-b68c-0b29a2af207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568679427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1568679427
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.229700190
Short name T495
Test name
Test status
Simulation time 164142399543 ps
CPU time 4744.59 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 07:50:25 PM PDT 24
Peak memory 805904 kb
Host smart-91a92f25-c147-4977-b003-818a5b65dd2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229700190 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.229700190
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3273545492
Short name T16
Test name
Test status
Simulation time 70651728999 ps
CPU time 385.23 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:37:44 PM PDT 24
Peak memory 476068 kb
Host smart-9d5f9428-6116-4923-8da7-e895eaedd439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273545492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3273545492
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2422218191
Short name T239
Test name
Test status
Simulation time 1880324493 ps
CPU time 72.89 seconds
Started Jul 14 06:31:14 PM PDT 24
Finished Jul 14 06:32:28 PM PDT 24
Peak memory 200532 kb
Host smart-77f63c37-fd2a-422a-b392-e11c1f281632
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2422218191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2422218191
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.695585952
Short name T242
Test name
Test status
Simulation time 5458896860 ps
CPU time 59.18 seconds
Started Jul 14 06:31:08 PM PDT 24
Finished Jul 14 06:32:09 PM PDT 24
Peak memory 200360 kb
Host smart-cf10dadd-20b5-4521-a07c-4bd1a4e2937c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=695585952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.695585952
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.131084981
Short name T230
Test name
Test status
Simulation time 9846704310 ps
CPU time 81.93 seconds
Started Jul 14 06:31:13 PM PDT 24
Finished Jul 14 06:32:36 PM PDT 24
Peak memory 200380 kb
Host smart-3279b7a1-58ea-48c7-ab75-85320bdb6b58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=131084981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.131084981
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.4021661275
Short name T458
Test name
Test status
Simulation time 154488071531 ps
CPU time 627.33 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:41:37 PM PDT 24
Peak memory 200364 kb
Host smart-e5f40fd8-cfc5-4de3-b4fc-e35c65c351a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4021661275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.4021661275
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.501803004
Short name T355
Test name
Test status
Simulation time 177742138601 ps
CPU time 2234.46 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 07:08:25 PM PDT 24
Peak memory 216588 kb
Host smart-092aca7d-89d7-4a11-8ce6-d5861e285941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=501803004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.501803004
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2188555149
Short name T163
Test name
Test status
Simulation time 150825497199 ps
CPU time 2146.33 seconds
Started Jul 14 06:31:11 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 215796 kb
Host smart-0a173ac2-0caf-475c-89f2-8f9b7725b604
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2188555149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2188555149
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2475572080
Short name T247
Test name
Test status
Simulation time 428004259 ps
CPU time 22.7 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:31:37 PM PDT 24
Peak memory 200316 kb
Host smart-9a843027-b943-40a6-8b2d-4340eee9f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475572080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2475572080
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2656075721
Short name T182
Test name
Test status
Simulation time 14598555 ps
CPU time 0.59 seconds
Started Jul 14 06:32:28 PM PDT 24
Finished Jul 14 06:32:30 PM PDT 24
Peak memory 195820 kb
Host smart-d2019e44-7fb5-4f0c-acfa-761779f13216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656075721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2656075721
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3008257671
Short name T108
Test name
Test status
Simulation time 2633968073 ps
CPU time 75.38 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:33:46 PM PDT 24
Peak memory 200436 kb
Host smart-85c7690f-c47e-41b5-b64f-a18616c3468f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008257671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3008257671
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4284355561
Short name T325
Test name
Test status
Simulation time 4378896002 ps
CPU time 77.34 seconds
Started Jul 14 06:32:27 PM PDT 24
Finished Jul 14 06:33:45 PM PDT 24
Peak memory 200484 kb
Host smart-27f4a9e7-9f4e-4549-b8ca-9b6c3b11600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284355561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4284355561
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.578090199
Short name T511
Test name
Test status
Simulation time 6597569959 ps
CPU time 1328.06 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 691956 kb
Host smart-54a561c7-220a-439c-820e-296ef7393e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578090199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.578090199
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1548313838
Short name T70
Test name
Test status
Simulation time 20400450309 ps
CPU time 171.48 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:35:22 PM PDT 24
Peak memory 200396 kb
Host smart-b71bcfeb-40b4-479d-bd33-72ddd7ff0533
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548313838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1548313838
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.4138634676
Short name T142
Test name
Test status
Simulation time 50944102229 ps
CPU time 228.41 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:36:20 PM PDT 24
Peak memory 200368 kb
Host smart-ad63d6db-fa7b-464a-8383-83e528d2c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138634676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4138634676
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2933119231
Short name T472
Test name
Test status
Simulation time 89538210 ps
CPU time 4.4 seconds
Started Jul 14 06:32:31 PM PDT 24
Finished Jul 14 06:32:37 PM PDT 24
Peak memory 200208 kb
Host smart-034d3f8d-ef8f-49fa-98bf-9563083e4d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933119231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2933119231
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.63449592
Short name T187
Test name
Test status
Simulation time 4834816229 ps
CPU time 84.21 seconds
Started Jul 14 06:32:28 PM PDT 24
Finished Jul 14 06:33:54 PM PDT 24
Peak memory 200368 kb
Host smart-471e3635-d8db-4f80-8f0f-8de55529b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63449592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.63449592
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1004742306
Short name T228
Test name
Test status
Simulation time 35627554 ps
CPU time 0.6 seconds
Started Jul 14 06:32:30 PM PDT 24
Finished Jul 14 06:32:32 PM PDT 24
Peak memory 195160 kb
Host smart-192937d0-3945-4fd3-8f10-a6c95d00a2f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004742306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1004742306
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3554617645
Short name T353
Test name
Test status
Simulation time 65448702 ps
CPU time 3.48 seconds
Started Jul 14 06:32:30 PM PDT 24
Finished Jul 14 06:32:35 PM PDT 24
Peak memory 200240 kb
Host smart-c2b036e3-b9aa-4d60-8fa7-90a66b34c6fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554617645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3554617645
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2813027451
Short name T384
Test name
Test status
Simulation time 8682830552 ps
CPU time 27.17 seconds
Started Jul 14 06:32:30 PM PDT 24
Finished Jul 14 06:32:59 PM PDT 24
Peak memory 200392 kb
Host smart-fa03b424-208f-4671-8b24-6f794297c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813027451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2813027451
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.873681335
Short name T501
Test name
Test status
Simulation time 519213480 ps
CPU time 107.76 seconds
Started Jul 14 06:32:30 PM PDT 24
Finished Jul 14 06:34:19 PM PDT 24
Peak memory 565912 kb
Host smart-24e80fe9-3c56-4511-a082-dea3e1f3d70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873681335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.873681335
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3672711626
Short name T362
Test name
Test status
Simulation time 16565178564 ps
CPU time 224.47 seconds
Started Jul 14 06:32:28 PM PDT 24
Finished Jul 14 06:36:14 PM PDT 24
Peak memory 200352 kb
Host smart-2110d03b-b986-4796-b17c-5c110eec8874
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672711626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3672711626
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3221885756
Short name T183
Test name
Test status
Simulation time 2652757108 ps
CPU time 33.61 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:33:04 PM PDT 24
Peak memory 200380 kb
Host smart-3863937d-359e-439d-8341-4691d076c3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221885756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3221885756
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3125425124
Short name T136
Test name
Test status
Simulation time 112329274 ps
CPU time 5.34 seconds
Started Jul 14 06:32:28 PM PDT 24
Finished Jul 14 06:32:35 PM PDT 24
Peak memory 200496 kb
Host smart-43c7224e-c7d9-41a0-b3bc-234561625c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125425124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3125425124
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3562441064
Short name T490
Test name
Test status
Simulation time 50749832540 ps
CPU time 339.24 seconds
Started Jul 14 06:32:30 PM PDT 24
Finished Jul 14 06:38:11 PM PDT 24
Peak memory 200680 kb
Host smart-b67b8d8b-3b94-4f24-b682-14eeb193f7a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562441064 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3562441064
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2969465791
Short name T31
Test name
Test status
Simulation time 13990671752 ps
CPU time 65.11 seconds
Started Jul 14 06:32:28 PM PDT 24
Finished Jul 14 06:33:35 PM PDT 24
Peak memory 200320 kb
Host smart-d33ebb27-2229-4b24-9832-3cab6c1c1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969465791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2969465791
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2190144168
Short name T233
Test name
Test status
Simulation time 64210662 ps
CPU time 0.6 seconds
Started Jul 14 06:32:37 PM PDT 24
Finished Jul 14 06:32:38 PM PDT 24
Peak memory 195072 kb
Host smart-8e2dc4e8-03cf-4086-a8bf-7d263ff0099f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190144168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2190144168
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.761946686
Short name T283
Test name
Test status
Simulation time 2502471626 ps
CPU time 30.82 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:33:05 PM PDT 24
Peak memory 200372 kb
Host smart-f31cf5d9-f9f6-4e86-a2b2-13ad38468e34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761946686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.761946686
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.4066838621
Short name T503
Test name
Test status
Simulation time 3137901295 ps
CPU time 22.28 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:32:57 PM PDT 24
Peak memory 200408 kb
Host smart-10870904-dac8-4766-9054-35c9b1d507ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066838621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.4066838621
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3228378400
Short name T409
Test name
Test status
Simulation time 5098344585 ps
CPU time 247.07 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:36:43 PM PDT 24
Peak memory 495656 kb
Host smart-df8002bd-e369-40fa-a18e-e52db31c40e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228378400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3228378400
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.331309024
Short name T64
Test name
Test status
Simulation time 22954154391 ps
CPU time 166.4 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:35:22 PM PDT 24
Peak memory 200248 kb
Host smart-e91dec83-774b-4d15-a098-21fb01928951
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331309024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.331309024
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3542385259
Short name T198
Test name
Test status
Simulation time 10429641168 ps
CPU time 156.51 seconds
Started Jul 14 06:32:36 PM PDT 24
Finished Jul 14 06:35:14 PM PDT 24
Peak memory 200276 kb
Host smart-ce588964-74c1-4ac5-9f23-c702d7e62ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542385259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3542385259
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2702134243
Short name T284
Test name
Test status
Simulation time 53308761 ps
CPU time 1.36 seconds
Started Jul 14 06:32:29 PM PDT 24
Finished Jul 14 06:32:32 PM PDT 24
Peak memory 200268 kb
Host smart-8cdc260d-48aa-46b9-ba57-985333ca9d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702134243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2702134243
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.223351421
Short name T54
Test name
Test status
Simulation time 14978995035 ps
CPU time 739.32 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:44:54 PM PDT 24
Peak memory 673544 kb
Host smart-9b062b3a-63fd-4399-aa90-2e94ba05dcb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223351421 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.223351421
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3177862914
Short name T180
Test name
Test status
Simulation time 1097831072 ps
CPU time 52.17 seconds
Started Jul 14 06:32:33 PM PDT 24
Finished Jul 14 06:33:25 PM PDT 24
Peak memory 200292 kb
Host smart-21faf88b-ad5c-4a7a-b4e1-72f79f80159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177862914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3177862914
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3207951074
Short name T351
Test name
Test status
Simulation time 14953423 ps
CPU time 0.58 seconds
Started Jul 14 06:32:42 PM PDT 24
Finished Jul 14 06:32:43 PM PDT 24
Peak memory 195076 kb
Host smart-214e3069-aec2-4ad7-af20-95d245f6c0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207951074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3207951074
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.655039243
Short name T218
Test name
Test status
Simulation time 1772479339 ps
CPU time 26.71 seconds
Started Jul 14 06:32:33 PM PDT 24
Finished Jul 14 06:33:01 PM PDT 24
Peak memory 200544 kb
Host smart-76389474-1d51-48aa-95dd-3f80a18c2fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655039243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.655039243
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4251383557
Short name T386
Test name
Test status
Simulation time 2242993413 ps
CPU time 14.88 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:32:50 PM PDT 24
Peak memory 200380 kb
Host smart-9477f2e5-31d6-4cd4-bbbc-4855f0f6e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251383557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4251383557
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4039925005
Short name T363
Test name
Test status
Simulation time 13916626988 ps
CPU time 1113.23 seconds
Started Jul 14 06:32:34 PM PDT 24
Finished Jul 14 06:51:08 PM PDT 24
Peak memory 734688 kb
Host smart-ac915ce5-0aa1-4a07-92f2-03a66fdb8523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039925005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4039925005
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4043772922
Short name T169
Test name
Test status
Simulation time 38499822973 ps
CPU time 117.09 seconds
Started Jul 14 06:32:44 PM PDT 24
Finished Jul 14 06:34:41 PM PDT 24
Peak memory 200316 kb
Host smart-73a78099-5cbe-4617-9ba0-f2deac2442d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043772922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4043772922
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4293939640
Short name T400
Test name
Test status
Simulation time 5190295821 ps
CPU time 91.55 seconds
Started Jul 14 06:32:35 PM PDT 24
Finished Jul 14 06:34:07 PM PDT 24
Peak memory 200420 kb
Host smart-76a49a4b-204b-48e8-bf26-04b5a4379ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293939640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4293939640
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3471288082
Short name T423
Test name
Test status
Simulation time 1892706938 ps
CPU time 8.34 seconds
Started Jul 14 06:32:35 PM PDT 24
Finished Jul 14 06:32:44 PM PDT 24
Peak memory 200312 kb
Host smart-fa94b716-ecd5-49d8-bfd1-08a928331ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471288082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3471288082
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.294578216
Short name T20
Test name
Test status
Simulation time 14518520411 ps
CPU time 193.86 seconds
Started Jul 14 06:32:41 PM PDT 24
Finished Jul 14 06:35:56 PM PDT 24
Peak memory 200344 kb
Host smart-62d9e5fd-df5c-432d-a5bc-64b385a2600b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294578216 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.294578216
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1438871698
Short name T497
Test name
Test status
Simulation time 17522270273 ps
CPU time 78.89 seconds
Started Jul 14 06:32:36 PM PDT 24
Finished Jul 14 06:33:56 PM PDT 24
Peak memory 200300 kb
Host smart-ffee1b70-3b63-4f9c-b833-69e4d37a2ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438871698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1438871698
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3422632885
Short name T316
Test name
Test status
Simulation time 11882056 ps
CPU time 0.63 seconds
Started Jul 14 06:32:46 PM PDT 24
Finished Jul 14 06:32:47 PM PDT 24
Peak memory 196088 kb
Host smart-9b9848bc-76dd-44f2-bcbb-893110a282a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422632885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3422632885
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1219355655
Short name T34
Test name
Test status
Simulation time 1421918584 ps
CPU time 88.18 seconds
Started Jul 14 06:32:45 PM PDT 24
Finished Jul 14 06:34:14 PM PDT 24
Peak memory 200204 kb
Host smart-a09b041e-8149-4c1c-9ba8-c8ad509e7321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219355655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1219355655
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3044762825
Short name T502
Test name
Test status
Simulation time 281662448 ps
CPU time 14.48 seconds
Started Jul 14 06:32:42 PM PDT 24
Finished Jul 14 06:32:57 PM PDT 24
Peak memory 200204 kb
Host smart-accf2897-0366-427d-b859-66feafb4403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044762825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3044762825
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2238905184
Short name T226
Test name
Test status
Simulation time 2535885262 ps
CPU time 100.75 seconds
Started Jul 14 06:32:40 PM PDT 24
Finished Jul 14 06:34:21 PM PDT 24
Peak memory 324756 kb
Host smart-1dd002b0-d6b1-4964-86d1-51f9694e803f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238905184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2238905184
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.656973271
Short name T27
Test name
Test status
Simulation time 167380810071 ps
CPU time 152.11 seconds
Started Jul 14 06:32:41 PM PDT 24
Finished Jul 14 06:35:14 PM PDT 24
Peak memory 200324 kb
Host smart-3d5487a6-9874-44af-a9b6-1b8712ba2879
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656973271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.656973271
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2479497850
Short name T464
Test name
Test status
Simulation time 984048691 ps
CPU time 13.07 seconds
Started Jul 14 06:32:41 PM PDT 24
Finished Jul 14 06:32:55 PM PDT 24
Peak memory 200248 kb
Host smart-dd30defa-0dfd-4c4c-ba5b-fe0a641fcf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479497850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2479497850
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.528899686
Short name T135
Test name
Test status
Simulation time 77042116 ps
CPU time 3.22 seconds
Started Jul 14 06:32:41 PM PDT 24
Finished Jul 14 06:32:45 PM PDT 24
Peak memory 200344 kb
Host smart-877a0af2-c79f-49ad-aad5-909e31ea8db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528899686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.528899686
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1799758136
Short name T236
Test name
Test status
Simulation time 207400435766 ps
CPU time 1460.81 seconds
Started Jul 14 06:32:42 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 619272 kb
Host smart-3eef8623-729d-420d-b937-6b4de1a7be29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799758136 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1799758136
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2430173907
Short name T424
Test name
Test status
Simulation time 2138017378 ps
CPU time 104.54 seconds
Started Jul 14 06:32:46 PM PDT 24
Finished Jul 14 06:34:31 PM PDT 24
Peak memory 200180 kb
Host smart-9026ce26-1a36-4d21-8ec6-1c8bbb976ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430173907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2430173907
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1245886232
Short name T209
Test name
Test status
Simulation time 28841026 ps
CPU time 0.64 seconds
Started Jul 14 06:32:44 PM PDT 24
Finished Jul 14 06:32:45 PM PDT 24
Peak memory 196188 kb
Host smart-3a7a60b5-d608-4ba3-8859-e8c8fc6fee16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245886232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1245886232
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3306779494
Short name T139
Test name
Test status
Simulation time 1664783508 ps
CPU time 98.09 seconds
Started Jul 14 06:32:40 PM PDT 24
Finished Jul 14 06:34:18 PM PDT 24
Peak memory 200276 kb
Host smart-eab1ab67-b96d-47f9-9362-93a22eb396b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306779494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3306779494
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.252549309
Short name T215
Test name
Test status
Simulation time 21495597675 ps
CPU time 53.23 seconds
Started Jul 14 06:32:42 PM PDT 24
Finished Jul 14 06:33:36 PM PDT 24
Peak memory 200336 kb
Host smart-2c0bc933-201e-4104-99a6-bba0371bf86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252549309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.252549309
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.562110044
Short name T287
Test name
Test status
Simulation time 6088490315 ps
CPU time 933.17 seconds
Started Jul 14 06:32:40 PM PDT 24
Finished Jul 14 06:48:14 PM PDT 24
Peak memory 745236 kb
Host smart-5fb38a0e-8b5c-4c69-82f3-c8c5d81017c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562110044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.562110044
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2789036362
Short name T294
Test name
Test status
Simulation time 4618401253 ps
CPU time 29.62 seconds
Started Jul 14 06:32:42 PM PDT 24
Finished Jul 14 06:33:12 PM PDT 24
Peak memory 200224 kb
Host smart-335d52dd-3e0f-42f1-a023-ed6c471fe2f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789036362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2789036362
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.324012659
Short name T314
Test name
Test status
Simulation time 1635546419 ps
CPU time 94.89 seconds
Started Jul 14 06:32:41 PM PDT 24
Finished Jul 14 06:34:16 PM PDT 24
Peak memory 200332 kb
Host smart-32c3eb38-cdfe-40a9-a8c4-9e3f562883eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324012659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.324012659
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3666567924
Short name T295
Test name
Test status
Simulation time 1735655964 ps
CPU time 10.21 seconds
Started Jul 14 06:32:40 PM PDT 24
Finished Jul 14 06:32:51 PM PDT 24
Peak memory 200268 kb
Host smart-34cf73c6-434b-42bb-825e-1c6a2c4faeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666567924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3666567924
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.428324721
Short name T460
Test name
Test status
Simulation time 467073577939 ps
CPU time 1354.1 seconds
Started Jul 14 06:32:41 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 728612 kb
Host smart-02ba50ba-44ca-4092-816b-1b83972a7fe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428324721 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.428324721
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1937462983
Short name T304
Test name
Test status
Simulation time 4558689331 ps
CPU time 61.44 seconds
Started Jul 14 06:32:45 PM PDT 24
Finished Jul 14 06:33:47 PM PDT 24
Peak memory 200268 kb
Host smart-96ed0316-8785-4fd6-8bf7-512128ce5595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937462983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1937462983
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3278759105
Short name T312
Test name
Test status
Simulation time 49008776 ps
CPU time 0.6 seconds
Started Jul 14 06:32:47 PM PDT 24
Finished Jul 14 06:32:48 PM PDT 24
Peak memory 195820 kb
Host smart-2e672671-abc5-49c9-97fc-a6ddd5d49fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278759105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3278759105
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2630551770
Short name T14
Test name
Test status
Simulation time 463508659 ps
CPU time 25.13 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:33:15 PM PDT 24
Peak memory 200356 kb
Host smart-df4865bf-b2bc-4a54-85b5-7add3c9b3fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630551770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2630551770
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.352952264
Short name T272
Test name
Test status
Simulation time 2661589748 ps
CPU time 19.11 seconds
Started Jul 14 06:32:48 PM PDT 24
Finished Jul 14 06:33:07 PM PDT 24
Peak memory 200396 kb
Host smart-05158a50-106e-4150-8672-1e210923c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352952264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.352952264
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.565498267
Short name T319
Test name
Test status
Simulation time 1124630087 ps
CPU time 130.58 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:35:01 PM PDT 24
Peak memory 594272 kb
Host smart-df6adcf5-9b40-4262-a3e1-7c27ad5cabf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565498267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.565498267
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.373527917
Short name T525
Test name
Test status
Simulation time 40696800767 ps
CPU time 139.49 seconds
Started Jul 14 06:32:50 PM PDT 24
Finished Jul 14 06:35:11 PM PDT 24
Peak memory 200380 kb
Host smart-698285e6-cffe-4c56-af17-f2f6bf676da8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373527917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.373527917
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3773423329
Short name T186
Test name
Test status
Simulation time 6241278802 ps
CPU time 87.31 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:34:18 PM PDT 24
Peak memory 200276 kb
Host smart-819fd7ca-fa9d-41dc-8300-bff94e35de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773423329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3773423329
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3202350542
Short name T433
Test name
Test status
Simulation time 34792973 ps
CPU time 1.32 seconds
Started Jul 14 06:32:42 PM PDT 24
Finished Jul 14 06:32:44 PM PDT 24
Peak memory 200276 kb
Host smart-7eb29e51-a913-4005-a66b-7d5aeabc2111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202350542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3202350542
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.4012027537
Short name T270
Test name
Test status
Simulation time 9038628361 ps
CPU time 476.99 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:40:47 PM PDT 24
Peak memory 697048 kb
Host smart-477e4bac-1d01-40b0-9cd2-734c503f3e89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012027537 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4012027537
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.214120666
Short name T30
Test name
Test status
Simulation time 3371481961 ps
CPU time 22.6 seconds
Started Jul 14 06:32:51 PM PDT 24
Finished Jul 14 06:33:14 PM PDT 24
Peak memory 200300 kb
Host smart-df9dc408-aeb4-4f32-9dc2-9ed282b80b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214120666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.214120666
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2784891194
Short name T164
Test name
Test status
Simulation time 13105371 ps
CPU time 0.59 seconds
Started Jul 14 06:32:59 PM PDT 24
Finished Jul 14 06:33:02 PM PDT 24
Peak memory 195856 kb
Host smart-51c2ec66-3a82-4074-8fbd-3621835c5257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784891194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2784891194
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1982777240
Short name T449
Test name
Test status
Simulation time 1185813520 ps
CPU time 67.62 seconds
Started Jul 14 06:32:48 PM PDT 24
Finished Jul 14 06:33:56 PM PDT 24
Peak memory 200308 kb
Host smart-3b40eb39-9e94-43d9-a58f-fc6c622daa84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982777240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1982777240
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.528797588
Short name T149
Test name
Test status
Simulation time 603341154 ps
CPU time 32.13 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:33:22 PM PDT 24
Peak memory 200332 kb
Host smart-d7cd8be3-8945-4116-9180-688604a96b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528797588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.528797588
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.954152761
Short name T157
Test name
Test status
Simulation time 1043882094 ps
CPU time 140.95 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:35:12 PM PDT 24
Peak memory 408556 kb
Host smart-f962a173-a9a0-4568-b9f1-d16081aeb1ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954152761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.954152761
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1895707072
Short name T361
Test name
Test status
Simulation time 1471754666 ps
CPU time 18.34 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:33:09 PM PDT 24
Peak memory 200264 kb
Host smart-e83e95d2-8252-4535-85bb-29b64a16535a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895707072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1895707072
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3225308268
Short name T86
Test name
Test status
Simulation time 15083868960 ps
CPU time 140.51 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:35:10 PM PDT 24
Peak memory 200488 kb
Host smart-6547bded-cb3d-44f9-bc69-641916d02c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225308268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3225308268
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.137364972
Short name T411
Test name
Test status
Simulation time 190389925 ps
CPU time 9.41 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:33:00 PM PDT 24
Peak memory 200280 kb
Host smart-2eada822-e0d9-44fc-92a6-6352b0759cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137364972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.137364972
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.4034889004
Short name T465
Test name
Test status
Simulation time 154704361898 ps
CPU time 1587.46 seconds
Started Jul 14 06:32:58 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 684456 kb
Host smart-3e2ed28c-1ef2-4ffd-9432-594fd67795b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034889004 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.4034889004
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2752302156
Short name T207
Test name
Test status
Simulation time 4168394431 ps
CPU time 74.85 seconds
Started Jul 14 06:32:49 PM PDT 24
Finished Jul 14 06:34:05 PM PDT 24
Peak memory 200276 kb
Host smart-bedc19de-ecf7-428a-8b8e-734ed4ada1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752302156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2752302156
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1896966540
Short name T303
Test name
Test status
Simulation time 19770994 ps
CPU time 0.6 seconds
Started Jul 14 06:32:56 PM PDT 24
Finished Jul 14 06:32:58 PM PDT 24
Peak memory 196868 kb
Host smart-2db74238-01f0-4c22-b46d-a5f217506553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896966540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1896966540
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.135170113
Short name T275
Test name
Test status
Simulation time 1775978475 ps
CPU time 97.42 seconds
Started Jul 14 06:32:57 PM PDT 24
Finished Jul 14 06:34:37 PM PDT 24
Peak memory 200304 kb
Host smart-968244f8-eb30-4c4b-8656-2695cda2a910
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135170113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.135170113
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2373497288
Short name T451
Test name
Test status
Simulation time 1754384457 ps
CPU time 16.67 seconds
Started Jul 14 06:32:58 PM PDT 24
Finished Jul 14 06:33:16 PM PDT 24
Peak memory 200308 kb
Host smart-2e287882-53e2-429e-8793-db70476dc51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373497288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2373497288
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.166997910
Short name T517
Test name
Test status
Simulation time 6200389069 ps
CPU time 1211.57 seconds
Started Jul 14 06:32:59 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 752988 kb
Host smart-ef8e58f8-c175-4528-bd82-cc778355aa3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166997910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.166997910
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.306420973
Short name T344
Test name
Test status
Simulation time 100337090422 ps
CPU time 165.32 seconds
Started Jul 14 06:32:56 PM PDT 24
Finished Jul 14 06:35:43 PM PDT 24
Peak memory 200328 kb
Host smart-fedde4c1-fc6f-40ac-807c-5e33a098770b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306420973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.306420973
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.246177342
Short name T462
Test name
Test status
Simulation time 3380580289 ps
CPU time 59.61 seconds
Started Jul 14 06:32:56 PM PDT 24
Finished Jul 14 06:33:57 PM PDT 24
Peak memory 200380 kb
Host smart-e1d9488c-7f11-4b73-b1d7-0866333396a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246177342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.246177342
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3558015440
Short name T388
Test name
Test status
Simulation time 1090390224 ps
CPU time 3.09 seconds
Started Jul 14 06:32:55 PM PDT 24
Finished Jul 14 06:33:00 PM PDT 24
Peak memory 200228 kb
Host smart-7b5783f7-0a37-40ac-9a4d-f0785dd362bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558015440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3558015440
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.677343415
Short name T494
Test name
Test status
Simulation time 199192488437 ps
CPU time 182.47 seconds
Started Jul 14 06:32:58 PM PDT 24
Finished Jul 14 06:36:03 PM PDT 24
Peak memory 200348 kb
Host smart-07dbea91-2e20-4558-a67b-2a0a88d2e5aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677343415 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.677343415
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3328061133
Short name T331
Test name
Test status
Simulation time 15210093479 ps
CPU time 69.9 seconds
Started Jul 14 06:32:56 PM PDT 24
Finished Jul 14 06:34:09 PM PDT 24
Peak memory 200396 kb
Host smart-ad51c1e5-304f-425f-b219-35afc7925d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328061133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3328061133
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3829280770
Short name T466
Test name
Test status
Simulation time 12637721 ps
CPU time 0.64 seconds
Started Jul 14 06:33:00 PM PDT 24
Finished Jul 14 06:33:03 PM PDT 24
Peak memory 196084 kb
Host smart-c95b88d3-f935-438f-adce-c2fa83d20f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829280770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3829280770
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4050992141
Short name T224
Test name
Test status
Simulation time 854662811 ps
CPU time 48.56 seconds
Started Jul 14 06:32:56 PM PDT 24
Finished Jul 14 06:33:47 PM PDT 24
Peak memory 200340 kb
Host smart-1ff4b340-5e13-48e4-b19d-d6da1283e14b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050992141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4050992141
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3628666278
Short name T512
Test name
Test status
Simulation time 1216736018 ps
CPU time 6.65 seconds
Started Jul 14 06:32:58 PM PDT 24
Finished Jul 14 06:33:07 PM PDT 24
Peak memory 200232 kb
Host smart-0a75ddfc-59bd-40ea-895e-3ac77b6090cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628666278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3628666278
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1442630290
Short name T65
Test name
Test status
Simulation time 15955620170 ps
CPU time 706.24 seconds
Started Jul 14 06:32:59 PM PDT 24
Finished Jul 14 06:44:48 PM PDT 24
Peak memory 717516 kb
Host smart-87a52801-acc3-40a0-acca-14de1248a9f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442630290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1442630290
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2622171089
Short name T172
Test name
Test status
Simulation time 31909262156 ps
CPU time 108.43 seconds
Started Jul 14 06:32:59 PM PDT 24
Finished Jul 14 06:34:50 PM PDT 24
Peak memory 200328 kb
Host smart-a8b6077b-66b5-495a-93ed-d4595a422bc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622171089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2622171089
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1817918796
Short name T222
Test name
Test status
Simulation time 17666490483 ps
CPU time 228.21 seconds
Started Jul 14 06:33:01 PM PDT 24
Finished Jul 14 06:36:52 PM PDT 24
Peak memory 200364 kb
Host smart-0dffd885-6cb2-4288-821c-f76cf52c6834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817918796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1817918796
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2068214550
Short name T321
Test name
Test status
Simulation time 5903135444 ps
CPU time 18.65 seconds
Started Jul 14 06:32:57 PM PDT 24
Finished Jul 14 06:33:18 PM PDT 24
Peak memory 200384 kb
Host smart-d1da1d7a-0b1d-4b1d-bd6f-13a80cc4e934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068214550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2068214550
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1321479908
Short name T387
Test name
Test status
Simulation time 48864916161 ps
CPU time 1155.75 seconds
Started Jul 14 06:33:00 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 735540 kb
Host smart-acc2bb17-48f3-4b11-be00-9d91ff55aacb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321479908 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1321479908
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.369338237
Short name T41
Test name
Test status
Simulation time 3446436223 ps
CPU time 50.18 seconds
Started Jul 14 06:32:57 PM PDT 24
Finished Jul 14 06:33:49 PM PDT 24
Peak memory 200328 kb
Host smart-9d3d449b-cf82-4a17-9dc8-7ed952eb682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369338237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.369338237
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4036300491
Short name T106
Test name
Test status
Simulation time 14361403 ps
CPU time 0.61 seconds
Started Jul 14 06:31:09 PM PDT 24
Finished Jul 14 06:31:10 PM PDT 24
Peak memory 195156 kb
Host smart-344a8ba5-4d10-4e91-84d6-17a60756c5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036300491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4036300491
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.76010956
Short name T178
Test name
Test status
Simulation time 4752760374 ps
CPU time 24.93 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:31:44 PM PDT 24
Peak memory 200308 kb
Host smart-0a84f734-1016-4838-8bb6-6906581eff45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76010956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.76010956
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2998083164
Short name T144
Test name
Test status
Simulation time 596664898 ps
CPU time 33.74 seconds
Started Jul 14 06:31:14 PM PDT 24
Finished Jul 14 06:31:49 PM PDT 24
Peak memory 200504 kb
Host smart-8c95c90f-5b5f-45f5-92f9-97f68630f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998083164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2998083164
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1632397048
Short name T381
Test name
Test status
Simulation time 4069741132 ps
CPU time 747.29 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:43:41 PM PDT 24
Peak memory 723752 kb
Host smart-d077d87c-7bb5-4937-b56b-08043c74a957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632397048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1632397048
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3707302762
Short name T161
Test name
Test status
Simulation time 1766752618 ps
CPU time 97.77 seconds
Started Jul 14 06:31:11 PM PDT 24
Finished Jul 14 06:32:50 PM PDT 24
Peak memory 200272 kb
Host smart-3ef008dd-0e12-44dd-801d-98f479b15408
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707302762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3707302762
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3603498116
Short name T235
Test name
Test status
Simulation time 11249737008 ps
CPU time 115.22 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:33:11 PM PDT 24
Peak memory 200292 kb
Host smart-80f480d7-f29c-4387-ba00-520cfb46a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603498116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3603498116
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.303566033
Short name T176
Test name
Test status
Simulation time 921717298 ps
CPU time 12.03 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:31:28 PM PDT 24
Peak memory 200224 kb
Host smart-7024dc2c-180a-4860-a721-d742d405bc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303566033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.303566033
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3424019299
Short name T75
Test name
Test status
Simulation time 180823864283 ps
CPU time 1430.9 seconds
Started Jul 14 06:31:12 PM PDT 24
Finished Jul 14 06:55:04 PM PDT 24
Peak memory 630236 kb
Host smart-2e6e5cbb-73c5-4e5e-98d5-0caf282849fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424019299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3424019299
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3542896631
Short name T382
Test name
Test status
Simulation time 3484219813 ps
CPU time 59.58 seconds
Started Jul 14 06:31:11 PM PDT 24
Finished Jul 14 06:32:12 PM PDT 24
Peak memory 200376 kb
Host smart-856fe131-f166-4d84-86fa-b308d4e7e16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542896631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3542896631
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2119568174
Short name T56
Test name
Test status
Simulation time 11184552 ps
CPU time 0.6 seconds
Started Jul 14 06:31:23 PM PDT 24
Finished Jul 14 06:31:27 PM PDT 24
Peak memory 195096 kb
Host smart-0d6a074f-95a4-4a51-8d44-6eef326eb826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119568174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2119568174
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3296816431
Short name T21
Test name
Test status
Simulation time 1364080436 ps
CPU time 78.21 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:32:35 PM PDT 24
Peak memory 200300 kb
Host smart-aa2b73fe-0212-4516-9050-bf7c1d5e0bfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296816431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3296816431
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3210346057
Short name T322
Test name
Test status
Simulation time 2120217566 ps
CPU time 28.07 seconds
Started Jul 14 06:31:20 PM PDT 24
Finished Jul 14 06:31:51 PM PDT 24
Peak memory 200308 kb
Host smart-9e399fa2-35ff-4c49-8135-4c260c0fabb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210346057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3210346057
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3969787085
Short name T197
Test name
Test status
Simulation time 14885357690 ps
CPU time 343.34 seconds
Started Jul 14 06:31:24 PM PDT 24
Finished Jul 14 06:37:11 PM PDT 24
Peak memory 671604 kb
Host smart-3c5501db-b0ad-4041-8fd4-459d6af57cd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969787085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3969787085
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2774415710
Short name T281
Test name
Test status
Simulation time 27215856167 ps
CPU time 240.77 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:35:17 PM PDT 24
Peak memory 200400 kb
Host smart-0b13e484-46fb-476c-a24c-4ede69646add
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774415710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2774415710
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4256848305
Short name T342
Test name
Test status
Simulation time 30472427300 ps
CPU time 103.95 seconds
Started Jul 14 06:31:14 PM PDT 24
Finished Jul 14 06:33:00 PM PDT 24
Peak memory 200632 kb
Host smart-ffb27b03-8bbb-4cdb-a3ff-119fac5c133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256848305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4256848305
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2740553337
Short name T486
Test name
Test status
Simulation time 3835883588 ps
CPU time 12.62 seconds
Started Jul 14 06:31:10 PM PDT 24
Finished Jul 14 06:31:24 PM PDT 24
Peak memory 200300 kb
Host smart-29dd3bf1-d345-43d9-90bc-c1f6f5e88cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740553337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2740553337
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3592397781
Short name T269
Test name
Test status
Simulation time 143335774 ps
CPU time 0.94 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 06:31:21 PM PDT 24
Peak memory 200072 kb
Host smart-5a3bac93-2019-46ed-917f-1c5711c538a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592397781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3592397781
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1160299380
Short name T10
Test name
Test status
Simulation time 99118780782 ps
CPU time 1974.59 seconds
Started Jul 14 06:31:26 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 772516 kb
Host smart-ea76a4e0-560e-480b-83ee-4dce199381b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160299380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1160299380
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1541808105
Short name T188
Test name
Test status
Simulation time 6359535265 ps
CPU time 62.51 seconds
Started Jul 14 06:31:33 PM PDT 24
Finished Jul 14 06:32:37 PM PDT 24
Peak memory 200376 kb
Host smart-9ef6b130-1ab2-4e25-8c23-2e46da43f0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541808105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1541808105
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.876466340
Short name T428
Test name
Test status
Simulation time 20635779 ps
CPU time 0.6 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:31:18 PM PDT 24
Peak memory 196128 kb
Host smart-2db011d4-5809-4e8f-9610-d0bbcdbdaed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876466340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.876466340
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1673513236
Short name T435
Test name
Test status
Simulation time 306601748 ps
CPU time 16.42 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:31:32 PM PDT 24
Peak memory 200288 kb
Host smart-b7f57a09-9006-4bf4-8396-5ece03d8b6c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673513236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1673513236
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1227753768
Short name T109
Test name
Test status
Simulation time 3661395003 ps
CPU time 45.67 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:32:05 PM PDT 24
Peak memory 200408 kb
Host smart-09cab130-5a13-4d3c-ab19-c9c127283fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227753768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1227753768
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2647873375
Short name T437
Test name
Test status
Simulation time 8861805679 ps
CPU time 777.05 seconds
Started Jul 14 06:31:24 PM PDT 24
Finished Jul 14 06:44:24 PM PDT 24
Peak memory 665632 kb
Host smart-a8cefc1a-aa29-4425-a79a-059cb8042dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647873375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2647873375
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3939861408
Short name T431
Test name
Test status
Simulation time 4335208403 ps
CPU time 49.34 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 06:32:09 PM PDT 24
Peak memory 200368 kb
Host smart-6de9bb61-f72b-4017-9b3c-7e1843845357
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939861408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3939861408
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.856945844
Short name T299
Test name
Test status
Simulation time 721993778 ps
CPU time 41.98 seconds
Started Jul 14 06:31:22 PM PDT 24
Finished Jul 14 06:32:07 PM PDT 24
Peak memory 200316 kb
Host smart-e79a905c-b04a-4290-99cb-ec91c1c30777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856945844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.856945844
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.736999884
Short name T524
Test name
Test status
Simulation time 669339658 ps
CPU time 11.33 seconds
Started Jul 14 06:31:26 PM PDT 24
Finished Jul 14 06:31:40 PM PDT 24
Peak memory 200280 kb
Host smart-f365a26e-5146-4256-adb6-63674394ded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736999884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.736999884
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.773019144
Short name T24
Test name
Test status
Simulation time 256350890876 ps
CPU time 4852.14 seconds
Started Jul 14 06:31:18 PM PDT 24
Finished Jul 14 07:52:13 PM PDT 24
Peak memory 833568 kb
Host smart-57ce4846-c7fb-4758-b713-c19274dca9f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773019144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.773019144
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2320561700
Short name T273
Test name
Test status
Simulation time 8440035738 ps
CPU time 78.6 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:32:37 PM PDT 24
Peak memory 200552 kb
Host smart-2165ae72-9334-4eb0-ae3b-25f0e983fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320561700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2320561700
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3525279236
Short name T44
Test name
Test status
Simulation time 37198669 ps
CPU time 0.57 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 06:31:20 PM PDT 24
Peak memory 196208 kb
Host smart-befa93bf-0d33-4bfd-8831-b03e37ff9fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525279236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3525279236
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1564281567
Short name T526
Test name
Test status
Simulation time 729897999 ps
CPU time 9.3 seconds
Started Jul 14 06:31:21 PM PDT 24
Finished Jul 14 06:31:33 PM PDT 24
Peak memory 200232 kb
Host smart-1ab22b0b-eeb1-4dbe-86c3-8ad744f9f2a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564281567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1564281567
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1659917008
Short name T427
Test name
Test status
Simulation time 915784153 ps
CPU time 45.43 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:32:05 PM PDT 24
Peak memory 200292 kb
Host smart-99ebf3ac-de8f-4e44-a24f-fd42b08185ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659917008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1659917008
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1161586427
Short name T297
Test name
Test status
Simulation time 189148888 ps
CPU time 18.87 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 06:31:39 PM PDT 24
Peak memory 236436 kb
Host smart-e5c7bb3c-bc2b-406b-af5d-5fd98c916b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161586427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1161586427
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1245474006
Short name T416
Test name
Test status
Simulation time 225538093693 ps
CPU time 151.23 seconds
Started Jul 14 06:31:18 PM PDT 24
Finished Jul 14 06:33:53 PM PDT 24
Peak memory 200356 kb
Host smart-b1c9b8ba-592d-4861-ae6f-46598906aac1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245474006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1245474006
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1028644
Short name T290
Test name
Test status
Simulation time 2562819016 ps
CPU time 142.87 seconds
Started Jul 14 06:31:29 PM PDT 24
Finished Jul 14 06:33:53 PM PDT 24
Peak memory 200420 kb
Host smart-a9b9e866-77d8-4868-af37-248705000ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1028644
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1036025095
Short name T420
Test name
Test status
Simulation time 359645207 ps
CPU time 4.17 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 06:31:22 PM PDT 24
Peak memory 200300 kb
Host smart-7a8a4357-1dff-46c2-8abd-4e5337131045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036025095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1036025095
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3230123600
Short name T259
Test name
Test status
Simulation time 284743594757 ps
CPU time 3198.76 seconds
Started Jul 14 06:31:16 PM PDT 24
Finished Jul 14 07:24:37 PM PDT 24
Peak memory 834204 kb
Host smart-dd6499f5-2a81-43b2-ab56-4a82cf52a0f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230123600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3230123600
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2359019847
Short name T11
Test name
Test status
Simulation time 681094748149 ps
CPU time 1764.52 seconds
Started Jul 14 06:31:17 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 462120 kb
Host smart-4ca6e99b-a05e-40ae-bd6a-09b83b38efc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359019847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2359019847
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4110084676
Short name T356
Test name
Test status
Simulation time 13303218464 ps
CPU time 86.84 seconds
Started Jul 14 06:31:27 PM PDT 24
Finished Jul 14 06:32:56 PM PDT 24
Peak memory 200344 kb
Host smart-cdee17b0-6045-4d6c-9906-6660db171b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110084676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4110084676
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3850420312
Short name T392
Test name
Test status
Simulation time 20668954 ps
CPU time 0.6 seconds
Started Jul 14 06:31:30 PM PDT 24
Finished Jul 14 06:31:31 PM PDT 24
Peak memory 196104 kb
Host smart-4558a13e-bf2e-43d6-959e-717ca2fd6241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850420312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3850420312
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.969752490
Short name T241
Test name
Test status
Simulation time 990127071 ps
CPU time 52.72 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:32:25 PM PDT 24
Peak memory 200284 kb
Host smart-d5d86e4f-8c57-4ce4-95b9-659a692ea620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969752490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.969752490
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3148355410
Short name T414
Test name
Test status
Simulation time 2108946411 ps
CPU time 18.84 seconds
Started Jul 14 06:31:19 PM PDT 24
Finished Jul 14 06:31:41 PM PDT 24
Peak memory 200248 kb
Host smart-ebfef5cb-15f7-4d1b-97e1-fccfc56ca870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148355410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3148355410
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.698103621
Short name T483
Test name
Test status
Simulation time 14335080 ps
CPU time 0.71 seconds
Started Jul 14 06:31:18 PM PDT 24
Finished Jul 14 06:31:21 PM PDT 24
Peak memory 198624 kb
Host smart-446418a4-db00-42ee-8f9a-c4982ec1bebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698103621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.698103621
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1751691146
Short name T243
Test name
Test status
Simulation time 25937425534 ps
CPU time 92.76 seconds
Started Jul 14 06:31:20 PM PDT 24
Finished Jul 14 06:32:56 PM PDT 24
Peak memory 200300 kb
Host smart-93dd7d4a-9048-4fa6-86a3-a7d949d8d4db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751691146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1751691146
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3621839332
Short name T292
Test name
Test status
Simulation time 2103570713 ps
CPU time 123.22 seconds
Started Jul 14 06:31:24 PM PDT 24
Finished Jul 14 06:33:30 PM PDT 24
Peak memory 200252 kb
Host smart-95741bf1-eb53-4428-b825-3b4c5d5762f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621839332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3621839332
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.80579914
Short name T214
Test name
Test status
Simulation time 810264971 ps
CPU time 8.85 seconds
Started Jul 14 06:31:27 PM PDT 24
Finished Jul 14 06:31:37 PM PDT 24
Peak memory 200256 kb
Host smart-55c884a8-b3ac-4233-b803-55a4f72d1431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80579914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.80579914
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3346341517
Short name T477
Test name
Test status
Simulation time 37621653475 ps
CPU time 471.46 seconds
Started Jul 14 06:31:27 PM PDT 24
Finished Jul 14 06:39:21 PM PDT 24
Peak memory 216720 kb
Host smart-3219023e-9ff2-4dce-8aac-841c7c161ab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346341517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3346341517
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1753388081
Short name T26
Test name
Test status
Simulation time 60741836929 ps
CPU time 1280.53 seconds
Started Jul 14 06:31:15 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 544100 kb
Host smart-5b3839cb-5aed-4fbc-8c8d-49064291b39d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753388081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1753388081
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2491076533
Short name T396
Test name
Test status
Simulation time 8023652057 ps
CPU time 84.09 seconds
Started Jul 14 06:31:31 PM PDT 24
Finished Jul 14 06:32:56 PM PDT 24
Peak memory 200424 kb
Host smart-6d5536cc-77dc-48c3-a162-d5c88d9a5c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491076533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2491076533
Directory /workspace/9.hmac_wipe_secret/latest
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