Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18072783	1			T1	21187		T2	32430		T3	39918
all_values[1]	18072783	1			T1	21187		T2	32430		T3	39918
all_values[2]	18072783	1			T1	21187		T2	32430		T3	39918

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298478

1

T1

2

T3

1184

T4

56

auto[1]

53919871

1

T1

63559

T2

97290

T3

118570

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46204128

1

T1

57976

T2

72154

T3

104118

auto[1]

8014221

1

T1

5585

T2

25136

T3

15636

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	124588	1			T5	941		T9	69		T17	14
all_values[0]	auto[0]	auto[1]	396	1			T5	2		T9	2		T17	4
all_values[0]	auto[1]	auto[0]	17928676	1			T1	21175		T2	32419		T3	39905
all_values[0]	auto[1]	auto[1]	19123	1			T1	12		T2	11		T3	13
all_values[1]	auto[0]	auto[0]	94283	1			T1	2		T5	2		T16	191
all_values[1]	auto[0]	auto[1]	206	1			T17	4		T47	4		T6	5
all_values[1]	auto[1]	auto[0]	17977975	1			T1	21185		T2	32430		T3	39918
all_values[1]	auto[1]	auto[1]	319	1			T5	3		T17	6		T47	2
all_values[2]	auto[0]	auto[0]	40276	1			T3	288		T4	56		T5	299
all_values[2]	auto[0]	auto[1]	38729	1			T3	896		T5	366		T17	4
all_values[2]	auto[1]	auto[0]	10038330	1			T1	15614		T2	7305		T3	24007
all_values[2]	auto[1]	auto[1]	7955448	1			T1	5573		T2	25125		T3	14727