Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107876

1

T2

34

T4

2198

T5

196

auto[1]

111156

1

T1

20

T2

32

T3

30

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	83034	1			T1	4		T2	21		T3	13
len_1026_2046	5578	1			T2	3		T4	390		T5	8
len_514_1022	3198	1			T4	13		T10	3		T17	42
len_2_510	3359	1			T4	7		T5	1		T10	3
len_2056	194	1			T10	7		T17	3		T44	2
len_2048	333	1			T3	1		T10	4		T17	2
len_2040	146	1			T5	3		T44	2		T107	1
len_1032	147	1			T10	1		T26	3		T44	2
len_1024	1772	1			T1	1		T5	4		T9	1
len_1016	174	1			T10	1		T26	3		T44	1
len_520	163	1			T26	2		T44	8		T107	3
len_512	317	1			T4	1		T17	1		T44	1
len_504	169	1			T5	3		T10	2		T26	5
len_8	1086	1			T1	5		T3	1		T17	21
len_0	9848	1			T2	9		T5	21		T9	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

122

1

T9

2

T16

2

T44

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	42027	1			T2	13		T4	699		T5	77
auto[0]	len_1026_2046	2675	1			T2	1		T4	382		T5	6
auto[0]	len_514_1022	2080	1			T4	10		T10	3		T17	16
auto[0]	len_2_510	1971	1			T4	7		T10	2		T17	14
auto[0]	len_2056	92	1			T10	5		T17	1		T44	2
auto[0]	len_2048	184	1			T10	3		T107	2		T47	1
auto[0]	len_2040	89	1			T5	3		T44	1		T107	1
auto[0]	len_1032	78	1			T26	3		T107	2		T108	2
auto[0]	len_1024	276	1			T5	2		T17	1		T47	1
auto[0]	len_1016	110	1			T10	1		T26	2		T44	1
auto[0]	len_520	90	1			T26	2		T44	5		T107	2
auto[0]	len_512	188	1			T4	1		T47	2		T108	3
auto[0]	len_504	92	1			T5	1		T26	3		T107	1
auto[0]	len_8	25	1			T56	5		T61	1		T124	2
auto[0]	len_0	3963	1			T2	3		T5	9		T10	4
auto[1]	len_2050_plus	41007	1			T1	4		T2	8		T3	13
auto[1]	len_1026_2046	2903	1			T2	2		T4	8		T5	2
auto[1]	len_514_1022	1118	1			T4	3		T17	26		T44	1
auto[1]	len_2_510	1388	1			T5	1		T10	1		T17	9
auto[1]	len_2056	102	1			T10	2		T17	2		T46	3
auto[1]	len_2048	149	1			T3	1		T10	1		T17	2
auto[1]	len_2040	57	1			T44	1		T68	2		T125	2
auto[1]	len_1032	69	1			T10	1		T44	2		T107	1
auto[1]	len_1024	1496	1			T1	1		T5	2		T9	1
auto[1]	len_1016	64	1			T26	1		T59	2		T109	1
auto[1]	len_520	73	1			T44	3		T107	1		T126	3
auto[1]	len_512	129	1			T17	1		T44	1		T107	2
auto[1]	len_504	77	1			T5	2		T10	2		T26	2
auto[1]	len_8	1061	1			T1	5		T3	1		T17	21
auto[1]	len_0	5885	1			T2	6		T5	12		T9	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

71

1

T16

2

T39

1

T108

2

auto[1]

len_upper

51

1

T9

2

T44

2

T47

2