Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4592190

1

T1

1679

T2

2725

T3

6112

auto[1]

2803486

1

T1

8703

T2

1476

T3

13599

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2854948

1

T1

5973

T2

3322

T3

10547

auto[1]

4540728

1

T1

4409

T2

879

T3

9164

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3242086

1

T2

3685

T4

4521

T5

22298

auto[1]

4153590

1

T1

10382

T2

516

T3

19711

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4635256

1

T1

6783

T2

1219

T3

10973

auto[1]

2760420

1

T1

3599

T2

2982

T3

8738

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6646899	1			T1	8780		T2	3682		T3	17167
fifo_depth[1]	122624	1			T1	224		T2	127		T3	403
fifo_depth[2]	95221	1			T1	240		T2	108		T3	405
fifo_depth[3]	77161	1			T1	261		T2	111		T3	399
fifo_depth[4]	68706	1			T1	228		T2	70		T3	385
fifo_depth[5]	54582	1			T1	183		T2	52		T3	367
fifo_depth[6]	43071	1			T1	188		T2	28		T3	255
fifo_depth[7]	28982	1			T1	121		T2	10		T3	183

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

748777

1

T1

1602

T2

519

T3

2544

auto[1]

6646899

1

T1

8780

T2

3682

T3

17167

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7382340

1

T1

10382

T2

4201

T3

19711

auto[1]

13336

1

T20

69

T23

2

T24

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

32290

1

T2

136

T4

22

T5

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34141

1

T2

103

T4

25

T5

298

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31314

1

T2

50

T4

6

T5

1427

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

33565

1

T2

95

T5

835

T16

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

172430

1

T4

1

T5

134

T9

22

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22405

1

T2

77

T5

376

T16

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26505

1

T4

34

T5

303

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

47337

1

T5

207

T9

9

T16

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48751

1

T2

51

T3

180

T4

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

42871

1

T2

7

T3

455

T4

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45859

1

T1

1177

T5

100

T10

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34561

1

T1

119

T3

253

T5

238

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49482

1

T3

493

T9

5

T16

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38841

1

T3

378

T5

198

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41442

1

T1

306

T3

785

T17

100

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46983

1

T4

11

T9

4

T16

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

176047

1

T2

347

T4

907

T5

806

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

168290

1

T2

988

T4

980

T5

2387

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

182257

1

T2

249

T4

85

T5

4707

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

155114

1

T2

846

T4

701

T5

3451

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1661725

1

T2

2

T4

68

T5

1733

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

168450

1

T2

788

T4

134

T5

1949

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

171125

1

T2

1

T4

1213

T5

3010

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

159091

1

T2

3

T4

345

T5

673

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

492654

1

T1

530

T2

153

T3

598

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

464229

1

T1

2

T2

70

T3

762

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

451628

1

T1

3761

T2

227

T3

5004

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

461377

1

T1

384

T3

3295

T4

190

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

574413

1

T1

1

T2

1

T3

1447

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

445171

1

T1

1146

T2

2

T3

1799

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

477334

1

T1

1008

T2

2

T3

2466

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

437994

1

T1

1948

T2

3

T3

1796

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

207489

1

T2

483

T4

929

T5

808

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

200902

1

T2

1091

T4

1005

T5

2685

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

213003

1

T2

299

T4

91

T5

6134

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

187732

1

T2

941

T4

701

T5

4286

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1833683

1

T2

2

T4

69

T5

1867

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

190562

1

T2

865

T4

134

T5

2325

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

196603

1

T2

1

T4

1247

T5

3313

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

204068

1

T2

3

T4

345

T5

880

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

540537

1

T1

530

T2

204

T3

778

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

506583

1

T1

2

T2

77

T3

1217

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

496615

1

T1

4938

T2

227

T3

5004

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

495564

1

T1

503

T3

3548

T4

190

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

623255

1

T1

1

T2

1

T3

1940

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

483699

1

T1

1146

T2

2

T3

2177

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

518246

1

T1

1314

T2

2

T3

3251

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

483799

1

T1

1948

T2

3

T3

1796

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

848

1

T20

2

T40

298

T8

80

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1529

1

T24

1

T43

23

T132

243

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

568

1

T40

1

T133

1

T134

40

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

947

1

T135

1

T136

1

T43

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

472

1

T42

32

T133

45

T137

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

293

1

T20

22

T135

6

T8

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1027

1

T135

366

T132

7

T8

29

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2360

1

T23

2

T40

6

T43

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

868

1

T138

20

T42

129

T133

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

517

1

T20

42

T8

1

T42

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

872

1

T43

144

T8

94

T137

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

374

1

T40

27

T43

2

T8

138

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

640

1

T20

3

T43

3

T132

42

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

313

1

T132

7

T139

6

T140

28

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

530

1

T40

62

T141

194

T142

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1178

1

T132

33

T8

1

T42

36

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

176047

1

T2

347

T4

907

T5

806

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

168290

1

T2

988

T4

980

T5

2387

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

182257

1

T2

249

T4

85

T5

4707

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

155114

1

T2

846

T4

701

T5

3451

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1661725

1

T2

2

T4

68

T5

1733

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

168450

1

T2

788

T4

134

T5

1949

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

171125

1

T2

1

T4

1213

T5

3010

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

159091

1

T2

3

T4

345

T5

673

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

492654

1

T1

530

T2

153

T3

598

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

464229

1

T1

2

T2

70

T3

762

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

451628

1

T1

3761

T2

227

T3

5004

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

461377

1

T1

384

T3

3295

T4

190

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

574413

1

T1

1

T2

1

T3

1447

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

445171

1

T1

1146

T2

2

T3

1799

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

477334

1

T1

1008

T2

2

T3

2466

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

437994

1

T1

1948

T2

3

T3

1796

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3684

1

T2

36

T4

5

T17

62

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3796

1

T2

23

T4

8

T5

42

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4037

1

T2

9

T5

230

T17

36

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3327

1

T2

32

T5

147

T10

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

45693

1

T5

40

T9

16

T17

114

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3142

1

T2

18

T5

63

T17

83

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3256

1

T4

10

T5

51

T10

2

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3638

1

T5

31

T9

7

T17

49

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

7031

1

T2

7

T3

25

T5

74

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5710

1

T2

2

T3

78

T5

26

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7089

1

T1

156

T5

15

T10

3

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5512

1

T1

19

T3

40

T5

63

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8227

1

T3

88

T9

4

T10

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5748

1

T3

49

T5

49

T10

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6740

1

T1

49

T3

123

T17

36

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5994

1

T4

3

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93

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234

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55

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44

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67

fifo_depth[3]

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16

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1

T1

22

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36

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38

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91

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20

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1

fifo_depth[3]

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1

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56

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28

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1

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1

T1

46

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122

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21

fifo_depth[3]

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4

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2

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23

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4

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5

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48

fifo_depth[4]

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7

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5

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204

fifo_depth[4]

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119

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fifo_depth[4]

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8

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1

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9

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49

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18

fifo_depth[4]

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47

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34

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1

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1

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7

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29

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10

fifo_depth[4]

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T2

3

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73

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4

fifo_depth[4]

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166

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15

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8

fifo_depth[4]

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1

T1

15

T3

36

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24

fifo_depth[4]

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1

T3

72

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5

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1

fifo_depth[4]

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1

T3

60

T5

39

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21

fifo_depth[4]

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1

T1

47

T3

115

T17

12

fifo_depth[4]

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1

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6

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1

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1

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1

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1

T2

15

T5

37

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7

fifo_depth[5]

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1

T2

10

T5

189

T17

7

fifo_depth[5]

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T2

1

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101

T17

1

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2

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fifo_depth[5]

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T2

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56

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1

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3

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49

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1

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1

T5

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20

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1

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36

fifo_depth[5]

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1

T3

72

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11

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1

T1

138

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9

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4

fifo_depth[5]

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1

T1

10

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30

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20

fifo_depth[5]

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1

T3

67

T17

1

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1

fifo_depth[5]

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1

T3

48

T5

13

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5

fifo_depth[5]

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1

T1

35

T3

120

T17

2

fifo_depth[5]

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1

T4

1

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3

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11

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5

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1

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6

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34

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fifo_depth[6]

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1

T2

2

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144

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10

fifo_depth[6]

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1

T5

71

T16

1

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3

fifo_depth[6]

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1

T5

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14

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1

fifo_depth[6]

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1

T2

6

T5

39

T17

11

fifo_depth[6]

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26

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1

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1

fifo_depth[6]

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1

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21

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12

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2

fifo_depth[6]

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3449

1

T2

9

T3

15

T5

27

fifo_depth[6]

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1

T3

39

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3

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31

fifo_depth[6]

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T1

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11

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6

fifo_depth[6]

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1

T1

15

T3

28

T5

14

fifo_depth[6]

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1

T3

53

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1

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2

fifo_depth[6]

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1

T3

34

T5

15

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3

fifo_depth[6]

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1

T1

38

T3

86

T17

1

fifo_depth[6]

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1

T37

6

T38

7

T127

11

fifo_depth[7]

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1

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1

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3

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2

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1

T2

2

T5

26

T17

1

fifo_depth[7]

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1

T2

1

T5

100

T17

4

fifo_depth[7]

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1

T5

43

T38

6

T143

4

fifo_depth[7]

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1

T5

7

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8

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8

fifo_depth[7]

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574

1

T2

2

T5

23

T17

3

fifo_depth[7]

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1

T5

20

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5

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1

fifo_depth[7]

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1

T5

13

T46

9

T56

1

fifo_depth[7]

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2358

1

T2

5

T3

18

T4

1

fifo_depth[7]

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1

T3

24

T5

2

T38

28

fifo_depth[7]

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1993

1

T1

87

T5

10

T17

2

fifo_depth[7]

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1594

1

T1

13

T3

20

T5

11

fifo_depth[7]

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2278

1

T3

25

T144

175

T145

7

fifo_depth[7]

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1

T3

36

T5

8

T46

13

fifo_depth[7]

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1

T1

21

T3

60

T46

13

fifo_depth[7]

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1

T37

2

T38

9

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3