Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18072783	1			T1	21187		T2	32430		T3	39918
all_pins[1]	18072783	1			T1	21187		T2	32430		T3	39918
all_pins[2]	18072783	1			T1	21187		T2	32430		T3	39918

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46242511	1			T1	57974		T2	72154		T3	105010
values[0x1]	7975838	1			T1	5587		T2	25136		T3	14744
transitions[0x0=>0x1]	7975659	1			T1	5587		T2	25136		T3	14744
transitions[0x1=>0x0]	7975674	1			T1	5587		T2	25136		T3	14744

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18052748	1			T1	21173		T2	32419		T3	39901
all_pins[0]	values[0x1]	20035	1			T1	14		T2	11		T3	17
all_pins[0]	transitions[0x0=>0x1]	19962	1			T1	14		T2	11		T3	17
all_pins[0]	transitions[0x1=>0x0]	7955390	1			T1	5573		T2	25125		T3	14727
all_pins[1]	values[0x0]	18072428	1			T1	21187		T2	32430		T3	39918
all_pins[1]	values[0x1]	355	1			T5	3		T17	6		T47	2
all_pins[1]	transitions[0x0=>0x1]	307	1			T5	1		T17	5		T47	2
all_pins[1]	transitions[0x1=>0x0]	19987	1			T1	14		T2	11		T3	17
all_pins[2]	values[0x0]	10117335	1			T1	15614		T2	7305		T3	25191
all_pins[2]	values[0x1]	7955448	1			T1	5573		T2	25125		T3	14727
all_pins[2]	transitions[0x0=>0x1]	7955390	1			T1	5573		T2	25125		T3	14727
all_pins[2]	transitions[0x1=>0x0]	297	1			T17	6		T47	2		T6	1