Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 880 1 T5 7 T17 28 T47 17
all_values[1] 880 1 T5 7 T17 28 T47 17
all_values[2] 880 1 T5 7 T17 28 T47 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1415 1 T5 5 T17 42 T47 31
auto[1] 1225 1 T5 16 T17 42 T47 20


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 921 1 T5 8 T17 30 T47 26
auto[1] 1719 1 T5 13 T17 54 T47 25


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1521 1 T5 14 T17 48 T47 32
auto[1] 1119 1 T5 7 T17 36 T47 19


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 162 1 T5 1 T17 5 T47 4
all_values[0] auto[0] auto[0] auto[1] 99 1 T5 1 T17 2 T47 1
all_values[0] auto[0] auto[1] auto[0] 157 1 T5 1 T17 5 T47 5
all_values[0] auto[0] auto[1] auto[1] 91 1 T5 1 T17 4 T6 3
all_values[0] auto[1] auto[0] auto[1] 193 1 T5 1 T17 9 T47 5
all_values[0] auto[1] auto[1] auto[1] 178 1 T5 2 T17 3 T47 2
all_values[1] auto[0] auto[0] auto[0] 152 1 T5 1 T17 8 T47 6
all_values[1] auto[0] auto[0] auto[1] 116 1 T17 2 T47 3 T6 2
all_values[1] auto[0] auto[1] auto[0] 113 1 T5 2 T17 3 T47 1
all_values[1] auto[0] auto[1] auto[1] 113 1 T5 1 T17 5 T47 1
all_values[1] auto[1] auto[0] auto[1] 220 1 T17 5 T47 4 T6 5
all_values[1] auto[1] auto[1] auto[1] 166 1 T5 3 T17 5 T47 2
all_values[2] auto[0] auto[0] auto[0] 194 1 T5 1 T17 2 T47 3
all_values[2] auto[0] auto[0] auto[1] 89 1 T17 2 T6 6 T56 1
all_values[2] auto[0] auto[1] auto[0] 143 1 T5 2 T17 7 T47 7
all_values[2] auto[0] auto[1] auto[1] 92 1 T5 3 T17 3 T47 1
all_values[2] auto[1] auto[0] auto[1] 190 1 T17 7 T47 5 T6 6
all_values[2] auto[1] auto[1] auto[1] 172 1 T5 1 T17 7 T47 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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