Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4102	1			T1	3		T2	11		T3	1
sha2_none	4075	1			T2	4		T3	5		T4	11
sha2_512	7504	1			T1	11		T2	7		T3	7
sha2_384	7220	1			T1	5		T2	8		T3	2
sha2_256	5880	1			T1	2		T2	5		T3	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18207

1

T1

6

T2

24

T3

11

auto[1]

10950

1

T1

15

T2

12

T3

11

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10993

1

T1

11

T2

22

T3

11

auto[1]

18164

1

T1

10

T2

14

T3

11

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15245

1

T1

21

T2

16

T3

22

disabled

13912

1

T2

20

T4

19

T5

114

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4468	1			T1	6		T2	12		T3	2
key_none	7496	1			T1	1		T2	4		T3	6
key_1024	4250	1			T1	3		T2	2		T3	2
key_512	3658	1			T1	2		T2	9		T3	2
key_384	3335	1			T1	6		T2	4		T3	4
key_256	3018	1			T1	3		T2	3		T3	3
key_128	2857	1			T2	2		T3	3		T4	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18473

1

T1

13

T2

17

T3

12

auto[1]

10684

1

T1

8

T2

19

T3

10

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28960

1

T1

21

T2

35

T3

22

disabled

197

1

T2

1

T5

3

T48

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1637

1

T1

3

T2

6

T3

4

enabled

auto[0]

auto[0]

auto[1]

1508

1

T1

1

T2

2

T3

1

enabled

auto[0]

auto[1]

auto[0]

1570

1

T1

4

T2

3

T3

3

enabled

auto[0]

auto[1]

auto[1]

1564

1

T1

3

T3

3

T4

3

enabled

auto[1]

auto[0]

auto[0]

4263

1

T1

1

T2

1

T3

3

enabled

auto[1]

auto[0]

auto[1]

1513

1

T1

1

T2

2

T3

3

enabled

auto[1]

auto[1]

auto[0]

1708

1

T1

5

T2

1

T3

2

enabled

auto[1]

auto[1]

auto[1]

1482

1

T1

3

T2

1

T3

3

disabled

auto[0]

auto[0]

auto[0]

1173

1

T2

1

T4

4

T5

11

disabled

auto[0]

auto[0]

auto[1]

1225

1

T2

6

T4

4

T5

13

disabled

auto[0]

auto[1]

auto[0]

1200

1

T2

3

T4

2

T5

16

disabled

auto[0]

auto[1]

auto[1]

1116

1

T2

1

T4

2

T5

17

disabled

auto[1]

auto[0]

auto[0]

5769

1

T2

2

T4

1

T5

12

disabled

auto[1]

auto[0]

auto[1]

1119

1

T2

4

T4

2

T5

19

disabled

auto[1]

auto[1]

auto[0]

1153

1

T4

3

T5

12

T16

2

disabled

auto[1]

auto[1]

auto[1]

1157

1

T2

3

T4

1

T5

14

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15159

1

T1

21

T2

15

T3

22

enabled

disabled

86

1

T2

1

T5

1

T122

3

disabled

disabled

111

1

T5

2

T48

2

T123

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13801

1

T2

20

T4

19

T5

112

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1095	1			T2	6		T5	11		T16	3
key_invalid	sha2_none	830	1			T2	1		T3	1		T4	2
key_invalid	sha2_512	815	1			T1	4		T2	1		T5	5
key_invalid	sha2_384	833	1			T1	1		T2	1		T4	1
key_invalid	sha2_256	792	1			T1	1		T2	2		T3	1
key_none	sha2_invalid	516	1			T2	1		T5	3		T16	2
key_none	sha2_none	542	1			T3	2		T4	2		T5	5
key_none	sha2_512	2522	1			T1	1		T2	1		T3	1
key_none	sha2_384	2513	1			T2	1		T3	1		T5	6
key_none	sha2_256	1351	1			T2	1		T3	2		T4	1
key_1024	sha2_invalid	485	1			T1	1		T4	3		T5	8
key_1024	sha2_none	537	1			T4	1		T5	7		T10	4
key_1024	sha2_512	1724	1			T1	2		T3	2		T4	3
key_1024	sha2_384	925	1			T2	2		T5	5		T9	1
key_512	sha2_invalid	477	1			T2	2		T4	1		T5	2
key_512	sha2_none	527	1			T2	2		T3	1		T4	2
key_512	sha2_512	584	1			T2	2		T4	1		T5	7
key_512	sha2_384	1201	1			T1	2		T2	2		T3	1
key_512	sha2_256	817	1			T2	1		T5	3		T16	1
key_384	sha2_invalid	521	1			T1	1		T3	1		T4	1
key_384	sha2_none	537	1			T2	1		T4	2		T5	5
key_384	sha2_512	647	1			T1	4		T2	2		T3	2
key_384	sha2_384	530	1			T2	1		T5	4		T16	3
key_384	sha2_256	1051	1			T1	1		T3	1		T4	1
key_256	sha2_invalid	510	1			T1	1		T2	2		T5	7
key_256	sha2_none	539	1			T4	1		T5	1		T10	1
key_256	sha2_512	611	1			T3	2		T4	1		T5	4
key_256	sha2_384	568	1			T1	2		T4	2		T5	6
key_256	sha2_256	767	1			T2	1		T3	1		T4	1
key_128	sha2_invalid	470	1			T4	3		T5	2		T9	1
key_128	sha2_none	554	1			T3	1		T4	1		T5	4
key_128	sha2_512	589	1			T2	1		T4	1		T5	5
key_128	sha2_384	640	1			T2	1		T5	7		T9	3
key_128	sha2_256	552	1			T3	2		T5	2		T10	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

536

1

T5

4

T16

2

T17

8

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1095	1			T2	6		T5	11		T16	3
key_invalid	sha2_none	830	1			T2	1		T3	1		T4	2
key_invalid	sha2_512	815	1			T1	4		T2	1		T5	5
key_invalid	sha2_384	833	1			T1	1		T2	1		T4	1
key_invalid	sha2_256	792	1			T1	1		T2	2		T3	1
key_none	sha2_invalid	516	1			T2	1		T5	3		T16	2
key_none	sha2_none	542	1			T3	2		T4	2		T5	5
key_none	sha2_512	2522	1			T1	1		T2	1		T3	1
key_none	sha2_384	2513	1			T2	1		T3	1		T5	6
key_none	sha2_256	1351	1			T2	1		T3	2		T4	1
key_1024	sha2_invalid	485	1			T1	1		T4	3		T5	8
key_1024	sha2_none	537	1			T4	1		T5	7		T10	4
key_1024	sha2_512	1724	1			T1	2		T3	2		T4	3
key_1024	sha2_384	925	1			T2	2		T5	5		T9	1
key_1024	sha2_256	536	1			T5	4		T16	2		T17	8
key_512	sha2_invalid	477	1			T2	2		T4	1		T5	2
key_512	sha2_none	527	1			T2	2		T3	1		T4	2
key_512	sha2_512	584	1			T2	2		T4	1		T5	7
key_512	sha2_384	1201	1			T1	2		T2	2		T3	1
key_512	sha2_256	817	1			T2	1		T5	3		T16	1
key_384	sha2_invalid	521	1			T1	1		T3	1		T4	1
key_384	sha2_none	537	1			T2	1		T4	2		T5	5
key_384	sha2_512	647	1			T1	4		T2	2		T3	2
key_384	sha2_384	530	1			T2	1		T5	4		T16	3
key_384	sha2_256	1051	1			T1	1		T3	1		T4	1
key_256	sha2_invalid	510	1			T1	1		T2	2		T5	7
key_256	sha2_none	539	1			T4	1		T5	1		T10	1
key_256	sha2_512	611	1			T3	2		T4	1		T5	4
key_256	sha2_384	568	1			T1	2		T4	2		T5	6
key_256	sha2_256	767	1			T2	1		T3	1		T4	1
key_128	sha2_invalid	470	1			T4	3		T5	2		T9	1
key_128	sha2_none	554	1			T3	1		T4	1		T5	4
key_128	sha2_512	589	1			T2	1		T4	1		T5	5
key_128	sha2_384	640	1			T2	1		T5	7		T9	3
key_128	sha2_256	552	1			T3	2		T5	2		T10	1