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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.35 95.26 97.22 100.00 100.00 98.12 97.97 99.85


Total test records in report: 658
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T535 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1955112041 Jul 15 06:27:16 PM PDT 24 Jul 15 06:27:18 PM PDT 24 13819584 ps
T536 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3883264354 Jul 15 06:26:43 PM PDT 24 Jul 15 06:26:46 PM PDT 24 510122025 ps
T537 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.457770887 Jul 15 06:27:05 PM PDT 24 Jul 15 06:27:07 PM PDT 24 206288550 ps
T82 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2894205518 Jul 15 06:26:51 PM PDT 24 Jul 15 06:26:53 PM PDT 24 32850984 ps
T538 /workspace/coverage/cover_reg_top/0.hmac_intr_test.4038478950 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:46 PM PDT 24 30400626 ps
T539 /workspace/coverage/cover_reg_top/24.hmac_intr_test.685202254 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:13 PM PDT 24 65385271 ps
T64 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3797298493 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:15 PM PDT 24 367520953 ps
T540 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2524578124 Jul 15 06:27:07 PM PDT 24 Jul 15 06:27:10 PM PDT 24 212649132 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2725335283 Jul 15 06:26:45 PM PDT 24 Jul 15 06:26:49 PM PDT 24 25684380 ps
T541 /workspace/coverage/cover_reg_top/43.hmac_intr_test.4140960254 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:17 PM PDT 24 25115789 ps
T99 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2522970030 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:13 PM PDT 24 56282325 ps
T117 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2831582995 Jul 15 06:27:07 PM PDT 24 Jul 15 06:27:10 PM PDT 24 1597510237 ps
T83 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2113873168 Jul 15 06:26:51 PM PDT 24 Jul 15 06:26:53 PM PDT 24 30175435 ps
T542 /workspace/coverage/cover_reg_top/21.hmac_intr_test.216116895 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:12 PM PDT 24 19614073 ps
T113 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1793323685 Jul 15 06:26:50 PM PDT 24 Jul 15 06:26:56 PM PDT 24 1139050844 ps
T543 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3200117019 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:12 PM PDT 24 42561985 ps
T544 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1029325114 Jul 15 06:27:14 PM PDT 24 Jul 15 06:27:15 PM PDT 24 49364760 ps
T545 /workspace/coverage/cover_reg_top/41.hmac_intr_test.4151345532 Jul 15 06:27:18 PM PDT 24 Jul 15 06:27:19 PM PDT 24 36031468 ps
T100 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.318056970 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:04 PM PDT 24 79250658 ps
T84 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1367229781 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:51 PM PDT 24 938448556 ps
T546 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2484296348 Jul 15 06:26:57 PM PDT 24 Jul 15 06:26:59 PM PDT 24 83656651 ps
T85 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.379404704 Jul 15 06:26:45 PM PDT 24 Jul 15 06:27:02 PM PDT 24 342927139 ps
T65 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2346550499 Jul 15 06:27:13 PM PDT 24 Jul 15 06:27:17 PM PDT 24 1262831033 ps
T115 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1263357845 Jul 15 06:27:03 PM PDT 24 Jul 15 06:27:06 PM PDT 24 200817027 ps
T547 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3673269905 Jul 15 06:26:52 PM PDT 24 Jul 15 06:26:54 PM PDT 24 50485914 ps
T548 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2503384472 Jul 15 06:27:18 PM PDT 24 Jul 15 06:27:19 PM PDT 24 78548420 ps
T101 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1009690148 Jul 15 06:26:50 PM PDT 24 Jul 15 06:26:52 PM PDT 24 238356180 ps
T118 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.312283388 Jul 15 06:26:40 PM PDT 24 Jul 15 06:26:45 PM PDT 24 429236486 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3540259819 Jul 15 06:26:56 PM PDT 24 Jul 15 06:26:58 PM PDT 24 30495167 ps
T103 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2042409240 Jul 15 06:26:53 PM PDT 24 Jul 15 06:26:54 PM PDT 24 332918759 ps
T549 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1000321405 Jul 15 06:26:55 PM PDT 24 Jul 15 06:26:56 PM PDT 24 19375396 ps
T104 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.228911997 Jul 15 06:26:57 PM PDT 24 Jul 15 06:26:59 PM PDT 24 32977381 ps
T105 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3997016965 Jul 15 06:26:41 PM PDT 24 Jul 15 06:26:45 PM PDT 24 485472762 ps
T550 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1772272736 Jul 15 06:26:54 PM PDT 24 Jul 15 06:26:56 PM PDT 24 44921699 ps
T551 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.159995432 Jul 15 06:26:39 PM PDT 24 Jul 15 06:26:41 PM PDT 24 20389661 ps
T552 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4230509746 Jul 15 06:26:47 PM PDT 24 Jul 15 06:27:04 PM PDT 24 2028167824 ps
T553 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3872368925 Jul 15 06:27:09 PM PDT 24 Jul 15 06:27:10 PM PDT 24 17844857 ps
T554 /workspace/coverage/cover_reg_top/12.hmac_intr_test.10621613 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:03 PM PDT 24 31331289 ps
T555 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3615119506 Jul 15 06:27:17 PM PDT 24 Jul 15 06:27:18 PM PDT 24 35957267 ps
T86 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1064540573 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:04 PM PDT 24 14516506 ps
T556 /workspace/coverage/cover_reg_top/35.hmac_intr_test.152623897 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:16 PM PDT 24 14360275 ps
T557 /workspace/coverage/cover_reg_top/13.hmac_intr_test.450614642 Jul 15 06:27:01 PM PDT 24 Jul 15 06:27:02 PM PDT 24 23296034 ps
T558 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3623421424 Jul 15 06:26:56 PM PDT 24 Jul 15 06:26:59 PM PDT 24 77846470 ps
T559 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2235337874 Jul 15 06:26:55 PM PDT 24 Jul 15 06:26:57 PM PDT 24 35352120 ps
T87 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3987309180 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:04 PM PDT 24 224117984 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1950138658 Jul 15 06:27:04 PM PDT 24 Jul 15 06:27:07 PM PDT 24 481264194 ps
T561 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3101204714 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:11 PM PDT 24 54863715 ps
T562 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1230720265 Jul 15 06:26:49 PM PDT 24 Jul 15 06:39:16 PM PDT 24 322535783580 ps
T563 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2993405333 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:14 PM PDT 24 64351555 ps
T564 /workspace/coverage/cover_reg_top/18.hmac_intr_test.146850170 Jul 15 06:27:09 PM PDT 24 Jul 15 06:27:11 PM PDT 24 28319253 ps
T565 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3199531339 Jul 15 06:26:58 PM PDT 24 Jul 15 06:27:02 PM PDT 24 507446178 ps
T566 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4131496270 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:53 PM PDT 24 159387074 ps
T567 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2278967272 Jul 15 06:26:49 PM PDT 24 Jul 15 06:26:54 PM PDT 24 169531976 ps
T568 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4179307530 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:15 PM PDT 24 764522578 ps
T569 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1871670491 Jul 15 06:27:03 PM PDT 24 Jul 15 06:27:04 PM PDT 24 18895639 ps
T88 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2655122533 Jul 15 06:26:49 PM PDT 24 Jul 15 06:26:51 PM PDT 24 152875499 ps
T570 /workspace/coverage/cover_reg_top/4.hmac_intr_test.4239822996 Jul 15 06:26:52 PM PDT 24 Jul 15 06:26:53 PM PDT 24 13692997 ps
T89 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.243492365 Jul 15 06:27:07 PM PDT 24 Jul 15 06:27:08 PM PDT 24 101410723 ps
T114 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.945727334 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:13 PM PDT 24 494235318 ps
T571 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2214906591 Jul 15 06:26:39 PM PDT 24 Jul 15 06:26:41 PM PDT 24 109876329 ps
T572 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2118678408 Jul 15 06:27:18 PM PDT 24 Jul 15 06:27:19 PM PDT 24 13380929 ps
T573 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3662470934 Jul 15 06:26:54 PM PDT 24 Jul 15 06:26:59 PM PDT 24 1040825191 ps
T574 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3265678112 Jul 15 06:27:04 PM PDT 24 Jul 15 06:27:08 PM PDT 24 57083238 ps
T575 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3336940628 Jul 15 06:26:42 PM PDT 24 Jul 15 06:26:44 PM PDT 24 73727359 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3816520486 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:48 PM PDT 24 62095241 ps
T576 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2403209543 Jul 15 06:26:42 PM PDT 24 Jul 15 06:26:44 PM PDT 24 32657955 ps
T577 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3135593600 Jul 15 06:27:03 PM PDT 24 Jul 15 06:27:05 PM PDT 24 17624100 ps
T121 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1294898360 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:51 PM PDT 24 595044385 ps
T578 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3593557411 Jul 15 06:27:07 PM PDT 24 Jul 15 06:27:10 PM PDT 24 655818075 ps
T91 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1519511644 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:12 PM PDT 24 44395760 ps
T579 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3558219174 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:46 PM PDT 24 43493123 ps
T580 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.744055970 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:14 PM PDT 24 276203451 ps
T581 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3515341480 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:49 PM PDT 24 56246281 ps
T582 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.952203372 Jul 15 06:26:51 PM PDT 24 Jul 15 06:26:53 PM PDT 24 239574029 ps
T583 /workspace/coverage/cover_reg_top/46.hmac_intr_test.957211715 Jul 15 06:27:17 PM PDT 24 Jul 15 06:27:18 PM PDT 24 12862853 ps
T584 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2569894977 Jul 15 06:26:57 PM PDT 24 Jul 15 06:26:59 PM PDT 24 12915682 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2378899018 Jul 15 06:26:50 PM PDT 24 Jul 15 06:26:54 PM PDT 24 729420658 ps
T586 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4152504334 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:17 PM PDT 24 47288139 ps
T587 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3367407270 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:16 PM PDT 24 45947284 ps
T588 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1472787211 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:13 PM PDT 24 158761605 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4172827995 Jul 15 06:26:51 PM PDT 24 Jul 15 06:26:58 PM PDT 24 390393131 ps
T589 /workspace/coverage/cover_reg_top/38.hmac_intr_test.324221738 Jul 15 06:27:17 PM PDT 24 Jul 15 06:27:18 PM PDT 24 12485703 ps
T590 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4234185344 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:50 PM PDT 24 84328579 ps
T591 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3591269237 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:10 PM PDT 24 44905595 ps
T592 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.414758074 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:14 PM PDT 24 45371701 ps
T593 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3608892076 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:10 PM PDT 24 37838293 ps
T594 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2049495231 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:04 PM PDT 24 34469866 ps
T595 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.797811783 Jul 15 06:27:12 PM PDT 24 Jul 15 06:27:14 PM PDT 24 25310778 ps
T596 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3613716370 Jul 15 06:26:57 PM PDT 24 Jul 15 06:27:03 PM PDT 24 426504532 ps
T94 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.970756386 Jul 15 06:26:43 PM PDT 24 Jul 15 06:26:45 PM PDT 24 39814874 ps
T597 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.39824647 Jul 15 06:27:09 PM PDT 24 Jul 15 06:27:12 PM PDT 24 35240572 ps
T598 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2028088970 Jul 15 06:26:56 PM PDT 24 Jul 15 06:27:00 PM PDT 24 556911643 ps
T599 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4094363220 Jul 15 06:27:09 PM PDT 24 Jul 15 06:27:15 PM PDT 24 229285411 ps
T600 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3498684447 Jul 15 06:27:18 PM PDT 24 Jul 15 06:27:19 PM PDT 24 18427142 ps
T601 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1328749170 Jul 15 06:27:01 PM PDT 24 Jul 15 06:27:03 PM PDT 24 893680280 ps
T602 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.929729639 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:47 PM PDT 24 83118037 ps
T603 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2623466311 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:11 PM PDT 24 21696168 ps
T604 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2632839376 Jul 15 06:27:16 PM PDT 24 Jul 15 06:27:18 PM PDT 24 42783019 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1465289341 Jul 15 06:26:48 PM PDT 24 Jul 15 06:26:50 PM PDT 24 65893986 ps
T606 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1194834355 Jul 15 06:27:07 PM PDT 24 Jul 15 06:27:09 PM PDT 24 194942056 ps
T607 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2494000978 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:13 PM PDT 24 114824058 ps
T119 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4136313861 Jul 15 06:26:39 PM PDT 24 Jul 15 06:26:43 PM PDT 24 165905068 ps
T608 /workspace/coverage/cover_reg_top/2.hmac_intr_test.811593994 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:46 PM PDT 24 241914683 ps
T120 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4133901437 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:14 PM PDT 24 99455746 ps
T609 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3246810056 Jul 15 06:26:57 PM PDT 24 Jul 15 06:27:00 PM PDT 24 143239384 ps
T610 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.651310301 Jul 15 06:26:56 PM PDT 24 Jul 15 06:26:58 PM PDT 24 235467215 ps
T611 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3276914931 Jul 15 06:26:53 PM PDT 24 Jul 15 06:26:55 PM PDT 24 639317202 ps
T612 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2895842660 Jul 15 06:26:50 PM PDT 24 Jul 15 06:26:57 PM PDT 24 117818672 ps
T613 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3122779487 Jul 15 06:26:56 PM PDT 24 Jul 15 06:26:58 PM PDT 24 96172819 ps
T614 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3951625722 Jul 15 06:27:14 PM PDT 24 Jul 15 06:27:15 PM PDT 24 12800443 ps
T615 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1926828443 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:12 PM PDT 24 80249583 ps
T616 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4108767635 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:17 PM PDT 24 24514853 ps
T617 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3134590850 Jul 15 06:26:49 PM PDT 24 Jul 15 06:26:52 PM PDT 24 107947767 ps
T93 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1049772372 Jul 15 06:27:13 PM PDT 24 Jul 15 06:27:14 PM PDT 24 14778429 ps
T618 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.707159328 Jul 15 06:26:57 PM PDT 24 Jul 15 06:30:10 PM PDT 24 12369857112 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2579225480 Jul 15 06:27:06 PM PDT 24 Jul 15 06:27:10 PM PDT 24 2612857906 ps
T620 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4112507348 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:09 PM PDT 24 13859771 ps
T621 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2875459386 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:04 PM PDT 24 11938000 ps
T622 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3779646488 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:57 PM PDT 24 8725819109 ps
T623 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1390092026 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:11 PM PDT 24 118634974 ps
T624 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2371047047 Jul 15 06:27:10 PM PDT 24 Jul 15 06:30:34 PM PDT 24 141937472108 ps
T625 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1429059156 Jul 15 06:26:57 PM PDT 24 Jul 15 06:26:59 PM PDT 24 48778180 ps
T626 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1835166178 Jul 15 06:27:10 PM PDT 24 Jul 15 06:27:11 PM PDT 24 13652850 ps
T627 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1634318412 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:09 PM PDT 24 14923782 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1225373669 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:53 PM PDT 24 299041600 ps
T628 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2399494900 Jul 15 06:27:14 PM PDT 24 Jul 15 06:27:15 PM PDT 24 54396808 ps
T629 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.937759987 Jul 15 06:27:04 PM PDT 24 Jul 15 06:27:06 PM PDT 24 142247331 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2412331320 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:06 PM PDT 24 580987285 ps
T631 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2641216013 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:57 PM PDT 24 212734812 ps
T116 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1002045051 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:52 PM PDT 24 448363385 ps
T632 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.111383412 Jul 15 06:26:39 PM PDT 24 Jul 15 06:26:57 PM PDT 24 1667970752 ps
T633 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.589565153 Jul 15 06:26:50 PM PDT 24 Jul 15 06:26:53 PM PDT 24 37315956 ps
T634 /workspace/coverage/cover_reg_top/8.hmac_intr_test.964479141 Jul 15 06:26:56 PM PDT 24 Jul 15 06:26:57 PM PDT 24 17022102 ps
T635 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2583550728 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:17 PM PDT 24 14482028 ps
T636 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.647153478 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:03 PM PDT 24 20131544 ps
T637 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.812368786 Jul 15 06:27:02 PM PDT 24 Jul 15 06:27:04 PM PDT 24 166290932 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4011906171 Jul 15 06:26:49 PM PDT 24 Jul 15 06:26:52 PM PDT 24 94958173 ps
T639 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4286443939 Jul 15 06:27:06 PM PDT 24 Jul 15 06:27:09 PM PDT 24 50639119 ps
T640 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3203504074 Jul 15 06:27:03 PM PDT 24 Jul 15 06:27:05 PM PDT 24 83951209 ps
T641 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3924429671 Jul 15 06:27:08 PM PDT 24 Jul 15 06:27:11 PM PDT 24 266203150 ps
T642 /workspace/coverage/cover_reg_top/1.hmac_intr_test.288402633 Jul 15 06:26:37 PM PDT 24 Jul 15 06:26:39 PM PDT 24 54514902 ps
T643 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2678044875 Jul 15 06:26:57 PM PDT 24 Jul 15 06:27:00 PM PDT 24 142317732 ps
T644 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1145452199 Jul 15 06:27:03 PM PDT 24 Jul 15 06:27:06 PM PDT 24 160988003 ps
T645 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1062584128 Jul 15 06:27:03 PM PDT 24 Jul 15 06:27:06 PM PDT 24 120591463 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2884774942 Jul 15 06:27:03 PM PDT 24 Jul 15 06:46:21 PM PDT 24 413013399620 ps
T647 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3668715540 Jul 15 06:27:07 PM PDT 24 Jul 15 06:27:12 PM PDT 24 140339949 ps
T648 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1886617134 Jul 15 06:26:55 PM PDT 24 Jul 15 06:26:58 PM PDT 24 134666985 ps
T649 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2705461770 Jul 15 06:27:19 PM PDT 24 Jul 15 06:27:20 PM PDT 24 23766202 ps
T650 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3747342164 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:49 PM PDT 24 78282731 ps
T651 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2594472621 Jul 15 06:27:11 PM PDT 24 Jul 15 06:27:12 PM PDT 24 42360746 ps
T652 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2282864151 Jul 15 06:26:55 PM PDT 24 Jul 15 06:26:57 PM PDT 24 89637879 ps
T653 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1260106781 Jul 15 06:26:46 PM PDT 24 Jul 15 06:26:48 PM PDT 24 33926745 ps
T654 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1114413071 Jul 15 06:26:51 PM PDT 24 Jul 15 06:26:53 PM PDT 24 104688352 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2402255630 Jul 15 06:26:45 PM PDT 24 Jul 15 06:26:55 PM PDT 24 156743123 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4013906867 Jul 15 06:26:49 PM PDT 24 Jul 15 06:26:52 PM PDT 24 85369671 ps
T656 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2080232813 Jul 15 06:26:44 PM PDT 24 Jul 15 06:26:47 PM PDT 24 58317236 ps
T657 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2303217310 Jul 15 06:26:45 PM PDT 24 Jul 15 06:26:49 PM PDT 24 127661513 ps
T658 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2736205204 Jul 15 06:27:15 PM PDT 24 Jul 15 06:27:17 PM PDT 24 16055805 ps

Test location /workspace/coverage/default/26.hmac_stress_all.1990134020
Short name T17
Test name
Test status
Simulation time 182389275472 ps
CPU time 1904.2 seconds
Started Jul 15 06:28:08 PM PDT 24
Finished Jul 15 06:59:53 PM PDT 24
Peak memory 767760 kb
Host smart-6c5192cf-e51f-4392-af44-edfc42b2616b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990134020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1990134020
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3754267553
Short name T47
Test name
Test status
Simulation time 17069734837 ps
CPU time 280.97 seconds
Started Jul 15 06:28:50 PM PDT 24
Finished Jul 15 06:33:31 PM PDT 24
Peak memory 208544 kb
Host smart-e55962b7-f2f1-4e6f-9894-7ded7b46b063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754267553 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3754267553
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3028856291
Short name T21
Test name
Test status
Simulation time 293296199298 ps
CPU time 1077.96 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:45:19 PM PDT 24
Peak memory 634240 kb
Host smart-a34438d7-b6cf-46ad-9a69-48dd1611cf82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028856291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3028856291
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1908840224
Short name T6
Test name
Test status
Simulation time 147229652721 ps
CPU time 4926.39 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 07:49:43 PM PDT 24
Peak memory 846120 kb
Host smart-9979ce5a-e8da-424e-aacc-8634a606ae34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908840224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1908840224
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1793323685
Short name T113
Test name
Test status
Simulation time 1139050844 ps
CPU time 4.5 seconds
Started Jul 15 06:26:50 PM PDT 24
Finished Jul 15 06:26:56 PM PDT 24
Peak memory 200196 kb
Host smart-a2c1a9e7-aeae-4ecf-a251-edddd244ca19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793323685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1793323685
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1198020902
Short name T20
Test name
Test status
Simulation time 715958412 ps
CPU time 18.01 seconds
Started Jul 15 06:28:32 PM PDT 24
Finished Jul 15 06:28:51 PM PDT 24
Peak memory 200316 kb
Host smart-e69dfb42-af00-4678-919f-8ec375a8d3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198020902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1198020902
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3608994005
Short name T52
Test name
Test status
Simulation time 139262953 ps
CPU time 0.83 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:27:20 PM PDT 24
Peak memory 218260 kb
Host smart-ec2695c8-c378-4ef2-b048-7601ce82ff5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608994005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3608994005
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2655122533
Short name T88
Test name
Test status
Simulation time 152875499 ps
CPU time 1.07 seconds
Started Jul 15 06:26:49 PM PDT 24
Finished Jul 15 06:26:51 PM PDT 24
Peak memory 200076 kb
Host smart-1a498dae-700d-4ded-8141-2bb317472cdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655122533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2655122533
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4066813532
Short name T11
Test name
Test status
Simulation time 3953065979 ps
CPU time 208.91 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:32:33 PM PDT 24
Peak memory 200372 kb
Host smart-7dc137b8-5b6e-45d9-ad45-e0f937513f72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066813532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4066813532
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all.666753518
Short name T109
Test name
Test status
Simulation time 29390406165 ps
CPU time 1277.83 seconds
Started Jul 15 06:27:47 PM PDT 24
Finished Jul 15 06:49:06 PM PDT 24
Peak memory 728420 kb
Host smart-df681a6c-8556-436e-b597-5038b97e575c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666753518 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.666753518
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all.578264438
Short name T68
Test name
Test status
Simulation time 150618683681 ps
CPU time 3932.47 seconds
Started Jul 15 06:27:33 PM PDT 24
Finished Jul 15 07:33:07 PM PDT 24
Peak memory 780432 kb
Host smart-0f91f7d5-5dc6-4594-bcf0-cbbd3b246552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578264438 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.578264438
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2094749115
Short name T142
Test name
Test status
Simulation time 162001664043 ps
CPU time 2205.94 seconds
Started Jul 15 06:28:27 PM PDT 24
Finished Jul 15 07:05:13 PM PDT 24
Peak memory 748700 kb
Host smart-b17abc18-b688-4c14-9687-d0513eee5da6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094749115 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2094749115
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1002045051
Short name T116
Test name
Test status
Simulation time 448363385 ps
CPU time 4.49 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 200248 kb
Host smart-f2aa34f8-42b4-4ac2-9420-357062d5fc02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002045051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1002045051
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2659396267
Short name T56
Test name
Test status
Simulation time 52139938533 ps
CPU time 465.46 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:35:32 PM PDT 24
Peak memory 439248 kb
Host smart-0be9c108-71fa-4693-a385-92b555b6d26e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659396267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2659396267
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_alert_test.975608473
Short name T153
Test name
Test status
Simulation time 13367351 ps
CPU time 0.6 seconds
Started Jul 15 06:27:42 PM PDT 24
Finished Jul 15 06:27:43 PM PDT 24
Peak memory 195136 kb
Host smart-e15d4ceb-7898-4a40-a9ba-7dc656bc35f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975608473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.975608473
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2618257482
Short name T5
Test name
Test status
Simulation time 19200676158 ps
CPU time 541.47 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:36:46 PM PDT 24
Peak memory 200356 kb
Host smart-37df444e-ebac-45ad-b922-084da1745fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618257482 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2618257482
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3997016965
Short name T105
Test name
Test status
Simulation time 485472762 ps
CPU time 2.44 seconds
Started Jul 15 06:26:41 PM PDT 24
Finished Jul 15 06:26:45 PM PDT 24
Peak memory 200384 kb
Host smart-6b1a91c3-a6a8-4e9d-bd9d-be31bdfe30d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997016965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3997016965
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4185648538
Short name T237
Test name
Test status
Simulation time 2098201760 ps
CPU time 115.74 seconds
Started Jul 15 06:27:16 PM PDT 24
Finished Jul 15 06:29:13 PM PDT 24
Peak memory 200308 kb
Host smart-2d109dc8-a9cb-4538-81fd-998a1ef3c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185648538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4185648538
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3457385141
Short name T317
Test name
Test status
Simulation time 580981764 ps
CPU time 32.66 seconds
Started Jul 15 06:27:23 PM PDT 24
Finished Jul 15 06:27:56 PM PDT 24
Peak memory 200360 kb
Host smart-ff81c582-3e8f-4fdd-b01d-325f722ebd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457385141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3457385141
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_smoke.2822244056
Short name T67
Test name
Test status
Simulation time 402982776 ps
CPU time 4.89 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:27:47 PM PDT 24
Peak memory 200172 kb
Host smart-a9821ac4-a339-4f68-b44d-381b651831b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822244056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2822244056
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2346550499
Short name T65
Test name
Test status
Simulation time 1262831033 ps
CPU time 3.94 seconds
Started Jul 15 06:27:13 PM PDT 24
Finished Jul 15 06:27:17 PM PDT 24
Peak memory 200144 kb
Host smart-f1559b4c-93a0-4a64-b1a9-f140dc220663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346550499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2346550499
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3267235955
Short name T13
Test name
Test status
Simulation time 77048428254 ps
CPU time 315.25 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:32:31 PM PDT 24
Peak memory 208504 kb
Host smart-9d4444d7-be08-4a42-abef-2beb37424ce7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267235955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3267235955
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2402255630
Short name T96
Test name
Test status
Simulation time 156743123 ps
CPU time 8.36 seconds
Started Jul 15 06:26:45 PM PDT 24
Finished Jul 15 06:26:55 PM PDT 24
Peak memory 200300 kb
Host smart-88334148-cab3-41b9-a15f-320e23d59ac9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402255630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2402255630
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.111383412
Short name T632
Test name
Test status
Simulation time 1667970752 ps
CPU time 16.79 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 200304 kb
Host smart-600e884e-a7da-4de3-91dc-396616080b00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111383412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.111383412
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2214906591
Short name T571
Test name
Test status
Simulation time 109876329 ps
CPU time 1 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 200104 kb
Host smart-57e94cdc-d821-4e35-985b-8fcfb3a73177
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214906591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2214906591
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.159995432
Short name T551
Test name
Test status
Simulation time 20389661 ps
CPU time 1.19 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:41 PM PDT 24
Peak memory 200172 kb
Host smart-ebdeba58-74eb-4a8e-87df-85ffa3ea95c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159995432 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.159995432
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.970756386
Short name T94
Test name
Test status
Simulation time 39814874 ps
CPU time 0.81 seconds
Started Jul 15 06:26:43 PM PDT 24
Finished Jul 15 06:26:45 PM PDT 24
Peak memory 200080 kb
Host smart-9cc13752-4bf7-4955-abb0-b619f59d88fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970756386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.970756386
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.4038478950
Short name T538
Test name
Test status
Simulation time 30400626 ps
CPU time 0.62 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 195140 kb
Host smart-3ba1f2b7-bdd3-40b6-b01b-5d8ffb01f4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038478950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.4038478950
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.929729639
Short name T602
Test name
Test status
Simulation time 83118037 ps
CPU time 1.68 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:47 PM PDT 24
Peak memory 200304 kb
Host smart-994924df-f6d5-48a9-993e-60dfc0003b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929729639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.929729639
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4136313861
Short name T119
Test name
Test status
Simulation time 165905068 ps
CPU time 2.89 seconds
Started Jul 15 06:26:39 PM PDT 24
Finished Jul 15 06:26:43 PM PDT 24
Peak memory 200260 kb
Host smart-58637322-c939-4841-830d-8f31ebc1c393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136313861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4136313861
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4131496270
Short name T566
Test name
Test status
Simulation time 159387074 ps
CPU time 7.82 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 200252 kb
Host smart-1f65e4e4-508f-4029-bd34-6a5dc3f24606
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131496270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4131496270
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2641216013
Short name T631
Test name
Test status
Simulation time 212734812 ps
CPU time 9.51 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 200264 kb
Host smart-1b10c7f6-6cde-4550-a930-c01321aafd01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641216013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2641216013
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3747342164
Short name T650
Test name
Test status
Simulation time 78282731 ps
CPU time 1.6 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:49 PM PDT 24
Peak memory 200388 kb
Host smart-dfeb08a7-1c4f-4151-b934-19eb82cdf1a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747342164 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3747342164
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3816520486
Short name T90
Test name
Test status
Simulation time 62095241 ps
CPU time 0.87 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:48 PM PDT 24
Peak memory 199856 kb
Host smart-e6be640a-f017-4eba-a278-5d02f59aab99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816520486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3816520486
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.288402633
Short name T642
Test name
Test status
Simulation time 54514902 ps
CPU time 0.59 seconds
Started Jul 15 06:26:37 PM PDT 24
Finished Jul 15 06:26:39 PM PDT 24
Peak memory 195200 kb
Host smart-08795f65-faf7-46ca-8b76-1f988f66b831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288402633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.288402633
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2725335283
Short name T98
Test name
Test status
Simulation time 25684380 ps
CPU time 1.19 seconds
Started Jul 15 06:26:45 PM PDT 24
Finished Jul 15 06:26:49 PM PDT 24
Peak memory 200276 kb
Host smart-7973978b-618f-47a4-b401-d1e9b926092e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725335283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2725335283
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3883264354
Short name T536
Test name
Test status
Simulation time 510122025 ps
CPU time 2.07 seconds
Started Jul 15 06:26:43 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 200188 kb
Host smart-c3386fe6-ef9f-45ef-80e4-93a8f7876a25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883264354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3883264354
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.312283388
Short name T118
Test name
Test status
Simulation time 429236486 ps
CPU time 3 seconds
Started Jul 15 06:26:40 PM PDT 24
Finished Jul 15 06:26:45 PM PDT 24
Peak memory 200272 kb
Host smart-d98fa28c-ee83-4ef2-a470-abedcb85e443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312283388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.312283388
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3593557411
Short name T578
Test name
Test status
Simulation time 655818075 ps
CPU time 2.51 seconds
Started Jul 15 06:27:07 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 200328 kb
Host smart-43f2bb4e-29f7-408c-86a5-a31532b3c59b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593557411 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3593557411
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.797811783
Short name T595
Test name
Test status
Simulation time 25310778 ps
CPU time 0.84 seconds
Started Jul 15 06:27:12 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 199632 kb
Host smart-eebbb0b6-d8be-4e9f-b68d-1d27896664a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797811783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.797811783
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2569894977
Short name T584
Test name
Test status
Simulation time 12915682 ps
CPU time 0.57 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 195248 kb
Host smart-75cd60ac-3a43-414b-a2ef-d9129f75baed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569894977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2569894977
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2028088970
Short name T598
Test name
Test status
Simulation time 556911643 ps
CPU time 2.37 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:27:00 PM PDT 24
Peak memory 200288 kb
Host smart-13c6face-d916-4597-9dfb-f1de9c63ca1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028088970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2028088970
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3662470934
Short name T573
Test name
Test status
Simulation time 1040825191 ps
CPU time 4.03 seconds
Started Jul 15 06:26:54 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 200268 kb
Host smart-f48cd15d-449c-4505-9faf-7ad0dd02ac97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662470934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3662470934
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2831582995
Short name T117
Test name
Test status
Simulation time 1597510237 ps
CPU time 1.98 seconds
Started Jul 15 06:27:07 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 200236 kb
Host smart-aa690d38-65d2-4e15-bf96-b0c4e48d6811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831582995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2831582995
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.812368786
Short name T637
Test name
Test status
Simulation time 166290932 ps
CPU time 1.33 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 200380 kb
Host smart-26339480-dac1-4214-961d-7092a531583b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812368786 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.812368786
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1429059156
Short name T625
Test name
Test status
Simulation time 48778180 ps
CPU time 0.82 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 199828 kb
Host smart-77551236-feb1-4eac-bf5b-7d08551f0c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429059156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1429059156
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2484296348
Short name T546
Test name
Test status
Simulation time 83656651 ps
CPU time 0.63 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 195152 kb
Host smart-5b030aa1-64cf-40ba-8b9c-4ca90c1117e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484296348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2484296348
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1886617134
Short name T648
Test name
Test status
Simulation time 134666985 ps
CPU time 1.68 seconds
Started Jul 15 06:26:55 PM PDT 24
Finished Jul 15 06:26:58 PM PDT 24
Peak memory 200328 kb
Host smart-db38e555-9f8f-47ad-8b7e-8a3714d84f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886617134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1886617134
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1194834355
Short name T606
Test name
Test status
Simulation time 194942056 ps
CPU time 1.91 seconds
Started Jul 15 06:27:07 PM PDT 24
Finished Jul 15 06:27:09 PM PDT 24
Peak memory 200328 kb
Host smart-7e8b758d-7f33-45e5-922d-ee7fffe33aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194834355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1194834355
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4286443939
Short name T639
Test name
Test status
Simulation time 50639119 ps
CPU time 1.78 seconds
Started Jul 15 06:27:06 PM PDT 24
Finished Jul 15 06:27:09 PM PDT 24
Peak memory 200260 kb
Host smart-7d44a571-6fea-4190-a901-d5c852afa177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286443939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4286443939
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3265678112
Short name T574
Test name
Test status
Simulation time 57083238 ps
CPU time 3.64 seconds
Started Jul 15 06:27:04 PM PDT 24
Finished Jul 15 06:27:08 PM PDT 24
Peak memory 216660 kb
Host smart-e99c6b9d-ed5a-44e5-ad11-652c869c5432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265678112 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3265678112
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.647153478
Short name T636
Test name
Test status
Simulation time 20131544 ps
CPU time 0.74 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:03 PM PDT 24
Peak memory 198820 kb
Host smart-a1e062fd-2dee-4612-b8ed-555b85e5d84d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647153478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.647153478
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.10621613
Short name T554
Test name
Test status
Simulation time 31331289 ps
CPU time 0.65 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:03 PM PDT 24
Peak memory 195272 kb
Host smart-f9ac2199-7592-468d-92c0-e528636bf698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10621613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.10621613
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.318056970
Short name T100
Test name
Test status
Simulation time 79250658 ps
CPU time 1.86 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 200268 kb
Host smart-bfccad36-3a12-4b78-aafc-1233a91ee9ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318056970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.318056970
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1950138658
Short name T560
Test name
Test status
Simulation time 481264194 ps
CPU time 1.69 seconds
Started Jul 15 06:27:04 PM PDT 24
Finished Jul 15 06:27:07 PM PDT 24
Peak memory 200272 kb
Host smart-c45707f2-2cc4-42af-9cc7-e685758199d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950138658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1950138658
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1263357845
Short name T115
Test name
Test status
Simulation time 200817027 ps
CPU time 1.76 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 200280 kb
Host smart-229853fc-5ae8-4cdf-a409-524446418849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263357845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1263357845
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.457770887
Short name T537
Test name
Test status
Simulation time 206288550 ps
CPU time 1.78 seconds
Started Jul 15 06:27:05 PM PDT 24
Finished Jul 15 06:27:07 PM PDT 24
Peak memory 200384 kb
Host smart-779e8e1a-3a64-4863-9d78-de2ee69366d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457770887 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.457770887
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3987309180
Short name T87
Test name
Test status
Simulation time 224117984 ps
CPU time 0.84 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 200028 kb
Host smart-61754b95-ea96-4ac4-90e0-1ba72ef25011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987309180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3987309180
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.450614642
Short name T557
Test name
Test status
Simulation time 23296034 ps
CPU time 0.61 seconds
Started Jul 15 06:27:01 PM PDT 24
Finished Jul 15 06:27:02 PM PDT 24
Peak memory 195320 kb
Host smart-cdc9b479-2812-4fc1-9456-d1c093dbaebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450614642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.450614642
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3203504074
Short name T640
Test name
Test status
Simulation time 83951209 ps
CPU time 1.16 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:27:05 PM PDT 24
Peak memory 200228 kb
Host smart-20ca764a-4f6e-4de6-bc9f-f48da9220138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203504074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3203504074
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1472787211
Short name T588
Test name
Test status
Simulation time 158761605 ps
CPU time 4.37 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:13 PM PDT 24
Peak memory 200396 kb
Host smart-7297ee52-55f3-4c8a-95c7-0c492f1513a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472787211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1472787211
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2183475214
Short name T63
Test name
Test status
Simulation time 334343725 ps
CPU time 4.55 seconds
Started Jul 15 06:27:04 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 200288 kb
Host smart-f12a1fa7-3e18-427e-a982-c94932d37c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183475214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2183475214
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.937759987
Short name T629
Test name
Test status
Simulation time 142247331 ps
CPU time 1.16 seconds
Started Jul 15 06:27:04 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 200172 kb
Host smart-bf0bdfe2-295b-4a39-ad5d-1275e3abf2d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937759987 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.937759987
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1064540573
Short name T86
Test name
Test status
Simulation time 14516506 ps
CPU time 0.88 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 199940 kb
Host smart-b10a1c30-f732-455a-9ce3-586c083e8ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064540573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1064540573
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2875459386
Short name T621
Test name
Test status
Simulation time 11938000 ps
CPU time 0.59 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 195124 kb
Host smart-f80d847d-15d5-480f-9ddc-858ed2e4465c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875459386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2875459386
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2049495231
Short name T594
Test name
Test status
Simulation time 34469866 ps
CPU time 1.62 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 200308 kb
Host smart-15a27a2d-996e-42f7-83b9-c75e01dbef69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049495231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2049495231
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1328749170
Short name T601
Test name
Test status
Simulation time 893680280 ps
CPU time 1.94 seconds
Started Jul 15 06:27:01 PM PDT 24
Finished Jul 15 06:27:03 PM PDT 24
Peak memory 200236 kb
Host smart-d03e3a5e-6ef7-41e4-89ac-7c2abb9c3235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328749170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1328749170
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2579225480
Short name T619
Test name
Test status
Simulation time 2612857906 ps
CPU time 3.1 seconds
Started Jul 15 06:27:06 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 200304 kb
Host smart-0d1c3798-533d-4987-8fd8-b3e17f65d040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579225480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2579225480
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2884774942
Short name T646
Test name
Test status
Simulation time 413013399620 ps
CPU time 1157.38 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:46:21 PM PDT 24
Peak memory 216896 kb
Host smart-5d81642d-d114-40dd-966c-00590c1d5a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884774942 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2884774942
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1871670491
Short name T569
Test name
Test status
Simulation time 18895639 ps
CPU time 0.76 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 198300 kb
Host smart-a89d2549-43ca-410b-a42f-150650ac2dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871670491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1871670491
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3135593600
Short name T577
Test name
Test status
Simulation time 17624100 ps
CPU time 0.6 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:27:05 PM PDT 24
Peak memory 195188 kb
Host smart-d6b3a982-174d-46c5-8101-846c5d8d2fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135593600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3135593600
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1062584128
Short name T645
Test name
Test status
Simulation time 120591463 ps
CPU time 2.43 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 200260 kb
Host smart-2b248afa-63b8-40db-86f9-933a231d8d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062584128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1062584128
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1145452199
Short name T644
Test name
Test status
Simulation time 160988003 ps
CPU time 1.94 seconds
Started Jul 15 06:27:03 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 200256 kb
Host smart-3139b2d4-aa4f-4fb0-a9b6-adaa10cb0420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145452199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1145452199
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2412331320
Short name T630
Test name
Test status
Simulation time 580987285 ps
CPU time 3.17 seconds
Started Jul 15 06:27:02 PM PDT 24
Finished Jul 15 06:27:06 PM PDT 24
Peak memory 200264 kb
Host smart-239b8bcd-c77d-4f23-9c0c-dda90f0e711f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412331320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2412331320
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2993405333
Short name T563
Test name
Test status
Simulation time 64351555 ps
CPU time 1.99 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 200388 kb
Host smart-a11d45f2-3698-433d-8140-a988db89b483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993405333 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2993405333
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1049772372
Short name T93
Test name
Test status
Simulation time 14778429 ps
CPU time 0.68 seconds
Started Jul 15 06:27:13 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 197744 kb
Host smart-2bcf36cf-8fc3-414d-8596-218d6d9761d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049772372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1049772372
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3591269237
Short name T591
Test name
Test status
Simulation time 44905595 ps
CPU time 0.59 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 195304 kb
Host smart-6348ad2d-30ea-4529-9296-fb821758bace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591269237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3591269237
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3988839766
Short name T97
Test name
Test status
Simulation time 42517124 ps
CPU time 1.13 seconds
Started Jul 15 06:27:09 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 200360 kb
Host smart-6a97e667-4850-447a-9868-ae0429d2f86c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988839766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3988839766
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4094363220
Short name T599
Test name
Test status
Simulation time 229285411 ps
CPU time 4.28 seconds
Started Jul 15 06:27:09 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 200284 kb
Host smart-796433a0-5fd5-4e6b-84fd-32bdcdbdab95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094363220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.4094363220
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4133901437
Short name T120
Test name
Test status
Simulation time 99455746 ps
CPU time 2.89 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 200228 kb
Host smart-ff7defeb-eae0-48dc-9e79-198b26f2449f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133901437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4133901437
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.39824647
Short name T597
Test name
Test status
Simulation time 35240572 ps
CPU time 2.49 seconds
Started Jul 15 06:27:09 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 200632 kb
Host smart-d8dcdf69-f6a4-43cb-9ad3-812f0664fc1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824647 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.39824647
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1519511644
Short name T91
Test name
Test status
Simulation time 44395760 ps
CPU time 0.79 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 199376 kb
Host smart-b5b09186-4f8d-4030-949a-dd7eed35ea65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519511644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1519511644
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2623466311
Short name T603
Test name
Test status
Simulation time 21696168 ps
CPU time 0.61 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 195212 kb
Host smart-64922311-4521-4e62-a9d4-945f408d8520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623466311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2623466311
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3924429671
Short name T641
Test name
Test status
Simulation time 266203150 ps
CPU time 2.24 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 200252 kb
Host smart-4337198a-d777-4415-a645-15c1a4d30cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924429671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3924429671
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2494000978
Short name T607
Test name
Test status
Simulation time 114824058 ps
CPU time 1.77 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:13 PM PDT 24
Peak memory 200240 kb
Host smart-5bb59ee3-3af6-437c-9f51-d6e55323487a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494000978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2494000978
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3779646488
Short name T622
Test name
Test status
Simulation time 8725819109 ps
CPU time 47.24 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:57 PM PDT 24
Peak memory 216076 kb
Host smart-3c7c588e-1058-4964-9804-d10599a123be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779646488 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3779646488
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1926828443
Short name T615
Test name
Test status
Simulation time 80249583 ps
CPU time 0.82 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 199648 kb
Host smart-3ceb61db-49dd-4411-bded-81a9c17ea05b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926828443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1926828443
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.146850170
Short name T564
Test name
Test status
Simulation time 28319253 ps
CPU time 0.63 seconds
Started Jul 15 06:27:09 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 195240 kb
Host smart-ee259f11-bd46-4496-ab1f-f64be764f41a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146850170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.146850170
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.414758074
Short name T592
Test name
Test status
Simulation time 45371701 ps
CPU time 2.14 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 200108 kb
Host smart-5753af59-61ce-46d8-a995-0c03f9db4812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414758074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.414758074
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4179307530
Short name T568
Test name
Test status
Simulation time 764522578 ps
CPU time 4.08 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 200328 kb
Host smart-9e493404-02b4-43e5-b958-7a1e8815365a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179307530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4179307530
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.945727334
Short name T114
Test name
Test status
Simulation time 494235318 ps
CPU time 4.21 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:13 PM PDT 24
Peak memory 200312 kb
Host smart-fb45c562-8c88-4c29-8936-f5148d14911d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945727334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.945727334
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2371047047
Short name T624
Test name
Test status
Simulation time 141937472108 ps
CPU time 203.56 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:30:34 PM PDT 24
Peak memory 216456 kb
Host smart-a998422d-4d5e-4eab-ba47-64f3b0f0f4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371047047 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2371047047
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2522970030
Short name T99
Test name
Test status
Simulation time 56282325 ps
CPU time 0.98 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:13 PM PDT 24
Peak memory 199708 kb
Host smart-67b95bc9-bd22-4332-bfc5-870fa4da78a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522970030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2522970030
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2594472621
Short name T651
Test name
Test status
Simulation time 42360746 ps
CPU time 0.58 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 195308 kb
Host smart-9aace541-a629-421f-91e2-a76ed9b1de29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594472621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2594472621
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.744055970
Short name T580
Test name
Test status
Simulation time 276203451 ps
CPU time 2.35 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:14 PM PDT 24
Peak memory 200324 kb
Host smart-0d028e53-7d7a-49b6-8722-d3c6b1cd8854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744055970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.744055970
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3101204714
Short name T561
Test name
Test status
Simulation time 54863715 ps
CPU time 1.77 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 200288 kb
Host smart-452fabb5-f242-4079-9996-c2f57f8f7eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101204714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3101204714
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3797298493
Short name T64
Test name
Test status
Simulation time 367520953 ps
CPU time 3.98 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 200268 kb
Host smart-443c9fd8-1cf8-4a3e-9567-49db9c10657c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797298493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3797298493
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1225373669
Short name T95
Test name
Test status
Simulation time 299041600 ps
CPU time 8.11 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 200280 kb
Host smart-25e55894-2733-4ff2-afd1-6074d557b41b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225373669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1225373669
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4230509746
Short name T552
Test name
Test status
Simulation time 2028167824 ps
CPU time 15.79 seconds
Started Jul 15 06:26:47 PM PDT 24
Finished Jul 15 06:27:04 PM PDT 24
Peak memory 200212 kb
Host smart-d6a9d74a-a003-4121-8138-c8594e926612
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230509746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4230509746
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3515341480
Short name T581
Test name
Test status
Simulation time 56246281 ps
CPU time 0.89 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:49 PM PDT 24
Peak memory 199356 kb
Host smart-a207c348-0ed6-4d69-850e-9254370c4968
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515341480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3515341480
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1863464730
Short name T533
Test name
Test status
Simulation time 43759395 ps
CPU time 1.1 seconds
Started Jul 15 06:26:43 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 200092 kb
Host smart-78b4de9b-04d9-4c3d-9565-722f1d0708df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863464730 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1863464730
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1260106781
Short name T653
Test name
Test status
Simulation time 33926745 ps
CPU time 0.72 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:48 PM PDT 24
Peak memory 197796 kb
Host smart-e1084ac0-d269-476d-aa04-777155e48d69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260106781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1260106781
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.811593994
Short name T608
Test name
Test status
Simulation time 241914683 ps
CPU time 0.61 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 195272 kb
Host smart-6fdb1d60-915d-4601-b94c-3093f02bd9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811593994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.811593994
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4234185344
Short name T590
Test name
Test status
Simulation time 84328579 ps
CPU time 1.85 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:50 PM PDT 24
Peak memory 200108 kb
Host smart-07ad5b0a-fbb9-47f0-a3c9-aab45c8ada51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234185344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.4234185344
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2303217310
Short name T657
Test name
Test status
Simulation time 127661513 ps
CPU time 2.47 seconds
Started Jul 15 06:26:45 PM PDT 24
Finished Jul 15 06:26:49 PM PDT 24
Peak memory 200224 kb
Host smart-2b7f2a4a-2892-442b-9c99-3ec8522edaee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303217310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2303217310
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1294898360
Short name T121
Test name
Test status
Simulation time 595044385 ps
CPU time 2.91 seconds
Started Jul 15 06:26:46 PM PDT 24
Finished Jul 15 06:26:51 PM PDT 24
Peak memory 200352 kb
Host smart-4e2c9c2e-a832-4d59-8d30-67ce0fd89911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294898360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1294898360
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3872368925
Short name T553
Test name
Test status
Simulation time 17844857 ps
CPU time 0.61 seconds
Started Jul 15 06:27:09 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 195244 kb
Host smart-6458b529-0d3b-482c-98e9-2b45d35c7982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872368925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3872368925
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.216116895
Short name T542
Test name
Test status
Simulation time 19614073 ps
CPU time 0.62 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 195284 kb
Host smart-804c0971-fd43-497d-9f77-f403dd2f22d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216116895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.216116895
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3367407270
Short name T587
Test name
Test status
Simulation time 45947284 ps
CPU time 0.58 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:16 PM PDT 24
Peak memory 195284 kb
Host smart-a876ec60-543f-4fee-abcd-b694d218676b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367407270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3367407270
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3200117019
Short name T543
Test name
Test status
Simulation time 42561985 ps
CPU time 0.61 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 195332 kb
Host smart-1f7ef158-ea44-40e4-b21f-b70f13b1ebf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200117019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3200117019
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.685202254
Short name T539
Test name
Test status
Simulation time 65385271 ps
CPU time 0.57 seconds
Started Jul 15 06:27:11 PM PDT 24
Finished Jul 15 06:27:13 PM PDT 24
Peak memory 195204 kb
Host smart-a402f57f-3c46-4969-8779-b09dc0a5693c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685202254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.685202254
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4152504334
Short name T586
Test name
Test status
Simulation time 47288139 ps
CPU time 0.61 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:17 PM PDT 24
Peak memory 195288 kb
Host smart-9ec3cccb-57f1-4159-8e03-e498bbdc396b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152504334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4152504334
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3608892076
Short name T593
Test name
Test status
Simulation time 37838293 ps
CPU time 0.59 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 195196 kb
Host smart-25a456c7-6316-44d2-9228-2e0e1679a964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608892076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3608892076
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4112507348
Short name T620
Test name
Test status
Simulation time 13859771 ps
CPU time 0.6 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:09 PM PDT 24
Peak memory 195144 kb
Host smart-0dff045c-8f22-44af-9b47-5c1657793dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112507348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4112507348
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1634318412
Short name T627
Test name
Test status
Simulation time 14923782 ps
CPU time 0.62 seconds
Started Jul 15 06:27:08 PM PDT 24
Finished Jul 15 06:27:09 PM PDT 24
Peak memory 195128 kb
Host smart-b1263d2b-b35e-42b6-aef5-e20f81506b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634318412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1634318412
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1390092026
Short name T623
Test name
Test status
Simulation time 118634974 ps
CPU time 0.61 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 195272 kb
Host smart-443ecf82-8ad3-43ca-b195-7ee6235f9b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390092026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1390092026
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1367229781
Short name T84
Test name
Test status
Simulation time 938448556 ps
CPU time 6.14 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:51 PM PDT 24
Peak memory 200292 kb
Host smart-9a38aadf-e6fe-4ae2-b491-6afedc3e5178
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367229781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1367229781
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.379404704
Short name T85
Test name
Test status
Simulation time 342927139 ps
CPU time 15.22 seconds
Started Jul 15 06:26:45 PM PDT 24
Finished Jul 15 06:27:02 PM PDT 24
Peak memory 199372 kb
Host smart-a96cb590-b4fb-438a-bcbe-b3d47061468e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379404704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.379404704
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3336940628
Short name T575
Test name
Test status
Simulation time 73727359 ps
CPU time 0.75 seconds
Started Jul 15 06:26:42 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 197880 kb
Host smart-e62efda9-f79c-4ecb-a100-5684786d7bea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336940628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3336940628
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1230720265
Short name T562
Test name
Test status
Simulation time 322535783580 ps
CPU time 745.74 seconds
Started Jul 15 06:26:49 PM PDT 24
Finished Jul 15 06:39:16 PM PDT 24
Peak memory 224944 kb
Host smart-eaccf898-387c-4d28-9505-9b560be277cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230720265 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1230720265
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2403209543
Short name T576
Test name
Test status
Simulation time 32657955 ps
CPU time 0.67 seconds
Started Jul 15 06:26:42 PM PDT 24
Finished Jul 15 06:26:44 PM PDT 24
Peak memory 198132 kb
Host smart-6313350e-e1b4-492a-a728-99a3c2e1e15b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403209543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2403209543
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3558219174
Short name T579
Test name
Test status
Simulation time 43493123 ps
CPU time 0.59 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:46 PM PDT 24
Peak memory 195184 kb
Host smart-5066265f-a9df-4b25-bcce-d69194a9c3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558219174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3558219174
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3540259819
Short name T102
Test name
Test status
Simulation time 30495167 ps
CPU time 1.56 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:26:58 PM PDT 24
Peak memory 200360 kb
Host smart-9f5db914-5cde-4ce4-98d5-6b3ae7c6c8ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540259819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3540259819
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2080232813
Short name T656
Test name
Test status
Simulation time 58317236 ps
CPU time 1.49 seconds
Started Jul 15 06:26:44 PM PDT 24
Finished Jul 15 06:26:47 PM PDT 24
Peak memory 200256 kb
Host smart-c2e24267-f10e-468f-92fb-848f636adaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080232813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2080232813
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1835166178
Short name T626
Test name
Test status
Simulation time 13652850 ps
CPU time 0.62 seconds
Started Jul 15 06:27:10 PM PDT 24
Finished Jul 15 06:27:11 PM PDT 24
Peak memory 195252 kb
Host smart-ba269cb3-57d5-48e6-8dcd-2255fd5c2b45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835166178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1835166178
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2399494900
Short name T628
Test name
Test status
Simulation time 54396808 ps
CPU time 0.6 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 195168 kb
Host smart-ff28250b-c927-479d-b404-66f5c0c323e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399494900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2399494900
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3498684447
Short name T600
Test name
Test status
Simulation time 18427142 ps
CPU time 0.62 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:27:19 PM PDT 24
Peak memory 195272 kb
Host smart-ea81dabc-bdf1-426f-b89c-07c95824ebc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498684447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3498684447
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1029325114
Short name T544
Test name
Test status
Simulation time 49364760 ps
CPU time 0.62 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 195264 kb
Host smart-97769132-ae14-41d9-b26d-e528bfbf807d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029325114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1029325114
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2705461770
Short name T649
Test name
Test status
Simulation time 23766202 ps
CPU time 0.58 seconds
Started Jul 15 06:27:19 PM PDT 24
Finished Jul 15 06:27:20 PM PDT 24
Peak memory 195292 kb
Host smart-5c88b595-e48c-4b20-a5d2-279e73d5d41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705461770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2705461770
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.152623897
Short name T556
Test name
Test status
Simulation time 14360275 ps
CPU time 0.58 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:16 PM PDT 24
Peak memory 195144 kb
Host smart-e062572e-bbf9-43f2-a4fb-90afac1df304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152623897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.152623897
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2503384472
Short name T548
Test name
Test status
Simulation time 78548420 ps
CPU time 0.62 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:27:19 PM PDT 24
Peak memory 195236 kb
Host smart-95e92928-04bf-416a-872b-303a07d99615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503384472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2503384472
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2632839376
Short name T604
Test name
Test status
Simulation time 42783019 ps
CPU time 0.6 seconds
Started Jul 15 06:27:16 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 195124 kb
Host smart-7074bdb6-6b23-4d4a-a1f9-52b6af05f444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632839376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2632839376
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.324221738
Short name T589
Test name
Test status
Simulation time 12485703 ps
CPU time 0.64 seconds
Started Jul 15 06:27:17 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 195276 kb
Host smart-23777ea7-3d3a-4b64-8f29-8c07c49ffc3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324221738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.324221738
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3615119506
Short name T555
Test name
Test status
Simulation time 35957267 ps
CPU time 0.66 seconds
Started Jul 15 06:27:17 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 195272 kb
Host smart-463ac518-a452-45d9-a35b-aabea1be3544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615119506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3615119506
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4172827995
Short name T92
Test name
Test status
Simulation time 390393131 ps
CPU time 5.78 seconds
Started Jul 15 06:26:51 PM PDT 24
Finished Jul 15 06:26:58 PM PDT 24
Peak memory 200232 kb
Host smart-dc2c8c5d-f135-49fb-a81f-3b7e60453272
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172827995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4172827995
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2895842660
Short name T612
Test name
Test status
Simulation time 117818672 ps
CPU time 5.18 seconds
Started Jul 15 06:26:50 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 200252 kb
Host smart-ea605b68-5dd5-464e-9c9d-9cda305b2155
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895842660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2895842660
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1465289341
Short name T605
Test name
Test status
Simulation time 65893986 ps
CPU time 0.97 seconds
Started Jul 15 06:26:48 PM PDT 24
Finished Jul 15 06:26:50 PM PDT 24
Peak memory 199892 kb
Host smart-b7c719a7-29d5-411a-92cb-e547c6f9ea90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465289341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1465289341
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4013906867
Short name T655
Test name
Test status
Simulation time 85369671 ps
CPU time 1.57 seconds
Started Jul 15 06:26:49 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 200332 kb
Host smart-0b2124e2-0b9c-4710-93f1-bfbcce39de58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013906867 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4013906867
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2113873168
Short name T83
Test name
Test status
Simulation time 30175435 ps
CPU time 0.9 seconds
Started Jul 15 06:26:51 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 200136 kb
Host smart-df6e2ce4-75ef-47f3-ad5d-a6ea4bb59ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113873168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2113873168
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4239822996
Short name T570
Test name
Test status
Simulation time 13692997 ps
CPU time 0.6 seconds
Started Jul 15 06:26:52 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 195108 kb
Host smart-5b2048f3-bb77-4bf4-b81f-89b35484f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239822996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4239822996
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3134590850
Short name T617
Test name
Test status
Simulation time 107947767 ps
CPU time 2.21 seconds
Started Jul 15 06:26:49 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 200268 kb
Host smart-a0df8eb7-6b2b-4719-9c7f-518edaa48178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134590850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3134590850
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2378899018
Short name T585
Test name
Test status
Simulation time 729420658 ps
CPU time 3.2 seconds
Started Jul 15 06:26:50 PM PDT 24
Finished Jul 15 06:26:54 PM PDT 24
Peak memory 200280 kb
Host smart-b92b84e8-781a-44f5-a7a7-2e17a04691c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378899018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2378899018
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4011906171
Short name T638
Test name
Test status
Simulation time 94958173 ps
CPU time 1.88 seconds
Started Jul 15 06:26:49 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 200300 kb
Host smart-c51c96a4-74cb-4119-8834-222adfc5bfe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011906171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4011906171
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4108767635
Short name T616
Test name
Test status
Simulation time 24514853 ps
CPU time 0.59 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:17 PM PDT 24
Peak memory 195268 kb
Host smart-bf28309d-a70e-479d-878b-68bb6536fb72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108767635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4108767635
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.4151345532
Short name T545
Test name
Test status
Simulation time 36031468 ps
CPU time 0.61 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:27:19 PM PDT 24
Peak memory 195196 kb
Host smart-8c9a2ec2-9cbc-4dea-9d02-54951d527cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151345532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4151345532
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1955112041
Short name T535
Test name
Test status
Simulation time 13819584 ps
CPU time 0.63 seconds
Started Jul 15 06:27:16 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 195204 kb
Host smart-4ca23cc0-2222-45fb-a7db-90247de0cbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955112041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1955112041
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4140960254
Short name T541
Test name
Test status
Simulation time 25115789 ps
CPU time 0.59 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:17 PM PDT 24
Peak memory 195112 kb
Host smart-7575094a-f626-48df-96b8-b9836a639774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140960254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4140960254
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3951625722
Short name T614
Test name
Test status
Simulation time 12800443 ps
CPU time 0.59 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 195120 kb
Host smart-9de1114c-f616-4421-b264-bb8f806e3fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951625722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3951625722
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2063631356
Short name T532
Test name
Test status
Simulation time 12865253 ps
CPU time 0.65 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:27:15 PM PDT 24
Peak memory 195152 kb
Host smart-5e1c3b63-87e5-43eb-bdc6-19f9e8255a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063631356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2063631356
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.957211715
Short name T583
Test name
Test status
Simulation time 12862853 ps
CPU time 0.6 seconds
Started Jul 15 06:27:17 PM PDT 24
Finished Jul 15 06:27:18 PM PDT 24
Peak memory 195100 kb
Host smart-a77ccf45-f9fb-4905-a1ff-68637e2e7778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957211715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.957211715
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2583550728
Short name T635
Test name
Test status
Simulation time 14482028 ps
CPU time 0.6 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:17 PM PDT 24
Peak memory 195144 kb
Host smart-98b03330-5494-468d-b1ad-49d3c2abecb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583550728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2583550728
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2736205204
Short name T658
Test name
Test status
Simulation time 16055805 ps
CPU time 0.6 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:27:17 PM PDT 24
Peak memory 195184 kb
Host smart-29cb1452-d127-473d-bf6d-8abe33af63df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736205204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2736205204
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2118678408
Short name T572
Test name
Test status
Simulation time 13380929 ps
CPU time 0.6 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:27:19 PM PDT 24
Peak memory 195300 kb
Host smart-aef17548-3368-4992-8f89-46c28d52ac98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118678408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2118678408
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.589565153
Short name T633
Test name
Test status
Simulation time 37315956 ps
CPU time 2.25 seconds
Started Jul 15 06:26:50 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 200356 kb
Host smart-f0c0f342-7ff9-416e-939e-689325187682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589565153 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.589565153
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1114413071
Short name T654
Test name
Test status
Simulation time 104688352 ps
CPU time 0.92 seconds
Started Jul 15 06:26:51 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 199544 kb
Host smart-a9f79be7-5125-4ee3-91cf-8793dcd21ac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114413071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1114413071
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.666202517
Short name T531
Test name
Test status
Simulation time 16731142 ps
CPU time 0.64 seconds
Started Jul 15 06:26:48 PM PDT 24
Finished Jul 15 06:26:50 PM PDT 24
Peak memory 195188 kb
Host smart-0cc3cde5-78ef-47d5-b9ae-b2ecd2c012cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666202517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.666202517
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.952203372
Short name T582
Test name
Test status
Simulation time 239574029 ps
CPU time 1.11 seconds
Started Jul 15 06:26:51 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 198636 kb
Host smart-13989af9-a0b6-4c11-ae97-1a99b5630086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952203372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.952203372
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3276914931
Short name T611
Test name
Test status
Simulation time 639317202 ps
CPU time 1.78 seconds
Started Jul 15 06:26:53 PM PDT 24
Finished Jul 15 06:26:55 PM PDT 24
Peak memory 200312 kb
Host smart-145e7d50-e397-4075-8d27-53d41382778c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276914931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3276914931
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3623421424
Short name T558
Test name
Test status
Simulation time 77846470 ps
CPU time 2.55 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 200224 kb
Host smart-5a78a8de-2f0d-4283-b3cf-bd302a01fb8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623421424 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3623421424
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2894205518
Short name T82
Test name
Test status
Simulation time 32850984 ps
CPU time 0.85 seconds
Started Jul 15 06:26:51 PM PDT 24
Finished Jul 15 06:26:53 PM PDT 24
Peak memory 200068 kb
Host smart-005f57f9-8f43-4c7e-9f8f-9c557a2952ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894205518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2894205518
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3184078350
Short name T534
Test name
Test status
Simulation time 14115325 ps
CPU time 0.6 seconds
Started Jul 15 06:26:50 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 195204 kb
Host smart-2e86a6c7-c97e-44e3-bf30-902c69e77f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184078350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3184078350
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1009690148
Short name T101
Test name
Test status
Simulation time 238356180 ps
CPU time 1.27 seconds
Started Jul 15 06:26:50 PM PDT 24
Finished Jul 15 06:26:52 PM PDT 24
Peak memory 200276 kb
Host smart-00213047-3347-4f3a-af35-ad6d44cb5528
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009690148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1009690148
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2278967272
Short name T567
Test name
Test status
Simulation time 169531976 ps
CPU time 3.55 seconds
Started Jul 15 06:26:49 PM PDT 24
Finished Jul 15 06:26:54 PM PDT 24
Peak memory 200308 kb
Host smart-c16cb2d8-746e-4ff1-8477-d4e605933a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278967272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2278967272
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3673269905
Short name T547
Test name
Test status
Simulation time 50485914 ps
CPU time 1.72 seconds
Started Jul 15 06:26:52 PM PDT 24
Finished Jul 15 06:26:54 PM PDT 24
Peak memory 200280 kb
Host smart-257633c0-5ac9-4ec8-803b-810cc40873ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673269905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3673269905
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1772272736
Short name T550
Test name
Test status
Simulation time 44921699 ps
CPU time 1.43 seconds
Started Jul 15 06:26:54 PM PDT 24
Finished Jul 15 06:26:56 PM PDT 24
Peak memory 200364 kb
Host smart-c03dcfb8-7085-49b3-b6e3-13172c637f70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772272736 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1772272736
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2042409240
Short name T103
Test name
Test status
Simulation time 332918759 ps
CPU time 0.8 seconds
Started Jul 15 06:26:53 PM PDT 24
Finished Jul 15 06:26:54 PM PDT 24
Peak memory 199168 kb
Host smart-d6a04b44-6cb2-4e53-a107-7cfb3f2ce697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042409240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2042409240
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2235337874
Short name T559
Test name
Test status
Simulation time 35352120 ps
CPU time 0.58 seconds
Started Jul 15 06:26:55 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 195128 kb
Host smart-81cdd15f-89e0-4c83-8f7d-3bd1a85d1df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235337874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2235337874
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.228911997
Short name T104
Test name
Test status
Simulation time 32977381 ps
CPU time 1.54 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:26:59 PM PDT 24
Peak memory 200296 kb
Host smart-9b617476-f20c-4a9c-a135-62b4c9333862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228911997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.228911997
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.651310301
Short name T610
Test name
Test status
Simulation time 235467215 ps
CPU time 1.47 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:26:58 PM PDT 24
Peak memory 200312 kb
Host smart-27825ed6-82f6-4046-816f-57a4c96ee103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651310301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.651310301
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3668715540
Short name T647
Test name
Test status
Simulation time 140339949 ps
CPU time 4.26 seconds
Started Jul 15 06:27:07 PM PDT 24
Finished Jul 15 06:27:12 PM PDT 24
Peak memory 200260 kb
Host smart-95cfe7f8-9a39-4149-a9c9-20bab33572f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668715540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3668715540
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2524578124
Short name T540
Test name
Test status
Simulation time 212649132 ps
CPU time 1.73 seconds
Started Jul 15 06:27:07 PM PDT 24
Finished Jul 15 06:27:10 PM PDT 24
Peak memory 200372 kb
Host smart-13673b39-a574-4370-906b-03680da6fabf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524578124 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2524578124
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3122779487
Short name T613
Test name
Test status
Simulation time 96172819 ps
CPU time 0.88 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:26:58 PM PDT 24
Peak memory 200092 kb
Host smart-cdccffc2-e77b-4cf1-98dc-360c43b2e8a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122779487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3122779487
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.964479141
Short name T634
Test name
Test status
Simulation time 17022102 ps
CPU time 0.63 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 195288 kb
Host smart-f05ecc5b-cd47-4206-a14e-b5f081e8d383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964479141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.964479141
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3246810056
Short name T609
Test name
Test status
Simulation time 143239384 ps
CPU time 1.56 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:27:00 PM PDT 24
Peak memory 200328 kb
Host smart-5fa857a7-38e7-4b31-8b99-07e6f05b991f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246810056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3246810056
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2282864151
Short name T652
Test name
Test status
Simulation time 89637879 ps
CPU time 1.99 seconds
Started Jul 15 06:26:55 PM PDT 24
Finished Jul 15 06:26:57 PM PDT 24
Peak memory 200180 kb
Host smart-b03d793e-d970-4b79-85c7-590b42662d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282864151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2282864151
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2559838217
Short name T62
Test name
Test status
Simulation time 376971355 ps
CPU time 1.97 seconds
Started Jul 15 06:26:56 PM PDT 24
Finished Jul 15 06:26:58 PM PDT 24
Peak memory 200304 kb
Host smart-a8a1b05f-cae3-430f-bd59-1b21b80a50e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559838217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2559838217
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.707159328
Short name T618
Test name
Test status
Simulation time 12369857112 ps
CPU time 191.2 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:30:10 PM PDT 24
Peak memory 215976 kb
Host smart-21af4c7b-ceca-4fc8-9d73-dbe8a5bc3c35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707159328 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.707159328
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.243492365
Short name T89
Test name
Test status
Simulation time 101410723 ps
CPU time 0.81 seconds
Started Jul 15 06:27:07 PM PDT 24
Finished Jul 15 06:27:08 PM PDT 24
Peak memory 199348 kb
Host smart-770445ad-3514-4931-a07c-deb725984fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243492365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.243492365
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1000321405
Short name T549
Test name
Test status
Simulation time 19375396 ps
CPU time 0.57 seconds
Started Jul 15 06:26:55 PM PDT 24
Finished Jul 15 06:26:56 PM PDT 24
Peak memory 195112 kb
Host smart-fc2405c7-db88-41e7-945f-a9dcb5b1c5fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000321405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1000321405
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2678044875
Short name T643
Test name
Test status
Simulation time 142317732 ps
CPU time 2.38 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:27:00 PM PDT 24
Peak memory 200188 kb
Host smart-b43c9ccf-9986-4d96-8927-c90cc167c998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678044875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2678044875
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3199531339
Short name T565
Test name
Test status
Simulation time 507446178 ps
CPU time 3.22 seconds
Started Jul 15 06:26:58 PM PDT 24
Finished Jul 15 06:27:02 PM PDT 24
Peak memory 200292 kb
Host smart-ba80ce0e-ba18-444a-9890-74b54760b342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199531339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3199531339
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3613716370
Short name T596
Test name
Test status
Simulation time 426504532 ps
CPU time 4.43 seconds
Started Jul 15 06:26:57 PM PDT 24
Finished Jul 15 06:27:03 PM PDT 24
Peak memory 200304 kb
Host smart-17d5f813-4bed-4b91-9364-707181316280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613716370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3613716370
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2670202955
Short name T230
Test name
Test status
Simulation time 41183733 ps
CPU time 0.63 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:27:16 PM PDT 24
Peak memory 196848 kb
Host smart-91e924f9-a257-4fed-96d5-4def3394958a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670202955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2670202955
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1563482008
Short name T488
Test name
Test status
Simulation time 3910404048 ps
CPU time 22.47 seconds
Started Jul 15 06:27:17 PM PDT 24
Finished Jul 15 06:27:40 PM PDT 24
Peak memory 200452 kb
Host smart-7c3ca915-4757-4dc0-8c7c-2182e367fbb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563482008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1563482008
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3806613506
Short name T498
Test name
Test status
Simulation time 2532242474 ps
CPU time 31.21 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:27:46 PM PDT 24
Peak memory 200348 kb
Host smart-82f90ae9-f479-4095-a128-35ac0b36351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806613506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3806613506
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.4169060953
Short name T270
Test name
Test status
Simulation time 3745285673 ps
CPU time 777.01 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:40:16 PM PDT 24
Peak memory 697164 kb
Host smart-a31b0590-a17f-4c73-86d2-ff82c0fcb110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169060953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4169060953
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1458466551
Short name T163
Test name
Test status
Simulation time 11539625575 ps
CPU time 143.21 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 200404 kb
Host smart-15ef4c8c-ce21-4b4b-b3e1-73f4a0f5ac1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458466551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1458466551
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_smoke.1674579186
Short name T155
Test name
Test status
Simulation time 338975259 ps
CPU time 1.92 seconds
Started Jul 15 06:27:16 PM PDT 24
Finished Jul 15 06:27:19 PM PDT 24
Peak memory 200256 kb
Host smart-58f78dae-88f4-4009-8954-1988dee465f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674579186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1674579186
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1375302050
Short name T508
Test name
Test status
Simulation time 10335255179 ps
CPU time 68.99 seconds
Started Jul 15 06:27:17 PM PDT 24
Finished Jul 15 06:28:27 PM PDT 24
Peak memory 200372 kb
Host smart-66bf6942-4644-416b-99ca-0131bc7cf2af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375302050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1375302050
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3869321567
Short name T407
Test name
Test status
Simulation time 52555122053 ps
CPU time 75.38 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:28:31 PM PDT 24
Peak memory 200328 kb
Host smart-264c6a45-6bf2-4972-b941-fbdb4d0ab23f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3869321567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3869321567
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1446005975
Short name T444
Test name
Test status
Simulation time 11008772558 ps
CPU time 108.16 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:29:03 PM PDT 24
Peak memory 200344 kb
Host smart-5dd80404-6ffb-4e5f-a120-1a3191c609e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1446005975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1446005975
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2686271844
Short name T296
Test name
Test status
Simulation time 6522656283 ps
CPU time 116.72 seconds
Started Jul 15 06:27:17 PM PDT 24
Finished Jul 15 06:29:14 PM PDT 24
Peak memory 200392 kb
Host smart-cb49c55e-b34c-4e31-9129-24b025409286
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2686271844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2686271844
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1566015562
Short name T416
Test name
Test status
Simulation time 172955353694 ps
CPU time 570.52 seconds
Started Jul 15 06:27:15 PM PDT 24
Finished Jul 15 06:36:47 PM PDT 24
Peak memory 200352 kb
Host smart-e398a8d5-16ab-42c8-a371-be4a133b3126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1566015562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1566015562
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2178104523
Short name T264
Test name
Test status
Simulation time 39411941835 ps
CPU time 1947.47 seconds
Started Jul 15 06:27:14 PM PDT 24
Finished Jul 15 06:59:43 PM PDT 24
Peak memory 216832 kb
Host smart-42acc875-4109-4dc1-85d7-15e727da7276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2178104523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2178104523
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2512249800
Short name T459
Test name
Test status
Simulation time 353856125793 ps
CPU time 2484.67 seconds
Started Jul 15 06:27:16 PM PDT 24
Finished Jul 15 07:08:42 PM PDT 24
Peak memory 215840 kb
Host smart-0e7c9db9-cc65-41cf-a080-5bf4dce8c76c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2512249800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2512249800
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3924494989
Short name T295
Test name
Test status
Simulation time 5821284609 ps
CPU time 103.12 seconds
Started Jul 15 06:27:18 PM PDT 24
Finished Jul 15 06:29:02 PM PDT 24
Peak memory 200396 kb
Host smart-ac74a0f4-698d-4622-bc75-113ae405cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924494989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3924494989
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3096823755
Short name T409
Test name
Test status
Simulation time 41730898 ps
CPU time 0.57 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 06:27:30 PM PDT 24
Peak memory 195828 kb
Host smart-ed780bb0-9b3f-4ced-afe4-3d7b4ca48375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096823755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3096823755
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3070309094
Short name T244
Test name
Test status
Simulation time 4838952968 ps
CPU time 69.12 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:28:31 PM PDT 24
Peak memory 200396 kb
Host smart-f990eae1-0f91-4462-86fb-9d37b11ff46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070309094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3070309094
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1644578771
Short name T312
Test name
Test status
Simulation time 4547485643 ps
CPU time 830.44 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:41:11 PM PDT 24
Peak memory 723152 kb
Host smart-7a78de6d-9e74-4533-8698-312a84e2ffc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644578771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1644578771
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1303343871
Short name T48
Test name
Test status
Simulation time 9857441234 ps
CPU time 139.16 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 200340 kb
Host smart-ce9eb33f-5f54-41bb-ba7f-3ac5c1b819d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303343871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1303343871
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4263144424
Short name T519
Test name
Test status
Simulation time 1364160509 ps
CPU time 76 seconds
Started Jul 15 06:27:24 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200336 kb
Host smart-cfdc9d7b-4186-415d-85f3-46b83c9cead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263144424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4263144424
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3948782814
Short name T54
Test name
Test status
Simulation time 67788649 ps
CPU time 0.93 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:27:22 PM PDT 24
Peak memory 218448 kb
Host smart-fe205ea2-4b2d-4235-99f2-1894a91f0bed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948782814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3948782814
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1973442741
Short name T10
Test name
Test status
Simulation time 1203548622 ps
CPU time 15.01 seconds
Started Jul 15 06:27:24 PM PDT 24
Finished Jul 15 06:27:40 PM PDT 24
Peak memory 200288 kb
Host smart-081435c0-7756-424f-9f82-11f56d676efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973442741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1973442741
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.960380019
Short name T358
Test name
Test status
Simulation time 44835736045 ps
CPU time 213.3 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:30:55 PM PDT 24
Peak memory 200304 kb
Host smart-06c680b0-9e20-4f1d-8464-65f10c4f9eb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960380019 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.960380019
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1990258787
Short name T401
Test name
Test status
Simulation time 4906969090 ps
CPU time 76.67 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:28:39 PM PDT 24
Peak memory 200404 kb
Host smart-08b9e907-f98e-40bf-b2bc-df515eefb434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1990258787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1990258787
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3973451582
Short name T178
Test name
Test status
Simulation time 85484878970 ps
CPU time 98.56 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:29:01 PM PDT 24
Peak memory 200364 kb
Host smart-92b0893e-e2d1-48ad-9c28-438fbb80fe8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3973451582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3973451582
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.179392481
Short name T425
Test name
Test status
Simulation time 50434935437 ps
CPU time 139.47 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:29:40 PM PDT 24
Peak memory 200372 kb
Host smart-171e3e38-6591-4ad1-beb7-c6813f5dfa87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=179392481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.179392481
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2808666785
Short name T389
Test name
Test status
Simulation time 36531681421 ps
CPU time 515.96 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:35:58 PM PDT 24
Peak memory 200372 kb
Host smart-016aa29f-41d0-4222-951d-2cd8815f90c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2808666785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2808666785
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1903460410
Short name T206
Test name
Test status
Simulation time 156913045648 ps
CPU time 2258.46 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 07:05:00 PM PDT 24
Peak memory 215860 kb
Host smart-94dd55a6-203b-40aa-a470-89efc807f8a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1903460410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1903460410
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4236180631
Short name T177
Test name
Test status
Simulation time 141383882736 ps
CPU time 2597.03 seconds
Started Jul 15 06:27:19 PM PDT 24
Finished Jul 15 07:10:36 PM PDT 24
Peak memory 215992 kb
Host smart-6088f563-dbd5-4cd6-953f-c3200a54f3e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4236180631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4236180631
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3879519593
Short name T110
Test name
Test status
Simulation time 1614294249 ps
CPU time 70.87 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:28:32 PM PDT 24
Peak memory 200280 kb
Host smart-6828a806-8d9c-451f-b838-a65f416a16af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879519593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3879519593
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1299924471
Short name T243
Test name
Test status
Simulation time 5393104226 ps
CPU time 53.12 seconds
Started Jul 15 06:27:39 PM PDT 24
Finished Jul 15 06:28:33 PM PDT 24
Peak memory 200344 kb
Host smart-619553a6-a4e3-4db5-b9e0-58d2c9b42a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299924471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1299924471
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1937796243
Short name T29
Test name
Test status
Simulation time 2267227015 ps
CPU time 15.9 seconds
Started Jul 15 06:27:39 PM PDT 24
Finished Jul 15 06:27:56 PM PDT 24
Peak memory 200352 kb
Host smart-f92fb9b6-1c0c-4960-aba8-1354943e659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937796243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1937796243
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4107994421
Short name T287
Test name
Test status
Simulation time 16191127755 ps
CPU time 512.87 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:36:14 PM PDT 24
Peak memory 701284 kb
Host smart-9a10e354-078d-4661-9cfa-dce272b178d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107994421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4107994421
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3907459558
Short name T151
Test name
Test status
Simulation time 6285705535 ps
CPU time 77.5 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:28:56 PM PDT 24
Peak memory 200332 kb
Host smart-f3cdcec1-0b47-4935-a89e-1393d7a1c977
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907459558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3907459558
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.91300899
Short name T359
Test name
Test status
Simulation time 58157815360 ps
CPU time 101.74 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:29:22 PM PDT 24
Peak memory 200504 kb
Host smart-1629821e-b91a-4789-952a-323b783e84cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91300899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.91300899
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2334568239
Short name T180
Test name
Test status
Simulation time 155389686 ps
CPU time 1.71 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:27:38 PM PDT 24
Peak memory 200348 kb
Host smart-ef044f98-7983-4818-bba5-c6119ea0e618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334568239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2334568239
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3954510910
Short name T335
Test name
Test status
Simulation time 12504207764 ps
CPU time 69.09 seconds
Started Jul 15 06:27:39 PM PDT 24
Finished Jul 15 06:28:48 PM PDT 24
Peak memory 200388 kb
Host smart-20dd9e64-b355-488c-8b1e-5746c353dbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954510910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3954510910
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1327348811
Short name T186
Test name
Test status
Simulation time 16789490 ps
CPU time 0.62 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:27:42 PM PDT 24
Peak memory 196240 kb
Host smart-2226c5e0-a459-430f-8d20-aa24ce7d5d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327348811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1327348811
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4093251344
Short name T221
Test name
Test status
Simulation time 841829690 ps
CPU time 49.06 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:28:30 PM PDT 24
Peak memory 200288 kb
Host smart-765d8dec-68fd-43a3-a548-ed4e407bdaa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093251344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4093251344
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2155592151
Short name T129
Test name
Test status
Simulation time 1647591728 ps
CPU time 7.95 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:27:47 PM PDT 24
Peak memory 200192 kb
Host smart-ebc81e9e-e606-4e4f-8b49-3f390498b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155592151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2155592151
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4278691883
Short name T280
Test name
Test status
Simulation time 4329482806 ps
CPU time 165.56 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 627720 kb
Host smart-106fe6a8-1a00-4058-82b8-f6107d2f769a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278691883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4278691883
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2226644612
Short name T122
Test name
Test status
Simulation time 10914313358 ps
CPU time 205.31 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 200340 kb
Host smart-970bd34d-4e65-492f-b35d-5caef7900a95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226644612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2226644612
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4016018127
Short name T321
Test name
Test status
Simulation time 18381024057 ps
CPU time 64.19 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:28:46 PM PDT 24
Peak memory 216488 kb
Host smart-47fff256-6278-4e4a-9243-ffcd2c85683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016018127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4016018127
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.69114349
Short name T344
Test name
Test status
Simulation time 1475543800 ps
CPU time 13.27 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:27:52 PM PDT 24
Peak memory 200260 kb
Host smart-a31b3be5-75da-4a74-927a-887780555e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69114349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.69114349
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.225934198
Short name T81
Test name
Test status
Simulation time 19061361964 ps
CPU time 1299.8 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:49:21 PM PDT 24
Peak memory 618952 kb
Host smart-09278f3a-d6e3-4d9b-a06b-93df66dc9c83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225934198 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.225934198
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4217955998
Short name T522
Test name
Test status
Simulation time 30200547106 ps
CPU time 92.07 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:29:13 PM PDT 24
Peak memory 200364 kb
Host smart-1431ca6e-43b5-4c24-bbaa-053f39bdbcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217955998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4217955998
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.260352372
Short name T391
Test name
Test status
Simulation time 40936989 ps
CPU time 0.62 seconds
Started Jul 15 06:27:39 PM PDT 24
Finished Jul 15 06:27:40 PM PDT 24
Peak memory 196168 kb
Host smart-f03e4b4c-3eab-40b2-82ea-fac12aa14f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260352372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.260352372
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1862565784
Short name T253
Test name
Test status
Simulation time 1175603891 ps
CPU time 16.85 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:27:58 PM PDT 24
Peak memory 200276 kb
Host smart-7714aae6-34c4-473e-8acc-ae4cd499e9e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862565784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1862565784
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3554018538
Short name T42
Test name
Test status
Simulation time 4671425896 ps
CPU time 62.07 seconds
Started Jul 15 06:27:42 PM PDT 24
Finished Jul 15 06:28:44 PM PDT 24
Peak memory 200412 kb
Host smart-d8d40e71-a4bf-4244-a5bb-9cc7018c2de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554018538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3554018538
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3564146828
Short name T413
Test name
Test status
Simulation time 6554540538 ps
CPU time 1334.1 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:49:55 PM PDT 24
Peak memory 702908 kb
Host smart-e10ae6ce-5936-4f8e-94a5-0b7826b7befd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564146828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3564146828
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.230857932
Short name T328
Test name
Test status
Simulation time 2404764876 ps
CPU time 66.45 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:28:45 PM PDT 24
Peak memory 200352 kb
Host smart-9d392f5a-c529-4900-9a23-9ab3c2150a73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230857932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.230857932
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3324534770
Short name T322
Test name
Test status
Simulation time 12871614943 ps
CPU time 184.73 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 200360 kb
Host smart-fd486613-d4b9-44e7-ad84-0c13ace95fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324534770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3324534770
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3747911624
Short name T219
Test name
Test status
Simulation time 11679420007 ps
CPU time 1463.88 seconds
Started Jul 15 06:27:41 PM PDT 24
Finished Jul 15 06:52:06 PM PDT 24
Peak memory 703128 kb
Host smart-98b54990-d9fe-41d2-8092-96ede1ae629c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747911624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3747911624
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.986883207
Short name T79
Test name
Test status
Simulation time 20896585087 ps
CPU time 66.81 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:28:46 PM PDT 24
Peak memory 200324 kb
Host smart-8b0ad993-a5ff-476e-a1a2-eff5aa7ee778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986883207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.986883207
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2886709521
Short name T193
Test name
Test status
Simulation time 13942691 ps
CPU time 0.61 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:27:44 PM PDT 24
Peak memory 196208 kb
Host smart-1d58e19e-1415-4592-a93f-a517c15e2365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886709521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2886709521
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.502055924
Short name T18
Test name
Test status
Simulation time 1020591788 ps
CPU time 60.29 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200300 kb
Host smart-0a37eaa6-073f-4003-9e26-b8bd15a7f16e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502055924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.502055924
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2382213274
Short name T139
Test name
Test status
Simulation time 8411348326 ps
CPU time 55.66 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:28:40 PM PDT 24
Peak memory 208552 kb
Host smart-2910da62-c4fa-44a1-b6bc-f6ad780771ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382213274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2382213274
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1900176793
Short name T173
Test name
Test status
Simulation time 62115515 ps
CPU time 0.79 seconds
Started Jul 15 06:27:40 PM PDT 24
Finished Jul 15 06:27:42 PM PDT 24
Peak memory 198816 kb
Host smart-05475489-dbff-477b-9143-680f7f7f6a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900176793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1900176793
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1576968432
Short name T467
Test name
Test status
Simulation time 3865626192 ps
CPU time 105.28 seconds
Started Jul 15 06:27:39 PM PDT 24
Finished Jul 15 06:29:25 PM PDT 24
Peak memory 200352 kb
Host smart-4a976356-e90c-4c3a-b7fb-1cdae3aa32ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576968432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1576968432
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2606567066
Short name T497
Test name
Test status
Simulation time 456726888 ps
CPU time 26.58 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:28:06 PM PDT 24
Peak memory 200284 kb
Host smart-e3fb46df-7962-4537-a8bb-103725a633ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606567066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2606567066
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1473703082
Short name T329
Test name
Test status
Simulation time 267828038 ps
CPU time 2.76 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:27:47 PM PDT 24
Peak memory 200308 kb
Host smart-55fd9e62-91d6-4e9a-a980-d26a131da459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473703082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1473703082
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1875033789
Short name T334
Test name
Test status
Simulation time 2502274741 ps
CPU time 127.13 seconds
Started Jul 15 06:27:39 PM PDT 24
Finished Jul 15 06:29:47 PM PDT 24
Peak memory 200312 kb
Host smart-d9db28d8-0788-4d45-bb60-106dc446a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875033789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1875033789
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3658162882
Short name T431
Test name
Test status
Simulation time 49154235 ps
CPU time 0.57 seconds
Started Jul 15 06:27:48 PM PDT 24
Finished Jul 15 06:27:49 PM PDT 24
Peak memory 196876 kb
Host smart-49a33d24-4662-4e48-b7ea-54b39c3f9d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658162882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3658162882
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.728950229
Short name T297
Test name
Test status
Simulation time 4751104162 ps
CPU time 65 seconds
Started Jul 15 06:27:45 PM PDT 24
Finished Jul 15 06:28:50 PM PDT 24
Peak memory 200292 kb
Host smart-1e76369b-647c-4135-8bef-fd9069342ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728950229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.728950229
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3927308240
Short name T43
Test name
Test status
Simulation time 14845476971 ps
CPU time 40.49 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:28:28 PM PDT 24
Peak memory 208596 kb
Host smart-fb905d78-3a77-4f59-bc69-ba52d01d5e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927308240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3927308240
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.533421473
Short name T74
Test name
Test status
Simulation time 4869285345 ps
CPU time 1013.74 seconds
Started Jul 15 06:27:49 PM PDT 24
Finished Jul 15 06:44:44 PM PDT 24
Peak memory 774984 kb
Host smart-2327dd57-73b9-420a-b17c-68c9f11deaa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533421473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.533421473
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1315991910
Short name T218
Test name
Test status
Simulation time 383779542 ps
CPU time 10.34 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:27:57 PM PDT 24
Peak memory 200336 kb
Host smart-8947acbe-2a98-4797-834a-6458f55d2b3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315991910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1315991910
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2142848977
Short name T236
Test name
Test status
Simulation time 5120351104 ps
CPU time 77.71 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:29:05 PM PDT 24
Peak memory 208628 kb
Host smart-e8f9bcf4-b510-489e-ac2e-a80eb32fbb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142848977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2142848977
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1242607754
Short name T435
Test name
Test status
Simulation time 3046258393 ps
CPU time 8.55 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:27:56 PM PDT 24
Peak memory 200360 kb
Host smart-c2d9c690-85f6-4919-8243-7f670f233403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242607754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1242607754
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2005191490
Short name T71
Test name
Test status
Simulation time 80636219964 ps
CPU time 1956 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 07:00:23 PM PDT 24
Peak memory 725188 kb
Host smart-18244ccc-4ee8-4c2a-95f3-d98b8709eeb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005191490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2005191490
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1164118053
Short name T300
Test name
Test status
Simulation time 2832198748 ps
CPU time 41.38 seconds
Started Jul 15 06:27:48 PM PDT 24
Finished Jul 15 06:28:30 PM PDT 24
Peak memory 200400 kb
Host smart-dc21a9a6-b2b4-444e-9516-487085de70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164118053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1164118053
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2328075069
Short name T240
Test name
Test status
Simulation time 40883340 ps
CPU time 0.61 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 196248 kb
Host smart-55893c9b-20df-4cb9-9fc3-eb6c054110e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328075069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2328075069
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1624444244
Short name T272
Test name
Test status
Simulation time 3121690842 ps
CPU time 44.74 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:28:31 PM PDT 24
Peak memory 200324 kb
Host smart-49fa3a49-e986-4d7d-9d75-55b0ad1c10d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624444244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1624444244
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.598032364
Short name T308
Test name
Test status
Simulation time 5567883587 ps
CPU time 34.58 seconds
Started Jul 15 06:27:45 PM PDT 24
Finished Jul 15 06:28:20 PM PDT 24
Peak memory 200364 kb
Host smart-fb16be3b-d6b4-4bd6-8238-f24a42a05d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598032364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.598032364
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.4163973343
Short name T513
Test name
Test status
Simulation time 7195248543 ps
CPU time 1552.6 seconds
Started Jul 15 06:27:48 PM PDT 24
Finished Jul 15 06:53:42 PM PDT 24
Peak memory 746964 kb
Host smart-93d53eec-11fc-481e-a51c-17e1ba4add66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163973343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4163973343
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1648445319
Short name T475
Test name
Test status
Simulation time 1968894678 ps
CPU time 33.89 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:28:20 PM PDT 24
Peak memory 200212 kb
Host smart-105a8ec3-05b8-45c9-9ff7-36a53afb95e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648445319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1648445319
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1892673458
Short name T507
Test name
Test status
Simulation time 16257294430 ps
CPU time 118.13 seconds
Started Jul 15 06:27:45 PM PDT 24
Finished Jul 15 06:29:44 PM PDT 24
Peak memory 200372 kb
Host smart-5e0efefe-5f8a-4ac7-946f-8cf8c6ec8e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892673458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1892673458
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3471065022
Short name T472
Test name
Test status
Simulation time 1897412551 ps
CPU time 6.34 seconds
Started Jul 15 06:27:45 PM PDT 24
Finished Jul 15 06:27:52 PM PDT 24
Peak memory 200176 kb
Host smart-ff415b7a-9666-4859-b830-85112240d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471065022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3471065022
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1004277188
Short name T516
Test name
Test status
Simulation time 4495869729 ps
CPU time 125.97 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:29:50 PM PDT 24
Peak memory 208700 kb
Host smart-d42a1e70-9a3d-41cf-b2a9-58a8c660ff6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004277188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1004277188
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4139241162
Short name T436
Test name
Test status
Simulation time 3193659786 ps
CPU time 38.28 seconds
Started Jul 15 06:27:45 PM PDT 24
Finished Jul 15 06:28:24 PM PDT 24
Peak memory 200396 kb
Host smart-044f26c8-5127-47bb-81cf-34e63aa35fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139241162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4139241162
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1941227427
Short name T194
Test name
Test status
Simulation time 109095231 ps
CPU time 0.55 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:27:46 PM PDT 24
Peak memory 196184 kb
Host smart-bb23ab04-d100-4aff-bbff-ecabc70d8cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941227427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1941227427
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4035570672
Short name T350
Test name
Test status
Simulation time 2237976803 ps
CPU time 69.42 seconds
Started Jul 15 06:27:44 PM PDT 24
Finished Jul 15 06:28:54 PM PDT 24
Peak memory 200408 kb
Host smart-8d5d2c36-2668-4fe0-80af-a20c074c2cd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035570672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4035570672
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1496524854
Short name T182
Test name
Test status
Simulation time 5100177483 ps
CPU time 7.35 seconds
Started Jul 15 06:27:45 PM PDT 24
Finished Jul 15 06:27:53 PM PDT 24
Peak memory 200364 kb
Host smart-49187ef4-a953-46b4-8c4c-3fc8580957ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496524854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1496524854
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2487136519
Short name T346
Test name
Test status
Simulation time 3299390491 ps
CPU time 262.21 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:32:09 PM PDT 24
Peak memory 453500 kb
Host smart-aaf78410-b89f-4811-9caa-a56f2f9b4367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487136519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2487136519
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3014118624
Short name T443
Test name
Test status
Simulation time 2323886402 ps
CPU time 128.17 seconds
Started Jul 15 06:27:49 PM PDT 24
Finished Jul 15 06:29:57 PM PDT 24
Peak memory 200376 kb
Host smart-314c4dd7-e92e-4c61-888d-37100e435e67
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014118624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3014118624
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1598777246
Short name T367
Test name
Test status
Simulation time 715227764 ps
CPU time 37.56 seconds
Started Jul 15 06:27:48 PM PDT 24
Finished Jul 15 06:28:27 PM PDT 24
Peak memory 200268 kb
Host smart-85301fcf-600c-404e-86bd-503d1db92181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598777246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1598777246
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.384090320
Short name T156
Test name
Test status
Simulation time 454355557 ps
CPU time 5.58 seconds
Started Jul 15 06:27:47 PM PDT 24
Finished Jul 15 06:27:53 PM PDT 24
Peak memory 200324 kb
Host smart-b15925ea-4795-484f-b7ac-90229ef977d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384090320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.384090320
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.802182480
Short name T77
Test name
Test status
Simulation time 9017280619 ps
CPU time 112 seconds
Started Jul 15 06:27:47 PM PDT 24
Finished Jul 15 06:29:40 PM PDT 24
Peak memory 200364 kb
Host smart-d9422b8d-d8f3-43ff-a38a-e89906858a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802182480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.802182480
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1186200408
Short name T376
Test name
Test status
Simulation time 12761389 ps
CPU time 0.57 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:27:54 PM PDT 24
Peak memory 195192 kb
Host smart-70c27c36-399c-49ca-80aa-3bcc8aa6128d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186200408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1186200408
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4001816653
Short name T441
Test name
Test status
Simulation time 320108139 ps
CPU time 3.06 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:27:50 PM PDT 24
Peak memory 200232 kb
Host smart-af830333-28bb-40b9-af59-113fd47b7611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001816653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4001816653
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4120021190
Short name T24
Test name
Test status
Simulation time 231521420 ps
CPU time 3.65 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:27:56 PM PDT 24
Peak memory 200292 kb
Host smart-84d6deab-f39c-4a65-a1d3-54d13d79b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120021190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4120021190
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3822494582
Short name T179
Test name
Test status
Simulation time 5999821273 ps
CPU time 430.88 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:35:05 PM PDT 24
Peak memory 649264 kb
Host smart-763aaa2a-0d61-4300-8c30-d1fb3ed5bfcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822494582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3822494582
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2705191812
Short name T2
Test name
Test status
Simulation time 10638192101 ps
CPU time 153.33 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 200408 kb
Host smart-15c11665-6c5c-43fc-baa3-3774eefd2fec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705191812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2705191812
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1425445132
Short name T298
Test name
Test status
Simulation time 45909626107 ps
CPU time 130.69 seconds
Started Jul 15 06:27:46 PM PDT 24
Finished Jul 15 06:29:58 PM PDT 24
Peak memory 216800 kb
Host smart-acde2b74-8749-4390-9702-71c1ac480ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425445132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1425445132
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3172119865
Short name T126
Test name
Test status
Simulation time 293621158 ps
CPU time 9.99 seconds
Started Jul 15 06:27:47 PM PDT 24
Finished Jul 15 06:27:58 PM PDT 24
Peak memory 200356 kb
Host smart-9788e984-dad2-4b51-a202-acdbf666cc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172119865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3172119865
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1254380438
Short name T72
Test name
Test status
Simulation time 549705480535 ps
CPU time 2739.11 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 07:13:32 PM PDT 24
Peak memory 764556 kb
Host smart-f4d7e26e-4036-40d9-bb48-4c9d89a9e7f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254380438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1254380438
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1661495204
Short name T224
Test name
Test status
Simulation time 153549421 ps
CPU time 8.22 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:28:01 PM PDT 24
Peak memory 200336 kb
Host smart-52605634-f853-4b78-932a-85ef4ae0bec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661495204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1661495204
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2548566043
Short name T351
Test name
Test status
Simulation time 13523747 ps
CPU time 0.6 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:27:55 PM PDT 24
Peak memory 196204 kb
Host smart-b69d64de-129d-49f5-aba5-ebc5d5e69168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548566043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2548566043
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1103287346
Short name T514
Test name
Test status
Simulation time 4532203040 ps
CPU time 47.49 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:28:40 PM PDT 24
Peak memory 200372 kb
Host smart-92f06320-aeef-4560-aab5-b0c23e44d0f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103287346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1103287346
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1517770900
Short name T171
Test name
Test status
Simulation time 773392351 ps
CPU time 15.16 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:28:06 PM PDT 24
Peak memory 200240 kb
Host smart-7584dd43-16bc-4063-8bbe-a9165e701db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517770900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1517770900
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2509574322
Short name T480
Test name
Test status
Simulation time 2006133053 ps
CPU time 248.88 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:32:01 PM PDT 24
Peak memory 596824 kb
Host smart-9146c856-a821-4012-8320-55613e654af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509574322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2509574322
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.196725099
Short name T185
Test name
Test status
Simulation time 9521129813 ps
CPU time 80.48 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:29:14 PM PDT 24
Peak memory 200340 kb
Host smart-2cbefde5-7b3e-420b-8297-6ce3d3abbe79
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196725099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.196725099
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4226413300
Short name T222
Test name
Test status
Simulation time 2687646264 ps
CPU time 155.25 seconds
Started Jul 15 06:27:54 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 200380 kb
Host smart-e02b8d69-9293-4a2e-8640-2c6f8b44c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226413300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4226413300
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3122910007
Short name T384
Test name
Test status
Simulation time 1405245476 ps
CPU time 5.15 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:27:56 PM PDT 24
Peak memory 200252 kb
Host smart-519f32ce-5e33-42d5-9061-4bcf8573ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122910007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3122910007
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1809976889
Short name T227
Test name
Test status
Simulation time 78420725412 ps
CPU time 488.04 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:35:59 PM PDT 24
Peak memory 200276 kb
Host smart-14bc9c36-bbe9-4054-86cf-f8ab43d6380f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809976889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1809976889
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2287081818
Short name T400
Test name
Test status
Simulation time 32759691570 ps
CPU time 119.37 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:29:51 PM PDT 24
Peak memory 200280 kb
Host smart-90d55a6a-55c2-4985-b0c9-4e5c653e43ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287081818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2287081818
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1045240131
Short name T432
Test name
Test status
Simulation time 14630301 ps
CPU time 0.61 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:27:51 PM PDT 24
Peak memory 196180 kb
Host smart-c878d854-1a93-4832-8ce5-432ff55911a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045240131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1045240131
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1853220514
Short name T494
Test name
Test status
Simulation time 3703082880 ps
CPU time 102.42 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:29:41 PM PDT 24
Peak memory 208600 kb
Host smart-d608668b-aa25-4825-b592-225280f86fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853220514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1853220514
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.174319479
Short name T313
Test name
Test status
Simulation time 931707105 ps
CPU time 17.44 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:28:09 PM PDT 24
Peak memory 200348 kb
Host smart-639da8d8-cf26-485b-80da-f906124423b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174319479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.174319479
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.841478655
Short name T293
Test name
Test status
Simulation time 5408650937 ps
CPU time 406.68 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:34:37 PM PDT 24
Peak memory 625144 kb
Host smart-23c4c005-1fde-4448-93ea-5575ab81e956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841478655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.841478655
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3833195422
Short name T439
Test name
Test status
Simulation time 5845857841 ps
CPU time 53.36 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:28:47 PM PDT 24
Peak memory 200356 kb
Host smart-0c783fe6-7982-42c9-a0a0-0328ad44638a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833195422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3833195422
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2380322369
Short name T263
Test name
Test status
Simulation time 3942382028 ps
CPU time 85.42 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:29:17 PM PDT 24
Peak memory 200392 kb
Host smart-850e461c-f693-4854-b89f-d01b07cd0393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380322369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2380322369
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1755881798
Short name T385
Test name
Test status
Simulation time 633323864 ps
CPU time 14.14 seconds
Started Jul 15 06:27:56 PM PDT 24
Finished Jul 15 06:28:10 PM PDT 24
Peak memory 200284 kb
Host smart-500ab00e-ad9a-4e3a-aa8e-be7ba8668631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755881798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1755881798
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3079778323
Short name T410
Test name
Test status
Simulation time 235245267475 ps
CPU time 5073.87 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 07:52:29 PM PDT 24
Peak memory 832628 kb
Host smart-a03956b3-4c49-4da4-90b4-3d3ff43d3bb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079778323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3079778323
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2816096649
Short name T76
Test name
Test status
Simulation time 143200800113 ps
CPU time 96.14 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:29:29 PM PDT 24
Peak memory 200376 kb
Host smart-a7a90dfd-9aef-4402-bfdd-74143b63c797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816096649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2816096649
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3379707816
Short name T271
Test name
Test status
Simulation time 42140858 ps
CPU time 0.59 seconds
Started Jul 15 06:27:24 PM PDT 24
Finished Jul 15 06:27:25 PM PDT 24
Peak memory 196172 kb
Host smart-65f9a864-bf64-4ff3-a671-eca04efac936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379707816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3379707816
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2722980387
Short name T470
Test name
Test status
Simulation time 1038481177 ps
CPU time 62.03 seconds
Started Jul 15 06:27:25 PM PDT 24
Finished Jul 15 06:28:28 PM PDT 24
Peak memory 200308 kb
Host smart-bf1c0af4-80f4-4d48-9671-eb15b3647717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722980387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2722980387
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3126603767
Short name T127
Test name
Test status
Simulation time 3366680869 ps
CPU time 65.36 seconds
Started Jul 15 06:27:24 PM PDT 24
Finished Jul 15 06:28:30 PM PDT 24
Peak memory 200380 kb
Host smart-ac66cdbb-06c4-4517-9db5-e6b4476dd67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126603767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3126603767
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.214809263
Short name T347
Test name
Test status
Simulation time 2369494200 ps
CPU time 67.9 seconds
Started Jul 15 06:27:19 PM PDT 24
Finished Jul 15 06:28:27 PM PDT 24
Peak memory 322112 kb
Host smart-9b2f2713-9e94-4933-9158-9ed7200ed051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214809263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.214809263
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1165561031
Short name T315
Test name
Test status
Simulation time 7342338828 ps
CPU time 36.98 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:27:58 PM PDT 24
Peak memory 200280 kb
Host smart-a88662f3-b50f-4931-b480-4f244dd83e09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165561031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1165561031
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3588630243
Short name T269
Test name
Test status
Simulation time 5393172302 ps
CPU time 79.14 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 06:28:48 PM PDT 24
Peak memory 200344 kb
Host smart-37bd1594-bea6-443d-8f7f-c8a9b6dc19ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588630243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3588630243
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2600026529
Short name T51
Test name
Test status
Simulation time 146968861 ps
CPU time 0.81 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:27:22 PM PDT 24
Peak memory 218384 kb
Host smart-aab5e976-a5fb-4b2d-8c0a-f9e111eb0a23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600026529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2600026529
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.6297145
Short name T169
Test name
Test status
Simulation time 378342714 ps
CPU time 4.59 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:27:26 PM PDT 24
Peak memory 200284 kb
Host smart-6af972ce-7bc1-4064-9b5b-d9c92b82d027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6297145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.6297145
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.329992195
Short name T314
Test name
Test status
Simulation time 17191905417 ps
CPU time 216.03 seconds
Started Jul 15 06:27:19 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 208612 kb
Host smart-16d5e57d-56de-4f34-907c-175748f892bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329992195 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.329992195
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1647927743
Short name T8
Test name
Test status
Simulation time 34731797941 ps
CPU time 1255.99 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 06:48:17 PM PDT 24
Peak memory 606784 kb
Host smart-558c290c-e682-451d-b0d6-e9c2a7d85826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647927743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1647927743
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3140555774
Short name T521
Test name
Test status
Simulation time 4476721063 ps
CPU time 53.81 seconds
Started Jul 15 06:27:25 PM PDT 24
Finished Jul 15 06:28:19 PM PDT 24
Peak memory 200368 kb
Host smart-63fdfcfa-45a8-49f1-af53-ea91699dc80b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3140555774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3140555774
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1399248990
Short name T256
Test name
Test status
Simulation time 2339368693 ps
CPU time 83.8 seconds
Started Jul 15 06:27:19 PM PDT 24
Finished Jul 15 06:28:44 PM PDT 24
Peak memory 200252 kb
Host smart-1f4ed16b-65c2-40e4-8317-d5e385d18789
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1399248990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1399248990
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3348970148
Short name T170
Test name
Test status
Simulation time 2337337301 ps
CPU time 79.85 seconds
Started Jul 15 06:27:20 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200400 kb
Host smart-d039f0c2-e74f-4a04-871a-161f129e4cc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3348970148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3348970148
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3976450595
Short name T267
Test name
Test status
Simulation time 111298864792 ps
CPU time 2296.52 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 07:05:39 PM PDT 24
Peak memory 216548 kb
Host smart-21d14645-4300-43fe-a079-3fe4ffdfaf25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3976450595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3976450595
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1189905220
Short name T231
Test name
Test status
Simulation time 139641215938 ps
CPU time 2493.98 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 215892 kb
Host smart-13c3269f-9d9a-43d8-8cf2-09855ba6e75e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1189905220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1189905220
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2384919831
Short name T38
Test name
Test status
Simulation time 2316963716 ps
CPU time 121.15 seconds
Started Jul 15 06:27:22 PM PDT 24
Finished Jul 15 06:29:24 PM PDT 24
Peak memory 200432 kb
Host smart-279d5555-1f59-4a32-b94f-ca9547faa8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384919831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2384919831
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2376395012
Short name T482
Test name
Test status
Simulation time 82469508 ps
CPU time 0.61 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:27:53 PM PDT 24
Peak memory 196188 kb
Host smart-c5135dde-3d03-4010-a3e2-0f799d8fc203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376395012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2376395012
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.832957300
Short name T286
Test name
Test status
Simulation time 75867533 ps
CPU time 4.24 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:27:57 PM PDT 24
Peak memory 200304 kb
Host smart-05cf41ef-7c3a-47c9-ac49-6f0a8ca22116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832957300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.832957300
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1830707854
Short name T489
Test name
Test status
Simulation time 2926237389 ps
CPU time 38.92 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:28:30 PM PDT 24
Peak memory 200376 kb
Host smart-601e5844-0567-48dc-a0ef-89527c55b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830707854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1830707854
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1112651626
Short name T238
Test name
Test status
Simulation time 19454094324 ps
CPU time 931.07 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:43:25 PM PDT 24
Peak memory 644176 kb
Host smart-367ebe0b-1eb0-46a8-8f1f-4d745ffab7c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112651626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1112651626
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.116152213
Short name T402
Test name
Test status
Simulation time 4326043352 ps
CPU time 60.91 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:28:54 PM PDT 24
Peak memory 200408 kb
Host smart-2ca7df8a-2854-45a8-aaf6-8fdcc0a3f2ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116152213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.116152213
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3558903994
Short name T382
Test name
Test status
Simulation time 644521341 ps
CPU time 34.06 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:28:27 PM PDT 24
Peak memory 200308 kb
Host smart-d53876ee-55ff-4884-b79f-3e9e66de7649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558903994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3558903994
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2516649454
Short name T366
Test name
Test status
Simulation time 555666648 ps
CPU time 6.87 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:28:00 PM PDT 24
Peak memory 200304 kb
Host smart-8950709d-d673-4c93-9f8f-e7b848662ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516649454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2516649454
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3429276289
Short name T403
Test name
Test status
Simulation time 93998309306 ps
CPU time 3410.83 seconds
Started Jul 15 06:27:54 PM PDT 24
Finished Jul 15 07:24:46 PM PDT 24
Peak memory 848900 kb
Host smart-498c02f3-5c03-417b-a999-d45d03a39714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429276289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3429276289
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2311606549
Short name T207
Test name
Test status
Simulation time 1861715329 ps
CPU time 43.78 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:28:34 PM PDT 24
Peak memory 200324 kb
Host smart-e168031d-50e6-46fd-8289-dab0f04d1ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311606549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2311606549
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2830276082
Short name T212
Test name
Test status
Simulation time 97898278 ps
CPU time 0.59 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:27:59 PM PDT 24
Peak memory 195840 kb
Host smart-6c05f3b3-c30f-4e1a-9206-6ea70db89515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830276082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2830276082
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3883579042
Short name T394
Test name
Test status
Simulation time 669221167 ps
CPU time 35.07 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:28:28 PM PDT 24
Peak memory 200336 kb
Host smart-ce671b96-d0bf-40fc-a394-b5181ecc8085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883579042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3883579042
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.36711861
Short name T326
Test name
Test status
Simulation time 6460305444 ps
CPU time 60.84 seconds
Started Jul 15 06:27:55 PM PDT 24
Finished Jul 15 06:28:57 PM PDT 24
Peak memory 200608 kb
Host smart-cc9046ba-db5a-4b22-aad6-148eac5c7606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36711861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.36711861
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.866876253
Short name T164
Test name
Test status
Simulation time 2385444757 ps
CPU time 456.78 seconds
Started Jul 15 06:27:50 PM PDT 24
Finished Jul 15 06:35:28 PM PDT 24
Peak memory 650536 kb
Host smart-95be3484-7e54-4ee2-ae3c-ecc7e3dd224b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=866876253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.866876253
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1866405196
Short name T216
Test name
Test status
Simulation time 17811806683 ps
CPU time 125.92 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 200508 kb
Host smart-84e813b4-d7bb-45f0-af94-05937326861e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866405196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1866405196
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.651326880
Short name T31
Test name
Test status
Simulation time 108525883734 ps
CPU time 98.95 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 200428 kb
Host smart-9f3b978d-e694-4924-a6d8-9abe381a6738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651326880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.651326880
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2861424666
Short name T438
Test name
Test status
Simulation time 626580412 ps
CPU time 10.03 seconds
Started Jul 15 06:27:52 PM PDT 24
Finished Jul 15 06:28:03 PM PDT 24
Peak memory 200260 kb
Host smart-20c4dd73-2b9b-4cb5-a110-bf79e37ef3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861424666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2861424666
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.39573671
Short name T234
Test name
Test status
Simulation time 19072736145 ps
CPU time 286.41 seconds
Started Jul 15 06:27:55 PM PDT 24
Finished Jul 15 06:32:42 PM PDT 24
Peak memory 208188 kb
Host smart-cae55888-f958-4e55-9c95-5e97d9d18287
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573671 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.39573671
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3110546476
Short name T476
Test name
Test status
Simulation time 526234330 ps
CPU time 28.26 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:28:22 PM PDT 24
Peak memory 200308 kb
Host smart-df3629d9-2d73-48f3-ab34-9ea5a83a7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110546476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3110546476
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.285861448
Short name T277
Test name
Test status
Simulation time 13992426 ps
CPU time 0.62 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:28:00 PM PDT 24
Peak memory 196132 kb
Host smart-7ff5a2f3-8fbc-410c-9aee-b21c2a7f0144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285861448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.285861448
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3084863955
Short name T455
Test name
Test status
Simulation time 13458138409 ps
CPU time 83.78 seconds
Started Jul 15 06:27:55 PM PDT 24
Finished Jul 15 06:29:19 PM PDT 24
Peak memory 200172 kb
Host smart-3519a7fb-1af1-4993-8c4a-d3f3938a8e3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084863955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3084863955
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2355062362
Short name T136
Test name
Test status
Simulation time 299144137 ps
CPU time 16.29 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:28:10 PM PDT 24
Peak memory 200276 kb
Host smart-002149fe-5149-4a43-b477-dfaad4f62d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355062362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2355062362
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3172268502
Short name T168
Test name
Test status
Simulation time 1647658940 ps
CPU time 297.79 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:32:52 PM PDT 24
Peak memory 635536 kb
Host smart-98394381-5354-406f-8887-4770054c3ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172268502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3172268502
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.676754953
Short name T205
Test name
Test status
Simulation time 30742505427 ps
CPU time 97.84 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:29:29 PM PDT 24
Peak memory 200344 kb
Host smart-2cc4cc91-a245-4343-b4c2-244654478054
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676754953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.676754953
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2997563277
Short name T233
Test name
Test status
Simulation time 16416165408 ps
CPU time 142.75 seconds
Started Jul 15 06:27:53 PM PDT 24
Finished Jul 15 06:30:17 PM PDT 24
Peak memory 216744 kb
Host smart-1aed4a92-b56b-41a8-acdb-9a04c1936190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997563277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2997563277
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1768032881
Short name T107
Test name
Test status
Simulation time 460519389 ps
CPU time 10.87 seconds
Started Jul 15 06:27:51 PM PDT 24
Finished Jul 15 06:28:03 PM PDT 24
Peak memory 200272 kb
Host smart-6a939c1e-9f0e-41f6-b060-ed410fa04d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768032881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1768032881
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2858553142
Short name T486
Test name
Test status
Simulation time 72576438772 ps
CPU time 1519.29 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:53:17 PM PDT 24
Peak memory 728688 kb
Host smart-6a2dacbf-e29b-4370-94b6-571bc8a856f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858553142 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2858553142
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2747365267
Short name T483
Test name
Test status
Simulation time 1439402396 ps
CPU time 15.79 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:28:14 PM PDT 24
Peak memory 200320 kb
Host smart-a3153123-3ef0-4ff9-af8d-f420238b1e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747365267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2747365267
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.355843414
Short name T341
Test name
Test status
Simulation time 11858951 ps
CPU time 0.59 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:28:00 PM PDT 24
Peak memory 195164 kb
Host smart-f88155c9-4dff-4360-874e-485884413d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355843414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.355843414
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2714912614
Short name T226
Test name
Test status
Simulation time 141917684 ps
CPU time 8.23 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:28:07 PM PDT 24
Peak memory 200280 kb
Host smart-74ebf720-6a2b-4d37-80f2-da8a32822dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714912614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2714912614
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1478406947
Short name T342
Test name
Test status
Simulation time 1216536948 ps
CPU time 16.45 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:28:15 PM PDT 24
Peak memory 200328 kb
Host smart-2fc09560-008c-4109-92b5-ca0c7b9b54f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478406947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1478406947
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1349843430
Short name T304
Test name
Test status
Simulation time 5235669019 ps
CPU time 962.64 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:44:01 PM PDT 24
Peak memory 711612 kb
Host smart-4ee16d4a-2ef1-470d-b2f5-d944e8095de9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349843430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1349843430
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.876306410
Short name T30
Test name
Test status
Simulation time 25884295170 ps
CPU time 220.99 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 200348 kb
Host smart-f125631c-c27e-4144-8de0-ba50eb3a1fbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876306410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.876306410
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1263845526
Short name T235
Test name
Test status
Simulation time 60482250633 ps
CPU time 211.75 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:31:32 PM PDT 24
Peak memory 200344 kb
Host smart-522b2e06-b3d5-4364-8a41-977e2729aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263845526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1263845526
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.696081715
Short name T285
Test name
Test status
Simulation time 1234687081 ps
CPU time 9.42 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:28:08 PM PDT 24
Peak memory 200172 kb
Host smart-11d3a7b3-44e2-4b39-85cd-fc532f7af455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696081715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.696081715
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.385797961
Short name T69
Test name
Test status
Simulation time 414294539986 ps
CPU time 4223.86 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 07:38:22 PM PDT 24
Peak memory 857348 kb
Host smart-8b1852db-2652-43b6-90fb-ba820b6c6ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385797961 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.385797961
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1917501651
Short name T148
Test name
Test status
Simulation time 2758305950 ps
CPU time 52.19 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:28:50 PM PDT 24
Peak memory 200404 kb
Host smart-97ee4a08-f71d-4bb6-b0c6-0b3e24bdd0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917501651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1917501651
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3190667678
Short name T530
Test name
Test status
Simulation time 22751241 ps
CPU time 0.58 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:28:01 PM PDT 24
Peak memory 195164 kb
Host smart-f04ea809-2607-4c4f-921e-9c3656b2b5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190667678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3190667678
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1746337903
Short name T131
Test name
Test status
Simulation time 18151573790 ps
CPU time 98.34 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 208780 kb
Host smart-47fb915e-6018-48b1-ae07-ef2b3583c577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746337903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1746337903
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2572767544
Short name T135
Test name
Test status
Simulation time 674248134 ps
CPU time 33.02 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:28:30 PM PDT 24
Peak memory 200300 kb
Host smart-2a686c4a-80a2-4ad5-be04-a51640e3844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572767544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2572767544
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1886897331
Short name T302
Test name
Test status
Simulation time 18333403568 ps
CPU time 897.11 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:42:55 PM PDT 24
Peak memory 699620 kb
Host smart-cefa0a29-5a4d-4c3f-a951-7c77917c58c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886897331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1886897331
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.554622364
Short name T372
Test name
Test status
Simulation time 26945603323 ps
CPU time 162.96 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:30:42 PM PDT 24
Peak memory 200256 kb
Host smart-600dc720-14d1-4a96-b5d8-68192a69773f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554622364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.554622364
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2097446403
Short name T426
Test name
Test status
Simulation time 13768162 ps
CPU time 0.69 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:28:00 PM PDT 24
Peak memory 196728 kb
Host smart-0d7a6223-991f-491b-92df-9b0a2398d8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097446403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2097446403
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3282494193
Short name T429
Test name
Test status
Simulation time 635987841 ps
CPU time 10.76 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:28:09 PM PDT 24
Peak memory 200284 kb
Host smart-119ddc5e-4295-4d16-aedb-592b3a88c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282494193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3282494193
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3941113793
Short name T197
Test name
Test status
Simulation time 27761184975 ps
CPU time 1584.69 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:54:22 PM PDT 24
Peak memory 769980 kb
Host smart-852c76aa-434d-4fa4-a929-31980a586e55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941113793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3941113793
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3945647991
Short name T211
Test name
Test status
Simulation time 5451898807 ps
CPU time 50.77 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:28:50 PM PDT 24
Peak memory 200364 kb
Host smart-b7f94906-13cb-4d25-905f-36c5c88b3411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945647991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3945647991
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1225675592
Short name T469
Test name
Test status
Simulation time 86223283 ps
CPU time 0.59 seconds
Started Jul 15 06:28:00 PM PDT 24
Finished Jul 15 06:28:01 PM PDT 24
Peak memory 195728 kb
Host smart-1d1b666d-337f-4a88-9ae9-aea054f2ffd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225675592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1225675592
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3935825053
Short name T386
Test name
Test status
Simulation time 1000531618 ps
CPU time 57.62 seconds
Started Jul 15 06:27:59 PM PDT 24
Finished Jul 15 06:28:57 PM PDT 24
Peak memory 200356 kb
Host smart-621c6897-6081-4e35-9e48-063212525b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935825053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3935825053
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2199070795
Short name T133
Test name
Test status
Simulation time 5367415272 ps
CPU time 54.69 seconds
Started Jul 15 06:28:03 PM PDT 24
Finished Jul 15 06:28:58 PM PDT 24
Peak memory 200320 kb
Host smart-4fc39389-0c75-4040-9c27-27285b326e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199070795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2199070795
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1343327051
Short name T463
Test name
Test status
Simulation time 7679340346 ps
CPU time 1611.74 seconds
Started Jul 15 06:27:57 PM PDT 24
Finished Jul 15 06:54:49 PM PDT 24
Peak memory 781264 kb
Host smart-29dc0522-9c3f-4ade-8295-41e88f2232c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343327051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1343327051
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2287496369
Short name T525
Test name
Test status
Simulation time 16220830353 ps
CPU time 215.29 seconds
Started Jul 15 06:28:02 PM PDT 24
Finished Jul 15 06:31:38 PM PDT 24
Peak memory 200344 kb
Host smart-c12e4f60-7c1d-43c5-8484-3e9762742cd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287496369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2287496369
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1941440092
Short name T149
Test name
Test status
Simulation time 775420693 ps
CPU time 11.03 seconds
Started Jul 15 06:27:58 PM PDT 24
Finished Jul 15 06:28:10 PM PDT 24
Peak memory 200308 kb
Host smart-0c94a72a-a31c-4279-b663-c1872ac9ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941440092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1941440092
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.850647665
Short name T176
Test name
Test status
Simulation time 476138364 ps
CPU time 11.18 seconds
Started Jul 15 06:27:56 PM PDT 24
Finished Jul 15 06:28:08 PM PDT 24
Peak memory 200252 kb
Host smart-6b68a04e-0732-4b7d-a9a9-5845eda55966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850647665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.850647665
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3204902436
Short name T500
Test name
Test status
Simulation time 11354528192 ps
CPU time 687.36 seconds
Started Jul 15 06:28:05 PM PDT 24
Finished Jul 15 06:39:32 PM PDT 24
Peak memory 669148 kb
Host smart-a9720d9b-3a28-4d16-aacf-65a02aadcefb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204902436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3204902436
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2331148328
Short name T248
Test name
Test status
Simulation time 7286101538 ps
CPU time 40.03 seconds
Started Jul 15 06:28:04 PM PDT 24
Finished Jul 15 06:28:44 PM PDT 24
Peak memory 200392 kb
Host smart-0322a542-f167-4850-902c-81558893d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331148328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2331148328
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2974930175
Short name T246
Test name
Test status
Simulation time 31347602 ps
CPU time 0.59 seconds
Started Jul 15 06:28:05 PM PDT 24
Finished Jul 15 06:28:06 PM PDT 24
Peak memory 196840 kb
Host smart-e8b5b836-baae-4053-9ac6-22524a610ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974930175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2974930175
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3123844756
Short name T440
Test name
Test status
Simulation time 664606542 ps
CPU time 39.68 seconds
Started Jul 15 06:28:06 PM PDT 24
Finished Jul 15 06:28:47 PM PDT 24
Peak memory 200300 kb
Host smart-35fbce90-b1f8-4dc2-81bc-6b5a1d535729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123844756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3123844756
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1802145096
Short name T354
Test name
Test status
Simulation time 1224613134 ps
CPU time 16.64 seconds
Started Jul 15 06:28:06 PM PDT 24
Finished Jul 15 06:28:24 PM PDT 24
Peak memory 200344 kb
Host smart-e9b7c228-c1da-433f-a1ed-a3d14e1a648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802145096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1802145096
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2678480461
Short name T478
Test name
Test status
Simulation time 26221746458 ps
CPU time 709.27 seconds
Started Jul 15 06:28:07 PM PDT 24
Finished Jul 15 06:39:57 PM PDT 24
Peak memory 678028 kb
Host smart-cb3ce41e-f24c-485f-b83b-676c2ccf2fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678480461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2678480461
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.399909106
Short name T501
Test name
Test status
Simulation time 47868104626 ps
CPU time 134.63 seconds
Started Jul 15 06:28:06 PM PDT 24
Finished Jul 15 06:30:21 PM PDT 24
Peak memory 200408 kb
Host smart-178c4d13-f660-4564-af61-f86febf5c7fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399909106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.399909106
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2363593243
Short name T288
Test name
Test status
Simulation time 3161517348 ps
CPU time 20.56 seconds
Started Jul 15 06:28:08 PM PDT 24
Finished Jul 15 06:28:29 PM PDT 24
Peak memory 200364 kb
Host smart-f86af81b-808b-4f81-a965-f61d379fed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363593243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2363593243
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2446530952
Short name T512
Test name
Test status
Simulation time 1138306329 ps
CPU time 3.24 seconds
Started Jul 15 06:28:02 PM PDT 24
Finished Jul 15 06:28:06 PM PDT 24
Peak memory 200324 kb
Host smart-6f76e736-af09-406c-aae8-539601bd9cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446530952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2446530952
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.486943039
Short name T517
Test name
Test status
Simulation time 1521020401 ps
CPU time 68.03 seconds
Started Jul 15 06:28:07 PM PDT 24
Finished Jul 15 06:29:15 PM PDT 24
Peak memory 200272 kb
Host smart-05666249-aa45-4bad-ac14-7a5489ada5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486943039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.486943039
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2005982733
Short name T229
Test name
Test status
Simulation time 93258961 ps
CPU time 0.6 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:28:16 PM PDT 24
Peak memory 196196 kb
Host smart-d11aa0b2-1e87-4602-a82f-08aafb8de5f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005982733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2005982733
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.896369845
Short name T25
Test name
Test status
Simulation time 13528798251 ps
CPU time 74.09 seconds
Started Jul 15 06:28:08 PM PDT 24
Finished Jul 15 06:29:22 PM PDT 24
Peak memory 216740 kb
Host smart-c1ee482f-1f11-4666-8621-b4058f2482f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896369845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.896369845
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2218814833
Short name T183
Test name
Test status
Simulation time 3128731136 ps
CPU time 43.08 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:28:58 PM PDT 24
Peak memory 208576 kb
Host smart-7f3a746e-e41f-4cd0-a2c0-8d4827faa7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218814833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2218814833
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1971472910
Short name T3
Test name
Test status
Simulation time 13516563942 ps
CPU time 614.99 seconds
Started Jul 15 06:28:09 PM PDT 24
Finished Jul 15 06:38:25 PM PDT 24
Peak memory 703820 kb
Host smart-c4d99cc4-0daf-41de-857f-d037bc1e2b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971472910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1971472910
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3949667009
Short name T32
Test name
Test status
Simulation time 14527833769 ps
CPU time 70.77 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:29:26 PM PDT 24
Peak memory 200344 kb
Host smart-967a02c6-493b-429a-9b31-ee2ab4705251
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949667009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3949667009
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2675239057
Short name T289
Test name
Test status
Simulation time 9584839164 ps
CPU time 126.37 seconds
Started Jul 15 06:28:09 PM PDT 24
Finished Jul 15 06:30:16 PM PDT 24
Peak memory 200344 kb
Host smart-f98e088d-b7a3-4eba-b8b5-327e8c8318c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675239057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2675239057
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1893145075
Short name T520
Test name
Test status
Simulation time 416403625 ps
CPU time 2.77 seconds
Started Jul 15 06:28:08 PM PDT 24
Finished Jul 15 06:28:11 PM PDT 24
Peak memory 200364 kb
Host smart-918101b4-0894-4a5c-9517-c7e291ecdd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893145075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1893145075
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.216560234
Short name T73
Test name
Test status
Simulation time 38191608065 ps
CPU time 261.24 seconds
Started Jul 15 06:28:14 PM PDT 24
Finished Jul 15 06:32:36 PM PDT 24
Peak memory 216792 kb
Host smart-de97fcf9-19c6-47de-ba66-31e692101eea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216560234 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.216560234
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.930292959
Short name T161
Test name
Test status
Simulation time 3964578543 ps
CPU time 7.01 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:28:22 PM PDT 24
Peak memory 200340 kb
Host smart-6caaa513-8ea1-4381-8d3d-81d4cb7bc595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930292959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.930292959
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3648885153
Short name T364
Test name
Test status
Simulation time 14813374 ps
CPU time 0.58 seconds
Started Jul 15 06:28:13 PM PDT 24
Finished Jul 15 06:28:14 PM PDT 24
Peak memory 196196 kb
Host smart-1ea9787c-7b9b-4586-806e-c14e6ae88d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648885153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3648885153
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1200893933
Short name T299
Test name
Test status
Simulation time 665698073 ps
CPU time 35.86 seconds
Started Jul 15 06:28:14 PM PDT 24
Finished Jul 15 06:28:51 PM PDT 24
Peak memory 200260 kb
Host smart-a82b914d-593f-41d4-beec-bda5faf6b407
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200893933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1200893933
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1178891833
Short name T371
Test name
Test status
Simulation time 1844186681 ps
CPU time 50.89 seconds
Started Jul 15 06:28:13 PM PDT 24
Finished Jul 15 06:29:04 PM PDT 24
Peak memory 200252 kb
Host smart-3c027152-6f3d-4626-bea6-246be90bd55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178891833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1178891833
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2122388345
Short name T461
Test name
Test status
Simulation time 10915469865 ps
CPU time 449.29 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:35:45 PM PDT 24
Peak memory 587568 kb
Host smart-ed804bbe-5f93-43c3-bf9b-617cafb95e34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122388345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2122388345
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.219690320
Short name T378
Test name
Test status
Simulation time 143750400586 ps
CPU time 130.95 seconds
Started Jul 15 06:28:18 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 200404 kb
Host smart-fd916890-f506-4f94-8d70-05cdbc2f9d8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219690320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.219690320
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2579236062
Short name T447
Test name
Test status
Simulation time 3140590316 ps
CPU time 174.02 seconds
Started Jul 15 06:28:18 PM PDT 24
Finished Jul 15 06:31:12 PM PDT 24
Peak memory 200372 kb
Host smart-bf8dc955-9e89-43eb-9217-18300d48fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579236062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2579236062
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2386104958
Short name T108
Test name
Test status
Simulation time 2482849943 ps
CPU time 13.38 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:28:29 PM PDT 24
Peak memory 200356 kb
Host smart-aa45e8f8-0776-4fca-9713-7b93a3a9cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386104958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2386104958
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2403490363
Short name T41
Test name
Test status
Simulation time 17907461367 ps
CPU time 2933.83 seconds
Started Jul 15 06:28:14 PM PDT 24
Finished Jul 15 07:17:08 PM PDT 24
Peak memory 830484 kb
Host smart-83d642ff-dc7d-42a5-ba5d-07a01150684d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403490363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2403490363
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1184020142
Short name T255
Test name
Test status
Simulation time 3632407407 ps
CPU time 87.56 seconds
Started Jul 15 06:28:14 PM PDT 24
Finished Jul 15 06:29:43 PM PDT 24
Peak memory 200396 kb
Host smart-73c80a42-3d54-40bb-934c-9da9d6a49f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184020142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1184020142
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1029571792
Short name T491
Test name
Test status
Simulation time 12313561 ps
CPU time 0.59 seconds
Started Jul 15 06:28:22 PM PDT 24
Finished Jul 15 06:28:23 PM PDT 24
Peak memory 195820 kb
Host smart-1fe0d354-dcfd-40b2-9bcc-b01b5850b3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029571792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1029571792
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1849654789
Short name T496
Test name
Test status
Simulation time 2376848511 ps
CPU time 16.19 seconds
Started Jul 15 06:28:18 PM PDT 24
Finished Jul 15 06:28:35 PM PDT 24
Peak memory 200416 kb
Host smart-0d1c4296-00e6-4ad8-aca9-2d215430316b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849654789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1849654789
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2545359591
Short name T274
Test name
Test status
Simulation time 735836790 ps
CPU time 10.07 seconds
Started Jul 15 06:28:22 PM PDT 24
Finished Jul 15 06:28:32 PM PDT 24
Peak memory 200296 kb
Host smart-c569d7a6-0eb5-449d-8a05-cda83905681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545359591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2545359591
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.519201145
Short name T152
Test name
Test status
Simulation time 18685058845 ps
CPU time 831.51 seconds
Started Jul 15 06:28:20 PM PDT 24
Finished Jul 15 06:42:13 PM PDT 24
Peak memory 696348 kb
Host smart-5e525edd-de9a-4e1c-b186-648a001f6b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519201145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.519201145
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2569274139
Short name T181
Test name
Test status
Simulation time 13684076049 ps
CPU time 167.07 seconds
Started Jul 15 06:28:20 PM PDT 24
Finished Jul 15 06:31:08 PM PDT 24
Peak memory 200332 kb
Host smart-9c6bc7ed-9eec-4279-8ae9-e14b88ec65d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569274139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2569274139
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1894219017
Short name T202
Test name
Test status
Simulation time 27094846834 ps
CPU time 173.85 seconds
Started Jul 15 06:28:15 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 200360 kb
Host smart-96446a61-e79a-45e9-bf18-d80af211ce0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894219017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1894219017
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.725410421
Short name T408
Test name
Test status
Simulation time 167685488 ps
CPU time 3.94 seconds
Started Jul 15 06:28:18 PM PDT 24
Finished Jul 15 06:28:22 PM PDT 24
Peak memory 200300 kb
Host smart-cedc97bd-884e-4d32-b8f7-a784ecc97e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725410421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.725410421
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1902281681
Short name T283
Test name
Test status
Simulation time 101306636416 ps
CPU time 1744.98 seconds
Started Jul 15 06:28:19 PM PDT 24
Finished Jul 15 06:57:24 PM PDT 24
Peak memory 712836 kb
Host smart-62a94cd6-c69e-4ca4-b118-14a1a550b1a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902281681 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1902281681
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1361934090
Short name T460
Test name
Test status
Simulation time 5524747569 ps
CPU time 34.85 seconds
Started Jul 15 06:28:24 PM PDT 24
Finished Jul 15 06:28:59 PM PDT 24
Peak memory 200352 kb
Host smart-32632f23-4e46-451e-b4bc-82975c27476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361934090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1361934090
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2634760707
Short name T477
Test name
Test status
Simulation time 22917102 ps
CPU time 0.61 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:27:30 PM PDT 24
Peak memory 195892 kb
Host smart-95a2e66e-77e3-4c94-a5d6-bb07429ec555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634760707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2634760707
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1672142863
Short name T365
Test name
Test status
Simulation time 1542106154 ps
CPU time 95.18 seconds
Started Jul 15 06:27:25 PM PDT 24
Finished Jul 15 06:29:00 PM PDT 24
Peak memory 200344 kb
Host smart-83feb393-6f28-4d9e-a755-c2dfa7db13e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672142863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1672142863
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1349152012
Short name T393
Test name
Test status
Simulation time 401803459 ps
CPU time 6.7 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 06:27:37 PM PDT 24
Peak memory 200328 kb
Host smart-d6c73bc0-da65-4c9f-88e3-d6756a0b9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349152012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1349152012
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1726702986
Short name T130
Test name
Test status
Simulation time 10653583298 ps
CPU time 1214.18 seconds
Started Jul 15 06:27:22 PM PDT 24
Finished Jul 15 06:47:37 PM PDT 24
Peak memory 754700 kb
Host smart-03eaef25-ab85-4193-9922-66f0a6ace093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726702986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1726702986
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1168469350
Short name T162
Test name
Test status
Simulation time 210890806084 ps
CPU time 192.76 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 06:30:42 PM PDT 24
Peak memory 200312 kb
Host smart-96141ee1-7f67-4b22-88f6-218284519624
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168469350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1168469350
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2199796582
Short name T276
Test name
Test status
Simulation time 11858617492 ps
CPU time 169.84 seconds
Started Jul 15 06:27:22 PM PDT 24
Finished Jul 15 06:30:12 PM PDT 24
Peak memory 216724 kb
Host smart-3f6709a7-a33a-42bc-aeb2-3910a8da6620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199796582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2199796582
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2972875898
Short name T55
Test name
Test status
Simulation time 79210485 ps
CPU time 1.01 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:27:29 PM PDT 24
Peak memory 219392 kb
Host smart-c79be4b2-8952-49e7-81db-e284636fab14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972875898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2972875898
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.726550078
Short name T445
Test name
Test status
Simulation time 801627975 ps
CPU time 9.3 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:27:38 PM PDT 24
Peak memory 200284 kb
Host smart-4851a604-7f02-42bf-96ac-79d50c744c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726550078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.726550078
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4231919285
Short name T412
Test name
Test status
Simulation time 149498993234 ps
CPU time 4948.66 seconds
Started Jul 15 06:27:31 PM PDT 24
Finished Jul 15 07:50:01 PM PDT 24
Peak memory 866900 kb
Host smart-87cf3652-8140-40ef-b06e-5cde145a28cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231919285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4231919285
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2304303021
Short name T14
Test name
Test status
Simulation time 93494351644 ps
CPU time 2087.24 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 07:02:17 PM PDT 24
Peak memory 709708 kb
Host smart-f104558f-f89c-42fe-9675-c90ba67e2bdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304303021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2304303021
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2069919054
Short name T388
Test name
Test status
Simulation time 13511391669 ps
CPU time 70.81 seconds
Started Jul 15 06:27:30 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200228 kb
Host smart-21938869-1928-4502-a5e3-cd3f65c33caa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2069919054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2069919054
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2644805007
Short name T430
Test name
Test status
Simulation time 25908680577 ps
CPU time 91.68 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:29:04 PM PDT 24
Peak memory 200368 kb
Host smart-f9141ca7-015c-436a-a58a-b8bf4eb3fa09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2644805007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2644805007
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3995739197
Short name T144
Test name
Test status
Simulation time 2157822217 ps
CPU time 70.17 seconds
Started Jul 15 06:27:26 PM PDT 24
Finished Jul 15 06:28:37 PM PDT 24
Peak memory 200360 kb
Host smart-ee79f4f9-298c-450f-a2a1-b4aa6e348b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3995739197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3995739197
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.464137563
Short name T404
Test name
Test status
Simulation time 45045093911 ps
CPU time 575.03 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 06:37:05 PM PDT 24
Peak memory 200348 kb
Host smart-256a5bf6-90a9-4d4a-9147-6497f1f1ffae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=464137563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.464137563
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2426962510
Short name T468
Test name
Test status
Simulation time 41705976667 ps
CPU time 2267.43 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 07:05:17 PM PDT 24
Peak memory 215988 kb
Host smart-ff5ebe71-d95d-40df-befc-1be4ad48ebca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2426962510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2426962510
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3789666406
Short name T61
Test name
Test status
Simulation time 2924464111103 ps
CPU time 2604.63 seconds
Started Jul 15 06:27:21 PM PDT 24
Finished Jul 15 07:10:46 PM PDT 24
Peak memory 215808 kb
Host smart-88eb71cc-af36-4eab-986a-c62175e242bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3789666406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3789666406
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.274314112
Short name T451
Test name
Test status
Simulation time 1670304092 ps
CPU time 13.62 seconds
Started Jul 15 06:27:25 PM PDT 24
Finished Jul 15 06:27:39 PM PDT 24
Peak memory 200296 kb
Host smart-187dc3d7-8b2a-4de6-bae6-db39a0aecc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274314112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.274314112
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4248178197
Short name T213
Test name
Test status
Simulation time 13623854 ps
CPU time 0.61 seconds
Started Jul 15 06:28:20 PM PDT 24
Finished Jul 15 06:28:21 PM PDT 24
Peak memory 196172 kb
Host smart-7f35a572-ecb9-49c7-b12f-e7d7873a0a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248178197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4248178197
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3958517781
Short name T417
Test name
Test status
Simulation time 829423927 ps
CPU time 48.42 seconds
Started Jul 15 06:28:19 PM PDT 24
Finished Jul 15 06:29:08 PM PDT 24
Peak memory 200296 kb
Host smart-37adbe2c-89e1-45e0-a0de-ad96cff6b15c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958517781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3958517781
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.352627863
Short name T261
Test name
Test status
Simulation time 9301199710 ps
CPU time 7.5 seconds
Started Jul 15 06:28:19 PM PDT 24
Finished Jul 15 06:28:27 PM PDT 24
Peak memory 200340 kb
Host smart-416a5ef8-8ee8-4d5c-a87c-93b98d773b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352627863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.352627863
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1066100248
Short name T228
Test name
Test status
Simulation time 13039483917 ps
CPU time 1372.85 seconds
Started Jul 15 06:28:19 PM PDT 24
Finished Jul 15 06:51:13 PM PDT 24
Peak memory 739064 kb
Host smart-1a329a8d-0f79-453e-a9ca-cbd77232244a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066100248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1066100248
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1668670458
Short name T414
Test name
Test status
Simulation time 11635107320 ps
CPU time 187.91 seconds
Started Jul 15 06:28:21 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 200388 kb
Host smart-20e990a4-c43f-4b62-bf72-21c56681a4fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668670458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1668670458
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3962847733
Short name T422
Test name
Test status
Simulation time 6976646115 ps
CPU time 32.19 seconds
Started Jul 15 06:28:24 PM PDT 24
Finished Jul 15 06:28:57 PM PDT 24
Peak memory 200464 kb
Host smart-5e982994-6ff0-46c0-95ad-57dcc75b9e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962847733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3962847733
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3898173921
Short name T405
Test name
Test status
Simulation time 1333809616 ps
CPU time 16.33 seconds
Started Jul 15 06:28:24 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200264 kb
Host smart-132506c9-b807-4cda-831d-8b0d829d5aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898173921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3898173921
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3824293482
Short name T111
Test name
Test status
Simulation time 32676882405 ps
CPU time 2449.2 seconds
Started Jul 15 06:28:24 PM PDT 24
Finished Jul 15 07:09:14 PM PDT 24
Peak memory 805040 kb
Host smart-18f29740-a996-4633-bedf-7b7437f8e2fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824293482 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3824293482
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.667960440
Short name T292
Test name
Test status
Simulation time 9071308156 ps
CPU time 112.88 seconds
Started Jul 15 06:28:20 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 200284 kb
Host smart-fd3b2da1-65fa-4a8f-a8e3-d3b0ac46b69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667960440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.667960440
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.6058758
Short name T223
Test name
Test status
Simulation time 14949675 ps
CPU time 0.57 seconds
Started Jul 15 06:28:26 PM PDT 24
Finished Jul 15 06:28:27 PM PDT 24
Peak memory 195164 kb
Host smart-72322676-2f60-439e-8a4f-53958dded2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6058758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.6058758
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2206943408
Short name T35
Test name
Test status
Simulation time 3997425381 ps
CPU time 57.61 seconds
Started Jul 15 06:28:22 PM PDT 24
Finished Jul 15 06:29:20 PM PDT 24
Peak memory 200352 kb
Host smart-5ff499a4-1c10-4cbe-892c-abb47c772697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206943408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2206943408
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1623631152
Short name T305
Test name
Test status
Simulation time 7489782446 ps
CPU time 27.56 seconds
Started Jul 15 06:28:25 PM PDT 24
Finished Jul 15 06:28:53 PM PDT 24
Peak memory 200384 kb
Host smart-a5605d38-60a9-40ac-a19f-bc00bfc1e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623631152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1623631152
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3661076968
Short name T209
Test name
Test status
Simulation time 156079615 ps
CPU time 1.08 seconds
Started Jul 15 06:28:21 PM PDT 24
Finished Jul 15 06:28:22 PM PDT 24
Peak memory 200256 kb
Host smart-dc9a45b1-6339-4aa3-aef2-3b39a01b947d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661076968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3661076968
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1042206577
Short name T338
Test name
Test status
Simulation time 6090686219 ps
CPU time 68.27 seconds
Started Jul 15 06:28:28 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 200360 kb
Host smart-07f30a15-e6d7-4dde-b645-4b4c87094eab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042206577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1042206577
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1204337138
Short name T60
Test name
Test status
Simulation time 11129279309 ps
CPU time 75.46 seconds
Started Jul 15 06:28:20 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 200400 kb
Host smart-5329c5b0-20ce-4e9b-b822-beeedd237a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204337138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1204337138
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3295324437
Short name T291
Test name
Test status
Simulation time 904633557 ps
CPU time 10.52 seconds
Started Jul 15 06:28:24 PM PDT 24
Finished Jul 15 06:28:35 PM PDT 24
Peak memory 200252 kb
Host smart-8ca8d13d-53af-4e28-be06-951913faf350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295324437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3295324437
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.662204594
Short name T301
Test name
Test status
Simulation time 5572564847 ps
CPU time 106.65 seconds
Started Jul 15 06:28:29 PM PDT 24
Finished Jul 15 06:30:16 PM PDT 24
Peak memory 200356 kb
Host smart-d6fe7702-3f9c-48f1-8ed7-c99ab9eaa569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662204594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.662204594
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2161632378
Short name T319
Test name
Test status
Simulation time 40182421 ps
CPU time 0.59 seconds
Started Jul 15 06:28:27 PM PDT 24
Finished Jul 15 06:28:28 PM PDT 24
Peak memory 196168 kb
Host smart-ac847b1d-7e43-4696-877f-a5f7ecdb5a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161632378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2161632378
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2663132165
Short name T473
Test name
Test status
Simulation time 4448255439 ps
CPU time 31.46 seconds
Started Jul 15 06:28:25 PM PDT 24
Finished Jul 15 06:28:57 PM PDT 24
Peak memory 200360 kb
Host smart-3f28cc34-6a48-439c-8652-7070cfb2ae1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663132165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2663132165
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.990260739
Short name T140
Test name
Test status
Simulation time 2447361350 ps
CPU time 28 seconds
Started Jul 15 06:28:24 PM PDT 24
Finished Jul 15 06:28:53 PM PDT 24
Peak memory 200324 kb
Host smart-8d4e5db8-4c0a-4457-ad43-400d8b2c4cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990260739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.990260739
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3070361288
Short name T1
Test name
Test status
Simulation time 6251821065 ps
CPU time 279.68 seconds
Started Jul 15 06:28:28 PM PDT 24
Finished Jul 15 06:33:08 PM PDT 24
Peak memory 614164 kb
Host smart-63258ace-2325-48f0-a644-6cc43c89d4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070361288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3070361288
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3498999935
Short name T505
Test name
Test status
Simulation time 18107859644 ps
CPU time 77.64 seconds
Started Jul 15 06:28:27 PM PDT 24
Finished Jul 15 06:29:46 PM PDT 24
Peak memory 200300 kb
Host smart-4e75c0e6-3bf4-4bd2-80c5-1d64e51bb4a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498999935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3498999935
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.331320606
Short name T421
Test name
Test status
Simulation time 30404548559 ps
CPU time 24.03 seconds
Started Jul 15 06:28:27 PM PDT 24
Finished Jul 15 06:28:52 PM PDT 24
Peak memory 200308 kb
Host smart-92991985-621d-4675-adc6-1baf1288a939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331320606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.331320606
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2507422213
Short name T484
Test name
Test status
Simulation time 1380345617 ps
CPU time 12.74 seconds
Started Jul 15 06:28:27 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200232 kb
Host smart-cad5393d-74e5-4052-b908-92b3516f890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507422213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2507422213
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3179561361
Short name T273
Test name
Test status
Simulation time 70776388129 ps
CPU time 571.38 seconds
Started Jul 15 06:28:28 PM PDT 24
Finished Jul 15 06:38:00 PM PDT 24
Peak memory 200332 kb
Host smart-202fcccf-4347-4cec-b098-fb5000800b46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179561361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3179561361
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1854759193
Short name T37
Test name
Test status
Simulation time 857769119 ps
CPU time 36.01 seconds
Started Jul 15 06:28:29 PM PDT 24
Finished Jul 15 06:29:05 PM PDT 24
Peak memory 200340 kb
Host smart-736bb5c8-1e07-4a2b-a5fc-2d20a6b921af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854759193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1854759193
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4069252227
Short name T284
Test name
Test status
Simulation time 42230867 ps
CPU time 0.58 seconds
Started Jul 15 06:28:29 PM PDT 24
Finished Jul 15 06:28:30 PM PDT 24
Peak memory 195848 kb
Host smart-2fd9e255-fa4a-4916-9397-85bb60be18eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069252227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4069252227
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1004819307
Short name T379
Test name
Test status
Simulation time 985995170 ps
CPU time 45.37 seconds
Started Jul 15 06:28:27 PM PDT 24
Finished Jul 15 06:29:12 PM PDT 24
Peak memory 200332 kb
Host smart-fc0cdea9-b4be-471d-8f64-dc7f2bba2f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004819307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1004819307
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1610205578
Short name T362
Test name
Test status
Simulation time 109836305 ps
CPU time 1.95 seconds
Started Jul 15 06:28:31 PM PDT 24
Finished Jul 15 06:28:34 PM PDT 24
Peak memory 200212 kb
Host smart-4ba7b6bc-387a-4100-a789-cf599d278434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610205578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1610205578
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4005908848
Short name T380
Test name
Test status
Simulation time 4102237426 ps
CPU time 337.11 seconds
Started Jul 15 06:28:25 PM PDT 24
Finished Jul 15 06:34:03 PM PDT 24
Peak memory 468464 kb
Host smart-217129ee-dd85-417b-a16e-ec224be72bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005908848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4005908848
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.836756852
Short name T247
Test name
Test status
Simulation time 5896504478 ps
CPU time 171.07 seconds
Started Jul 15 06:28:34 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 200352 kb
Host smart-e7730cb5-6eb3-4d8a-9fcb-2d41127a6dc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836756852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.836756852
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3809767504
Short name T200
Test name
Test status
Simulation time 8292389028 ps
CPU time 105.66 seconds
Started Jul 15 06:28:26 PM PDT 24
Finished Jul 15 06:30:12 PM PDT 24
Peak memory 200348 kb
Host smart-496a5163-b0b2-4f29-8295-b133468b5f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809767504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3809767504
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2530986635
Short name T309
Test name
Test status
Simulation time 212948993 ps
CPU time 2.14 seconds
Started Jul 15 06:28:26 PM PDT 24
Finished Jul 15 06:28:29 PM PDT 24
Peak memory 200288 kb
Host smart-466dd115-32ce-4b98-a0df-a7477efecdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530986635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2530986635
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.191101537
Short name T499
Test name
Test status
Simulation time 31583896237 ps
CPU time 703.35 seconds
Started Jul 15 06:28:34 PM PDT 24
Finished Jul 15 06:40:18 PM PDT 24
Peak memory 510568 kb
Host smart-b5cdd369-c4ec-4cf8-b1dd-a3744ac6ed39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191101537 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.191101537
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3197003296
Short name T331
Test name
Test status
Simulation time 5284097860 ps
CPU time 54.08 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:29:28 PM PDT 24
Peak memory 200448 kb
Host smart-912fcf19-7756-4702-b581-ac3f61a5fb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197003296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3197003296
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3880693565
Short name T462
Test name
Test status
Simulation time 15052255 ps
CPU time 0.61 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:28:34 PM PDT 24
Peak memory 196196 kb
Host smart-1dafc721-a441-4113-b2f9-39fda102edde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880693565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3880693565
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1223049599
Short name T225
Test name
Test status
Simulation time 66459014 ps
CPU time 3.89 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:28:37 PM PDT 24
Peak memory 200284 kb
Host smart-e1a1fa16-464a-4a8b-bc11-2e2d91732b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223049599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1223049599
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3968703390
Short name T370
Test name
Test status
Simulation time 3528638421 ps
CPU time 32.34 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:29:06 PM PDT 24
Peak memory 200392 kb
Host smart-f72d2aff-9dfa-4635-9286-256c46c2378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968703390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3968703390
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3875774773
Short name T28
Test name
Test status
Simulation time 11784628964 ps
CPU time 769.53 seconds
Started Jul 15 06:28:34 PM PDT 24
Finished Jul 15 06:41:24 PM PDT 24
Peak memory 672336 kb
Host smart-390530e5-d986-4e57-9c04-289024947f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875774773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3875774773
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.172264658
Short name T353
Test name
Test status
Simulation time 2882030973 ps
CPU time 159.12 seconds
Started Jul 15 06:28:32 PM PDT 24
Finished Jul 15 06:31:12 PM PDT 24
Peak memory 200364 kb
Host smart-e5be8932-6491-44c7-a2b9-390791934ed3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172264658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.172264658
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1351084039
Short name T458
Test name
Test status
Simulation time 17553327177 ps
CPU time 112.67 seconds
Started Jul 15 06:28:31 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 200428 kb
Host smart-7495f68c-e01c-4ed7-a47c-1f41a0bdf560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351084039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1351084039
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2277991955
Short name T495
Test name
Test status
Simulation time 793361574 ps
CPU time 13.2 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:28:47 PM PDT 24
Peak memory 200308 kb
Host smart-49d701a6-58cb-4ffc-a01f-d302d944d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277991955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2277991955
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2143426303
Short name T418
Test name
Test status
Simulation time 9048544876 ps
CPU time 251.13 seconds
Started Jul 15 06:28:32 PM PDT 24
Finished Jul 15 06:32:43 PM PDT 24
Peak memory 200268 kb
Host smart-f5f56224-56c1-495f-ae4b-f8ae0dc88f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143426303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2143426303
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.674732100
Short name T158
Test name
Test status
Simulation time 87947502659 ps
CPU time 111.5 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:30:25 PM PDT 24
Peak memory 200356 kb
Host smart-585c19a1-2bef-465a-bc49-ef559ee5670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674732100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.674732100
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.374112198
Short name T34
Test name
Test status
Simulation time 17618508 ps
CPU time 0.62 seconds
Started Jul 15 06:28:34 PM PDT 24
Finished Jul 15 06:28:35 PM PDT 24
Peak memory 196916 kb
Host smart-6b9ef44d-543f-4f87-93db-1717031b2722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374112198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.374112198
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3145079632
Short name T45
Test name
Test status
Simulation time 913325937 ps
CPU time 53.25 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:29:26 PM PDT 24
Peak memory 200308 kb
Host smart-43ea52d8-66ce-4061-b8b2-2f8d61dee338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145079632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3145079632
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2434125062
Short name T146
Test name
Test status
Simulation time 19557892476 ps
CPU time 635.66 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:39:09 PM PDT 24
Peak memory 484056 kb
Host smart-e06259c1-3778-42e6-b11e-44226fc7e234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434125062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2434125062
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1149127961
Short name T160
Test name
Test status
Simulation time 12409488327 ps
CPU time 38.87 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:29:13 PM PDT 24
Peak memory 200320 kb
Host smart-b8ae0669-f268-4204-9229-aecda92284c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149127961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1149127961
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1396126117
Short name T357
Test name
Test status
Simulation time 1413301211 ps
CPU time 40.1 seconds
Started Jul 15 06:28:33 PM PDT 24
Finished Jul 15 06:29:14 PM PDT 24
Peak memory 200296 kb
Host smart-d5539fc0-1bfd-403d-82dd-f42379286e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396126117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1396126117
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.271227762
Short name T442
Test name
Test status
Simulation time 214345429 ps
CPU time 1.45 seconds
Started Jul 15 06:28:35 PM PDT 24
Finished Jul 15 06:28:37 PM PDT 24
Peak memory 200312 kb
Host smart-64345adc-1ee0-442b-be88-a0041a9a4e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271227762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.271227762
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2093141423
Short name T387
Test name
Test status
Simulation time 57930875905 ps
CPU time 120.82 seconds
Started Jul 15 06:28:31 PM PDT 24
Finished Jul 15 06:30:32 PM PDT 24
Peak memory 200236 kb
Host smart-b76e5223-af3e-431f-98a6-a927454bc4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093141423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2093141423
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.52114977
Short name T262
Test name
Test status
Simulation time 17729388 ps
CPU time 0.56 seconds
Started Jul 15 06:28:37 PM PDT 24
Finished Jul 15 06:28:38 PM PDT 24
Peak memory 195156 kb
Host smart-c95a3e35-18b1-4b7e-87ed-8b2a6576941d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52114977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.52114977
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3733111964
Short name T311
Test name
Test status
Simulation time 748495012 ps
CPU time 4.84 seconds
Started Jul 15 06:28:38 PM PDT 24
Finished Jul 15 06:28:44 PM PDT 24
Peak memory 200300 kb
Host smart-fc5eaeb2-16d8-4d2a-b5b0-69d150575fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733111964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3733111964
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.294333890
Short name T502
Test name
Test status
Simulation time 734702360 ps
CPU time 3.05 seconds
Started Jul 15 06:28:37 PM PDT 24
Finished Jul 15 06:28:41 PM PDT 24
Peak memory 200256 kb
Host smart-4140a859-513b-4c56-a5ca-b398930dc231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294333890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.294333890
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1698284466
Short name T150
Test name
Test status
Simulation time 3581680766 ps
CPU time 528.76 seconds
Started Jul 15 06:28:37 PM PDT 24
Finished Jul 15 06:37:26 PM PDT 24
Peak memory 640568 kb
Host smart-c95d0367-06a4-470f-9500-a9aafb4b6b35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698284466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1698284466
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3205259102
Short name T419
Test name
Test status
Simulation time 18015454871 ps
CPU time 215.01 seconds
Started Jul 15 06:28:39 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 200396 kb
Host smart-93f23282-b9f9-4c73-aa4f-112729977d64
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205259102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3205259102
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3640766740
Short name T208
Test name
Test status
Simulation time 2054661798 ps
CPU time 62 seconds
Started Jul 15 06:28:38 PM PDT 24
Finished Jul 15 06:29:40 PM PDT 24
Peak memory 200284 kb
Host smart-22a1ab1c-1eb3-4974-a1ef-8921f2d193bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640766740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3640766740
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.613552637
Short name T427
Test name
Test status
Simulation time 275961493 ps
CPU time 2.66 seconds
Started Jul 15 06:28:34 PM PDT 24
Finished Jul 15 06:28:37 PM PDT 24
Peak memory 200304 kb
Host smart-180aec50-3b13-4fa3-b587-00bda9d45d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613552637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.613552637
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.909611154
Short name T481
Test name
Test status
Simulation time 13575943831 ps
CPU time 550.01 seconds
Started Jul 15 06:28:38 PM PDT 24
Finished Jul 15 06:37:48 PM PDT 24
Peak memory 672552 kb
Host smart-e71f5b1d-52f9-4c2e-8ab1-57980cb0bc65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909611154 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.909611154
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2415707712
Short name T396
Test name
Test status
Simulation time 2039610480 ps
CPU time 32.67 seconds
Started Jul 15 06:28:39 PM PDT 24
Finished Jul 15 06:29:12 PM PDT 24
Peak memory 200248 kb
Host smart-57a7f1b9-edb5-4995-ba44-638189ed4f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415707712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2415707712
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.962257363
Short name T340
Test name
Test status
Simulation time 26494865 ps
CPU time 0.59 seconds
Started Jul 15 06:28:38 PM PDT 24
Finished Jul 15 06:28:39 PM PDT 24
Peak memory 196140 kb
Host smart-76e9377f-4995-4f56-b292-939ce2333a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962257363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.962257363
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2526296139
Short name T33
Test name
Test status
Simulation time 233978150 ps
CPU time 6.7 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:28:52 PM PDT 24
Peak memory 200272 kb
Host smart-a572a36f-21c8-4d6d-ae54-0633d21b64ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526296139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2526296139
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3998441158
Short name T40
Test name
Test status
Simulation time 3699565084 ps
CPU time 39.53 seconds
Started Jul 15 06:28:38 PM PDT 24
Finished Jul 15 06:29:19 PM PDT 24
Peak memory 200356 kb
Host smart-4ff8ca5a-1d02-445b-9117-0860806e3b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998441158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3998441158
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4259688109
Short name T318
Test name
Test status
Simulation time 11901643092 ps
CPU time 1279.15 seconds
Started Jul 15 06:28:36 PM PDT 24
Finished Jul 15 06:49:56 PM PDT 24
Peak memory 766856 kb
Host smart-d2c78dd2-ff36-42c8-9c89-04a9e8933733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259688109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4259688109
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3178826547
Short name T166
Test name
Test status
Simulation time 6749661685 ps
CPU time 120.53 seconds
Started Jul 15 06:28:37 PM PDT 24
Finished Jul 15 06:30:38 PM PDT 24
Peak memory 200360 kb
Host smart-d1e56c4f-9c89-46aa-9f67-ee90f6e1e306
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178826547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3178826547
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1985078314
Short name T327
Test name
Test status
Simulation time 318915447 ps
CPU time 13.53 seconds
Started Jul 15 06:28:36 PM PDT 24
Finished Jul 15 06:28:50 PM PDT 24
Peak memory 200296 kb
Host smart-a431b380-a6ef-4722-9c80-06b87c25f625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985078314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1985078314
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1195470904
Short name T450
Test name
Test status
Simulation time 257441404 ps
CPU time 4.34 seconds
Started Jul 15 06:28:39 PM PDT 24
Finished Jul 15 06:28:44 PM PDT 24
Peak memory 200312 kb
Host smart-d17c4fa1-475f-4800-a50c-4ef16e736f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195470904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1195470904
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.328846410
Short name T345
Test name
Test status
Simulation time 70236535175 ps
CPU time 742.52 seconds
Started Jul 15 06:28:43 PM PDT 24
Finished Jul 15 06:41:07 PM PDT 24
Peak memory 442396 kb
Host smart-0e8e0268-2efa-4210-a751-9e0ae3ed149b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328846410 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.328846410
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2521459693
Short name T518
Test name
Test status
Simulation time 78958697769 ps
CPU time 60.81 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:29:46 PM PDT 24
Peak memory 200344 kb
Host smart-2f4e601a-4205-4ff9-8df9-e13c30a2069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521459693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2521459693
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3507245641
Short name T310
Test name
Test status
Simulation time 30064081 ps
CPU time 0.6 seconds
Started Jul 15 06:28:43 PM PDT 24
Finished Jul 15 06:28:45 PM PDT 24
Peak memory 196160 kb
Host smart-1e32f341-eb60-42ef-8e99-3ebf3264f558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507245641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3507245641
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4004798651
Short name T294
Test name
Test status
Simulation time 74255748 ps
CPU time 4.3 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:28:49 PM PDT 24
Peak memory 200256 kb
Host smart-496bfb99-8cdd-446f-b30d-64e35a1f8b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004798651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4004798651
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2255605343
Short name T239
Test name
Test status
Simulation time 5855957488 ps
CPU time 26.39 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:29:12 PM PDT 24
Peak memory 200236 kb
Host smart-68a9a24f-e1d9-454d-bab8-375c0c355f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255605343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2255605343
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1740570959
Short name T356
Test name
Test status
Simulation time 40129307494 ps
CPU time 891 seconds
Started Jul 15 06:28:35 PM PDT 24
Finished Jul 15 06:43:26 PM PDT 24
Peak memory 649896 kb
Host smart-b96c6bab-67ec-49c3-a504-c7024aaf29dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740570959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1740570959
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2175298582
Short name T434
Test name
Test status
Simulation time 63484417346 ps
CPU time 187.52 seconds
Started Jul 15 06:28:42 PM PDT 24
Finished Jul 15 06:31:50 PM PDT 24
Peak memory 200364 kb
Host smart-951bc9ac-2df5-4cf8-961a-373a0cd6f6a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175298582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2175298582
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1369873214
Short name T143
Test name
Test status
Simulation time 2595183485 ps
CPU time 76.01 seconds
Started Jul 15 06:28:38 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 200376 kb
Host smart-08265a42-65e9-4a3d-b622-355c24c63f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369873214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1369873214
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.318137723
Short name T423
Test name
Test status
Simulation time 307736592 ps
CPU time 12.71 seconds
Started Jul 15 06:28:43 PM PDT 24
Finished Jul 15 06:28:56 PM PDT 24
Peak memory 200316 kb
Host smart-0b02c9fe-36c1-4207-9d03-ecdfb94dbd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318137723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.318137723
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2818981407
Short name T449
Test name
Test status
Simulation time 88263870050 ps
CPU time 432.31 seconds
Started Jul 15 06:28:46 PM PDT 24
Finished Jul 15 06:35:58 PM PDT 24
Peak memory 200360 kb
Host smart-1dca9384-497d-483e-9ad3-4f84368a8aad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818981407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2818981407
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4139438966
Short name T157
Test name
Test status
Simulation time 6387213778 ps
CPU time 114.51 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 200376 kb
Host smart-b7354ea9-6ee4-4851-9757-dae93434fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139438966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4139438966
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1363817142
Short name T49
Test name
Test status
Simulation time 14848386 ps
CPU time 0.59 seconds
Started Jul 15 06:28:45 PM PDT 24
Finished Jul 15 06:28:46 PM PDT 24
Peak memory 196184 kb
Host smart-c150f409-30da-4b89-86e8-2e39ddbbeb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363817142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1363817142
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2019001526
Short name T278
Test name
Test status
Simulation time 7132459773 ps
CPU time 98.3 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 200356 kb
Host smart-fbce4b3a-b031-44e7-97a1-b99fb1763d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019001526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2019001526
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2809461623
Short name T453
Test name
Test status
Simulation time 2380210628 ps
CPU time 34.56 seconds
Started Jul 15 06:28:45 PM PDT 24
Finished Jul 15 06:29:20 PM PDT 24
Peak memory 200400 kb
Host smart-f3f4b89c-d9a0-4861-87e3-8aa1adf434fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809461623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2809461623
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2559091899
Short name T433
Test name
Test status
Simulation time 5504650838 ps
CPU time 1100.21 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:47:05 PM PDT 24
Peak memory 734872 kb
Host smart-22ffd422-e65e-496d-b8ff-7ee6a3f6c6b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559091899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2559091899
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1816388625
Short name T448
Test name
Test status
Simulation time 555201502 ps
CPU time 31.37 seconds
Started Jul 15 06:28:45 PM PDT 24
Finished Jul 15 06:29:17 PM PDT 24
Peak memory 200216 kb
Host smart-c7258e0d-97f2-46a5-bc97-33e7feb34023
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816388625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1816388625
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.588515377
Short name T128
Test name
Test status
Simulation time 30157188646 ps
CPU time 136.58 seconds
Started Jul 15 06:28:44 PM PDT 24
Finished Jul 15 06:31:02 PM PDT 24
Peak memory 200340 kb
Host smart-d211aef3-ac04-4fb3-b016-cc669f45d60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588515377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.588515377
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3286642808
Short name T324
Test name
Test status
Simulation time 402932761 ps
CPU time 8.69 seconds
Started Jul 15 06:28:43 PM PDT 24
Finished Jul 15 06:28:52 PM PDT 24
Peak memory 200288 kb
Host smart-81b5c919-9988-4d16-b4f8-bc57b77a5093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286642808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3286642808
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1221340804
Short name T70
Test name
Test status
Simulation time 87480712757 ps
CPU time 2976.3 seconds
Started Jul 15 06:28:42 PM PDT 24
Finished Jul 15 07:18:19 PM PDT 24
Peak memory 800744 kb
Host smart-4b422a49-1b56-460e-9107-8a7ac80594a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221340804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1221340804
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.528879120
Short name T268
Test name
Test status
Simulation time 14389330713 ps
CPU time 49.81 seconds
Started Jul 15 06:28:45 PM PDT 24
Finished Jul 15 06:29:35 PM PDT 24
Peak memory 200372 kb
Host smart-061fdbe7-3198-40e9-a919-75be240cd004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528879120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.528879120
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.453017560
Short name T506
Test name
Test status
Simulation time 28806419 ps
CPU time 0.61 seconds
Started Jul 15 06:27:31 PM PDT 24
Finished Jul 15 06:27:32 PM PDT 24
Peak memory 195136 kb
Host smart-c05a60bf-d1df-41f8-95a1-f88722ccb888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453017560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.453017560
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1201111990
Short name T397
Test name
Test status
Simulation time 1549856991 ps
CPU time 81.33 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:28:54 PM PDT 24
Peak memory 200256 kb
Host smart-24c24c27-bce3-4ff6-befe-36ca1cd94f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201111990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1201111990
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1562299131
Short name T369
Test name
Test status
Simulation time 939032704 ps
CPU time 17.25 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 200352 kb
Host smart-ef4fa15e-73da-413e-a36f-a3eb7b0f3b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562299131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1562299131
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.161650280
Short name T411
Test name
Test status
Simulation time 1033273534 ps
CPU time 124.4 seconds
Started Jul 15 06:27:31 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 356128 kb
Host smart-4cf219bc-a6bb-4f00-a0db-d96275d24487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161650280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.161650280
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2103033112
Short name T123
Test name
Test status
Simulation time 1412536760 ps
CPU time 75.6 seconds
Started Jul 15 06:27:26 PM PDT 24
Finished Jul 15 06:28:42 PM PDT 24
Peak memory 200316 kb
Host smart-4d372b7b-e56d-4c2a-876b-a0db2829452c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103033112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2103033112
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3858664841
Short name T165
Test name
Test status
Simulation time 3246466113 ps
CPU time 91.52 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:29:00 PM PDT 24
Peak memory 200440 kb
Host smart-cc279339-0e4c-4cb6-b54c-23db8d1f63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858664841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3858664841
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3347614633
Short name T53
Test name
Test status
Simulation time 348939458 ps
CPU time 1.03 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:27:28 PM PDT 24
Peak memory 219472 kb
Host smart-610bdc9d-e8d3-4dc1-b87b-65438f55ae2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347614633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3347614633
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3604240604
Short name T361
Test name
Test status
Simulation time 1813137797 ps
CPU time 7.6 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:27:36 PM PDT 24
Peak memory 200248 kb
Host smart-d412a8c2-9429-4548-ac03-96a398fa07ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604240604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3604240604
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1220615328
Short name T46
Test name
Test status
Simulation time 22026352137 ps
CPU time 948.47 seconds
Started Jul 15 06:27:29 PM PDT 24
Finished Jul 15 06:43:18 PM PDT 24
Peak memory 708352 kb
Host smart-e7e27844-ca1f-4ff0-829b-dace726ca1a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220615328 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1220615328
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2862375952
Short name T12
Test name
Test status
Simulation time 60490650905 ps
CPU time 974.51 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:43:42 PM PDT 24
Peak memory 247364 kb
Host smart-cfbaea79-bf84-494b-824b-82cbdbfa38e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862375952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2862375952
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.122507502
Short name T58
Test name
Test status
Simulation time 13087572873 ps
CPU time 79.54 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:28:47 PM PDT 24
Peak memory 200336 kb
Host smart-fddd056e-ac0a-43ce-bb6f-c7296577ba96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=122507502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.122507502
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2804156397
Short name T373
Test name
Test status
Simulation time 107465613913 ps
CPU time 109.84 seconds
Started Jul 15 06:27:30 PM PDT 24
Finished Jul 15 06:29:21 PM PDT 24
Peak memory 200356 kb
Host smart-cee3cdcb-c03a-4240-bba6-f856695c94ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2804156397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2804156397
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2606096237
Short name T398
Test name
Test status
Simulation time 157624591083 ps
CPU time 87.79 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:29:00 PM PDT 24
Peak memory 200308 kb
Host smart-86c80ed6-7b9a-4ba5-94e4-9b4c332d6e08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2606096237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2606096237
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2092027341
Short name T184
Test name
Test status
Simulation time 238026647170 ps
CPU time 657.61 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:38:25 PM PDT 24
Peak memory 200396 kb
Host smart-b35dfd04-3a2b-4553-a2cc-8f59b13cd0d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2092027341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2092027341
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1139010116
Short name T190
Test name
Test status
Simulation time 2748293354509 ps
CPU time 2485.31 seconds
Started Jul 15 06:27:30 PM PDT 24
Finished Jul 15 07:08:56 PM PDT 24
Peak memory 216576 kb
Host smart-cf8b8c9e-6b99-498f-953e-b78219f47720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1139010116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1139010116
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2527854121
Short name T124
Test name
Test status
Simulation time 94100019244 ps
CPU time 2041.68 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 07:01:31 PM PDT 24
Peak memory 215828 kb
Host smart-5b5e79f0-4f74-4545-b606-c5c91e809437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2527854121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2527854121
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.621722108
Short name T527
Test name
Test status
Simulation time 25377403850 ps
CPU time 126.97 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 200508 kb
Host smart-6838202c-67b6-4733-bf75-e7d1007fffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621722108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.621722108
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2340953075
Short name T254
Test name
Test status
Simulation time 19652558 ps
CPU time 0.57 seconds
Started Jul 15 06:28:55 PM PDT 24
Finished Jul 15 06:28:56 PM PDT 24
Peak memory 195788 kb
Host smart-ab903624-e400-49e5-9019-829ecf648c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340953075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2340953075
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2506642932
Short name T159
Test name
Test status
Simulation time 1960073425 ps
CPU time 32.37 seconds
Started Jul 15 06:28:50 PM PDT 24
Finished Jul 15 06:29:23 PM PDT 24
Peak memory 200312 kb
Host smart-7959f20d-6ca6-4a50-ac66-63ef463fedf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506642932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2506642932
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1656997395
Short name T306
Test name
Test status
Simulation time 4826019462 ps
CPU time 45.03 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 200404 kb
Host smart-b6483186-38e8-4a80-9e83-7dc18f2c4cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656997395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1656997395
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3368482569
Short name T265
Test name
Test status
Simulation time 43248430 ps
CPU time 0.96 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:28:53 PM PDT 24
Peak memory 200156 kb
Host smart-e83d00d3-edeb-4b95-9004-f0d9a424f81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368482569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3368482569
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2508728381
Short name T260
Test name
Test status
Simulation time 4809716601 ps
CPU time 63.89 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:29:56 PM PDT 24
Peak memory 200300 kb
Host smart-08de8d29-9072-4e76-bc79-47466d37889e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508728381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2508728381
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.4250923468
Short name T375
Test name
Test status
Simulation time 50957454281 ps
CPU time 175.72 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:31:47 PM PDT 24
Peak memory 200344 kb
Host smart-23a26dfd-327e-496b-8261-3d35c2985a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250923468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4250923468
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.388188308
Short name T44
Test name
Test status
Simulation time 4829877771 ps
CPU time 13.87 seconds
Started Jul 15 06:28:43 PM PDT 24
Finished Jul 15 06:28:58 PM PDT 24
Peak memory 200416 kb
Host smart-68736da1-85f5-44ca-a335-53030431fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388188308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.388188308
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.134422374
Short name T307
Test name
Test status
Simulation time 28036990765 ps
CPU time 92.4 seconds
Started Jul 15 06:28:50 PM PDT 24
Finished Jul 15 06:30:23 PM PDT 24
Peak memory 200412 kb
Host smart-f60a7d9e-f4d8-4fca-becb-b472b5cce47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134422374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.134422374
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1831154505
Short name T282
Test name
Test status
Simulation time 40741712 ps
CPU time 0.58 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:28:59 PM PDT 24
Peak memory 195872 kb
Host smart-4bd11fdf-5e4e-4f86-9467-e83c993a8cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831154505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1831154505
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3566621454
Short name T210
Test name
Test status
Simulation time 1369495854 ps
CPU time 40.64 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:29:32 PM PDT 24
Peak memory 200332 kb
Host smart-297edffa-a06b-4c5f-899b-5bd6c406936d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566621454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3566621454
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1815488993
Short name T141
Test name
Test status
Simulation time 574819105 ps
CPU time 31.46 seconds
Started Jul 15 06:28:53 PM PDT 24
Finished Jul 15 06:29:25 PM PDT 24
Peak memory 200320 kb
Host smart-26d98d0a-d453-4472-b703-2141b913297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815488993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1815488993
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.409197474
Short name T203
Test name
Test status
Simulation time 7799895134 ps
CPU time 835.17 seconds
Started Jul 15 06:28:53 PM PDT 24
Finished Jul 15 06:42:49 PM PDT 24
Peak memory 743836 kb
Host smart-6f029c1b-03ea-4d5b-b47a-9a4922a55511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409197474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.409197474
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1365300960
Short name T257
Test name
Test status
Simulation time 96018968903 ps
CPU time 210.58 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 200372 kb
Host smart-361bc7c3-3035-4c2b-80b3-329a91e83620
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365300960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1365300960
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.702476370
Short name T57
Test name
Test status
Simulation time 38815510929 ps
CPU time 178.21 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:31:50 PM PDT 24
Peak memory 208572 kb
Host smart-fa8a3892-93ce-442e-9ddd-94047a7db74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702476370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.702476370
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.767018284
Short name T526
Test name
Test status
Simulation time 669643764 ps
CPU time 7.9 seconds
Started Jul 15 06:28:50 PM PDT 24
Finished Jul 15 06:28:59 PM PDT 24
Peak memory 200376 kb
Host smart-356ee6c8-a2b6-49eb-afbd-c964e7bf4d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767018284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.767018284
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1324352426
Short name T242
Test name
Test status
Simulation time 16371760108 ps
CPU time 226.47 seconds
Started Jul 15 06:28:51 PM PDT 24
Finished Jul 15 06:32:38 PM PDT 24
Peak memory 200396 kb
Host smart-7f15e3e2-11f2-4cea-bd2f-ec83d01fc199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324352426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1324352426
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.930964658
Short name T437
Test name
Test status
Simulation time 828426409 ps
CPU time 39.89 seconds
Started Jul 15 06:28:49 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 200280 kb
Host smart-9a9163c9-ae88-4073-ad89-f5b68c82f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930964658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.930964658
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3732857292
Short name T490
Test name
Test status
Simulation time 47569319 ps
CPU time 0.6 seconds
Started Jul 15 06:28:58 PM PDT 24
Finished Jul 15 06:29:00 PM PDT 24
Peak memory 196192 kb
Host smart-a73340b8-a0f6-44e1-adfe-921c5605902b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732857292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3732857292
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2630357548
Short name T258
Test name
Test status
Simulation time 3106802200 ps
CPU time 43.9 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:29:42 PM PDT 24
Peak memory 200412 kb
Host smart-96aa9a25-c0fb-4bbf-8b20-bb4baea57ec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630357548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2630357548
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3950591523
Short name T23
Test name
Test status
Simulation time 791275943 ps
CPU time 41.39 seconds
Started Jul 15 06:28:58 PM PDT 24
Finished Jul 15 06:29:41 PM PDT 24
Peak memory 200352 kb
Host smart-012b4ae8-eba3-4554-a174-745aa6c3a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950591523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3950591523
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4053205688
Short name T195
Test name
Test status
Simulation time 4425810529 ps
CPU time 765.27 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:41:44 PM PDT 24
Peak memory 709744 kb
Host smart-101ca045-f31f-43f7-927f-b9b5aff049f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053205688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4053205688
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2191863834
Short name T27
Test name
Test status
Simulation time 1430290877 ps
CPU time 75.71 seconds
Started Jul 15 06:28:58 PM PDT 24
Finished Jul 15 06:30:15 PM PDT 24
Peak memory 200288 kb
Host smart-0d167f44-3d4e-4dc3-93f4-cce1a2976721
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191863834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2191863834
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1560140341
Short name T172
Test name
Test status
Simulation time 622402238 ps
CPU time 11.92 seconds
Started Jul 15 06:28:58 PM PDT 24
Finished Jul 15 06:29:11 PM PDT 24
Peak memory 200296 kb
Host smart-d0142e54-5735-41b7-8e28-81f290a65a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560140341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1560140341
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2041181965
Short name T474
Test name
Test status
Simulation time 128487272 ps
CPU time 1.31 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:29:00 PM PDT 24
Peak memory 200316 kb
Host smart-7642dce0-6189-463b-b691-a18597045b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041181965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2041181965
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2533288110
Short name T125
Test name
Test status
Simulation time 2221416759 ps
CPU time 121.81 seconds
Started Jul 15 06:28:56 PM PDT 24
Finished Jul 15 06:30:59 PM PDT 24
Peak memory 200364 kb
Host smart-d90f039c-ebf2-46b2-bb33-a9fad21813f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533288110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2533288110
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3695918142
Short name T251
Test name
Test status
Simulation time 4421419121 ps
CPU time 52.65 seconds
Started Jul 15 06:28:55 PM PDT 24
Finished Jul 15 06:29:48 PM PDT 24
Peak memory 200396 kb
Host smart-9ae953cf-0768-4d59-a8ec-abecd6b31901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695918142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3695918142
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1152873571
Short name T333
Test name
Test status
Simulation time 27962189 ps
CPU time 0.55 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:29:05 PM PDT 24
Peak memory 195864 kb
Host smart-eeaef860-43cf-4564-8b44-04bd248f2951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152873571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1152873571
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.690692926
Short name T381
Test name
Test status
Simulation time 1270777605 ps
CPU time 73.81 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:30:12 PM PDT 24
Peak memory 200300 kb
Host smart-9a4f403e-6742-49dd-89be-53fbb01120dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690692926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.690692926
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2919569181
Short name T320
Test name
Test status
Simulation time 3273759054 ps
CPU time 43.29 seconds
Started Jul 15 06:28:58 PM PDT 24
Finished Jul 15 06:29:43 PM PDT 24
Peak memory 200372 kb
Host smart-67015c9d-2978-43da-a1e4-93712018551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919569181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2919569181
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1152760138
Short name T325
Test name
Test status
Simulation time 1279864208 ps
CPU time 101.12 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 412712 kb
Host smart-e1e9d208-16fb-473f-9bf0-713793c7b2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152760138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1152760138
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3095037810
Short name T390
Test name
Test status
Simulation time 9162853145 ps
CPU time 117.81 seconds
Started Jul 15 06:28:56 PM PDT 24
Finished Jul 15 06:30:55 PM PDT 24
Peak memory 200372 kb
Host smart-1bed1d0a-9fe9-4f04-b215-9c4515ce9539
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095037810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3095037810
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2959143875
Short name T39
Test name
Test status
Simulation time 3826053000 ps
CPU time 74.2 seconds
Started Jul 15 06:28:58 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 200412 kb
Host smart-46e31786-068a-411e-878f-95263abafe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959143875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2959143875
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3955792429
Short name T26
Test name
Test status
Simulation time 4305150123 ps
CPU time 12.42 seconds
Started Jul 15 06:28:56 PM PDT 24
Finished Jul 15 06:29:09 PM PDT 24
Peak memory 200392 kb
Host smart-6f291634-12b7-4985-8d81-8c5c3d6253c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955792429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3955792429
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1030907074
Short name T132
Test name
Test status
Simulation time 18533591306 ps
CPU time 1226.69 seconds
Started Jul 15 06:28:56 PM PDT 24
Finished Jul 15 06:49:23 PM PDT 24
Peak memory 753512 kb
Host smart-2eccf1c1-0243-4812-a100-7218f77a5721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030907074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1030907074
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1449450063
Short name T249
Test name
Test status
Simulation time 5826556685 ps
CPU time 55.78 seconds
Started Jul 15 06:28:57 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 200380 kb
Host smart-88f07249-9e34-4354-9657-b6fc69c976ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449450063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1449450063
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2023140257
Short name T15
Test name
Test status
Simulation time 13125658 ps
CPU time 0.64 seconds
Started Jul 15 06:29:02 PM PDT 24
Finished Jul 15 06:29:03 PM PDT 24
Peak memory 196204 kb
Host smart-3d2260a7-5692-4e51-b6ff-3ae05dba7d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023140257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2023140257
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4238648023
Short name T19
Test name
Test status
Simulation time 2832676006 ps
CPU time 79.91 seconds
Started Jul 15 06:29:04 PM PDT 24
Finished Jul 15 06:30:26 PM PDT 24
Peak memory 200360 kb
Host smart-ef2545f8-ba7f-41eb-a017-22802161e001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238648023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4238648023
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4148764105
Short name T465
Test name
Test status
Simulation time 6504714314 ps
CPU time 42.81 seconds
Started Jul 15 06:29:04 PM PDT 24
Finished Jul 15 06:29:48 PM PDT 24
Peak memory 200328 kb
Host smart-5e51738c-f6d0-47e5-8c27-8503f1e9ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148764105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4148764105
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2139801673
Short name T204
Test name
Test status
Simulation time 5295811942 ps
CPU time 89.51 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:30:33 PM PDT 24
Peak memory 440488 kb
Host smart-c370bcf3-163b-41f4-a745-8e046125437c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139801673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2139801673
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.415296686
Short name T452
Test name
Test status
Simulation time 12310761706 ps
CPU time 162.16 seconds
Started Jul 15 06:29:02 PM PDT 24
Finished Jul 15 06:31:46 PM PDT 24
Peak memory 200296 kb
Host smart-c588a3c5-1d75-4df8-bd62-3b04efe27a43
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415296686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.415296686
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.756301066
Short name T187
Test name
Test status
Simulation time 14416635377 ps
CPU time 176.85 seconds
Started Jul 15 06:29:02 PM PDT 24
Finished Jul 15 06:32:00 PM PDT 24
Peak memory 200352 kb
Host smart-bf9804bf-addb-4182-89ed-bac670785e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756301066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.756301066
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3763424769
Short name T352
Test name
Test status
Simulation time 310886441 ps
CPU time 13.81 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:29:18 PM PDT 24
Peak memory 200292 kb
Host smart-62a029b0-8193-4f13-adea-a403ae02fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763424769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3763424769
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.4141062774
Short name T134
Test name
Test status
Simulation time 7833715061 ps
CPU time 402.43 seconds
Started Jul 15 06:29:05 PM PDT 24
Finished Jul 15 06:35:49 PM PDT 24
Peak memory 200364 kb
Host smart-213e3ae2-cd6a-4482-b6b5-4bec98d240e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141062774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.4141062774
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.480788179
Short name T217
Test name
Test status
Simulation time 5986733057 ps
CPU time 101.27 seconds
Started Jul 15 06:29:05 PM PDT 24
Finished Jul 15 06:30:47 PM PDT 24
Peak memory 200364 kb
Host smart-241c33bf-9331-4d3d-b744-2d6d94822991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480788179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.480788179
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.351298033
Short name T332
Test name
Test status
Simulation time 47312587 ps
CPU time 0.59 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:29:10 PM PDT 24
Peak memory 195160 kb
Host smart-082f0f3f-7f18-4616-a3f4-0b30c4a186bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351298033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.351298033
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1863856976
Short name T420
Test name
Test status
Simulation time 2441822293 ps
CPU time 61.37 seconds
Started Jul 15 06:29:01 PM PDT 24
Finished Jul 15 06:30:03 PM PDT 24
Peak memory 200364 kb
Host smart-069246f6-df71-4ec7-ad06-582eec9ca5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863856976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1863856976
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3853357408
Short name T167
Test name
Test status
Simulation time 10540685489 ps
CPU time 67.17 seconds
Started Jul 15 06:29:05 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 200428 kb
Host smart-fe46d720-dfbf-40d5-9379-8e9c225b9214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853357408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3853357408
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2901979823
Short name T316
Test name
Test status
Simulation time 16261258246 ps
CPU time 450.91 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:36:36 PM PDT 24
Peak memory 711556 kb
Host smart-3f929569-0399-4795-956f-ef25be8392ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901979823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2901979823
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.511763205
Short name T457
Test name
Test status
Simulation time 16854944 ps
CPU time 0.69 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:29:05 PM PDT 24
Peak memory 196784 kb
Host smart-d90c8685-88fd-4874-b21c-5b4a02cb87ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511763205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.511763205
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3113560100
Short name T323
Test name
Test status
Simulation time 12581342454 ps
CPU time 113.68 seconds
Started Jul 15 06:29:02 PM PDT 24
Finished Jul 15 06:30:57 PM PDT 24
Peak memory 200368 kb
Host smart-eeef32dc-9785-4a63-8868-9744a4f6f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113560100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3113560100
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3907656677
Short name T275
Test name
Test status
Simulation time 1313982745 ps
CPU time 14.46 seconds
Started Jul 15 06:29:03 PM PDT 24
Finished Jul 15 06:29:18 PM PDT 24
Peak memory 200344 kb
Host smart-cda1b060-bc35-4150-a8fa-a62a378703c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907656677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3907656677
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.823752358
Short name T456
Test name
Test status
Simulation time 6021832992 ps
CPU time 26.54 seconds
Started Jul 15 06:29:04 PM PDT 24
Finished Jul 15 06:29:32 PM PDT 24
Peak memory 200372 kb
Host smart-7f49b3f3-83cc-457a-a6a3-91173c81355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823752358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.823752358
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.636527586
Short name T281
Test name
Test status
Simulation time 11196357 ps
CPU time 0.6 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:29:10 PM PDT 24
Peak memory 195812 kb
Host smart-221e2a6e-a9d7-46d2-83d2-24e5bac5d8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636527586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.636527586
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1155513867
Short name T377
Test name
Test status
Simulation time 1145978848 ps
CPU time 57.71 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:30:06 PM PDT 24
Peak memory 200336 kb
Host smart-f1b39686-1452-4e5b-9241-ec33af063275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155513867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1155513867
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1906606304
Short name T137
Test name
Test status
Simulation time 2018443094 ps
CPU time 55.15 seconds
Started Jul 15 06:29:12 PM PDT 24
Finished Jul 15 06:30:08 PM PDT 24
Peak memory 200284 kb
Host smart-ef697abd-1798-463c-9ce8-6950f091581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906606304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1906606304
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3940965187
Short name T395
Test name
Test status
Simulation time 8860913408 ps
CPU time 814.88 seconds
Started Jul 15 06:29:10 PM PDT 24
Finished Jul 15 06:42:45 PM PDT 24
Peak memory 722240 kb
Host smart-ce5fafac-eff7-47b7-a7be-dbb17627c6c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940965187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3940965187
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1011955773
Short name T464
Test name
Test status
Simulation time 74083743360 ps
CPU time 100.15 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:30:49 PM PDT 24
Peak memory 200396 kb
Host smart-1016464a-f36c-4e65-b472-c76a97cc1ab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011955773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1011955773
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.239854983
Short name T9
Test name
Test status
Simulation time 6893741436 ps
CPU time 24.26 seconds
Started Jul 15 06:29:12 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 200404 kb
Host smart-83b751bb-ae16-4276-a11a-06fb21da39e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239854983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.239854983
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3326290827
Short name T368
Test name
Test status
Simulation time 44580926 ps
CPU time 1.18 seconds
Started Jul 15 06:29:06 PM PDT 24
Finished Jul 15 06:29:08 PM PDT 24
Peak memory 200272 kb
Host smart-36d1cfbc-7ae0-4043-8e25-08ce52f24b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326290827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3326290827
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3639885861
Short name T279
Test name
Test status
Simulation time 7511156196 ps
CPU time 209.47 seconds
Started Jul 15 06:29:13 PM PDT 24
Finished Jul 15 06:32:43 PM PDT 24
Peak memory 216736 kb
Host smart-53f9cfed-c56a-4fb9-8171-5b27364b3a26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639885861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3639885861
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2152081426
Short name T454
Test name
Test status
Simulation time 22232805987 ps
CPU time 71.52 seconds
Started Jul 15 06:29:07 PM PDT 24
Finished Jul 15 06:30:20 PM PDT 24
Peak memory 200328 kb
Host smart-931cb720-ae49-46b1-b45c-7cb4249ad9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152081426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2152081426
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1136929208
Short name T528
Test name
Test status
Simulation time 13932212 ps
CPU time 0.63 seconds
Started Jul 15 06:29:07 PM PDT 24
Finished Jul 15 06:29:08 PM PDT 24
Peak memory 196844 kb
Host smart-c675b61e-a116-4efe-97f4-71fd32766efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136929208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1136929208
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3229349622
Short name T16
Test name
Test status
Simulation time 3418551957 ps
CPU time 60.11 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:30:09 PM PDT 24
Peak memory 216612 kb
Host smart-4b3f15b4-728d-4518-8c66-bb9771f1a25f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229349622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3229349622
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1833706472
Short name T138
Test name
Test status
Simulation time 467078167 ps
CPU time 26.46 seconds
Started Jul 15 06:29:13 PM PDT 24
Finished Jul 15 06:29:40 PM PDT 24
Peak memory 200300 kb
Host smart-636b0ff9-fff0-424d-816a-a87f01402977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833706472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1833706472
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3822363541
Short name T145
Test name
Test status
Simulation time 8733265000 ps
CPU time 1972.31 seconds
Started Jul 15 06:29:09 PM PDT 24
Finished Jul 15 07:02:02 PM PDT 24
Peak memory 791636 kb
Host smart-a3ff8e90-46f0-41ae-bb2f-5363c455dfb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822363541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3822363541
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2108175080
Short name T215
Test name
Test status
Simulation time 22733158567 ps
CPU time 65.39 seconds
Started Jul 15 06:29:09 PM PDT 24
Finished Jul 15 06:30:15 PM PDT 24
Peak memory 200276 kb
Host smart-604592b8-d864-4483-9c0a-769c25d6c8b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108175080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2108175080
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.534349893
Short name T492
Test name
Test status
Simulation time 19438606181 ps
CPU time 88.7 seconds
Started Jul 15 06:29:09 PM PDT 24
Finished Jul 15 06:30:38 PM PDT 24
Peak memory 200340 kb
Host smart-3f353147-5c56-4cce-8c14-59811ed9c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534349893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.534349893
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2971356203
Short name T59
Test name
Test status
Simulation time 881145156 ps
CPU time 5.45 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:29:15 PM PDT 24
Peak memory 200280 kb
Host smart-f1796086-b9f6-4209-a23e-ed594639c220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971356203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2971356203
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1010310620
Short name T112
Test name
Test status
Simulation time 84467687680 ps
CPU time 770.77 seconds
Started Jul 15 06:29:12 PM PDT 24
Finished Jul 15 06:42:03 PM PDT 24
Peak memory 200328 kb
Host smart-bb2753dc-4c78-47e2-9485-f189aa34c88f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010310620 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1010310620
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1411713124
Short name T511
Test name
Test status
Simulation time 14340790392 ps
CPU time 127.2 seconds
Started Jul 15 06:29:09 PM PDT 24
Finished Jul 15 06:31:17 PM PDT 24
Peak memory 200404 kb
Host smart-68acbfa8-c430-4b5d-92ae-e3444a0dcd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411713124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1411713124
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.717299580
Short name T154
Test name
Test status
Simulation time 173718985 ps
CPU time 0.58 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:29:16 PM PDT 24
Peak memory 196880 kb
Host smart-575b7aa9-731a-4ca2-8948-cee3cfa335d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717299580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.717299580
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1284267123
Short name T241
Test name
Test status
Simulation time 1693768677 ps
CPU time 94.06 seconds
Started Jul 15 06:29:11 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 200320 kb
Host smart-73d1dac5-c390-4338-ac18-050b150b2348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284267123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1284267123
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1427302620
Short name T479
Test name
Test status
Simulation time 8899713674 ps
CPU time 24.63 seconds
Started Jul 15 06:29:15 PM PDT 24
Finished Jul 15 06:29:40 PM PDT 24
Peak memory 200356 kb
Host smart-060d776c-eb91-45e5-9582-6de28e58741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427302620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1427302620
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.157356878
Short name T424
Test name
Test status
Simulation time 22322157731 ps
CPU time 1101.61 seconds
Started Jul 15 06:29:05 PM PDT 24
Finished Jul 15 06:47:28 PM PDT 24
Peak memory 747944 kb
Host smart-6a0e9b94-70fc-4730-a673-c3434a6b08a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157356878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.157356878
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1537524888
Short name T330
Test name
Test status
Simulation time 10727405802 ps
CPU time 150.56 seconds
Started Jul 15 06:29:15 PM PDT 24
Finished Jul 15 06:31:46 PM PDT 24
Peak memory 200336 kb
Host smart-56e8c47b-fe96-44f0-afaf-df04f89ef7b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537524888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1537524888
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3050333067
Short name T374
Test name
Test status
Simulation time 10362831928 ps
CPU time 140.57 seconds
Started Jul 15 06:29:08 PM PDT 24
Finished Jul 15 06:31:30 PM PDT 24
Peak memory 200376 kb
Host smart-4ffe1101-5969-4a7f-b39c-8426e49d768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050333067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3050333067
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.731823850
Short name T214
Test name
Test status
Simulation time 686000510 ps
CPU time 10.76 seconds
Started Jul 15 06:29:11 PM PDT 24
Finished Jul 15 06:29:22 PM PDT 24
Peak memory 200344 kb
Host smart-c08d90f3-18d4-42de-8e58-a5ffaddec105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731823850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.731823850
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.98248171
Short name T250
Test name
Test status
Simulation time 36299734302 ps
CPU time 112.28 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 209620 kb
Host smart-9c5146c2-4552-4155-ab0a-64ab61a80261
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98248171 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.98248171
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.685189833
Short name T399
Test name
Test status
Simulation time 10384521356 ps
CPU time 131.63 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 200372 kb
Host smart-6a318bb7-aa06-4b50-ae4e-3fc16f8b04c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685189833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.685189833
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.219757280
Short name T50
Test name
Test status
Simulation time 42728249 ps
CPU time 0.58 seconds
Started Jul 15 06:29:17 PM PDT 24
Finished Jul 15 06:29:18 PM PDT 24
Peak memory 195052 kb
Host smart-6166ee3a-5a82-49d5-af85-4b23c174bf30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219757280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.219757280
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1222179085
Short name T175
Test name
Test status
Simulation time 265212339 ps
CPU time 14.85 seconds
Started Jul 15 06:29:17 PM PDT 24
Finished Jul 15 06:29:32 PM PDT 24
Peak memory 200196 kb
Host smart-5a5db6d3-8461-4eda-993b-fa8125424efb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222179085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1222179085
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2832815649
Short name T363
Test name
Test status
Simulation time 43022033472 ps
CPU time 62.87 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:30:18 PM PDT 24
Peak memory 200404 kb
Host smart-6390a17e-6463-4c18-b8fb-c370d01badf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832815649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2832815649
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.781285727
Short name T339
Test name
Test status
Simulation time 7789771475 ps
CPU time 1485.84 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:54:01 PM PDT 24
Peak memory 712248 kb
Host smart-9cf20238-7826-4299-ab2c-497b9ea5feff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781285727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.781285727
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3592531020
Short name T259
Test name
Test status
Simulation time 25513132840 ps
CPU time 203.31 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:32:39 PM PDT 24
Peak memory 200396 kb
Host smart-b6d78b47-ed4a-471c-8d3d-92b443280eff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592531020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3592531020
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2637126588
Short name T523
Test name
Test status
Simulation time 45053625036 ps
CPU time 216.89 seconds
Started Jul 15 06:29:15 PM PDT 24
Finished Jul 15 06:32:53 PM PDT 24
Peak memory 208564 kb
Host smart-2f2c5419-fbc5-4fb9-bb89-c0ea0b899cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637126588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2637126588
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2258935581
Short name T415
Test name
Test status
Simulation time 1297387471 ps
CPU time 4.27 seconds
Started Jul 15 06:29:14 PM PDT 24
Finished Jul 15 06:29:19 PM PDT 24
Peak memory 200300 kb
Host smart-49c82176-7c7a-47a5-9ae4-7c9fa5055d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258935581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2258935581
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3449903314
Short name T303
Test name
Test status
Simulation time 220991535707 ps
CPU time 2221.41 seconds
Started Jul 15 06:29:15 PM PDT 24
Finished Jul 15 07:06:17 PM PDT 24
Peak memory 790008 kb
Host smart-4cf089ee-d24b-4dd3-a0a9-a3603b5f39c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449903314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3449903314
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3297966794
Short name T392
Test name
Test status
Simulation time 2556042037 ps
CPU time 114.85 seconds
Started Jul 15 06:29:13 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 200372 kb
Host smart-daddc1fd-ad44-47a6-b275-73a7d7fc6117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297966794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3297966794
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4284854050
Short name T509
Test name
Test status
Simulation time 144648198 ps
CPU time 0.56 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:27:35 PM PDT 24
Peak memory 195168 kb
Host smart-06fbcf79-c04d-4255-a497-cc7a8caedcc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284854050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4284854050
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2288273227
Short name T196
Test name
Test status
Simulation time 7054014778 ps
CPU time 110.01 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:29:19 PM PDT 24
Peak memory 200332 kb
Host smart-40965ae8-8c43-439e-bb90-60deda6d5873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288273227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2288273227
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.63522137
Short name T446
Test name
Test status
Simulation time 1205412228 ps
CPU time 21.92 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:27:54 PM PDT 24
Peak memory 200260 kb
Host smart-e7ab4570-301f-4ac7-819e-661d1fe0d1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63522137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.63522137
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.333562678
Short name T515
Test name
Test status
Simulation time 31018480461 ps
CPU time 414.03 seconds
Started Jul 15 06:27:26 PM PDT 24
Finished Jul 15 06:34:21 PM PDT 24
Peak memory 652456 kb
Host smart-a7fe51be-e988-4ba0-939d-115c7b92e76b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333562678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.333562678
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.140196697
Short name T360
Test name
Test status
Simulation time 3044399674 ps
CPU time 172.05 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:30:19 PM PDT 24
Peak memory 200336 kb
Host smart-95218970-8921-4bcf-9466-93bcf4abb3cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140196697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.140196697
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1825046206
Short name T487
Test name
Test status
Simulation time 61499880002 ps
CPU time 213.7 seconds
Started Jul 15 06:27:30 PM PDT 24
Finished Jul 15 06:31:04 PM PDT 24
Peak memory 216552 kb
Host smart-d281c3fb-4621-4261-b426-1d2307c19e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825046206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1825046206
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1646066670
Short name T245
Test name
Test status
Simulation time 5731628315 ps
CPU time 8.23 seconds
Started Jul 15 06:27:28 PM PDT 24
Finished Jul 15 06:27:37 PM PDT 24
Peak memory 200360 kb
Host smart-6ab47943-fbc4-44c9-bdd2-d3e4b75cd20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646066670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1646066670
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.540637523
Short name T343
Test name
Test status
Simulation time 11771666056 ps
CPU time 128.62 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:29:41 PM PDT 24
Peak memory 200388 kb
Host smart-ab99117e-f935-4ea1-9d52-910822dc9cb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540637523 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.540637523
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3854139115
Short name T493
Test name
Test status
Simulation time 30540269201 ps
CPU time 88.66 seconds
Started Jul 15 06:27:27 PM PDT 24
Finished Jul 15 06:28:56 PM PDT 24
Peak memory 200344 kb
Host smart-97015998-fdd6-4081-bc04-89e5af65f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854139115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3854139115
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.250078402
Short name T348
Test name
Test status
Simulation time 51589120 ps
CPU time 0.58 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:27:37 PM PDT 24
Peak memory 195136 kb
Host smart-56ed7bba-6439-4306-8efa-ffc614c5b460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250078402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.250078402
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1955839720
Short name T198
Test name
Test status
Simulation time 2621393957 ps
CPU time 76.71 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:28:52 PM PDT 24
Peak memory 200328 kb
Host smart-c6566821-3156-42b9-a179-0576130b8538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955839720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1955839720
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2854630055
Short name T106
Test name
Test status
Simulation time 1795028463 ps
CPU time 2.97 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:27:37 PM PDT 24
Peak memory 200292 kb
Host smart-4a4d7584-dd0c-457f-9f52-471e6a086aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854630055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2854630055
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3348251519
Short name T337
Test name
Test status
Simulation time 7244296164 ps
CPU time 1395.76 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:50:51 PM PDT 24
Peak memory 731536 kb
Host smart-26a42a41-78b0-4efd-b35b-00899e9ebd5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348251519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3348251519
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2127884269
Short name T349
Test name
Test status
Simulation time 3863944912 ps
CPU time 69.32 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:28:45 PM PDT 24
Peak memory 200280 kb
Host smart-e6b52f40-6b59-446a-a626-de461ca2d74c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127884269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2127884269
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3794871051
Short name T471
Test name
Test status
Simulation time 7035558113 ps
CPU time 132.04 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:29:48 PM PDT 24
Peak memory 200348 kb
Host smart-a18ade00-18a3-43b8-a3c0-bcfa9cb37a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794871051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3794871051
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2151392015
Short name T290
Test name
Test status
Simulation time 271236531 ps
CPU time 3.32 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:27:36 PM PDT 24
Peak memory 200296 kb
Host smart-f87d8110-b6f0-470c-9250-774a74e66f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151392015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2151392015
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1515145409
Short name T199
Test name
Test status
Simulation time 49525219558 ps
CPU time 1413.14 seconds
Started Jul 15 06:27:33 PM PDT 24
Finished Jul 15 06:51:07 PM PDT 24
Peak memory 682896 kb
Host smart-d0ff06b9-6c94-4ea1-8e2b-d923d5e5b65e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515145409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1515145409
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3115534247
Short name T22
Test name
Test status
Simulation time 38520550546 ps
CPU time 2599.73 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 07:10:55 PM PDT 24
Peak memory 527248 kb
Host smart-1e81809e-b5d1-4b99-9582-eae8bc1b41ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115534247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3115534247
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2957250042
Short name T80
Test name
Test status
Simulation time 27727929914 ps
CPU time 82.28 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:28:55 PM PDT 24
Peak memory 200364 kb
Host smart-d2c46a5b-e8b5-4f8a-9b08-d418c6e7ccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957250042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2957250042
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2123704565
Short name T192
Test name
Test status
Simulation time 13908650 ps
CPU time 0.64 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:27:36 PM PDT 24
Peak memory 196196 kb
Host smart-16d7c742-4b0b-49b1-88b7-2aeec7ac615e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123704565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2123704565
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1719961418
Short name T201
Test name
Test status
Simulation time 1273124593 ps
CPU time 74.61 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:28:49 PM PDT 24
Peak memory 200240 kb
Host smart-18a2cb10-29b2-4883-b670-2a1c67922148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719961418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1719961418
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1588306519
Short name T510
Test name
Test status
Simulation time 32873225966 ps
CPU time 49.38 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:28:25 PM PDT 24
Peak memory 200372 kb
Host smart-0cb13f52-4dc6-4b0a-ac3c-ab297e04710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588306519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1588306519
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1256588382
Short name T191
Test name
Test status
Simulation time 1990486041 ps
CPU time 337.54 seconds
Started Jul 15 06:27:37 PM PDT 24
Finished Jul 15 06:33:15 PM PDT 24
Peak memory 630864 kb
Host smart-c782fabc-d6b0-4b08-ba09-a3e035473dcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256588382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1256588382
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.174906750
Short name T147
Test name
Test status
Simulation time 3478915341 ps
CPU time 49.88 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:28:24 PM PDT 24
Peak memory 200292 kb
Host smart-7daedb72-59e8-4e3b-9c39-0bceca570902
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174906750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.174906750
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3411283118
Short name T336
Test name
Test status
Simulation time 1585807605 ps
CPU time 44.65 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:28:20 PM PDT 24
Peak memory 200300 kb
Host smart-d0b5e057-d848-4c8f-ad97-92bc5b446ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411283118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3411283118
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4110252201
Short name T174
Test name
Test status
Simulation time 1290368374 ps
CPU time 11.43 seconds
Started Jul 15 06:27:33 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 200280 kb
Host smart-6da8983b-5d48-4ff5-8509-8c7a19e384e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110252201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4110252201
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1958284785
Short name T66
Test name
Test status
Simulation time 58318972876 ps
CPU time 1679.96 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:55:36 PM PDT 24
Peak memory 709420 kb
Host smart-8c94920a-91ed-4dca-92e3-9417e97433aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958284785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1958284785
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1992376243
Short name T220
Test name
Test status
Simulation time 17426943288 ps
CPU time 133.47 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:29:48 PM PDT 24
Peak memory 200436 kb
Host smart-8183eede-8af4-47fd-a90d-5698a98b7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992376243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1992376243
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2072451744
Short name T266
Test name
Test status
Simulation time 27755809 ps
CPU time 0.61 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:27:35 PM PDT 24
Peak memory 196232 kb
Host smart-a66015ed-8fcd-455d-b98f-2f404c97a2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072451744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2072451744
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2679072141
Short name T466
Test name
Test status
Simulation time 3490555231 ps
CPU time 46.18 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:28:22 PM PDT 24
Peak memory 200224 kb
Host smart-415be40c-14d3-45cc-8534-a025d42caa5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679072141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2679072141
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1463873457
Short name T4
Test name
Test status
Simulation time 17073680184 ps
CPU time 54.28 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:28:31 PM PDT 24
Peak memory 200312 kb
Host smart-9de3ddb8-a04b-41ba-859e-5f20cdb56d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463873457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1463873457
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.689308068
Short name T252
Test name
Test status
Simulation time 5953039458 ps
CPU time 1017.51 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:44:34 PM PDT 24
Peak memory 763460 kb
Host smart-8c8cf067-ef46-445b-a248-c1c25e24d70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689308068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.689308068
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1346449873
Short name T428
Test name
Test status
Simulation time 3447211074 ps
CPU time 11.99 seconds
Started Jul 15 06:27:33 PM PDT 24
Finished Jul 15 06:27:45 PM PDT 24
Peak memory 200332 kb
Host smart-d15be386-9027-496b-b3cc-8791b310e2ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346449873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1346449873
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.984835688
Short name T485
Test name
Test status
Simulation time 2498467086 ps
CPU time 143.57 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 200396 kb
Host smart-8eb23ccb-5794-48a6-99f1-b2d0224fedcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984835688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.984835688
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.239119925
Short name T406
Test name
Test status
Simulation time 260783604 ps
CPU time 12.02 seconds
Started Jul 15 06:27:35 PM PDT 24
Finished Jul 15 06:27:48 PM PDT 24
Peak memory 200276 kb
Host smart-9ae9bb0b-5d74-445c-b587-2bfd9c610727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239119925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.239119925
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2984881279
Short name T524
Test name
Test status
Simulation time 224713421834 ps
CPU time 2452.56 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 07:08:32 PM PDT 24
Peak memory 752724 kb
Host smart-b5953e0c-0139-4561-834d-c6b470622385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984881279 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2984881279
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1054579472
Short name T7
Test name
Test status
Simulation time 43663456871 ps
CPU time 512.1 seconds
Started Jul 15 06:27:33 PM PDT 24
Finished Jul 15 06:36:05 PM PDT 24
Peak memory 432208 kb
Host smart-3a799384-7d22-46d0-938b-f99e8319dac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054579472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1054579472
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.659317662
Short name T78
Test name
Test status
Simulation time 1355652734 ps
CPU time 18.39 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:27:55 PM PDT 24
Peak memory 200296 kb
Host smart-072f1d79-7103-4c27-8118-58d57db1d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659317662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.659317662
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1240119635
Short name T232
Test name
Test status
Simulation time 13573939 ps
CPU time 0.58 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:27:37 PM PDT 24
Peak memory 195940 kb
Host smart-95244f90-2890-4e73-813f-666bcbc5e2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240119635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1240119635
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.44809835
Short name T189
Test name
Test status
Simulation time 1754766680 ps
CPU time 93.47 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:29:08 PM PDT 24
Peak memory 200304 kb
Host smart-d6c6cda8-a8b4-487a-91a8-aee17d8b5933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44809835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.44809835
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4196470564
Short name T504
Test name
Test status
Simulation time 3265690093 ps
CPU time 49.13 seconds
Started Jul 15 06:27:33 PM PDT 24
Finished Jul 15 06:28:23 PM PDT 24
Peak memory 200380 kb
Host smart-fb6c7d13-7332-4cc5-9bec-2cf3b361b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196470564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4196470564
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1501911177
Short name T503
Test name
Test status
Simulation time 4001373036 ps
CPU time 411.47 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:34:29 PM PDT 24
Peak memory 647704 kb
Host smart-9cfa67b9-1cbf-4594-92ad-8ba0553a23b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501911177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1501911177
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3969608346
Short name T529
Test name
Test status
Simulation time 6824899712 ps
CPU time 96.69 seconds
Started Jul 15 06:27:32 PM PDT 24
Finished Jul 15 06:29:09 PM PDT 24
Peak memory 200312 kb
Host smart-d7f3d935-9999-44ef-8edc-4143025ef878
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969608346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3969608346
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3797534160
Short name T355
Test name
Test status
Simulation time 21148869158 ps
CPU time 105.62 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:29:22 PM PDT 24
Peak memory 216568 kb
Host smart-c93d40d0-5151-44df-998f-1c4d22f4362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797534160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3797534160
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1487118625
Short name T383
Test name
Test status
Simulation time 815322743 ps
CPU time 12.89 seconds
Started Jul 15 06:27:36 PM PDT 24
Finished Jul 15 06:27:49 PM PDT 24
Peak memory 200356 kb
Host smart-d0aa0483-ec80-4ccd-9f4c-876da653efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487118625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1487118625
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2636622240
Short name T75
Test name
Test status
Simulation time 3809891703 ps
CPU time 199.22 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 216772 kb
Host smart-04d3fe3f-2ab0-46ee-b475-6c7c0a4deb30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636622240 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2636622240
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.889793571
Short name T36
Test name
Test status
Simulation time 115886964348 ps
CPU time 1631.35 seconds
Started Jul 15 06:27:34 PM PDT 24
Finished Jul 15 06:54:47 PM PDT 24
Peak memory 739380 kb
Host smart-98a2bebb-6a92-464c-b384-70871a9fc8be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889793571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.889793571
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3297759671
Short name T188
Test name
Test status
Simulation time 783897449 ps
CPU time 10.03 seconds
Started Jul 15 06:27:38 PM PDT 24
Finished Jul 15 06:27:49 PM PDT 24
Peak memory 200340 kb
Host smart-6159bb32-5035-4cab-8a8c-559522f7d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297759671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3297759671
Directory /workspace/9.hmac_wipe_secret/latest
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