Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18296265	1			T1	1536		T2	33435		T3	103157
all_values[1]	18296265	1			T1	1536		T2	33435		T3	103157
all_values[2]	18296265	1			T1	1536		T2	33435		T3	103157

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

275694

1

T3

2555

T6

54

T5

49

auto[1]

54613101

1

T1

4608

T2

100305

T3

306916

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46776349

1

T1

3705

T2

82031

T3

250845

auto[1]

8112446

1

T1

903

T2

18274

T3

58626

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	63279	1			T3	7		T6	10		T5	49
all_values[0]	auto[0]	auto[1]	381	1			T6	6		T24	5		T80	2
all_values[0]	auto[1]	auto[0]	18212976	1			T1	1522		T2	33427		T3	103041
all_values[0]	auto[1]	auto[1]	19629	1			T1	14		T2	8		T3	109
all_values[1]	auto[0]	auto[0]	103376	1			T3	2482		T6	8		T17	4
all_values[1]	auto[0]	auto[1]	215	1			T3	1		T6	7		T21	2
all_values[1]	auto[1]	auto[0]	18192355	1			T1	1531		T2	33435		T3	100670
all_values[1]	auto[1]	auto[1]	319	1			T1	5		T3	4		T6	8
all_values[2]	auto[0]	auto[0]	70395	1			T3	8		T6	9		T17	2
all_values[2]	auto[0]	auto[1]	38048	1			T3	57		T6	14		T17	2
all_values[2]	auto[1]	auto[0]	10133968	1			T1	652		T2	15169		T3	44637
all_values[2]	auto[1]	auto[1]	8053854	1			T1	884		T2	18266		T3	58455