Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128928

1

T1

674

T3

2822

T4

20

auto[1]

110708

1

T1

534

T2

24

T3

1008

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	87939	1			T1	567		T2	5		T3	1348
len_1026_2046	5884	1			T1	12		T3	84		T4	4
len_514_1022	3660	1			T1	9		T3	18		T21	3
len_2_510	4073	1			T1	7		T3	91		T21	3
len_2056	156	1			T24	2		T71	3		T120	1
len_2048	369	1			T1	3		T3	6		T4	3
len_2040	153	1			T3	3		T23	1		T24	1
len_1032	178	1			T3	1		T23	2		T24	3
len_1024	1731	1			T1	3		T3	7		T4	6
len_1016	533	1			T4	3		T23	1		T24	1
len_520	188	1			T4	1		T23	1		T71	7
len_512	275	1			T1	2		T3	3		T4	1
len_504	165	1			T3	3		T23	2		T71	2
len_8	1088	1			T2	7		T5	10		T17	16
len_0	13426	1			T1	1		T3	351		T4	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

102

1

T52

1

T55

1

T19

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	48896	1			T1	301		T3	1096		T6	27
auto[0]	len_1026_2046	2993	1			T1	12		T3	25		T4	2
auto[0]	len_514_1022	2328	1			T1	9		T3	13		T23	2
auto[0]	len_2_510	2581	1			T1	7		T3	15		T24	32
auto[0]	len_2056	71	1			T120	1		T41	2		T121	1
auto[0]	len_2048	210	1			T1	3		T3	5		T4	2
auto[0]	len_2040	68	1			T3	1		T24	1		T71	2
auto[0]	len_1032	102	1			T3	1		T23	1		T24	2
auto[0]	len_1024	245	1			T1	3		T3	2		T4	2
auto[0]	len_1016	463	1			T4	2		T23	1		T24	1
auto[0]	len_520	100	1			T23	1		T71	1		T122	1
auto[0]	len_512	168	1			T1	2		T3	3		T55	1
auto[0]	len_504	82	1			T3	1		T23	1		T71	2
auto[0]	len_8	28	1			T71	4		T123	2		T124	1
auto[0]	len_0	6129	1			T3	249		T4	2		T6	1
auto[1]	len_2050_plus	39043	1			T1	266		T2	5		T3	252
auto[1]	len_1026_2046	2891	1			T3	59		T4	2		T21	3
auto[1]	len_514_1022	1332	1			T3	5		T21	3		T24	4
auto[1]	len_2_510	1492	1			T3	76		T21	3		T25	13
auto[1]	len_2056	85	1			T24	2		T71	3		T41	1
auto[1]	len_2048	159	1			T3	1		T4	1		T5	1
auto[1]	len_2040	85	1			T3	2		T23	1		T125	5
auto[1]	len_1032	76	1			T23	1		T24	1		T125	1
auto[1]	len_1024	1486	1			T3	5		T4	4		T17	1
auto[1]	len_1016	70	1			T4	1		T71	1		T41	2
auto[1]	len_520	88	1			T4	1		T71	6		T125	1
auto[1]	len_512	107	1			T4	1		T24	1		T25	1
auto[1]	len_504	83	1			T3	2		T23	1		T126	1
auto[1]	len_8	1060	1			T2	7		T5	10		T17	16
auto[1]	len_0	7297	1			T1	1		T3	102		T6	5

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

57

1

T52

1

T19

1

T127

2

auto[1]

len_upper

45

1

T55

1

T128

1

T129

1