Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4619185

1

T1

2424

T2

9807

T3

17875

auto[1]

2906604

1

T1

2154

T2

6771

T3

22564

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2926343

1

T1

3582

T2

9690

T3

24703

auto[1]

4599446

1

T1

996

T2

6888

T3

15736

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3364311

1

T1

3486

T3

24029

T4

196

auto[1]

4161478

1

T1

1092

T2

16578

T3

16410

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4660181

1

T1

1420

T2

13750

T3

17360

auto[1]

2865608

1

T1

3158

T2

2828

T3

23079

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6826240	1			T1	2027		T2	15542		T3	39930
fifo_depth[1]	116796	1			T1	4		T2	145		T3	288
fifo_depth[2]	86773	1			T1	37		T2	161		T3	122
fifo_depth[3]	67813	1			T1	8		T2	148		T3	39
fifo_depth[4]	62855	1			T1	35		T2	135		T3	29
fifo_depth[5]	50299	1			T1	24		T2	143		T3	17
fifo_depth[6]	40385	1			T1	35		T2	126		T3	7
fifo_depth[7]	26709	1			T1	17		T2	81		T3	4

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

699549

1

T1

2551

T2

1036

T3

509

auto[1]

6826240

1

T1

2027

T2

15542

T3

39930

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7515427

1

T1

3838

T2

16578

T3

40439

auto[1]

10362

1

T1

740

T24

97

T25

508

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

33954

1

T1

453

T3

57

T4

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

32649

1

T3

16

T6

148

T21

820

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

33705

1

T1

339

T3

16

T6

205

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

48255

1

T1

1245

T3

29

T21

77

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

122578

1

T1

357

T3

86

T21

548

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

35490

1

T3

46

T6

19

T21

821

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41555

1

T3

31

T6

116

T21

597

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24516

1

T1

157

T3

59

T6

238

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38482

1

T2

765

T3

52

T5

1170

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

38753

1

T3

1

T4

2

T17

865

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45288

1

T3

23

T5

756

T17

842

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32880

1

T2

108

T3

33

T17

685

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45062

1

T3

2

T4

1

T17

24

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

39984

1

T2

150

T3

31

T4

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39794

1

T2

13

T3

21

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46604

1

T3

6

T5

981

T18

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

191081

1

T1

130

T3

2299

T4

39

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

187593

1

T1

353

T3

3474

T6

493

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

188432

1

T1

102

T3

2456

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

177475

1

T1

12

T3

6860

T4

23

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1727343

1

T1

39

T3

2368

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

166006

1

T3

478

T4

74

T6

491

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

164480

1

T3

3793

T4

57

T6

502

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

189199

1

T1

299

T3

1961

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

480891

1

T2

3773

T3

1744

T6

43

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

483223

1

T1

948

T2

1711

T3

3797

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

459436

1

T2

2968

T3

1690

T4

45

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

454246

1

T2

365

T3

2156

T4

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

563174

1

T2

2914

T3

989

T4

29

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

432922

1

T1

144

T2

494

T3

2435

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

484926

1

T2

3317

T3

1733

T4

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

475813

1

T3

1697

T4

57

T6

240

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

224353

1

T1

583

T3

2356

T4

40

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

219700

1

T1

353

T3

3490

T6

641

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

221513

1

T1

439

T3

2472

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

223673

1

T1

519

T3

6889

T4

23

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1848929

1

T1

396

T3

2454

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

200418

1

T3

524

T4

74

T6

510

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

205086

1

T3

3824

T4

57

T6

618

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

213477

1

T1

456

T3

2020

T4

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

519036

1

T2

4538

T3

1796

T6

43

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

521887

1

T1

948

T2

1711

T3

3798

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

504585

1

T2

2968

T3

1713

T4

45

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

486814

1

T2

473

T3

2189

T4

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

607640

1

T2

2914

T3

991

T4

30

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

472423

1

T1

144

T2

644

T3

2466

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

523983

1

T2

3330

T3

1754

T4

21

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

521910

1

T3

1703

T4

57

T6

240

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

682

1

T20

7

T133

7

T53

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

542

1

T53

1

T134

1

T135

88

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

624

1

T1

2

T24

79

T25

178

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2057

1

T1

738

T25

224

T38

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

992

1

T38

29

T53

8

T134

144

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1078

1

T20

5

T38

185

T133

27

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

949

1

T25

1

T20

24

T133

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

238

1

T25

7

T136

4

T137

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

337

1

T136

1

T138

188

T139

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

89

1

T25

4

T133

2

T140

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

139

1

T25

12

T20

31

T53

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

312

1

T25

79

T38

6

T53

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

596

1

T20

5

T38

42

T53

92

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

483

1

T53

33

T141

43

T12

224

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

737

1

T38

34

T133

105

T141

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

507

1

T24

18

T25

3

T20

16

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

191081

1

T1

130

T3

2299

T4

39

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

187593

1

T1

353

T3

3474

T6

493

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

188432

1

T1

102

T3

2456

T4

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

177475

1

T1

12

T3

6860

T4

23

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1727343

1

T1

39

T3

2368

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

166006

1

T3

478

T4

74

T6

491

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

164480

1

T3

3793

T4

57

T6

502

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

189199

1

T1

299

T3

1961

T4

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

480891

1

T2

3773

T3

1744

T6

43

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

483223

1

T1

948

T2

1711

T3

3797

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

459436

1

T2

2968

T3

1690

T4

45

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

454246

1

T2

365

T3

2156

T4

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

563174

1

T2

2914

T3

989

T4

29

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

432922

1

T1

144

T2

494

T3

2435

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

484926

1

T2

3317

T3

1733

T4

20

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

475813

1

T3

1697

T4

57

T6

240

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4467

1

T1

2

T3

34

T21

103

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3952

1

T3

7

T6

42

T21

129

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3495

1

T3

11

T6

42

T21

50

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3147

1

T3

14

T21

8

T24

73

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

39228

1

T3

65

T21

86

T27

8

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3051

1

T3

5

T6

7

T21

138

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3626

1

T3

15

T6

21

T21

112

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3256

1

T1

2

T3

27

T6

62

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6677

1

T2

108

T3

45

T5

196

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6378

1

T4

1

T17

132

T21

138

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7215

1

T3

16

T5

120

T17

139

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

4693

1

T2

13

T3

15

T17

95

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7879

1

T3

1

T4

1

T17

3

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6571

1

T2

23

T3

19

T4

2

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6596

1

T2

1

T3

13

T21

78

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6565

1

T3

1

T5

152

T18

4

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

3601

1

T1

2

T3

12

T4

1

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[1]

3277

1

T3

6

T6

33

T21

127

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[0]

2833

1

T3

4

T6

50

T21

38

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[1]

2622

1

T3

8

T21

17

T24

86

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[0]

23261

1

T1

7

T3

13

T21

82

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[1]

2317

1

T3

22

T6

2

T21

156

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[0]

3135

1

T3

13

T6

19

T21

113

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[1]

2565

1

T1

28

T3

14

T6

51

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[0]

5474

1

T2

123

T3

5

T5

174

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[1]

5239

1

T3

1

T17

111

T21

116

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[0]

6341

1

T3

5

T5

118

T17

145

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[1]

3880

1

T2

11

T3

5

T17

102

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[0]

6211

1

T3

1

T17

2

T18

2

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[1]

5236

1

T2

25

T3

5

T5

33

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

5213

1

T2

2

T3

7

T4

1

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[1]

5568

1

T3

1

T5

140

T21

27

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[0]

2718

1

T1

2

T3

6

T21

104

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[1]

2525

1

T6

38

T21

133

T24

173

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[0]

1968

1

T3

1

T6

44

T21

41

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[1]

1960

1

T1

1

T3

1

T21

11

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[0]

15764

1

T3

3

T21

88

T24

48

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[1]

1807

1

T3

5

T6

7

T21

145

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[0]

2150

1

T6

21

T21

107

T24

67

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[1]

1821

1

T1

5

T3

9

T6

55

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

4894

1

T2

105

T3

2

T5

214

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

4495

1

T4

1

T17

133

T21

107

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[0]

5407

1

T3

1

T5

107

T17

133

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

3398

1

T2

15

T3

5

T17

94

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

5080

1

T17

5

T21

52

T24

73

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

4570

1

T2

27

T3

3

T5

40

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

4511

1

T2

1

T3

1

T21

71

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

4745

1

T3

2

T5

148

T21

20

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

2721

1

T1

1

T3

1

T21

89

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

2588

1

T6

27

T21

125

T24

119

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

2054

1

T6

29

T21

39

T24

85

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2167

1

T1

1

T3

3

T21

11

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

11593

1

T1

2

T3

2

T21

78

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

1720

1

T3

11

T6

3

T21

118

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[0]

2590

1

T3

2

T6

15

T21

91

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

1817

1

T1

31

T3

5

T6

43

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

4768

1

T2

102

T5

170

T17

167

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

4346

1

T17

133

T21

105

T24

1

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

5194

1

T3

1

T5

106

T17

127

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

3229

1

T2

13

T3

2

T17

103

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

4938

1

T17

4

T21

55

T24

71

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

4191

1

T2

17

T3

2

T5

27

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4360

1

T2

3

T21

72

T24

116

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

4579

1

T5

157

T21

30

T23

1

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

2106

1

T1

2

T3

2

T21

72

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

2113

1

T3

3

T6

5

T21

119

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1528

1

T1

9

T6

14

T21

37

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1626

1

T1

3

T3

2

T21

15

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

8021

1

T1

5

T3

2

T21

72

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[1]

1507

1

T3

1

T21

112

T24

31

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[0]

1687

1

T6

13

T21

91

T24

62

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[1]

1319

1

T1

5

T3

2

T6

17

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[0]

4088

1

T2

108

T5

152

T17

131

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[1]

3760

1

T17

115

T21

94

T24

2

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[0]

4505

1

T5

104

T17

129

T21

47

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[1]

2841

1

T2

12

T3

2

T17

97

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3885

1

T17

1

T21

35

T24

67

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

3590

1

T2

22

T3

2

T5

25

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[0]

3778

1

T2

1

T21

59

T24

72

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[1]

3945

1

T3

1

T5

119

T21

24

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1645

1

T1

2

T3

1

T21

41

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

1749

1

T6

3

T21

83

T24

56

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1350

1

T1

2

T6

10

T21

21

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1458

1

T21

4

T24

51

T28

15

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

5670

1

T1

5

T3

1

T21

60

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1171

1

T3

1

T21

70

T24

11

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[0]

1679

1

T6

12

T21

39

T24

50

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[1]

1185

1

T1

26

T3

2

T6

9

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

3274

1

T2

91

T5

124

T17

76

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2991

1

T17

101

T21

64

T25

24

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

3582

1

T5

81

T17

89

T21

45

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

2386

1

T2

19

T3

2

T17

68

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

3242

1

T17

3

T21

32

T24

65

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

2837

1

T2

14

T5

25

T21

54

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

3058

1

T2

2

T21

38

T24

64

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

3108

1

T5

122

T21

19

T23

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

1036

1

T1

2

T3

1

T21

23

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

1321

1

T21

50

T24

20

T25

3

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

839

1

T1

10

T6

6

T21

17

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

1086

1

T1

1

T21

4

T24

37

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

3424

1

T1

2

T21

37

T24

25

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

854

1

T21

45

T24

7

T69

4

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

1008

1

T6

9

T21

26

T24

19

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

687

1

T1

2

T6

1

T21

45

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

2223

1

T2

58

T5

69

T17

61

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

2097

1

T17

71

T21

25

T25

8

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

2401

1

T5

63

T17

49

T21

24

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

1646

1

T2

12

T3

2

T17

64

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

2085

1

T17

3

T21

15

T24

35

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

1951

1

T2

10

T5

13

T21

40

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

1949

1

T2

1

T21

26

T24

29

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

2102

1

T3

1

T5

73

T21

11