Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18296265	1			T1	1536		T2	33435		T3	103157
all_pins[1]	18296265	1			T1	1536		T2	33435		T3	103157
all_pins[2]	18296265	1			T1	1536		T2	33435		T3	103157

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46814110	1			T1	3704		T2	82030		T3	250901
values[0x1]	8074685	1			T1	904		T2	18275		T3	58570
transitions[0x0=>0x1]	8074499	1			T1	904		T2	18275		T3	58567
transitions[0x1=>0x0]	8074514	1			T1	904		T2	18275		T3	58567

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18275783	1			T1	1521		T2	33426		T3	103046
all_pins[0]	values[0x1]	20482	1			T1	15		T2	9		T3	111
all_pins[0]	transitions[0x0=>0x1]	20396	1			T1	15		T2	9		T3	110
all_pins[0]	transitions[0x1=>0x0]	8053783	1			T1	884		T2	18266		T3	58454
all_pins[1]	values[0x0]	18295916	1			T1	1531		T2	33435		T3	103153
all_pins[1]	values[0x1]	349	1			T1	5		T3	4		T6	8
all_pins[1]	transitions[0x0=>0x1]	300	1			T1	5		T3	2		T6	7
all_pins[1]	transitions[0x1=>0x0]	20433	1			T1	15		T2	9		T3	109
all_pins[2]	values[0x0]	10242411	1			T1	652		T2	15169		T3	44702
all_pins[2]	values[0x1]	8053854	1			T1	884		T2	18266		T3	58455
all_pins[2]	transitions[0x0=>0x1]	8053803	1			T1	884		T2	18266		T3	58455
all_pins[2]	transitions[0x1=>0x0]	298	1			T1	5		T3	4		T6	7