Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1006 1 T3 14 T6 31 T21 11
all_values[1] 1006 1 T3 14 T6 31 T21 11
all_values[2] 1006 1 T3 14 T6 31 T21 11


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1585 1 T3 21 T6 46 T21 14
auto[1] 1433 1 T3 21 T6 47 T21 19


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1058 1 T3 19 T6 22 T21 19
auto[1] 1960 1 T3 23 T6 71 T21 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1735 1 T3 24 T6 48 T21 22
auto[1] 1283 1 T3 18 T6 45 T21 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 196 1 T3 3 T6 5 T21 3
all_values[0] auto[0] auto[0] auto[1] 113 1 T6 3 T24 2 T74 5
all_values[0] auto[0] auto[1] auto[0] 167 1 T3 3 T6 6 T21 5
all_values[0] auto[0] auto[1] auto[1] 99 1 T3 1 T6 3 T24 4
all_values[0] auto[1] auto[0] auto[1] 217 1 T3 4 T6 5 T24 5
all_values[0] auto[1] auto[1] auto[1] 214 1 T3 3 T6 9 T21 3
all_values[1] auto[0] auto[0] auto[0] 177 1 T3 1 T6 3 T21 1
all_values[1] auto[0] auto[0] auto[1] 120 1 T3 2 T6 4 T21 2
all_values[1] auto[0] auto[1] auto[0] 159 1 T3 4 T6 3 T21 3
all_values[1] auto[0] auto[1] auto[1] 123 1 T3 2 T6 6 T21 1
all_values[1] auto[1] auto[0] auto[1] 234 1 T3 4 T6 5 T21 2
all_values[1] auto[1] auto[1] auto[1] 193 1 T3 1 T6 10 T21 2
all_values[2] auto[0] auto[0] auto[0] 180 1 T3 6 T6 3 T21 5
all_values[2] auto[0] auto[0] auto[1] 128 1 T6 8 T7 1 T74 2
all_values[2] auto[0] auto[1] auto[0] 179 1 T3 2 T6 2 T21 2
all_values[2] auto[0] auto[1] auto[1] 94 1 T6 2 T24 3 T71 1
all_values[2] auto[1] auto[0] auto[1] 220 1 T3 1 T6 10 T21 1
all_values[2] auto[1] auto[1] auto[1] 205 1 T3 5 T6 6 T21 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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