Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4193	1			T1	3		T2	2		T3	42
sha2_none	4240	1			T1	2		T2	4		T3	45
sha2_512	7597	1			T2	8		T3	37		T4	5
sha2_384	7322	1			T1	6		T2	1		T3	42
sha2_256	6269	1			T1	4		T3	48		T4	6

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18783

1

T1

9

T2

9

T3

117

auto[1]

11245

1

T1

7

T2

7

T3

99

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11243

1

T1

11

T2

9

T3

114

auto[1]

18785

1

T1

5

T2

7

T3

102

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15571

1

T1

4

T2

16

T3

100

disabled

14457

1

T1

12

T3

116

T4

10

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4570	1			T1	4		T2	3		T3	51
key_none	7724	1			T1	1		T2	1		T3	28
key_1024	4346	1			T1	2		T2	4		T3	26
key_512	3824	1			T1	3		T3	36		T4	6
key_384	3421	1			T1	1		T2	2		T3	22
key_256	3130	1			T1	1		T2	3		T3	26
key_128	2932	1			T1	4		T2	2		T3	27

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18935

1

T1

9

T2

9

T3

100

auto[1]

11093

1

T1

7

T2

7

T3

116

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29835

1

T1

16

T2

16

T3

213

disabled

193

1

T3

3

T6

3

T18

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1654

1

T2

2

T3

13

T6

2

enabled

auto[0]

auto[0]

auto[1]

1605

1

T1

2

T2

3

T3

15

enabled

auto[0]

auto[1]

auto[0]

1577

1

T1

1

T2

2

T3

14

enabled

auto[0]

auto[1]

auto[1]

1531

1

T2

2

T3

10

T4

1

enabled

auto[1]

auto[0]

auto[0]

4374

1

T2

2

T3

8

T4

2

enabled

auto[1]

auto[0]

auto[1]

1535

1

T1

1

T2

2

T3

19

enabled

auto[1]

auto[1]

auto[0]

1731

1

T2

3

T3

10

T4

2

enabled

auto[1]

auto[1]

auto[1]

1564

1

T3

11

T4

4

T6

2

disabled

auto[0]

auto[0]

auto[0]

1245

1

T1

2

T3

17

T4

1

disabled

auto[0]

auto[0]

auto[1]

1195

1

T1

1

T3

17

T6

3

disabled

auto[0]

auto[1]

auto[0]

1191

1

T1

3

T3

11

T4

1

disabled

auto[0]

auto[1]

auto[1]

1245

1

T1

2

T3

17

T4

3

disabled

auto[1]

auto[0]

auto[0]

5951

1

T1

3

T3

12

T18

3

disabled

auto[1]

auto[0]

auto[1]

1224

1

T3

16

T4

2

T6

2

disabled

auto[1]

auto[1]

auto[0]

1212

1

T3

15

T4

2

T6

5

disabled

auto[1]

auto[1]

auto[1]

1194

1

T1

1

T3

11

T4

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15489

1

T1

4

T2

16

T3

98

enabled

disabled

82

1

T3

2

T6

1

T18

1

disabled

disabled

111

1

T3

1

T6

2

T71

6

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14346

1

T1

12

T3

115

T4

10

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1070	1			T1	2		T2	1		T3	11
key_invalid	sha2_none	870	1			T3	8		T5	2		T17	1
key_invalid	sha2_512	809	1			T2	2		T3	11		T6	2
key_invalid	sha2_384	850	1			T1	1		T3	9		T4	1
key_invalid	sha2_256	859	1			T1	1		T3	12		T4	3
key_none	sha2_invalid	526	1			T1	1		T3	6		T5	2
key_none	sha2_none	547	1			T3	3		T4	1		T5	1
key_none	sha2_512	2531	1			T2	1		T3	4		T4	2
key_none	sha2_384	2508	1			T3	7		T4	2		T6	1
key_none	sha2_256	1567	1			T3	8		T4	1		T6	2
key_1024	sha2_invalid	496	1			T3	8		T6	3		T5	1
key_1024	sha2_none	527	1			T1	1		T2	1		T3	3
key_1024	sha2_512	1761	1			T2	1		T3	3		T6	1
key_1024	sha2_384	922	1			T1	1		T2	1		T3	5
key_512	sha2_invalid	508	1			T3	4		T6	1		T5	2
key_512	sha2_none	544	1			T1	1		T3	7		T4	1
key_512	sha2_512	642	1			T3	11		T4	1		T6	1
key_512	sha2_384	1236	1			T1	2		T3	9		T4	2
key_512	sha2_256	845	1			T3	5		T4	2		T6	3
key_384	sha2_invalid	516	1			T2	1		T3	3		T6	1
key_384	sha2_none	571	1			T3	8		T4	1		T21	11
key_384	sha2_512	654	1			T2	1		T3	3		T5	1
key_384	sha2_384	570	1			T3	3		T4	1		T6	1
key_384	sha2_256	1051	1			T1	1		T3	4		T6	1
key_256	sha2_invalid	543	1			T3	7		T4	1		T6	1
key_256	sha2_none	598	1			T2	2		T3	5		T6	2
key_256	sha2_512	602	1			T2	1		T3	2		T6	1
key_256	sha2_384	613	1			T3	3		T17	6		T21	6
key_256	sha2_256	727	1			T3	9		T6	1		T17	3
key_128	sha2_invalid	516	1			T3	3		T17	1		T21	6
key_128	sha2_none	569	1			T3	11		T21	7		T27	2
key_128	sha2_512	587	1			T2	2		T3	3		T4	1
key_128	sha2_384	601	1			T1	2		T3	6		T6	1
key_128	sha2_256	606	1			T1	2		T3	4		T6	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

599

1

T3

6

T5

2

T21

6

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1070	1			T1	2		T2	1		T3	11
key_invalid	sha2_none	870	1			T3	8		T5	2		T17	1
key_invalid	sha2_512	809	1			T2	2		T3	11		T6	2
key_invalid	sha2_384	850	1			T1	1		T3	9		T4	1
key_invalid	sha2_256	859	1			T1	1		T3	12		T4	3
key_none	sha2_invalid	526	1			T1	1		T3	6		T5	2
key_none	sha2_none	547	1			T3	3		T4	1		T5	1
key_none	sha2_512	2531	1			T2	1		T3	4		T4	2
key_none	sha2_384	2508	1			T3	7		T4	2		T6	1
key_none	sha2_256	1567	1			T3	8		T4	1		T6	2
key_1024	sha2_invalid	496	1			T3	8		T6	3		T5	1
key_1024	sha2_none	527	1			T1	1		T2	1		T3	3
key_1024	sha2_512	1761	1			T2	1		T3	3		T6	1
key_1024	sha2_384	922	1			T1	1		T2	1		T3	5
key_1024	sha2_256	599	1			T3	6		T5	2		T21	6
key_512	sha2_invalid	508	1			T3	4		T6	1		T5	2
key_512	sha2_none	544	1			T1	1		T3	7		T4	1
key_512	sha2_512	642	1			T3	11		T4	1		T6	1
key_512	sha2_384	1236	1			T1	2		T3	9		T4	2
key_512	sha2_256	845	1			T3	5		T4	2		T6	3
key_384	sha2_invalid	516	1			T2	1		T3	3		T6	1
key_384	sha2_none	571	1			T3	8		T4	1		T21	11
key_384	sha2_512	654	1			T2	1		T3	3		T5	1
key_384	sha2_384	570	1			T3	3		T4	1		T6	1
key_384	sha2_256	1051	1			T1	1		T3	4		T6	1
key_256	sha2_invalid	543	1			T3	7		T4	1		T6	1
key_256	sha2_none	598	1			T2	2		T3	5		T6	2
key_256	sha2_512	602	1			T2	1		T3	2		T6	1
key_256	sha2_384	613	1			T3	3		T17	6		T21	6
key_256	sha2_256	727	1			T3	9		T6	1		T17	3
key_128	sha2_invalid	516	1			T3	3		T17	1		T21	6
key_128	sha2_none	569	1			T3	11		T21	7		T27	2
key_128	sha2_512	587	1			T2	2		T3	3		T4	1
key_128	sha2_384	601	1			T1	2		T3	6		T6	1
key_128	sha2_256	606	1			T1	2		T3	4		T6	2