Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 659
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T89 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.930338481 Jul 16 06:56:48 PM PDT 24 Jul 16 06:56:51 PM PDT 24 26615645 ps
T530 /workspace/coverage/cover_reg_top/44.hmac_intr_test.207609835 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 14331382 ps
T531 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1754873451 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:29 PM PDT 24 51481756 ps
T532 /workspace/coverage/cover_reg_top/24.hmac_intr_test.4118095191 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 23101075 ps
T106 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2214650948 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:11 PM PDT 24 71634474 ps
T533 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3528017897 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 34354405 ps
T534 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2200555150 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:30 PM PDT 24 91797438 ps
T535 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2773946824 Jul 16 06:56:36 PM PDT 24 Jul 16 06:56:38 PM PDT 24 16672712 ps
T536 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1860093203 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:31 PM PDT 24 46677315 ps
T537 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1136766676 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:29 PM PDT 24 29643607 ps
T538 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2519021422 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:09 PM PDT 24 103895275 ps
T539 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3851490621 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:10 PM PDT 24 260627394 ps
T60 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3584265506 Jul 16 06:56:17 PM PDT 24 Jul 16 06:56:23 PM PDT 24 210072468 ps
T540 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.362478931 Jul 16 06:56:05 PM PDT 24 Jul 16 06:56:08 PM PDT 24 56018936 ps
T107 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.969007244 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:10 PM PDT 24 127021425 ps
T541 /workspace/coverage/cover_reg_top/5.hmac_intr_test.86419877 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:05 PM PDT 24 12860600 ps
T542 /workspace/coverage/cover_reg_top/33.hmac_intr_test.971622921 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:30 PM PDT 24 23739172 ps
T543 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2834460124 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:13 PM PDT 24 482510041 ps
T108 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3834338893 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:22 PM PDT 24 321247787 ps
T544 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1701026371 Jul 16 06:56:15 PM PDT 24 Jul 16 07:13:06 PM PDT 24 102988537902 ps
T545 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3726567635 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:24 PM PDT 24 58271644 ps
T90 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3530593802 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:12 PM PDT 24 19423364 ps
T61 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.561927766 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:13 PM PDT 24 695109116 ps
T546 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4293246509 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:18 PM PDT 24 101401770 ps
T547 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1631751443 Jul 16 06:56:01 PM PDT 24 Jul 16 06:56:04 PM PDT 24 78726263 ps
T548 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1661395312 Jul 16 06:56:16 PM PDT 24 Jul 16 06:56:19 PM PDT 24 134714213 ps
T549 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4228135 Jul 16 06:56:22 PM PDT 24 Jul 16 06:56:27 PM PDT 24 15536340 ps
T550 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3365294666 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:32 PM PDT 24 898535519 ps
T551 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4208237565 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:13 PM PDT 24 114615464 ps
T552 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1100133735 Jul 16 06:56:20 PM PDT 24 Jul 16 06:56:26 PM PDT 24 315956112 ps
T553 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2390476051 Jul 16 06:56:05 PM PDT 24 Jul 16 06:56:10 PM PDT 24 192716963 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3696308459 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:07 PM PDT 24 281247339 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1455303513 Jul 16 06:56:09 PM PDT 24 Jul 16 06:56:12 PM PDT 24 27227657 ps
T62 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2454800842 Jul 16 06:56:13 PM PDT 24 Jul 16 06:56:15 PM PDT 24 192459498 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1969227164 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:12 PM PDT 24 20222766 ps
T554 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3760817121 Jul 16 06:56:17 PM PDT 24 Jul 16 06:56:21 PM PDT 24 251179354 ps
T555 /workspace/coverage/cover_reg_top/7.hmac_intr_test.570366769 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:09 PM PDT 24 33593193 ps
T556 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3509564271 Jul 16 06:56:03 PM PDT 24 Jul 16 06:57:37 PM PDT 24 35719252141 ps
T557 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1870328409 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:10 PM PDT 24 25352123 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3523688360 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:11 PM PDT 24 410808244 ps
T558 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1927588342 Jul 16 06:56:16 PM PDT 24 Jul 16 06:56:19 PM PDT 24 106327095 ps
T112 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2812726942 Jul 16 06:56:20 PM PDT 24 Jul 16 06:56:26 PM PDT 24 456905793 ps
T559 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3433336609 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 19152131 ps
T560 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.836918818 Jul 16 06:55:57 PM PDT 24 Jul 16 06:56:04 PM PDT 24 706206861 ps
T561 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1453750367 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:13 PM PDT 24 163627107 ps
T562 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2297268901 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:06 PM PDT 24 68559618 ps
T563 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4255680010 Jul 16 06:56:14 PM PDT 24 Jul 16 06:56:16 PM PDT 24 34561346 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_intr_test.912085289 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:10 PM PDT 24 47940858 ps
T565 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1039179173 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:29 PM PDT 24 128074370 ps
T566 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4172542960 Jul 16 06:56:25 PM PDT 24 Jul 16 06:56:30 PM PDT 24 14039766 ps
T567 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1702123418 Jul 16 06:56:05 PM PDT 24 Jul 16 06:56:10 PM PDT 24 1629079531 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4151391232 Jul 16 06:56:10 PM PDT 24 Jul 16 06:56:21 PM PDT 24 446968985 ps
T113 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.526682393 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:30 PM PDT 24 1242994639 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2928801467 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:07 PM PDT 24 25787434 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2462050816 Jul 16 06:56:05 PM PDT 24 Jul 16 06:56:08 PM PDT 24 12377412 ps
T116 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2029324001 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:09 PM PDT 24 254550511 ps
T568 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3258002161 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:26 PM PDT 24 1083091680 ps
T569 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3250344094 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:09 PM PDT 24 33870597 ps
T570 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2593073041 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:16 PM PDT 24 42137867 ps
T571 /workspace/coverage/cover_reg_top/37.hmac_intr_test.4283315438 Jul 16 06:56:16 PM PDT 24 Jul 16 06:56:19 PM PDT 24 17374096 ps
T572 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1220634087 Jul 16 06:56:25 PM PDT 24 Jul 16 06:56:30 PM PDT 24 12406823 ps
T573 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4017271726 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:31 PM PDT 24 179836563 ps
T574 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.132191523 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:18 PM PDT 24 273830317 ps
T575 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2017686414 Jul 16 06:56:01 PM PDT 24 Jul 16 06:56:02 PM PDT 24 20958915 ps
T576 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2916065079 Jul 16 06:56:25 PM PDT 24 Jul 16 06:56:30 PM PDT 24 142505488 ps
T577 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2499380696 Jul 16 06:56:14 PM PDT 24 Jul 16 06:56:17 PM PDT 24 51121263 ps
T578 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1981338946 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:17 PM PDT 24 25633831 ps
T579 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2557406982 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:29 PM PDT 24 33915871 ps
T580 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.395299970 Jul 16 06:56:16 PM PDT 24 Jul 16 06:56:18 PM PDT 24 102712093 ps
T581 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1030903111 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:12 PM PDT 24 197167453 ps
T582 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.933187863 Jul 16 06:56:05 PM PDT 24 Jul 16 06:56:08 PM PDT 24 239329072 ps
T583 /workspace/coverage/cover_reg_top/11.hmac_intr_test.599689554 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:06 PM PDT 24 26878884 ps
T584 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3810273575 Jul 16 06:56:09 PM PDT 24 Jul 16 06:56:13 PM PDT 24 26342596 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_intr_test.347949847 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:07 PM PDT 24 29081323 ps
T99 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.180089116 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:28 PM PDT 24 22803279 ps
T586 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3565103265 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:24 PM PDT 24 128673866 ps
T587 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2735774570 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:27 PM PDT 24 36415215 ps
T588 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2615026739 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:29 PM PDT 24 21273753 ps
T589 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2302399119 Jul 16 06:56:02 PM PDT 24 Jul 16 06:56:06 PM PDT 24 47170047 ps
T590 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3072254778 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:12 PM PDT 24 869306886 ps
T591 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2658754075 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:17 PM PDT 24 48410900 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1815619158 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:16 PM PDT 24 711326714 ps
T592 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1280247524 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:12 PM PDT 24 54065302 ps
T593 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1937765647 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:05 PM PDT 24 52853303 ps
T594 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.918107449 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:12 PM PDT 24 434071722 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4183456754 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:27 PM PDT 24 10466019691 ps
T595 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1204140242 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:31 PM PDT 24 131340223 ps
T596 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1856135070 Jul 16 06:56:02 PM PDT 24 Jul 16 06:56:04 PM PDT 24 158791157 ps
T101 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3085915172 Jul 16 06:56:10 PM PDT 24 Jul 16 06:56:13 PM PDT 24 38889471 ps
T597 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1968905077 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 24624632 ps
T598 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2581456616 Jul 16 06:56:01 PM PDT 24 Jul 16 06:56:05 PM PDT 24 59436537 ps
T599 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1755062362 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:09 PM PDT 24 138291451 ps
T600 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2546068160 Jul 16 06:56:05 PM PDT 24 Jul 16 06:56:10 PM PDT 24 47405658 ps
T601 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3506984609 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:14 PM PDT 24 211107329 ps
T602 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.97334313 Jul 16 06:56:09 PM PDT 24 Jul 16 06:56:13 PM PDT 24 21799709 ps
T603 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3339407584 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:19 PM PDT 24 1401160822 ps
T604 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2560225654 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:31 PM PDT 24 536009855 ps
T118 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3707153632 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:14 PM PDT 24 1086792486 ps
T119 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4181899346 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:10 PM PDT 24 870419421 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3074878342 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:07 PM PDT 24 16737462 ps
T102 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2190417845 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:06 PM PDT 24 20252368 ps
T606 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2875316548 Jul 16 06:56:17 PM PDT 24 Jul 16 06:56:21 PM PDT 24 96452448 ps
T607 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1682872160 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:22 PM PDT 24 92049492 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4023008696 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:10 PM PDT 24 192408116 ps
T609 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1352534838 Jul 16 06:56:20 PM PDT 24 Jul 16 06:56:24 PM PDT 24 11125098 ps
T610 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1235933351 Jul 16 06:56:21 PM PDT 24 Jul 16 06:56:25 PM PDT 24 25362614 ps
T611 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.9439209 Jul 16 06:56:17 PM PDT 24 Jul 16 06:56:21 PM PDT 24 76561950 ps
T612 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2019342115 Jul 16 06:56:16 PM PDT 24 Jul 16 06:56:19 PM PDT 24 33309547 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1243713579 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:07 PM PDT 24 12786541 ps
T614 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1826809151 Jul 16 06:56:17 PM PDT 24 Jul 16 06:56:22 PM PDT 24 149992929 ps
T615 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3032997823 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:12 PM PDT 24 260340418 ps
T117 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.561990234 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:13 PM PDT 24 449025436 ps
T616 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3555523658 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:23 PM PDT 24 64868180 ps
T617 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.250098090 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:30 PM PDT 24 458131121 ps
T103 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1075857734 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:06 PM PDT 24 27372781 ps
T618 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4174527393 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:13 PM PDT 24 943409335 ps
T619 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2124349788 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:28 PM PDT 24 1579586556 ps
T620 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2489074548 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:28 PM PDT 24 60785324 ps
T621 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3123002634 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:23 PM PDT 24 77805662 ps
T622 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2180842733 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:18 PM PDT 24 61684909 ps
T623 /workspace/coverage/cover_reg_top/29.hmac_intr_test.490831059 Jul 16 06:56:21 PM PDT 24 Jul 16 06:56:25 PM PDT 24 16519311 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2738815039 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:22 PM PDT 24 110269540 ps
T625 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4047383664 Jul 16 06:56:22 PM PDT 24 Jul 16 06:56:28 PM PDT 24 115502238 ps
T626 /workspace/coverage/cover_reg_top/25.hmac_intr_test.353563122 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:29 PM PDT 24 32927068 ps
T627 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3808036139 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:14 PM PDT 24 279925200 ps
T628 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3620998295 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:07 PM PDT 24 159877740 ps
T629 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3975972679 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:24 PM PDT 24 151362790 ps
T630 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3541726374 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:06 PM PDT 24 49113076 ps
T631 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2142247818 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:30 PM PDT 24 300436492 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.298576362 Jul 16 06:56:03 PM PDT 24 Jul 16 06:56:08 PM PDT 24 1461806619 ps
T633 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3020324180 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 30274357 ps
T634 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3630927651 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:15 PM PDT 24 115640429 ps
T635 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2441632847 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 13628406 ps
T636 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2337920692 Jul 16 06:56:18 PM PDT 24 Jul 16 06:56:21 PM PDT 24 32765474 ps
T114 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3029819241 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:13 PM PDT 24 2726199793 ps
T637 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4097058397 Jul 16 06:56:06 PM PDT 24 Jul 16 06:56:09 PM PDT 24 12965652 ps
T638 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2760972466 Jul 16 06:56:08 PM PDT 24 Jul 16 06:56:14 PM PDT 24 107334269 ps
T639 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1585718151 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:07 PM PDT 24 214026888 ps
T640 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2064505710 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:10 PM PDT 24 24260586 ps
T641 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1334577165 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:10 PM PDT 24 60572600 ps
T642 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3395504896 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:25 PM PDT 24 54742956 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3287211443 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:11 PM PDT 24 35877904 ps
T644 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3220889044 Jul 16 06:56:01 PM PDT 24 Jul 16 06:56:04 PM PDT 24 380989132 ps
T645 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3819944294 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:33 PM PDT 24 64860647 ps
T646 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3629286039 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:23 PM PDT 24 12651967 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.593232504 Jul 16 06:56:04 PM PDT 24 Jul 16 06:56:07 PM PDT 24 14353441 ps
T648 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2013771230 Jul 16 06:56:24 PM PDT 24 Jul 16 06:56:32 PM PDT 24 132606474 ps
T649 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2392118405 Jul 16 06:56:11 PM PDT 24 Jul 16 06:56:19 PM PDT 24 393298378 ps
T650 /workspace/coverage/cover_reg_top/48.hmac_intr_test.236013418 Jul 16 06:56:21 PM PDT 24 Jul 16 06:56:25 PM PDT 24 95479182 ps
T651 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2723149673 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:16 PM PDT 24 17082545 ps
T652 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2585006829 Jul 16 06:56:19 PM PDT 24 Jul 16 06:56:22 PM PDT 24 66113902 ps
T115 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1738422582 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:13 PM PDT 24 326140956 ps
T653 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3210310144 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:14 PM PDT 24 573292649 ps
T654 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3387027656 Jul 16 06:56:07 PM PDT 24 Jul 16 06:56:18 PM PDT 24 1276693461 ps
T655 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.12571230 Jul 16 06:56:06 PM PDT 24 Jul 16 07:06:40 PM PDT 24 222409353240 ps
T656 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3079145563 Jul 16 06:56:17 PM PDT 24 Jul 16 06:56:21 PM PDT 24 46958025 ps
T657 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2348737789 Jul 16 06:56:15 PM PDT 24 Jul 16 06:56:17 PM PDT 24 29039450 ps
T658 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1273830470 Jul 16 06:56:23 PM PDT 24 Jul 16 06:56:28 PM PDT 24 11280267 ps
T659 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1734068096 Jul 16 06:56:16 PM PDT 24 Jul 16 06:56:18 PM PDT 24 11209272 ps

Test location /workspace/coverage/default/37.hmac_stress_all.1555159059
Short name T3
Test name
Test status
Simulation time 43200190571 ps
CPU time 587.44 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 07:07:12 PM PDT 24
Peak memory 200280 kb
Host smart-af619ba9-c3e2-4770-8778-e3c4b9093c78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555159059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1555159059
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.635181127
Short name T5
Test name
Test status
Simulation time 13061192014 ps
CPU time 629.26 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 07:07:35 PM PDT 24
Peak memory 706852 kb
Host smart-90de0eb4-590b-47a1-a84f-0bc5c036d03a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=635181127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.635181127
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3488978751
Short name T7
Test name
Test status
Simulation time 195574316053 ps
CPU time 183.6 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 07:00:06 PM PDT 24
Peak memory 208692 kb
Host smart-81bd58e0-01e5-427a-94aa-4366d90aa83c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488978751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3488978751
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2817313909
Short name T24
Test name
Test status
Simulation time 13213699227 ps
CPU time 766.76 seconds
Started Jul 16 06:56:59 PM PDT 24
Finished Jul 16 07:09:47 PM PDT 24
Peak memory 580032 kb
Host smart-9b70dbe6-8be7-47e3-abf5-1021c4f33cd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817313909 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2817313909
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.561927766
Short name T61
Test name
Test status
Simulation time 695109116 ps
CPU time 2.96 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200312 kb
Host smart-41588f58-5954-4038-abeb-bdc6d823f695
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561927766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.561927766
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2374806935
Short name T8
Test name
Test status
Simulation time 113544557431 ps
CPU time 4031.37 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 08:03:56 PM PDT 24
Peak memory 841128 kb
Host smart-8a2c3685-644f-4f5d-a457-11af8cf2fcbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374806935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2374806935
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3754682854
Short name T57
Test name
Test status
Simulation time 106330454 ps
CPU time 1 seconds
Started Jul 16 06:56:36 PM PDT 24
Finished Jul 16 06:56:38 PM PDT 24
Peak memory 218252 kb
Host smart-df250956-fdf2-4878-9b2a-d1e427713aeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754682854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3754682854
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3037939419
Short name T12
Test name
Test status
Simulation time 104157760227 ps
CPU time 2062.15 seconds
Started Jul 16 06:56:34 PM PDT 24
Finished Jul 16 07:30:58 PM PDT 24
Peak memory 765440 kb
Host smart-14c3f4d2-8f99-4009-8b92-45109202d9f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037939419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3037939419
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.930338481
Short name T89
Test name
Test status
Simulation time 26615645 ps
CPU time 0.84 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:56:51 PM PDT 24
Peak memory 199884 kb
Host smart-996ddacb-b2d1-407b-a68c-72823bd87a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930338481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.930338481
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1513388625
Short name T20
Test name
Test status
Simulation time 1042534419 ps
CPU time 55.94 seconds
Started Jul 16 06:57:41 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 200344 kb
Host smart-1e1fff18-da9a-4f21-8f0d-ef96db2e7696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513388625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1513388625
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1570649095
Short name T71
Test name
Test status
Simulation time 149561119605 ps
CPU time 4203.87 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 08:06:50 PM PDT 24
Peak memory 834336 kb
Host smart-05add078-1734-45f9-86b6-7ce32ece1260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570649095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1570649095
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2779523342
Short name T30
Test name
Test status
Simulation time 1168677017 ps
CPU time 61.68 seconds
Started Jul 16 06:57:03 PM PDT 24
Finished Jul 16 06:58:06 PM PDT 24
Peak memory 200340 kb
Host smart-dba42ca2-c913-4cea-bd22-16665a557a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779523342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2779523342
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3258437675
Short name T25
Test name
Test status
Simulation time 964889682 ps
CPU time 52.57 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 200336 kb
Host smart-62a19980-b6ff-4555-84f8-42f91758420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258437675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3258437675
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2454800842
Short name T62
Test name
Test status
Simulation time 192459498 ps
CPU time 1.67 seconds
Started Jul 16 06:56:13 PM PDT 24
Finished Jul 16 06:56:15 PM PDT 24
Peak memory 200308 kb
Host smart-e5e9fae0-9eb8-4228-a363-046941c6c9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454800842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2454800842
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1437064942
Short name T205
Test name
Test status
Simulation time 22778599 ps
CPU time 0.63 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:57:14 PM PDT 24
Peak memory 196204 kb
Host smart-ec6b2e88-91f0-48a5-8f59-46ce976f39c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437064942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1437064942
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2650128346
Short name T138
Test name
Test status
Simulation time 129184688924 ps
CPU time 3870.51 seconds
Started Jul 16 06:56:53 PM PDT 24
Finished Jul 16 08:01:25 PM PDT 24
Peak memory 843260 kb
Host smart-a1dd7dc2-45e2-4267-a61e-6afa0ebf6a98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650128346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2650128346
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all.997014827
Short name T187
Test name
Test status
Simulation time 39257869585 ps
CPU time 1597.45 seconds
Started Jul 16 06:57:41 PM PDT 24
Finished Jul 16 07:24:20 PM PDT 24
Peak memory 785548 kb
Host smart-e5923226-88bd-434b-8e4e-a1e1dee90fe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997014827 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.997014827
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.561990234
Short name T117
Test name
Test status
Simulation time 449025436 ps
CPU time 1.75 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200288 kb
Host smart-95ea473c-7b29-4468-a1ea-3cd4c8666441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561990234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.561990234
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2204905907
Short name T129
Test name
Test status
Simulation time 4725118246 ps
CPU time 790.71 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 07:09:36 PM PDT 24
Peak memory 685976 kb
Host smart-5a98e1ba-805c-41d8-99bc-72d3302290fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204905907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2204905907
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2392118405
Short name T649
Test name
Test status
Simulation time 393298378 ps
CPU time 6.23 seconds
Started Jul 16 06:56:11 PM PDT 24
Finished Jul 16 06:56:19 PM PDT 24
Peak memory 200236 kb
Host smart-66743cbd-9d5f-4c3e-a45f-b691fbff62cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392118405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2392118405
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2124349788
Short name T619
Test name
Test status
Simulation time 1579586556 ps
CPU time 17.71 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:28 PM PDT 24
Peak memory 199196 kb
Host smart-d3b3814e-2d99-4758-bdd6-271b326ebf31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124349788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2124349788
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2928801467
Short name T95
Test name
Test status
Simulation time 25787434 ps
CPU time 0.77 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 198540 kb
Host smart-d2eb19ec-f5ba-439c-b84e-a3ba1f5e93d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928801467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2928801467
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.12571230
Short name T655
Test name
Test status
Simulation time 222409353240 ps
CPU time 630.43 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 07:06:40 PM PDT 24
Peak memory 216796 kb
Host smart-97545e9b-941b-45b7-89a1-bba4f50c6569
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12571230 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.12571230
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2462050816
Short name T96
Test name
Test status
Simulation time 12377412 ps
CPU time 0.74 seconds
Started Jul 16 06:56:05 PM PDT 24
Finished Jul 16 06:56:08 PM PDT 24
Peak memory 197828 kb
Host smart-430ea368-8dfa-4416-b70e-7729afb6681d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462050816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2462050816
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.4099499652
Short name T529
Test name
Test status
Simulation time 22267063 ps
CPU time 0.57 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:11 PM PDT 24
Peak memory 195212 kb
Host smart-aa4a7f49-4345-4bf2-8e22-3f900b06764a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099499652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.4099499652
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4023008696
Short name T608
Test name
Test status
Simulation time 192408116 ps
CPU time 1.58 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 200248 kb
Host smart-c377cb35-af08-421c-aa97-45e61cf018ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023008696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4023008696
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.836918818
Short name T560
Test name
Test status
Simulation time 706206861 ps
CPU time 4.21 seconds
Started Jul 16 06:55:57 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 200280 kb
Host smart-aac92214-daa7-40ad-879e-4e8b285c8c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836918818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.836918818
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4174527393
Short name T618
Test name
Test status
Simulation time 943409335 ps
CPU time 1.9 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200304 kb
Host smart-90eaf220-cd84-401e-a11d-e93ddb9b1630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174527393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4174527393
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3387027656
Short name T654
Test name
Test status
Simulation time 1276693461 ps
CPU time 7.95 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 200172 kb
Host smart-2d6762e9-78d0-4cb5-920c-ae378f893794
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387027656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3387027656
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1815619158
Short name T98
Test name
Test status
Simulation time 711326714 ps
CPU time 11.28 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:16 PM PDT 24
Peak memory 200260 kb
Host smart-3f4ab501-568b-46ec-b9e8-0503591e8725
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815619158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1815619158
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3250344094
Short name T569
Test name
Test status
Simulation time 33870597 ps
CPU time 0.8 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 198428 kb
Host smart-5dde1361-129b-4cfa-bfe8-ba7be3cdd00d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250344094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3250344094
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1631751443
Short name T547
Test name
Test status
Simulation time 78726263 ps
CPU time 2 seconds
Started Jul 16 06:56:01 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 200324 kb
Host smart-1381f7b3-6f5d-4533-a6a0-439416dffdea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631751443 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1631751443
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2064505710
Short name T640
Test name
Test status
Simulation time 24260586 ps
CPU time 0.9 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 199832 kb
Host smart-cfe349df-7e7b-4a4b-ac76-e5ac8995864d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064505710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2064505710
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1243713579
Short name T613
Test name
Test status
Simulation time 12786541 ps
CPU time 0.64 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 195384 kb
Host smart-a71ced98-dfc5-41d8-bab9-edc08b4ee676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243713579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1243713579
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.933187863
Short name T582
Test name
Test status
Simulation time 239329072 ps
CPU time 1.18 seconds
Started Jul 16 06:56:05 PM PDT 24
Finished Jul 16 06:56:08 PM PDT 24
Peak memory 198688 kb
Host smart-eb7a080c-011e-429a-8187-8c2a7552645a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933187863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.933187863
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2499380696
Short name T577
Test name
Test status
Simulation time 51121263 ps
CPU time 2.5 seconds
Started Jul 16 06:56:14 PM PDT 24
Finished Jul 16 06:56:17 PM PDT 24
Peak memory 200300 kb
Host smart-6702c6c1-61d2-4c28-af5b-653652ffb61b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499380696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2499380696
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3707153632
Short name T118
Test name
Test status
Simulation time 1086792486 ps
CPU time 4.39 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:14 PM PDT 24
Peak memory 200336 kb
Host smart-29c1fbfe-e7b3-4e41-b734-b34da35f09de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707153632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3707153632
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4208237565
Short name T551
Test name
Test status
Simulation time 114615464 ps
CPU time 1.85 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200260 kb
Host smart-d433e008-8a74-4d98-a4e3-675156d721b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208237565 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4208237565
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1455303513
Short name T91
Test name
Test status
Simulation time 27227657 ps
CPU time 0.81 seconds
Started Jul 16 06:56:09 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 199488 kb
Host smart-b4d7179f-713f-4280-a4a3-902fdf499094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455303513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1455303513
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1280247524
Short name T592
Test name
Test status
Simulation time 54065302 ps
CPU time 0.6 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 195304 kb
Host smart-ab76945b-c821-4280-9c91-af85ec797765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280247524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1280247524
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1453750367
Short name T561
Test name
Test status
Simulation time 163627107 ps
CPU time 1.79 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200200 kb
Host smart-3c41ed57-23e9-4b0b-8908-9adeff36c0c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453750367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1453750367
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3506984609
Short name T601
Test name
Test status
Simulation time 211107329 ps
CPU time 2.92 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:14 PM PDT 24
Peak memory 200328 kb
Host smart-18107dbc-1676-4bbf-8c09-fdfb0244fe9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506984609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3506984609
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2546068160
Short name T600
Test name
Test status
Simulation time 47405658 ps
CPU time 2.97 seconds
Started Jul 16 06:56:05 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 215876 kb
Host smart-24feee35-ccef-43b3-aa78-8ff7b1e23873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546068160 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2546068160
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3530593802
Short name T90
Test name
Test status
Simulation time 19423364 ps
CPU time 0.92 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 199980 kb
Host smart-301eff38-2150-419b-ad2f-3d05ba2bbdf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530593802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3530593802
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.599689554
Short name T583
Test name
Test status
Simulation time 26878884 ps
CPU time 0.65 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 195204 kb
Host smart-59a1a491-3fea-413c-aabe-de3e0a478a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599689554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.599689554
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1075876603
Short name T104
Test name
Test status
Simulation time 232656227 ps
CPU time 1.29 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 198676 kb
Host smart-33cf79c1-47e5-42ea-bce7-ae5f852d22e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075876603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1075876603
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3630927651
Short name T634
Test name
Test status
Simulation time 115640429 ps
CPU time 3.35 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:15 PM PDT 24
Peak memory 200276 kb
Host smart-66837828-fba3-4939-9aa4-bb8885070042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630927651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3630927651
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3808036139
Short name T627
Test name
Test status
Simulation time 279925200 ps
CPU time 4.5 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:14 PM PDT 24
Peak memory 200296 kb
Host smart-806bbb67-90e1-4d5f-b033-99bd34f984d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808036139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3808036139
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1860093203
Short name T536
Test name
Test status
Simulation time 46677315 ps
CPU time 2.67 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 200352 kb
Host smart-2ef31b6f-f152-4551-a4e0-ae272e57b0da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860093203 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1860093203
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.180089116
Short name T99
Test name
Test status
Simulation time 22803279 ps
CPU time 0.67 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:28 PM PDT 24
Peak memory 197932 kb
Host smart-114739f2-b495-4a20-9fa9-86f519af74a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180089116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.180089116
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2738815039
Short name T624
Test name
Test status
Simulation time 110269540 ps
CPU time 0.61 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:22 PM PDT 24
Peak memory 195192 kb
Host smart-61c417e1-a0d5-49a4-b5de-59de257102c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738815039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2738815039
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.250098090
Short name T617
Test name
Test status
Simulation time 458131121 ps
CPU time 1.9 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 200288 kb
Host smart-8557d999-70ae-42c9-8609-09e6389cfc41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250098090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.250098090
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1702123418
Short name T567
Test name
Test status
Simulation time 1629079531 ps
CPU time 3.23 seconds
Started Jul 16 06:56:05 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 200336 kb
Host smart-9860909f-d2bf-4119-ab74-e009e063e3b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702123418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1702123418
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1738422582
Short name T115
Test name
Test status
Simulation time 326140956 ps
CPU time 2.92 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200320 kb
Host smart-1579ec11-b626-4f83-94b5-26d83b727818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738422582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1738422582
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4017271726
Short name T573
Test name
Test status
Simulation time 179836563 ps
CPU time 2.29 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 208552 kb
Host smart-d0dee187-2038-499b-87fc-0da089c6e49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017271726 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4017271726
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2180842733
Short name T622
Test name
Test status
Simulation time 61684909 ps
CPU time 0.95 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 199992 kb
Host smart-18478274-70b4-4c83-beec-73fa0136367c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180842733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2180842733
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2593073041
Short name T570
Test name
Test status
Simulation time 42137867 ps
CPU time 0.58 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:16 PM PDT 24
Peak memory 195196 kb
Host smart-a767f1e6-a8bf-4739-8b9e-11e4d00df135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593073041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2593073041
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3834338893
Short name T108
Test name
Test status
Simulation time 321247787 ps
CPU time 1.77 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:22 PM PDT 24
Peak memory 200280 kb
Host smart-88bfb8d0-4f6b-4e1c-bded-19a52f3478b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834338893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3834338893
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1100133735
Short name T552
Test name
Test status
Simulation time 315956112 ps
CPU time 2.17 seconds
Started Jul 16 06:56:20 PM PDT 24
Finished Jul 16 06:56:26 PM PDT 24
Peak memory 200276 kb
Host smart-5153b580-c2ef-4635-81bb-68c3d0dfd378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100133735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1100133735
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2875316548
Short name T606
Test name
Test status
Simulation time 96452448 ps
CPU time 1.78 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 200196 kb
Host smart-6b0c02fc-26b2-4f8d-87e7-095cf149d69b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875316548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2875316548
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.9439209
Short name T611
Test name
Test status
Simulation time 76561950 ps
CPU time 1.89 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 200260 kb
Host smart-d4f8e6ae-69cc-4810-95b6-1cb3afc02d1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9439209 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.9439209
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3079145563
Short name T656
Test name
Test status
Simulation time 46958025 ps
CPU time 0.84 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 199904 kb
Host smart-3b85dd1d-e8d8-41f4-96b3-16b5501745f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079145563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3079145563
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1661395312
Short name T548
Test name
Test status
Simulation time 134714213 ps
CPU time 0.57 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 06:56:19 PM PDT 24
Peak memory 195228 kb
Host smart-2112ee3d-6e46-4c01-b4cb-f51ad93bd4d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661395312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1661395312
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1826809151
Short name T614
Test name
Test status
Simulation time 149992929 ps
CPU time 2.49 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:56:22 PM PDT 24
Peak memory 200340 kb
Host smart-fb019a71-3bab-4527-abd3-df062375ce77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826809151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1826809151
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3555523658
Short name T616
Test name
Test status
Simulation time 64868180 ps
CPU time 1.92 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:23 PM PDT 24
Peak memory 200324 kb
Host smart-9c04e99c-7d12-46a2-8129-cc086c933043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555523658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3555523658
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.526682393
Short name T113
Test name
Test status
Simulation time 1242994639 ps
CPU time 3.08 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 200280 kb
Host smart-5a7a3bbd-f940-4da9-877a-9a46b5313cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526682393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.526682393
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2200555150
Short name T534
Test name
Test status
Simulation time 91797438 ps
CPU time 1.48 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 200272 kb
Host smart-ca848a25-1597-4477-b2ab-163ef54ffc26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200555150 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2200555150
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2723149673
Short name T651
Test name
Test status
Simulation time 17082545 ps
CPU time 0.86 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:16 PM PDT 24
Peak memory 200180 kb
Host smart-9db18533-9db9-44d1-8d9d-75451b535963
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723149673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2723149673
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2348737789
Short name T657
Test name
Test status
Simulation time 29039450 ps
CPU time 0.64 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:17 PM PDT 24
Peak memory 195208 kb
Host smart-be8634fa-da8d-4364-b056-dec361b75397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348737789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2348737789
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3975972679
Short name T629
Test name
Test status
Simulation time 151362790 ps
CPU time 1.74 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:24 PM PDT 24
Peak memory 200356 kb
Host smart-63ec4b50-4c35-4529-9b4b-fa7d6188427b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975972679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3975972679
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2560225654
Short name T604
Test name
Test status
Simulation time 536009855 ps
CPU time 3.03 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 200212 kb
Host smart-5c5bb34d-9cd4-4c50-a104-8c2fa2e6808f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560225654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2560225654
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3339407584
Short name T603
Test name
Test status
Simulation time 1401160822 ps
CPU time 3.24 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:19 PM PDT 24
Peak memory 200204 kb
Host smart-d9379e1a-fc6c-46da-8f9f-45563d772b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339407584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3339407584
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3395504896
Short name T642
Test name
Test status
Simulation time 54742956 ps
CPU time 3.61 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 215880 kb
Host smart-f2ffedbe-3bca-4915-b2a4-8827c1f3df46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395504896 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3395504896
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3819944294
Short name T645
Test name
Test status
Simulation time 64860647 ps
CPU time 0.73 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:33 PM PDT 24
Peak memory 198552 kb
Host smart-5469906a-7dbf-4ca4-826c-9d195ed473a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819944294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3819944294
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1981338946
Short name T578
Test name
Test status
Simulation time 25633831 ps
CPU time 0.6 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:17 PM PDT 24
Peak memory 195188 kb
Host smart-e47e35bf-440f-4f1f-993d-953706333588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981338946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1981338946
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3760817121
Short name T554
Test name
Test status
Simulation time 251179354 ps
CPU time 1.27 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 200128 kb
Host smart-f49570de-8c5d-4ff5-87a2-a771eb1566f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760817121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3760817121
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3365294666
Short name T550
Test name
Test status
Simulation time 898535519 ps
CPU time 3.37 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:32 PM PDT 24
Peak memory 200220 kb
Host smart-def4db31-4082-49c6-84fd-c4ba9026984f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365294666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3365294666
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3584265506
Short name T60
Test name
Test status
Simulation time 210072468 ps
CPU time 3.93 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:56:23 PM PDT 24
Peak memory 200248 kb
Host smart-e9c468e1-68be-413d-a1dc-648fbb5a966a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584265506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3584265506
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.132191523
Short name T574
Test name
Test status
Simulation time 273830317 ps
CPU time 2.31 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 200352 kb
Host smart-6cdc8747-dfbe-466d-8cc0-11048b3d6e59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132191523 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.132191523
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.395299970
Short name T580
Test name
Test status
Simulation time 102712093 ps
CPU time 0.85 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 200148 kb
Host smart-6dd08e13-13e8-4595-b2c5-70482bc74f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395299970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.395299970
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2585006829
Short name T652
Test name
Test status
Simulation time 66113902 ps
CPU time 0.61 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:22 PM PDT 24
Peak memory 195248 kb
Host smart-a48c89c8-0f6f-4aed-b381-0c5edc2f2a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585006829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2585006829
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4047383664
Short name T625
Test name
Test status
Simulation time 115502238 ps
CPU time 2.28 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:56:28 PM PDT 24
Peak memory 200244 kb
Host smart-b7088d3f-c2df-4f31-b7f2-3e8f71839ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047383664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4047383664
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3726567635
Short name T545
Test name
Test status
Simulation time 58271644 ps
CPU time 3.16 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:24 PM PDT 24
Peak memory 200328 kb
Host smart-f911d216-1f81-42de-8f9b-91df1326f21a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726567635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3726567635
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2812726942
Short name T112
Test name
Test status
Simulation time 456905793 ps
CPU time 3.98 seconds
Started Jul 16 06:56:20 PM PDT 24
Finished Jul 16 06:56:26 PM PDT 24
Peak memory 200360 kb
Host smart-fe34b20d-670d-4877-8422-41cd1542a60e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812726942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2812726942
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3565103265
Short name T586
Test name
Test status
Simulation time 128673866 ps
CPU time 1.21 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:24 PM PDT 24
Peak memory 200248 kb
Host smart-fa054c87-6371-45a1-804e-b1f337b6ced6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565103265 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3565103265
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2019342115
Short name T612
Test name
Test status
Simulation time 33309547 ps
CPU time 0.61 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 06:56:19 PM PDT 24
Peak memory 195380 kb
Host smart-a161a577-9865-40f8-83a1-6f4607d642f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019342115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2019342115
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3123002634
Short name T621
Test name
Test status
Simulation time 77805662 ps
CPU time 1.68 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:23 PM PDT 24
Peak memory 200284 kb
Host smart-4e18fee8-89e3-4b51-a454-6094619fcdd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123002634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3123002634
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4293246509
Short name T546
Test name
Test status
Simulation time 101401770 ps
CPU time 2.61 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 200156 kb
Host smart-670dda9f-8756-4559-98d9-64e12f616639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293246509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4293246509
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2013771230
Short name T648
Test name
Test status
Simulation time 132606474 ps
CPU time 4.02 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:32 PM PDT 24
Peak memory 200268 kb
Host smart-38800d29-239d-4223-af58-5e400d2638e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013771230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2013771230
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1701026371
Short name T544
Test name
Test status
Simulation time 102988537902 ps
CPU time 1009.21 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 07:13:06 PM PDT 24
Peak memory 216840 kb
Host smart-2d9ff6c2-c0f3-4ab7-84ab-42e6aae5141a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701026371 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1701026371
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2337920692
Short name T636
Test name
Test status
Simulation time 32765474 ps
CPU time 0.7 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 198272 kb
Host smart-14038eba-125a-4a7c-8c6d-17775f13e6d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337920692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2337920692
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1927588342
Short name T558
Test name
Test status
Simulation time 106327095 ps
CPU time 0.66 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 06:56:19 PM PDT 24
Peak memory 195264 kb
Host smart-401a148f-0d37-4955-8743-c844f4d51fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927588342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1927588342
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1682872160
Short name T607
Test name
Test status
Simulation time 92049492 ps
CPU time 1.07 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:22 PM PDT 24
Peak memory 200248 kb
Host smart-5225f3de-7ba9-4824-865b-2586ab5cb830
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682872160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1682872160
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2142247818
Short name T631
Test name
Test status
Simulation time 300436492 ps
CPU time 3.02 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 200280 kb
Host smart-53c0e5a9-e033-4577-8dff-806e5911fe02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142247818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2142247818
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1204140242
Short name T595
Test name
Test status
Simulation time 131340223 ps
CPU time 4.09 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 200276 kb
Host smart-cd802564-b575-43a2-b97c-98d073a59f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204140242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1204140242
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3523688360
Short name T93
Test name
Test status
Simulation time 410808244 ps
CPU time 5.69 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:11 PM PDT 24
Peak memory 200188 kb
Host smart-862c9da9-6f86-4c5a-b8cb-5ff73ac6ee12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523688360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3523688360
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.245985192
Short name T97
Test name
Test status
Simulation time 1278861361 ps
CPU time 13.99 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 199364 kb
Host smart-e1c80994-4d22-4843-bca7-e201ddbd071c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245985192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.245985192
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2519021422
Short name T538
Test name
Test status
Simulation time 103895275 ps
CPU time 0.77 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 198432 kb
Host smart-6606316a-49ad-44a9-b7b9-d1a3f45f672c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519021422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2519021422
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3851490621
Short name T539
Test name
Test status
Simulation time 260627394 ps
CPU time 1.78 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 200288 kb
Host smart-1bf49338-18c2-4ea0-92eb-e574aeca65f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851490621 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3851490621
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3287211443
Short name T643
Test name
Test status
Simulation time 35877904 ps
CPU time 0.71 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:11 PM PDT 24
Peak memory 198308 kb
Host smart-669203d1-2930-40d2-8256-9eec8d1b0487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287211443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3287211443
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.912085289
Short name T564
Test name
Test status
Simulation time 47940858 ps
CPU time 0.59 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 195268 kb
Host smart-6d0f16d4-a572-4d4a-be0c-d48cf23c2fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912085289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.912085289
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.623695286
Short name T105
Test name
Test status
Simulation time 50298655 ps
CPU time 1.15 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:11 PM PDT 24
Peak memory 198852 kb
Host smart-7da923bd-b4d2-44db-88da-0f4a35db09e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623695286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.623695286
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3072254778
Short name T590
Test name
Test status
Simulation time 869306886 ps
CPU time 3.94 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 200264 kb
Host smart-3bb5fdf7-8056-4128-9a98-762d1ceee5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072254778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3072254778
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3210310144
Short name T653
Test name
Test status
Simulation time 573292649 ps
CPU time 3.97 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:14 PM PDT 24
Peak memory 200252 kb
Host smart-a2c6ab25-7fb4-4bec-9cb6-31fba82cfdbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210310144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3210310144
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3528017897
Short name T533
Test name
Test status
Simulation time 34354405 ps
CPU time 0.57 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195120 kb
Host smart-d2faa208-7b42-40a5-937e-09ff00858cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528017897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3528017897
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2557406982
Short name T579
Test name
Test status
Simulation time 33915871 ps
CPU time 0.59 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 195240 kb
Host smart-a6ecafd0-6efc-4457-afbf-3ebd95493bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557406982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2557406982
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3629286039
Short name T646
Test name
Test status
Simulation time 12651967 ps
CPU time 0.62 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:56:23 PM PDT 24
Peak memory 195048 kb
Host smart-2e109ecb-47f2-4864-b141-96c7ee3b3aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629286039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3629286039
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1734068096
Short name T659
Test name
Test status
Simulation time 11209272 ps
CPU time 0.57 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 06:56:18 PM PDT 24
Peak memory 195216 kb
Host smart-3bc01b16-12fd-4c17-9d3f-01ee125d866a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734068096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1734068096
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4118095191
Short name T532
Test name
Test status
Simulation time 23101075 ps
CPU time 0.62 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195192 kb
Host smart-71107bad-b4a1-4d0f-8b5e-a6e337a8df80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118095191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4118095191
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.353563122
Short name T626
Test name
Test status
Simulation time 32927068 ps
CPU time 0.61 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 195296 kb
Host smart-23d92d2c-4793-4e09-b227-a18ea0c8f8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353563122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.353563122
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2916065079
Short name T576
Test name
Test status
Simulation time 142505488 ps
CPU time 0.63 seconds
Started Jul 16 06:56:25 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 195300 kb
Host smart-74f8efeb-fe29-4428-8c65-f0edd5aea060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916065079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2916065079
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1220634087
Short name T572
Test name
Test status
Simulation time 12406823 ps
CPU time 0.6 seconds
Started Jul 16 06:56:25 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 194340 kb
Host smart-ed8e49ea-f983-4519-8c6a-55a91e6424dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220634087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1220634087
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2615026739
Short name T588
Test name
Test status
Simulation time 21273753 ps
CPU time 0.58 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 195180 kb
Host smart-a49385b5-c07b-48bd-bce0-48b4b5c13fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615026739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2615026739
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.490831059
Short name T623
Test name
Test status
Simulation time 16519311 ps
CPU time 0.6 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 195156 kb
Host smart-aad44be5-87ea-4cfd-9351-04b0ad48070f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490831059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.490831059
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4151391232
Short name T94
Test name
Test status
Simulation time 446968985 ps
CPU time 8.88 seconds
Started Jul 16 06:56:10 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 199976 kb
Host smart-f13ea594-c399-4be1-8dad-36d6da1e8822
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151391232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4151391232
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4183456754
Short name T100
Test name
Test status
Simulation time 10466019691 ps
CPU time 17.85 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:27 PM PDT 24
Peak memory 200396 kb
Host smart-d9b77943-d510-41fa-8b34-824a9a3d586d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183456754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.4183456754
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1969227164
Short name T92
Test name
Test status
Simulation time 20222766 ps
CPU time 0.96 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 200084 kb
Host smart-c449dc7d-10ea-435f-845a-4ab5990a6f5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969227164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1969227164
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2297268901
Short name T562
Test name
Test status
Simulation time 68559618 ps
CPU time 1.86 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 200440 kb
Host smart-af7fdabb-7a5a-4a1f-b3e0-a4e87fc45af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297268901 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2297268901
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3074878342
Short name T605
Test name
Test status
Simulation time 16737462 ps
CPU time 0.81 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 200064 kb
Host smart-89f2bd1c-fd35-4da6-97b6-1eb0cc63d508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074878342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3074878342
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2017686414
Short name T575
Test name
Test status
Simulation time 20958915 ps
CPU time 0.62 seconds
Started Jul 16 06:56:01 PM PDT 24
Finished Jul 16 06:56:02 PM PDT 24
Peak memory 195124 kb
Host smart-f00d5837-1f4e-45b6-919b-42aee768d4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017686414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2017686414
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3696308459
Short name T109
Test name
Test status
Simulation time 281247339 ps
CPU time 1.61 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 200264 kb
Host smart-b3ea8b46-0758-4b8c-a791-dc759fd0fa51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696308459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3696308459
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.362478931
Short name T540
Test name
Test status
Simulation time 56018936 ps
CPU time 1.49 seconds
Started Jul 16 06:56:05 PM PDT 24
Finished Jul 16 06:56:08 PM PDT 24
Peak memory 200384 kb
Host smart-4a10de2c-f61b-40df-9bc9-be7189229fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362478931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.362478931
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4181899346
Short name T119
Test name
Test status
Simulation time 870419421 ps
CPU time 4.43 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 200212 kb
Host smart-0831103f-8c80-4825-bb12-d1c656695a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181899346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4181899346
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3433336609
Short name T559
Test name
Test status
Simulation time 19152131 ps
CPU time 0.63 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195272 kb
Host smart-f444a2d1-3b47-4896-ab74-4abedb1c7f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433336609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3433336609
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1352534838
Short name T609
Test name
Test status
Simulation time 11125098 ps
CPU time 0.65 seconds
Started Jul 16 06:56:20 PM PDT 24
Finished Jul 16 06:56:24 PM PDT 24
Peak memory 195336 kb
Host smart-68c7288d-38a0-4c96-b8de-a496b9e9e537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352534838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1352534838
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.4172542960
Short name T566
Test name
Test status
Simulation time 14039766 ps
CPU time 0.59 seconds
Started Jul 16 06:56:25 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 194408 kb
Host smart-38cc9491-7d25-445e-baaf-6b6f14004be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172542960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4172542960
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.971622921
Short name T542
Test name
Test status
Simulation time 23739172 ps
CPU time 0.61 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:30 PM PDT 24
Peak memory 195228 kb
Host smart-9afa1ca8-e0b8-4332-9575-932d547db0b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971622921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.971622921
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2658754075
Short name T591
Test name
Test status
Simulation time 48410900 ps
CPU time 0.61 seconds
Started Jul 16 06:56:15 PM PDT 24
Finished Jul 16 06:56:17 PM PDT 24
Peak memory 195476 kb
Host smart-c58226ea-5c51-4447-9ad9-d120c1cd3499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658754075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2658754075
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2773946824
Short name T535
Test name
Test status
Simulation time 16672712 ps
CPU time 0.62 seconds
Started Jul 16 06:56:36 PM PDT 24
Finished Jul 16 06:56:38 PM PDT 24
Peak memory 195332 kb
Host smart-56c247d2-6bdb-4989-8d9a-e97284349f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773946824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2773946824
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2441632847
Short name T635
Test name
Test status
Simulation time 13628406 ps
CPU time 0.63 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195328 kb
Host smart-3941c655-9ca1-4728-b4e8-004d090b0968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441632847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2441632847
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.4283315438
Short name T571
Test name
Test status
Simulation time 17374096 ps
CPU time 0.61 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 06:56:19 PM PDT 24
Peak memory 195248 kb
Host smart-b8fc7fac-f6c7-46e5-8266-a938d9cb80c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283315438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.4283315438
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2735774570
Short name T587
Test name
Test status
Simulation time 36415215 ps
CPU time 0.58 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:27 PM PDT 24
Peak memory 195212 kb
Host smart-a2119089-216a-492e-83fe-9649be172b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735774570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2735774570
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1968905077
Short name T597
Test name
Test status
Simulation time 24624632 ps
CPU time 0.63 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195172 kb
Host smart-1c8ad310-a866-4417-b7d3-6bc4be0c7e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968905077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1968905077
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3417871687
Short name T87
Test name
Test status
Simulation time 605872816 ps
CPU time 3.3 seconds
Started Jul 16 06:56:10 PM PDT 24
Finished Jul 16 06:56:15 PM PDT 24
Peak memory 200256 kb
Host smart-2d37597e-1d70-4df1-b55a-0d0a3d02d7b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417871687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3417871687
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3258002161
Short name T568
Test name
Test status
Simulation time 1083091680 ps
CPU time 15.42 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:26 PM PDT 24
Peak memory 200344 kb
Host smart-f71a63f5-5a36-4d7c-b289-feb3bb6f5e7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258002161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3258002161
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3810273575
Short name T584
Test name
Test status
Simulation time 26342596 ps
CPU time 0.88 seconds
Started Jul 16 06:56:09 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 199816 kb
Host smart-2413c6a9-5705-4f0f-907a-5ae1378052c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810273575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3810273575
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3220889044
Short name T644
Test name
Test status
Simulation time 380989132 ps
CPU time 2.32 seconds
Started Jul 16 06:56:01 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 200368 kb
Host smart-d0a8103a-5a83-4292-9e54-b7ae78604a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220889044 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3220889044
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.593232504
Short name T647
Test name
Test status
Simulation time 14353441 ps
CPU time 0.78 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 199180 kb
Host smart-dc7cadb7-a833-4377-95b3-f08b01d840ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593232504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.593232504
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.347949847
Short name T585
Test name
Test status
Simulation time 29081323 ps
CPU time 0.64 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 195196 kb
Host smart-a4d3b3a8-a92c-4278-997a-345b261adf9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347949847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.347949847
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1585718151
Short name T639
Test name
Test status
Simulation time 214026888 ps
CPU time 1.14 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 200348 kb
Host smart-b324b48b-25ea-4a8d-9ca0-c4ce3abe55ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585718151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1585718151
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2834460124
Short name T543
Test name
Test status
Simulation time 482510041 ps
CPU time 1.82 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200320 kb
Host smart-4c656250-e524-4b42-96c7-4bdeb2c64437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834460124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2834460124
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2029324001
Short name T116
Test name
Test status
Simulation time 254550511 ps
CPU time 1.71 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 200092 kb
Host smart-b04302eb-8804-4b57-ac32-3138efe21953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029324001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2029324001
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1039179173
Short name T565
Test name
Test status
Simulation time 128074370 ps
CPU time 0.57 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 195180 kb
Host smart-be6c03b1-2aec-4688-b15a-ff9bb5b95ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039179173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1039179173
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1754873451
Short name T531
Test name
Test status
Simulation time 51481756 ps
CPU time 0.61 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 195256 kb
Host smart-dedcc9f6-f914-4964-a07a-54cd3f379154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754873451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1754873451
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3020324180
Short name T633
Test name
Test status
Simulation time 30274357 ps
CPU time 0.61 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195140 kb
Host smart-fae44cc9-1a0c-490f-8be8-aa9376fd524b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020324180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3020324180
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1136766676
Short name T537
Test name
Test status
Simulation time 29643607 ps
CPU time 0.62 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:56:29 PM PDT 24
Peak memory 195264 kb
Host smart-1e4f75d2-ad46-4118-910c-35eb4e1f203f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136766676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1136766676
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.207609835
Short name T530
Test name
Test status
Simulation time 14331382 ps
CPU time 0.61 seconds
Started Jul 16 06:56:18 PM PDT 24
Finished Jul 16 06:56:21 PM PDT 24
Peak memory 195168 kb
Host smart-1eb84357-0a21-41bd-947e-ec1cc559c29c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207609835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.207609835
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2489074548
Short name T620
Test name
Test status
Simulation time 60785324 ps
CPU time 0.58 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:28 PM PDT 24
Peak memory 195128 kb
Host smart-32cbbcff-a407-4718-bb8e-8085f6c57ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489074548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2489074548
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1235933351
Short name T610
Test name
Test status
Simulation time 25362614 ps
CPU time 0.62 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 195228 kb
Host smart-8e5906c8-7b93-4fa4-84b5-5825d7689ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235933351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1235933351
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4228135
Short name T549
Test name
Test status
Simulation time 15536340 ps
CPU time 0.6 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:56:27 PM PDT 24
Peak memory 195160 kb
Host smart-9f8e9e00-b67e-48da-b54d-5b1436be33d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4228135
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.236013418
Short name T650
Test name
Test status
Simulation time 95479182 ps
CPU time 0.59 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 06:56:25 PM PDT 24
Peak memory 195232 kb
Host smart-d47bdb87-abfc-4aef-9da7-0c4f2daa5f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236013418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.236013418
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1273830470
Short name T658
Test name
Test status
Simulation time 11280267 ps
CPU time 0.62 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:56:28 PM PDT 24
Peak memory 195256 kb
Host smart-55c6221c-1a26-4ca1-85bd-4fb136efe232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273830470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1273830470
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2390476051
Short name T553
Test name
Test status
Simulation time 192716963 ps
CPU time 2.45 seconds
Started Jul 16 06:56:05 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 200412 kb
Host smart-7832898c-adea-4dae-b249-b5b9e3ef0170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390476051 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2390476051
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1330850845
Short name T88
Test name
Test status
Simulation time 51377477 ps
CPU time 0.93 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:08 PM PDT 24
Peak memory 200092 kb
Host smart-0400b01a-79a1-4711-a15a-398ad9390b41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330850845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1330850845
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.86419877
Short name T541
Test name
Test status
Simulation time 12860600 ps
CPU time 0.63 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:05 PM PDT 24
Peak memory 195256 kb
Host smart-61dcbf82-8097-4c00-8f62-b2b0e0908ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86419877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.86419877
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.97334313
Short name T602
Test name
Test status
Simulation time 21799709 ps
CPU time 1.09 seconds
Started Jul 16 06:56:09 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 198796 kb
Host smart-93983f21-c7e8-441d-b748-44b38a2d21af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97334313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_o
utstanding.97334313
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3032997823
Short name T615
Test name
Test status
Simulation time 260340418 ps
CPU time 4.42 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 200252 kb
Host smart-e7d8fff5-10d6-4881-969d-27e039ba30aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032997823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3032997823
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1856135070
Short name T596
Test name
Test status
Simulation time 158791157 ps
CPU time 1.81 seconds
Started Jul 16 06:56:02 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 200292 kb
Host smart-5fb585ff-87c5-4d9c-8ba3-09beb09f16cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856135070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1856135070
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.298576362
Short name T632
Test name
Test status
Simulation time 1461806619 ps
CPU time 2.78 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:08 PM PDT 24
Peak memory 200388 kb
Host smart-064ad143-e11b-4e3b-9360-79b82a440144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298576362 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.298576362
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1075857734
Short name T103
Test name
Test status
Simulation time 27372781 ps
CPU time 0.82 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 199468 kb
Host smart-02887aad-f970-4902-98a4-8260e709a441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075857734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1075857734
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1334577165
Short name T641
Test name
Test status
Simulation time 60572600 ps
CPU time 0.62 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 195116 kb
Host smart-332bb1b9-48f1-4334-a078-daa5f2475339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334577165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1334577165
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4255680010
Short name T563
Test name
Test status
Simulation time 34561346 ps
CPU time 1.04 seconds
Started Jul 16 06:56:14 PM PDT 24
Finished Jul 16 06:56:16 PM PDT 24
Peak memory 200192 kb
Host smart-ffd0e50d-749e-4d2a-97b0-1513a9ba55b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255680010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4255680010
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1755062362
Short name T599
Test name
Test status
Simulation time 138291451 ps
CPU time 3.12 seconds
Started Jul 16 06:56:04 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 200236 kb
Host smart-74f78586-0078-4c82-a0ac-8b03223b436e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755062362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1755062362
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.918107449
Short name T594
Test name
Test status
Simulation time 434071722 ps
CPU time 1.92 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 200348 kb
Host smart-78869505-6fba-4816-9c50-f92b59f0296a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918107449 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.918107449
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3085915172
Short name T101
Test name
Test status
Simulation time 38889471 ps
CPU time 1 seconds
Started Jul 16 06:56:10 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200044 kb
Host smart-af9c1346-d0ff-45d3-850c-b6828d5a5288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085915172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3085915172
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.570366769
Short name T555
Test name
Test status
Simulation time 33593193 ps
CPU time 0.59 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 195252 kb
Host smart-996ca3d8-26a5-4e66-8ff3-01db37d9a5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570366769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.570366769
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2302399119
Short name T589
Test name
Test status
Simulation time 47170047 ps
CPU time 2.14 seconds
Started Jul 16 06:56:02 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 200284 kb
Host smart-6b6cfa60-b7e8-4be9-a9c8-45777a83168c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302399119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2302399119
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2581456616
Short name T598
Test name
Test status
Simulation time 59436537 ps
CPU time 3.01 seconds
Started Jul 16 06:56:01 PM PDT 24
Finished Jul 16 06:56:05 PM PDT 24
Peak memory 200224 kb
Host smart-22b8dbf3-5bda-4957-b983-e71ef0c5eac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581456616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2581456616
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3029819241
Short name T114
Test name
Test status
Simulation time 2726199793 ps
CPU time 4.25 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:13 PM PDT 24
Peak memory 200396 kb
Host smart-38c0ed4f-d0cc-4f68-a47f-78b13bfd2ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029819241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3029819241
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3509564271
Short name T556
Test name
Test status
Simulation time 35719252141 ps
CPU time 92.63 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:57:37 PM PDT 24
Peak memory 216132 kb
Host smart-72e28647-1c7c-4442-a89d-b302f5552a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509564271 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3509564271
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2190417845
Short name T102
Test name
Test status
Simulation time 20252368 ps
CPU time 0.76 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 198032 kb
Host smart-ec21cd48-b093-42df-88ba-789a2dfa3ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190417845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2190417845
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3541726374
Short name T630
Test name
Test status
Simulation time 49113076 ps
CPU time 0.63 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:06 PM PDT 24
Peak memory 195348 kb
Host smart-beeb47d5-18d9-4348-ae0e-916ada24ba74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541726374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3541726374
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.969007244
Short name T107
Test name
Test status
Simulation time 127021425 ps
CPU time 1.02 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 199020 kb
Host smart-86584f64-ddea-47c0-a620-789789f5ad23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969007244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.969007244
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1937765647
Short name T593
Test name
Test status
Simulation time 52853303 ps
CPU time 1.3 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:05 PM PDT 24
Peak memory 200244 kb
Host smart-2bd97c29-b99b-476c-91a6-11c087bc873e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937765647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1937765647
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1030903111
Short name T581
Test name
Test status
Simulation time 197167453 ps
CPU time 1.86 seconds
Started Jul 16 06:56:07 PM PDT 24
Finished Jul 16 06:56:12 PM PDT 24
Peak memory 200236 kb
Host smart-96342f3b-baad-4cd4-9a56-0e59145fbeef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030903111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1030903111
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2760972466
Short name T638
Test name
Test status
Simulation time 107334269 ps
CPU time 3.38 seconds
Started Jul 16 06:56:08 PM PDT 24
Finished Jul 16 06:56:14 PM PDT 24
Peak memory 215796 kb
Host smart-39cde4f2-4246-4b8e-84f8-d43320c603ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760972466 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2760972466
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1870328409
Short name T557
Test name
Test status
Simulation time 25352123 ps
CPU time 0.84 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:10 PM PDT 24
Peak memory 199456 kb
Host smart-5fe58b56-6804-41d3-9acc-4212874b94e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870328409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1870328409
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4097058397
Short name T637
Test name
Test status
Simulation time 12965652 ps
CPU time 0.61 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:09 PM PDT 24
Peak memory 195116 kb
Host smart-0b700864-2aa1-4cd1-b196-236fc6c2e256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097058397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4097058397
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2214650948
Short name T106
Test name
Test status
Simulation time 71634474 ps
CPU time 1.8 seconds
Started Jul 16 06:56:06 PM PDT 24
Finished Jul 16 06:56:11 PM PDT 24
Peak memory 200188 kb
Host smart-4af0aa2f-99f0-4480-a8d9-c442033d51be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214650948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2214650948
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3620998295
Short name T628
Test name
Test status
Simulation time 159877740 ps
CPU time 2.05 seconds
Started Jul 16 06:56:03 PM PDT 24
Finished Jul 16 06:56:07 PM PDT 24
Peak memory 200372 kb
Host smart-99e449d0-4d6b-4b47-a144-5bf108881af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620998295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3620998295
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1095400278
Short name T244
Test name
Test status
Simulation time 42069529 ps
CPU time 0.59 seconds
Started Jul 16 06:56:27 PM PDT 24
Finished Jul 16 06:56:31 PM PDT 24
Peak memory 196876 kb
Host smart-7f5b709f-e7be-4c6c-b5d5-62055fbee746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095400278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1095400278
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2341985440
Short name T232
Test name
Test status
Simulation time 1082788381 ps
CPU time 58.55 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:57:25 PM PDT 24
Peak memory 200248 kb
Host smart-a49bcb1b-046d-4aa0-81f8-452fbe2bf3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341985440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2341985440
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3840104715
Short name T398
Test name
Test status
Simulation time 687540702 ps
CPU time 12.4 seconds
Started Jul 16 06:56:26 PM PDT 24
Finished Jul 16 06:56:42 PM PDT 24
Peak memory 200296 kb
Host smart-5e1d74a1-16ac-4bc0-8080-78dcba978f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840104715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3840104715
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_error.3812686549
Short name T370
Test name
Test status
Simulation time 3635060836 ps
CPU time 205.73 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 06:59:51 PM PDT 24
Peak memory 200292 kb
Host smart-7e021ca5-2402-48d2-9890-03ce71fdb66f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812686549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3812686549
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3332850085
Short name T297
Test name
Test status
Simulation time 3134107610 ps
CPU time 183.08 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:59:29 PM PDT 24
Peak memory 200376 kb
Host smart-3d3e23bb-26be-4118-b74e-cc9d57a3553d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332850085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3332850085
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3146673423
Short name T51
Test name
Test status
Simulation time 123532498 ps
CPU time 0.9 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:56:26 PM PDT 24
Peak memory 218260 kb
Host smart-e2f917a8-cf77-483d-bdf6-031283a89975
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146673423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3146673423
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3698807536
Short name T343
Test name
Test status
Simulation time 1252478659 ps
CPU time 15.04 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 06:56:40 PM PDT 24
Peak memory 200312 kb
Host smart-8f29eae7-c873-4667-8e0f-399ede250508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698807536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3698807536
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2803651211
Short name T428
Test name
Test status
Simulation time 10939005810 ps
CPU time 832.46 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 07:10:19 PM PDT 24
Peak memory 639808 kb
Host smart-de823d6d-8f76-49ce-8305-c72f46138a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803651211 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2803651211
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1703533993
Short name T63
Test name
Test status
Simulation time 131398760464 ps
CPU time 2772.94 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 07:42:39 PM PDT 24
Peak memory 783584 kb
Host smart-a3422cc4-e346-462e-84b9-18d13ca7bcc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703533993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1703533993
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2514906429
Short name T335
Test name
Test status
Simulation time 4402531758 ps
CPU time 39.21 seconds
Started Jul 16 06:56:25 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 200404 kb
Host smart-22f5fb96-81fa-4b43-abb8-2ac1c663030c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2514906429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2514906429
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3630299255
Short name T284
Test name
Test status
Simulation time 2461013413 ps
CPU time 84.96 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:57:53 PM PDT 24
Peak memory 200360 kb
Host smart-b7bd5f8a-3b97-4721-900d-868cd10bad12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3630299255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3630299255
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3608372896
Short name T150
Test name
Test status
Simulation time 43537845464 ps
CPU time 124.55 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 06:58:33 PM PDT 24
Peak memory 200336 kb
Host smart-0f66d534-59f9-43c4-92a0-a37af81ef5e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3608372896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3608372896
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3262320820
Short name T480
Test name
Test status
Simulation time 57110395632 ps
CPU time 677.73 seconds
Started Jul 16 06:56:26 PM PDT 24
Finished Jul 16 07:07:48 PM PDT 24
Peak memory 200356 kb
Host smart-014e37ae-a284-4393-8dff-685a1c8d5220
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3262320820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3262320820
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3155997009
Short name T327
Test name
Test status
Simulation time 202876061642 ps
CPU time 2597.26 seconds
Started Jul 16 06:56:26 PM PDT 24
Finished Jul 16 07:39:47 PM PDT 24
Peak memory 216060 kb
Host smart-3b313f0f-52f5-441d-9377-abe64b0578d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3155997009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3155997009
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.922828689
Short name T499
Test name
Test status
Simulation time 229406646083 ps
CPU time 2599.57 seconds
Started Jul 16 06:56:26 PM PDT 24
Finished Jul 16 07:39:50 PM PDT 24
Peak memory 216012 kb
Host smart-1443d0c6-43ec-495e-bf8e-51549f3fc888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=922828689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.922828689
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1677498100
Short name T523
Test name
Test status
Simulation time 20626543558 ps
CPU time 132.72 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 200308 kb
Host smart-ce7c8f29-7058-4063-a83a-c886aff305dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677498100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1677498100
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2213450170
Short name T215
Test name
Test status
Simulation time 20717575 ps
CPU time 0.58 seconds
Started Jul 16 06:56:29 PM PDT 24
Finished Jul 16 06:56:32 PM PDT 24
Peak memory 196840 kb
Host smart-14b71214-9cd3-41b6-bc22-a189d9bda40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213450170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2213450170
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4177829151
Short name T448
Test name
Test status
Simulation time 18477842556 ps
CPU time 72.18 seconds
Started Jul 16 06:56:23 PM PDT 24
Finished Jul 16 06:57:40 PM PDT 24
Peak memory 200372 kb
Host smart-ed4f3564-1621-471f-ab42-4ed795a160d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177829151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4177829151
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3611051559
Short name T258
Test name
Test status
Simulation time 1595443954 ps
CPU time 10.77 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:56:36 PM PDT 24
Peak memory 200228 kb
Host smart-cc21e76c-7638-4858-8ce9-2bf24eac6463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611051559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3611051559
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.128340365
Short name T270
Test name
Test status
Simulation time 5214797522 ps
CPU time 227.01 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 07:00:14 PM PDT 24
Peak memory 610740 kb
Host smart-7be6603f-4b0d-46e5-bd0d-5d6a5265b83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128340365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.128340365
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2934159200
Short name T452
Test name
Test status
Simulation time 754614696 ps
CPU time 41.48 seconds
Started Jul 16 06:56:20 PM PDT 24
Finished Jul 16 06:57:04 PM PDT 24
Peak memory 200244 kb
Host smart-2dce5fdb-f2cf-445a-92da-ace2c3cc8db4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934159200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2934159200
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3653771086
Short name T59
Test name
Test status
Simulation time 148153240 ps
CPU time 0.96 seconds
Started Jul 16 06:56:30 PM PDT 24
Finished Jul 16 06:56:33 PM PDT 24
Peak memory 218480 kb
Host smart-c971a0ae-133a-4923-a275-d90448f70b1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653771086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3653771086
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3307020721
Short name T81
Test name
Test status
Simulation time 1575841825 ps
CPU time 12.28 seconds
Started Jul 16 06:56:20 PM PDT 24
Finished Jul 16 06:56:36 PM PDT 24
Peak memory 200312 kb
Host smart-12aa04d5-1575-4acf-a2a1-e8f4f6e1ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307020721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3307020721
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2256848923
Short name T288
Test name
Test status
Simulation time 207629004992 ps
CPU time 2009.35 seconds
Started Jul 16 06:56:42 PM PDT 24
Finished Jul 16 07:30:12 PM PDT 24
Peak memory 738292 kb
Host smart-8bc48a1d-3a41-490c-841d-1f9b7a19d978
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256848923 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2256848923
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.308745770
Short name T64
Test name
Test status
Simulation time 95409703653 ps
CPU time 3534.08 seconds
Started Jul 16 06:56:33 PM PDT 24
Finished Jul 16 07:55:28 PM PDT 24
Peak memory 823308 kb
Host smart-e59cc62a-c441-4870-a499-1ad35667b637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308745770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.308745770
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1943880419
Short name T70
Test name
Test status
Simulation time 10834767145 ps
CPU time 43.43 seconds
Started Jul 16 06:56:17 PM PDT 24
Finished Jul 16 06:57:03 PM PDT 24
Peak memory 200352 kb
Host smart-90e08b8a-5980-4d9a-9899-f13f7b371264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943880419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1943880419
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2364245889
Short name T239
Test name
Test status
Simulation time 2238553801 ps
CPU time 87.91 seconds
Started Jul 16 06:56:19 PM PDT 24
Finished Jul 16 06:57:49 PM PDT 24
Peak memory 200272 kb
Host smart-38d18094-c0a5-4967-aaf3-4662acd79f73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2364245889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2364245889
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1798140590
Short name T445
Test name
Test status
Simulation time 12205839784 ps
CPU time 119.7 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 06:58:24 PM PDT 24
Peak memory 200404 kb
Host smart-ca383445-a7eb-433c-a1db-3250fc53698a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1798140590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1798140590
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.547100468
Short name T434
Test name
Test status
Simulation time 37913952926 ps
CPU time 492.01 seconds
Started Jul 16 06:56:24 PM PDT 24
Finished Jul 16 07:04:41 PM PDT 24
Peak memory 200296 kb
Host smart-974c08fd-2d82-47e7-a5cb-48242b901382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=547100468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.547100468
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2780056845
Short name T421
Test name
Test status
Simulation time 196607176589 ps
CPU time 2534.07 seconds
Started Jul 16 06:56:16 PM PDT 24
Finished Jul 16 07:38:33 PM PDT 24
Peak memory 215916 kb
Host smart-b2d7b785-751d-43de-be83-75b1959ff970
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2780056845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2780056845
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.591361264
Short name T177
Test name
Test status
Simulation time 206514812472 ps
CPU time 2238.6 seconds
Started Jul 16 06:56:21 PM PDT 24
Finished Jul 16 07:33:44 PM PDT 24
Peak memory 216548 kb
Host smart-f774eead-913c-4408-80a2-67379ddeca35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=591361264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.591361264
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3109485836
Short name T483
Test name
Test status
Simulation time 3410952882 ps
CPU time 41.18 seconds
Started Jul 16 06:56:22 PM PDT 24
Finished Jul 16 06:57:07 PM PDT 24
Peak memory 200412 kb
Host smart-35239215-474c-4397-ba14-f74c38f764ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109485836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3109485836
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.206662173
Short name T468
Test name
Test status
Simulation time 37177554 ps
CPU time 0.55 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:56:54 PM PDT 24
Peak memory 195104 kb
Host smart-4e4d70bd-cc00-47a4-a085-9be332e2ebd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206662173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.206662173
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3922258631
Short name T375
Test name
Test status
Simulation time 836295662 ps
CPU time 40.52 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:33 PM PDT 24
Peak memory 200236 kb
Host smart-fac62410-7cb2-42cf-8573-adec55588396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922258631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3922258631
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3154570664
Short name T139
Test name
Test status
Simulation time 9421245613 ps
CPU time 63.45 seconds
Started Jul 16 06:56:49 PM PDT 24
Finished Jul 16 06:57:54 PM PDT 24
Peak memory 200332 kb
Host smart-b38e6b32-dc44-45a2-8b06-d03b58fd62d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154570664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3154570664
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3420394372
Short name T460
Test name
Test status
Simulation time 6540629518 ps
CPU time 1137.94 seconds
Started Jul 16 06:56:53 PM PDT 24
Finished Jul 16 07:15:52 PM PDT 24
Peak memory 736012 kb
Host smart-e7ba297b-22f9-43a9-944b-0d8ccd345302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420394372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3420394372
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1866363377
Short name T27
Test name
Test status
Simulation time 8918113704 ps
CPU time 149.13 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:59:23 PM PDT 24
Peak memory 200400 kb
Host smart-5dfbfbc6-bf83-4ce1-a9fd-9b121b02b9b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866363377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1866363377
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3276156867
Short name T218
Test name
Test status
Simulation time 58954041522 ps
CPU time 142.15 seconds
Started Jul 16 06:56:56 PM PDT 24
Finished Jul 16 06:59:19 PM PDT 24
Peak memory 200408 kb
Host smart-c98adcb0-470d-44de-a3b4-8a2a7810c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276156867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3276156867
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1741402230
Short name T525
Test name
Test status
Simulation time 608629312 ps
CPU time 13.58 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:06 PM PDT 24
Peak memory 200300 kb
Host smart-0fc063a3-38a8-4541-9d64-8067c8806324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741402230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1741402230
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.533501385
Short name T137
Test name
Test status
Simulation time 4012497970 ps
CPU time 181.36 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:59:51 PM PDT 24
Peak memory 200364 kb
Host smart-7cc5965d-e762-44cf-9f9c-edadfccf25be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533501385 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.533501385
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.204445937
Short name T86
Test name
Test status
Simulation time 8253245193 ps
CPU time 65.53 seconds
Started Jul 16 06:56:49 PM PDT 24
Finished Jul 16 06:57:56 PM PDT 24
Peak memory 200200 kb
Host smart-2b315f5b-b1f4-411a-b867-5468c10648b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204445937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.204445937
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1923526910
Short name T285
Test name
Test status
Simulation time 12371174 ps
CPU time 0.59 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:57:03 PM PDT 24
Peak memory 195188 kb
Host smart-7865e956-3588-4e5b-8cd7-86b933703778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923526910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1923526910
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.332206619
Short name T356
Test name
Test status
Simulation time 4090035394 ps
CPU time 52.26 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 06:57:47 PM PDT 24
Peak memory 200272 kb
Host smart-5ac873f5-6174-4061-88f7-f8ffe96a0d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332206619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.332206619
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2442046861
Short name T221
Test name
Test status
Simulation time 1735123468 ps
CPU time 28.38 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:57:22 PM PDT 24
Peak memory 200320 kb
Host smart-4c8090ca-e413-4b5e-997e-65b400387a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442046861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2442046861
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3393736688
Short name T437
Test name
Test status
Simulation time 5943150086 ps
CPU time 1119.4 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 07:15:29 PM PDT 24
Peak memory 689684 kb
Host smart-44a42f3a-5d4d-4a8b-a6cb-3665e9b691a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393736688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3393736688
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1070014821
Short name T34
Test name
Test status
Simulation time 600427887 ps
CPU time 17.23 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:57:27 PM PDT 24
Peak memory 200268 kb
Host smart-e4737178-e2e4-482f-953a-8cf5513e7464
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070014821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1070014821
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.222880262
Short name T360
Test name
Test status
Simulation time 5181930813 ps
CPU time 90.91 seconds
Started Jul 16 06:56:55 PM PDT 24
Finished Jul 16 06:58:27 PM PDT 24
Peak memory 200416 kb
Host smart-fcf8fca9-6fa8-4be6-9617-fe2e0d324cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222880262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.222880262
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1554561261
Short name T151
Test name
Test status
Simulation time 899537553 ps
CPU time 9.78 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:02 PM PDT 24
Peak memory 200244 kb
Host smart-78d466e8-4bbf-40a8-9e6c-c5f4e8213ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554561261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1554561261
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4264862888
Short name T278
Test name
Test status
Simulation time 171383802220 ps
CPU time 183.68 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:59:53 PM PDT 24
Peak memory 208756 kb
Host smart-1f4d0e18-17b4-470b-97ee-ec3072a59b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264862888 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4264862888
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.18289089
Short name T321
Test name
Test status
Simulation time 53409467809 ps
CPU time 64.4 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 200368 kb
Host smart-1f7fedf4-23cf-4560-af84-8fb8bd7eb7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18289089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.18289089
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3269776172
Short name T303
Test name
Test status
Simulation time 13557972 ps
CPU time 0.58 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 06:56:45 PM PDT 24
Peak memory 195948 kb
Host smart-dcf8b43c-e52e-42fc-8bef-db476fcebee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269776172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3269776172
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4224135249
Short name T313
Test name
Test status
Simulation time 1573780697 ps
CPU time 90.08 seconds
Started Jul 16 06:56:53 PM PDT 24
Finished Jul 16 06:58:25 PM PDT 24
Peak memory 200148 kb
Host smart-989b0869-3dcd-492f-983d-0e0e1b76ee99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224135249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4224135249
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.530033275
Short name T159
Test name
Test status
Simulation time 2719796597 ps
CPU time 49.74 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:57:43 PM PDT 24
Peak memory 200408 kb
Host smart-2cfa7f91-5608-4b56-96f1-b644fe23bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530033275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.530033275
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4271103884
Short name T442
Test name
Test status
Simulation time 2887829368 ps
CPU time 574.54 seconds
Started Jul 16 06:56:58 PM PDT 24
Finished Jul 16 07:06:33 PM PDT 24
Peak memory 726060 kb
Host smart-c15cdad4-702e-4758-975f-8fcd0ca6f2db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271103884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4271103884
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2775316600
Short name T160
Test name
Test status
Simulation time 2979951851 ps
CPU time 160.59 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:59:42 PM PDT 24
Peak memory 200120 kb
Host smart-4368060c-fe2d-4008-ab90-e63fbbe73de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775316600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2775316600
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1172075863
Short name T155
Test name
Test status
Simulation time 1628171274 ps
CPU time 48.08 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 06:57:43 PM PDT 24
Peak memory 200312 kb
Host smart-9e706e9d-28a9-4b17-ab10-594ff60b395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172075863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1172075863
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.192499313
Short name T171
Test name
Test status
Simulation time 2045964190 ps
CPU time 9.86 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:57:04 PM PDT 24
Peak memory 200316 kb
Host smart-6e0118e5-edbe-409c-b8ef-72df934cee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192499313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.192499313
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2729100581
Short name T230
Test name
Test status
Simulation time 69185467424 ps
CPU time 1757.9 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 07:26:30 PM PDT 24
Peak memory 687392 kb
Host smart-7d24e7fa-1d75-470b-8dbc-8fa7b0f78568
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729100581 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2729100581
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2859818176
Short name T431
Test name
Test status
Simulation time 10250036099 ps
CPU time 30.92 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 06:57:26 PM PDT 24
Peak memory 200268 kb
Host smart-3b64e235-2d86-4493-bbcf-205741565859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859818176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2859818176
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2353055844
Short name T395
Test name
Test status
Simulation time 15401101 ps
CPU time 0.6 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 06:56:52 PM PDT 24
Peak memory 195724 kb
Host smart-5a044733-a70f-43bd-9f7f-54e60b71ab96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353055844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2353055844
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2513124843
Short name T54
Test name
Test status
Simulation time 1854355362 ps
CPU time 113.26 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 200304 kb
Host smart-b3ed3e87-072a-4c12-82f9-51c3018b5af2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513124843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2513124843
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2649113435
Short name T359
Test name
Test status
Simulation time 236171922 ps
CPU time 12.86 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 200320 kb
Host smart-d8c38f86-4b6c-45af-9974-c533632d5529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649113435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2649113435
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4124946972
Short name T324
Test name
Test status
Simulation time 6615013319 ps
CPU time 1297.93 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 07:18:26 PM PDT 24
Peak memory 772324 kb
Host smart-c3a18390-81a4-45f4-adfc-01163f5d8a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124946972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4124946972
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3095052822
Short name T348
Test name
Test status
Simulation time 3941962182 ps
CPU time 70.16 seconds
Started Jul 16 06:56:59 PM PDT 24
Finished Jul 16 06:58:11 PM PDT 24
Peak memory 200352 kb
Host smart-81683584-d321-43e2-9593-a35bb8d8e1e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095052822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3095052822
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1094270282
Short name T463
Test name
Test status
Simulation time 17557212529 ps
CPU time 122.31 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:58:51 PM PDT 24
Peak memory 200580 kb
Host smart-97d6516e-d7ee-42fe-a4c0-8fbb430e783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094270282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1094270282
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2901973965
Short name T293
Test name
Test status
Simulation time 1166845121 ps
CPU time 5.71 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:56:55 PM PDT 24
Peak memory 200320 kb
Host smart-d137aa59-e126-4332-8285-c22830b0fd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901973965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2901973965
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.583607685
Short name T496
Test name
Test status
Simulation time 91615906 ps
CPU time 1.47 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:56:50 PM PDT 24
Peak memory 200284 kb
Host smart-78f222ef-888a-4505-ae7a-f99f452efd72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583607685 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.583607685
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3394286877
Short name T178
Test name
Test status
Simulation time 258130911 ps
CPU time 14.78 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:57:03 PM PDT 24
Peak memory 200228 kb
Host smart-a358e833-d380-4ce8-960b-4665ffad9613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394286877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3394286877
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1816920439
Short name T393
Test name
Test status
Simulation time 43022658 ps
CPU time 0.59 seconds
Started Jul 16 06:56:57 PM PDT 24
Finished Jul 16 06:56:59 PM PDT 24
Peak memory 195196 kb
Host smart-b12433b2-6224-44c1-a96a-e232d0d3ff95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816920439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1816920439
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2746871775
Short name T384
Test name
Test status
Simulation time 776956671 ps
CPU time 9.36 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:56:58 PM PDT 24
Peak memory 200332 kb
Host smart-81d9e81c-cab2-4986-b89b-3ec8ca12ae47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746871775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2746871775
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2457983963
Short name T236
Test name
Test status
Simulation time 8522841813 ps
CPU time 39.94 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:32 PM PDT 24
Peak memory 200348 kb
Host smart-9893afac-2669-413a-9a0f-273b2220e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457983963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2457983963
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2394813592
Short name T366
Test name
Test status
Simulation time 8008036918 ps
CPU time 1563.59 seconds
Started Jul 16 06:56:56 PM PDT 24
Finished Jul 16 07:23:00 PM PDT 24
Peak memory 789308 kb
Host smart-a0576ff6-b973-4b54-aba5-5d2e982d13f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394813592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2394813592
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.469755932
Short name T231
Test name
Test status
Simulation time 8914374961 ps
CPU time 109.4 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 200344 kb
Host smart-30f2d07f-711a-4b20-9544-efd1227ee3cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469755932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.469755932
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1875573616
Short name T427
Test name
Test status
Simulation time 7015953375 ps
CPU time 126.2 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:58:53 PM PDT 24
Peak memory 200368 kb
Host smart-74edcfd2-267f-4e80-8161-9d0e48b7151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875573616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1875573616
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.874145438
Short name T334
Test name
Test status
Simulation time 2573627793 ps
CPU time 7.09 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 06:56:51 PM PDT 24
Peak memory 200228 kb
Host smart-2fca1d1f-91c7-4ff9-8e60-ab0c98cfaca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874145438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.874145438
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2278573853
Short name T521
Test name
Test status
Simulation time 5457151780 ps
CPU time 5.66 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:56:56 PM PDT 24
Peak memory 200320 kb
Host smart-fa07171a-dac2-48e8-8bea-92b03f1c92fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278573853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2278573853
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1913488877
Short name T502
Test name
Test status
Simulation time 14435176 ps
CPU time 0.58 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:56:49 PM PDT 24
Peak memory 195064 kb
Host smart-ca03a571-73c2-468a-8e92-849a23537a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913488877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1913488877
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2709813538
Short name T351
Test name
Test status
Simulation time 96547782 ps
CPU time 2.92 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 06:56:58 PM PDT 24
Peak memory 200176 kb
Host smart-518b9c8b-940a-411c-be3f-9e807d5ae63d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709813538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2709813538
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4020494109
Short name T136
Test name
Test status
Simulation time 501826834 ps
CPU time 25.16 seconds
Started Jul 16 06:56:53 PM PDT 24
Finished Jul 16 06:57:19 PM PDT 24
Peak memory 200244 kb
Host smart-90386213-8448-4087-acab-0436832c5f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020494109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4020494109
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1707300026
Short name T451
Test name
Test status
Simulation time 2743594806 ps
CPU time 386.21 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 07:03:16 PM PDT 24
Peak memory 451520 kb
Host smart-c1119a09-8049-498b-b0e7-7ba73d3c4104
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707300026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1707300026
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4231827861
Short name T18
Test name
Test status
Simulation time 5533167434 ps
CPU time 102.65 seconds
Started Jul 16 06:56:46 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 200340 kb
Host smart-28ecaf99-c811-4788-99d6-9c6800aa9c26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231827861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4231827861
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.398812119
Short name T212
Test name
Test status
Simulation time 68270968106 ps
CPU time 141.71 seconds
Started Jul 16 06:56:58 PM PDT 24
Finished Jul 16 06:59:21 PM PDT 24
Peak memory 200352 kb
Host smart-339d511e-06a9-422a-b02b-10e35e344a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398812119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.398812119
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1477699604
Short name T322
Test name
Test status
Simulation time 962856115 ps
CPU time 16.61 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:10 PM PDT 24
Peak memory 200332 kb
Host smart-8a001416-1c8f-470f-8ad1-4ecd33ba3db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477699604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1477699604
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3078147379
Short name T469
Test name
Test status
Simulation time 9977670224 ps
CPU time 655.15 seconds
Started Jul 16 06:56:49 PM PDT 24
Finished Jul 16 07:07:46 PM PDT 24
Peak memory 617236 kb
Host smart-9f55f39d-8cb0-4ea5-ad27-e020f72d416d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078147379 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3078147379
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3453673925
Short name T473
Test name
Test status
Simulation time 1116297802 ps
CPU time 56.56 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200276 kb
Host smart-602a938c-c0c4-4ea9-9ae6-0a240bc26595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453673925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3453673925
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3237714030
Short name T454
Test name
Test status
Simulation time 32800139 ps
CPU time 0.66 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 196048 kb
Host smart-e58c9101-deef-441d-b14d-f9a321da4080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237714030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3237714030
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.629476412
Short name T68
Test name
Test status
Simulation time 639275791 ps
CPU time 37.38 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:57:31 PM PDT 24
Peak memory 200152 kb
Host smart-418cd7a2-ec85-4886-9564-896e0d9d4e8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629476412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.629476412
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.932471449
Short name T262
Test name
Test status
Simulation time 7919063087 ps
CPU time 35.57 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:28 PM PDT 24
Peak memory 200340 kb
Host smart-074c5115-3170-4970-9138-5f9bd770d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932471449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.932471449
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.989039175
Short name T268
Test name
Test status
Simulation time 42725893152 ps
CPU time 726.53 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 07:09:02 PM PDT 24
Peak memory 704572 kb
Host smart-2ba1d461-282a-4059-a20e-82daaeb41b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989039175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.989039175
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2807303738
Short name T418
Test name
Test status
Simulation time 18883867245 ps
CPU time 132.19 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:59:06 PM PDT 24
Peak memory 200312 kb
Host smart-0abae520-f85f-491c-a0e4-71a693fd73d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807303738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2807303738
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3801871680
Short name T35
Test name
Test status
Simulation time 2928764579 ps
CPU time 89.68 seconds
Started Jul 16 06:56:49 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 200288 kb
Host smart-e1442338-b487-469b-95aa-260e8fdbb213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801871680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3801871680
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2004092033
Short name T164
Test name
Test status
Simulation time 161336773 ps
CPU time 7.76 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 06:56:54 PM PDT 24
Peak memory 200228 kb
Host smart-bb32ec76-c856-4bcf-be0e-086784314e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004092033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2004092033
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2983484652
Short name T337
Test name
Test status
Simulation time 2206283502 ps
CPU time 54.59 seconds
Started Jul 16 06:56:55 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200376 kb
Host smart-4fc86d5f-2f5d-4fb9-afa9-75ec59094d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983484652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2983484652
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3548369455
Short name T11
Test name
Test status
Simulation time 1547138631 ps
CPU time 94.34 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:58:45 PM PDT 24
Peak memory 200280 kb
Host smart-9833975a-1bec-4f7c-8843-2f2d8e5067d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548369455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3548369455
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3495967219
Short name T314
Test name
Test status
Simulation time 2991355239 ps
CPU time 24.42 seconds
Started Jul 16 06:57:07 PM PDT 24
Finished Jul 16 06:57:34 PM PDT 24
Peak memory 200336 kb
Host smart-7d1fb465-dfed-41a9-bd51-4d76a8fb05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495967219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3495967219
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3622041544
Short name T172
Test name
Test status
Simulation time 3879909323 ps
CPU time 544.13 seconds
Started Jul 16 06:57:02 PM PDT 24
Finished Jul 16 07:06:07 PM PDT 24
Peak memory 701484 kb
Host smart-39709546-ec51-4025-bb22-c2badeb96ae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622041544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3622041544
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3761906556
Short name T282
Test name
Test status
Simulation time 5381558255 ps
CPU time 100.43 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 200300 kb
Host smart-747e90c2-0b15-4077-9aae-62e055e730e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761906556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3761906556
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1602551500
Short name T367
Test name
Test status
Simulation time 8921734632 ps
CPU time 54.15 seconds
Started Jul 16 06:57:14 PM PDT 24
Finished Jul 16 06:58:09 PM PDT 24
Peak memory 200348 kb
Host smart-32f18a8c-589a-46ca-a905-46fff2a20d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602551500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1602551500
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2985647880
Short name T392
Test name
Test status
Simulation time 170077979 ps
CPU time 7.65 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 06:57:19 PM PDT 24
Peak memory 200292 kb
Host smart-2346096b-b6ff-454c-a7bb-ee911b3f73ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985647880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2985647880
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4182464231
Short name T409
Test name
Test status
Simulation time 491712537126 ps
CPU time 2868.27 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 07:44:55 PM PDT 24
Peak memory 790788 kb
Host smart-c25f19f7-cfc3-4a84-bb8c-0417de1ef4c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182464231 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4182464231
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.35395211
Short name T37
Test name
Test status
Simulation time 9774859463 ps
CPU time 87.64 seconds
Started Jul 16 06:57:07 PM PDT 24
Finished Jul 16 06:58:37 PM PDT 24
Peak memory 200316 kb
Host smart-4b64de96-a80b-4f3f-8379-555c33d87af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35395211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.35395211
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.16795605
Short name T246
Test name
Test status
Simulation time 12461837 ps
CPU time 0.59 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 06:57:07 PM PDT 24
Peak memory 196248 kb
Host smart-4a6bfd1a-73b5-4788-a6f1-641b6ffce3fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16795605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.16795605
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1586430113
Short name T19
Test name
Test status
Simulation time 879969879 ps
CPU time 48.27 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200220 kb
Host smart-5cdc56e0-10ae-4832-a198-2a3cc6f2a15d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586430113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1586430113
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3401334246
Short name T412
Test name
Test status
Simulation time 378488134 ps
CPU time 19.24 seconds
Started Jul 16 06:57:07 PM PDT 24
Finished Jul 16 06:57:29 PM PDT 24
Peak memory 200248 kb
Host smart-e3db965b-6722-4e10-8563-a217b8321106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401334246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3401334246
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.985075439
Short name T163
Test name
Test status
Simulation time 5819889024 ps
CPU time 867.91 seconds
Started Jul 16 06:57:02 PM PDT 24
Finished Jul 16 07:11:31 PM PDT 24
Peak memory 733728 kb
Host smart-dd2aa6e1-6ec8-4da2-aeec-b851c3c06157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985075439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.985075439
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4023477542
Short name T193
Test name
Test status
Simulation time 31422087206 ps
CPU time 104.36 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:58:57 PM PDT 24
Peak memory 200328 kb
Host smart-d8231364-9c12-42e6-9828-061329caa7f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023477542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4023477542
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4202262361
Short name T237
Test name
Test status
Simulation time 12472203987 ps
CPU time 228.82 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 07:00:56 PM PDT 24
Peak memory 200336 kb
Host smart-9b34e15a-e15c-4ebb-bd1d-b78dc05abc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202262361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4202262361
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2410330258
Short name T309
Test name
Test status
Simulation time 345588899 ps
CPU time 15.35 seconds
Started Jul 16 06:57:03 PM PDT 24
Finished Jul 16 06:57:19 PM PDT 24
Peak memory 200344 kb
Host smart-9c3f7de5-bb00-450c-82f2-e08607cc8d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410330258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2410330258
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2342018668
Short name T518
Test name
Test status
Simulation time 24847399885 ps
CPU time 1498.64 seconds
Started Jul 16 06:57:06 PM PDT 24
Finished Jul 16 07:22:07 PM PDT 24
Peak memory 719060 kb
Host smart-084dbeca-91f4-4f57-a464-215a7e837014
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342018668 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2342018668
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4205048551
Short name T174
Test name
Test status
Simulation time 4501667608 ps
CPU time 29.48 seconds
Started Jul 16 06:57:03 PM PDT 24
Finished Jul 16 06:57:33 PM PDT 24
Peak memory 200336 kb
Host smart-9484ca81-e5a5-4ede-a3fd-b9edf0e3d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205048551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4205048551
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3091132367
Short name T265
Test name
Test status
Simulation time 85019408 ps
CPU time 0.6 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 196876 kb
Host smart-fb234e0b-41c5-4b5f-a553-21f91c29edf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091132367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3091132367
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.821258113
Short name T52
Test name
Test status
Simulation time 1635284212 ps
CPU time 92.51 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 200256 kb
Host smart-d5ce7e3d-1046-4fda-95c4-30f673087775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821258113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.821258113
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.895420746
Short name T283
Test name
Test status
Simulation time 7420217422 ps
CPU time 56.68 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:58:06 PM PDT 24
Peak memory 208548 kb
Host smart-2421f046-b143-48f7-8ae1-dedce1c7f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895420746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.895420746
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3717754973
Short name T233
Test name
Test status
Simulation time 26566947616 ps
CPU time 840.95 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 07:11:12 PM PDT 24
Peak memory 687004 kb
Host smart-dc5d8fd8-23be-4971-81f0-85853d30c6e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3717754973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3717754973
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.709166337
Short name T425
Test name
Test status
Simulation time 3689616229 ps
CPU time 52.69 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 200340 kb
Host smart-4d1365f9-43c8-490e-955a-0f10ba6e7b02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709166337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.709166337
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.215513900
Short name T422
Test name
Test status
Simulation time 2288323421 ps
CPU time 125.72 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:59:17 PM PDT 24
Peak memory 200244 kb
Host smart-4a9f216a-e238-40f4-a077-8e4956e21464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215513900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.215513900
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3495804364
Short name T125
Test name
Test status
Simulation time 939377239 ps
CPU time 12.29 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:57:22 PM PDT 24
Peak memory 200244 kb
Host smart-f99d5ced-e2f4-483a-88ee-2f7f97c8a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495804364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3495804364
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3107087180
Short name T391
Test name
Test status
Simulation time 71905364239 ps
CPU time 223.67 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 07:00:51 PM PDT 24
Peak memory 216704 kb
Host smart-bfa2d7a8-a06e-4fa2-a2af-a55212047cf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107087180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3107087180
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3283895249
Short name T176
Test name
Test status
Simulation time 3211973163 ps
CPU time 25.53 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:57:36 PM PDT 24
Peak memory 200260 kb
Host smart-092f13cc-5897-4173-801f-40deda9b498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283895249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3283895249
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3359231656
Short name T238
Test name
Test status
Simulation time 61357961 ps
CPU time 0.59 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 06:56:45 PM PDT 24
Peak memory 196196 kb
Host smart-541f6f42-6fcc-4c02-af2d-ce7af45c03ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359231656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3359231656
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.426248998
Short name T407
Test name
Test status
Simulation time 303081799 ps
CPU time 18.25 seconds
Started Jul 16 06:56:42 PM PDT 24
Finished Jul 16 06:57:01 PM PDT 24
Peak memory 200520 kb
Host smart-9fd20828-dbde-4a44-a693-f2addc9aff46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426248998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.426248998
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2887609413
Short name T443
Test name
Test status
Simulation time 2477139516 ps
CPU time 33.79 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 06:57:18 PM PDT 24
Peak memory 200412 kb
Host smart-db652fba-c249-4de1-a372-ef67494574c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887609413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2887609413
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.152909467
Short name T308
Test name
Test status
Simulation time 8277478612 ps
CPU time 820.35 seconds
Started Jul 16 06:56:37 PM PDT 24
Finished Jul 16 07:10:19 PM PDT 24
Peak memory 725832 kb
Host smart-885879f0-eb38-4c28-a6bb-5a7441e7fcc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152909467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.152909467
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2429656918
Short name T276
Test name
Test status
Simulation time 14314206177 ps
CPU time 53.14 seconds
Started Jul 16 06:56:29 PM PDT 24
Finished Jul 16 06:57:25 PM PDT 24
Peak memory 200408 kb
Host smart-38eed847-079f-43fa-901c-39be4434f79a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429656918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2429656918
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1935377262
Short name T386
Test name
Test status
Simulation time 296906111 ps
CPU time 4.81 seconds
Started Jul 16 06:56:35 PM PDT 24
Finished Jul 16 06:56:41 PM PDT 24
Peak memory 200156 kb
Host smart-6ae6ad01-b875-4648-aadf-f4aa2018fe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935377262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1935377262
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.2288454876
Short name T333
Test name
Test status
Simulation time 30792610 ps
CPU time 0.69 seconds
Started Jul 16 06:56:36 PM PDT 24
Finished Jul 16 06:56:37 PM PDT 24
Peak memory 196736 kb
Host smart-d0975d35-09d9-431b-9e90-82ca98f8b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288454876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2288454876
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3192609437
Short name T491
Test name
Test status
Simulation time 39794580725 ps
CPU time 577.73 seconds
Started Jul 16 06:56:43 PM PDT 24
Finished Jul 16 07:06:21 PM PDT 24
Peak memory 231460 kb
Host smart-a1b5581e-ccd8-4273-9703-f58749783ff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192609437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3192609437
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.409572492
Short name T14
Test name
Test status
Simulation time 114103496148 ps
CPU time 1287.28 seconds
Started Jul 16 06:56:37 PM PDT 24
Finished Jul 16 07:18:06 PM PDT 24
Peak memory 729480 kb
Host smart-63d9833b-f2ea-4aa8-adca-8e5c2524f97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409572492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.409572492
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3513754981
Short name T318
Test name
Test status
Simulation time 13056087283 ps
CPU time 43.02 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200300 kb
Host smart-049488ff-8e5b-4045-81e5-ce824e0c044b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3513754981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3513754981
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2853360135
Short name T376
Test name
Test status
Simulation time 6666352013 ps
CPU time 55.87 seconds
Started Jul 16 06:56:46 PM PDT 24
Finished Jul 16 06:57:43 PM PDT 24
Peak memory 200336 kb
Host smart-7f219631-9023-4597-b272-b8a401326a26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2853360135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2853360135
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3169807828
Short name T340
Test name
Test status
Simulation time 5715645434 ps
CPU time 85.83 seconds
Started Jul 16 06:56:32 PM PDT 24
Finished Jul 16 06:57:59 PM PDT 24
Peak memory 200400 kb
Host smart-d700499d-fec4-4f18-a04d-ab06dbfc796f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3169807828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3169807828
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2966138241
Short name T243
Test name
Test status
Simulation time 42090764130 ps
CPU time 595.11 seconds
Started Jul 16 06:56:31 PM PDT 24
Finished Jul 16 07:06:28 PM PDT 24
Peak memory 200252 kb
Host smart-3bf12273-b7af-49eb-ac30-0964bb47de02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2966138241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2966138241
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.4212651931
Short name T267
Test name
Test status
Simulation time 41761474186 ps
CPU time 2333.85 seconds
Started Jul 16 06:56:37 PM PDT 24
Finished Jul 16 07:35:32 PM PDT 24
Peak memory 216160 kb
Host smart-e592e5d6-779b-4738-a787-78adf0ff9671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4212651931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.4212651931
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1424866682
Short name T229
Test name
Test status
Simulation time 199519325094 ps
CPU time 2395.03 seconds
Started Jul 16 06:56:31 PM PDT 24
Finished Jul 16 07:36:28 PM PDT 24
Peak memory 216464 kb
Host smart-980f3e5f-c776-40c4-8587-efe42724098b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424866682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1424866682
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.55268667
Short name T331
Test name
Test status
Simulation time 3380069988 ps
CPU time 97.03 seconds
Started Jul 16 06:56:42 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 200380 kb
Host smart-eedbb157-fccf-45bc-95cf-6580b53982dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55268667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.55268667
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4057309335
Short name T199
Test name
Test status
Simulation time 44598089 ps
CPU time 0.59 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:57:13 PM PDT 24
Peak memory 195772 kb
Host smart-50403f74-83ee-46b4-8a03-24ce3786a144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057309335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4057309335
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.809045368
Short name T175
Test name
Test status
Simulation time 1408403288 ps
CPU time 40.03 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:57:53 PM PDT 24
Peak memory 200312 kb
Host smart-ff0140dc-92ef-42a0-94d1-8e1225a062b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809045368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.809045368
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3601149453
Short name T152
Test name
Test status
Simulation time 16371767379 ps
CPU time 44.76 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:57:58 PM PDT 24
Peak memory 200548 kb
Host smart-3e517e0b-0595-4666-a03b-1f0c17980198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601149453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3601149453
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2114636848
Short name T346
Test name
Test status
Simulation time 16374552961 ps
CPU time 664.32 seconds
Started Jul 16 06:57:03 PM PDT 24
Finished Jul 16 07:08:08 PM PDT 24
Peak memory 670704 kb
Host smart-e4b5d0b7-b7b6-4f05-8942-eeb10e68bbd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114636848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2114636848
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4281535601
Short name T256
Test name
Test status
Simulation time 10101334165 ps
CPU time 143.2 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 06:59:29 PM PDT 24
Peak memory 200336 kb
Host smart-79b651f2-e4ea-43c6-9bbc-d7e1e4ab2b50
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281535601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4281535601
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.128411105
Short name T373
Test name
Test status
Simulation time 3860559068 ps
CPU time 18.34 seconds
Started Jul 16 06:57:02 PM PDT 24
Finished Jul 16 06:57:21 PM PDT 24
Peak memory 200260 kb
Host smart-f4c13198-6760-422c-bc40-2ee078f8efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128411105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.128411105
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2962415152
Short name T245
Test name
Test status
Simulation time 489830597 ps
CPU time 6.67 seconds
Started Jul 16 06:57:03 PM PDT 24
Finished Jul 16 06:57:10 PM PDT 24
Peak memory 200364 kb
Host smart-8939f20c-cd61-40bf-8e64-ff7afbffdbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962415152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2962415152
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3160567966
Short name T76
Test name
Test status
Simulation time 1624479342185 ps
CPU time 1556.68 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 07:23:08 PM PDT 24
Peak memory 747712 kb
Host smart-70ff7bd8-b27a-436d-be60-1985792ccf07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160567966 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3160567966
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1444915573
Short name T332
Test name
Test status
Simulation time 7120169677 ps
CPU time 66.53 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 200316 kb
Host smart-00f884b5-fef3-4b83-a2b3-e932401d28f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444915573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1444915573
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3298151971
Short name T291
Test name
Test status
Simulation time 11437356 ps
CPU time 0.6 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 06:57:06 PM PDT 24
Peak memory 196232 kb
Host smart-b77256aa-59a7-4240-8100-c6a516178f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298151971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3298151971
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.26361446
Short name T217
Test name
Test status
Simulation time 1669808044 ps
CPU time 97.92 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 06:58:43 PM PDT 24
Peak memory 200300 kb
Host smart-9d54429f-1b0b-44de-965b-fb98e17fd2a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26361446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.26361446
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3775881440
Short name T127
Test name
Test status
Simulation time 10134364771 ps
CPU time 39.27 seconds
Started Jul 16 06:57:03 PM PDT 24
Finished Jul 16 06:57:43 PM PDT 24
Peak memory 200336 kb
Host smart-d7eebda6-82d5-4d6c-9f7e-7aea61da3416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775881440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3775881440
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_error.2978630477
Short name T300
Test name
Test status
Simulation time 4218621346 ps
CPU time 20.96 seconds
Started Jul 16 06:57:11 PM PDT 24
Finished Jul 16 06:57:34 PM PDT 24
Peak memory 200220 kb
Host smart-d537fbef-eafe-4e5b-a27f-91dd40a00c8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978630477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2978630477
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.363299835
Short name T453
Test name
Test status
Simulation time 15043597941 ps
CPU time 55.55 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:58:03 PM PDT 24
Peak memory 200332 kb
Host smart-ca887a29-c77c-4e30-b391-018f48a3209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363299835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.363299835
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2509947767
Short name T438
Test name
Test status
Simulation time 851171085 ps
CPU time 8.55 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:15 PM PDT 24
Peak memory 200224 kb
Host smart-45b22aad-0245-4135-9f3a-eb4dd6207303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509947767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2509947767
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2231736027
Short name T75
Test name
Test status
Simulation time 32380365789 ps
CPU time 410.35 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 07:03:56 PM PDT 24
Peak memory 216708 kb
Host smart-ae8cc369-11e7-4eec-a09d-880700219121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231736027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2231736027
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.432958121
Short name T84
Test name
Test status
Simulation time 35684679619 ps
CPU time 115.9 seconds
Started Jul 16 06:57:02 PM PDT 24
Finished Jul 16 06:58:59 PM PDT 24
Peak memory 200376 kb
Host smart-d7428602-100a-412e-ade5-083382266b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432958121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.432958121
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1873631272
Short name T357
Test name
Test status
Simulation time 13484052 ps
CPU time 0.57 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:57:14 PM PDT 24
Peak memory 195804 kb
Host smart-c70bcc9f-1577-42cd-94c1-13aef94bb0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873631272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1873631272
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1291879601
Short name T476
Test name
Test status
Simulation time 2202550025 ps
CPU time 9.87 seconds
Started Jul 16 06:57:04 PM PDT 24
Finished Jul 16 06:57:15 PM PDT 24
Peak memory 200364 kb
Host smart-5eb29775-26b0-46c1-8067-39485db40dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291879601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1291879601
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.425971722
Short name T328
Test name
Test status
Simulation time 17646797165 ps
CPU time 1033.04 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 07:14:36 PM PDT 24
Peak memory 728520 kb
Host smart-c8aea803-67f3-4f61-840c-5ff5135f1270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425971722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.425971722
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3609273890
Short name T490
Test name
Test status
Simulation time 21821226526 ps
CPU time 197.93 seconds
Started Jul 16 06:57:11 PM PDT 24
Finished Jul 16 07:00:30 PM PDT 24
Peak memory 200356 kb
Host smart-dd44b48f-e773-412d-a6f5-e2daf05f7f73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609273890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3609273890
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3153674407
Short name T195
Test name
Test status
Simulation time 2620473051 ps
CPU time 47.59 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:57:59 PM PDT 24
Peak memory 200360 kb
Host smart-e82e5197-55ef-46e4-92b7-8deca823a866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153674407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3153674407
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2989338947
Short name T485
Test name
Test status
Simulation time 105221574 ps
CPU time 2.08 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:57:16 PM PDT 24
Peak memory 200312 kb
Host smart-c6fac738-03e2-4010-8920-41574d94cecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989338947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2989338947
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3134865352
Short name T197
Test name
Test status
Simulation time 3633809737 ps
CPU time 72.5 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 06:58:24 PM PDT 24
Peak memory 200340 kb
Host smart-b1e79375-fcfd-4ba0-bc07-92e8385a3aa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134865352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3134865352
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.86561310
Short name T475
Test name
Test status
Simulation time 7334260392 ps
CPU time 95.35 seconds
Started Jul 16 06:57:11 PM PDT 24
Finished Jul 16 06:58:48 PM PDT 24
Peak memory 200348 kb
Host smart-a6056bad-51f6-4058-aeb6-28146d7ce6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86561310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.86561310
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3151996357
Short name T429
Test name
Test status
Simulation time 34213081 ps
CPU time 0.59 seconds
Started Jul 16 06:57:07 PM PDT 24
Finished Jul 16 06:57:10 PM PDT 24
Peak memory 195188 kb
Host smart-185b8161-a27c-4c73-b473-be509666a0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151996357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3151996357
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.353283605
Short name T156
Test name
Test status
Simulation time 729742329 ps
CPU time 39.07 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:57:49 PM PDT 24
Peak memory 200248 kb
Host smart-e4e3e324-e50e-4610-a5fb-77b4d4d6e59f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353283605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.353283605
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4033314075
Short name T134
Test name
Test status
Simulation time 599124645 ps
CPU time 30.39 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:38 PM PDT 24
Peak memory 200276 kb
Host smart-ee40c850-3e98-4fe7-97d9-f88711ba5100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033314075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4033314075
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.323446819
Short name T441
Test name
Test status
Simulation time 79537628 ps
CPU time 1.3 seconds
Started Jul 16 06:57:06 PM PDT 24
Finished Jul 16 06:57:10 PM PDT 24
Peak memory 200160 kb
Host smart-ba85b103-779f-48ff-9735-1d91f47c83a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323446819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.323446819
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2737034943
Short name T260
Test name
Test status
Simulation time 21001980187 ps
CPU time 66.4 seconds
Started Jul 16 06:57:00 PM PDT 24
Finished Jul 16 06:58:07 PM PDT 24
Peak memory 200540 kb
Host smart-8fa8947a-24f4-4710-8b37-29b7e941569d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737034943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2737034943
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2718195852
Short name T292
Test name
Test status
Simulation time 15489808276 ps
CPU time 98.73 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:58:45 PM PDT 24
Peak memory 200288 kb
Host smart-9cdf1b95-1015-4017-a16c-5774c7cf0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718195852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2718195852
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2080322701
Short name T204
Test name
Test status
Simulation time 112336830 ps
CPU time 4.21 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:57:16 PM PDT 24
Peak memory 200332 kb
Host smart-56a7357a-37fd-48ed-a08b-c9a3e810840d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080322701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2080322701
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3415261569
Short name T464
Test name
Test status
Simulation time 89823461825 ps
CPU time 2441.38 seconds
Started Jul 16 06:57:00 PM PDT 24
Finished Jul 16 07:37:42 PM PDT 24
Peak memory 812660 kb
Host smart-8574a55d-a820-4159-ab40-9696bec6da16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415261569 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3415261569
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1048588504
Short name T341
Test name
Test status
Simulation time 7567637329 ps
CPU time 135.85 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:59:23 PM PDT 24
Peak memory 200376 kb
Host smart-2bcc028b-4ee5-4112-9d69-4173064930f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048588504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1048588504
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1546141239
Short name T372
Test name
Test status
Simulation time 14480323 ps
CPU time 0.6 seconds
Started Jul 16 06:57:11 PM PDT 24
Finished Jul 16 06:57:13 PM PDT 24
Peak memory 196868 kb
Host smart-20865f81-5a4c-4cd6-9814-ffb0b7108826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546141239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1546141239
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1147992232
Short name T161
Test name
Test status
Simulation time 8383029360 ps
CPU time 35.29 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:57:47 PM PDT 24
Peak memory 199920 kb
Host smart-a19fc329-22c8-4e93-ba81-02af36216f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147992232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1147992232
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4115307344
Short name T404
Test name
Test status
Simulation time 14006204987 ps
CPU time 677.63 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 07:08:24 PM PDT 24
Peak memory 694976 kb
Host smart-e1258b84-055b-406d-b88a-61f58c29e812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115307344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4115307344
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1094626833
Short name T361
Test name
Test status
Simulation time 952486838 ps
CPU time 16.56 seconds
Started Jul 16 06:57:14 PM PDT 24
Finished Jul 16 06:57:32 PM PDT 24
Peak memory 200312 kb
Host smart-460c1b9b-4641-4364-8ec4-9c6af14d573c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094626833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1094626833
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1261760518
Short name T378
Test name
Test status
Simulation time 9857705554 ps
CPU time 172.84 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 07:00:05 PM PDT 24
Peak memory 208472 kb
Host smart-237369e5-ac21-49dc-bf32-df1b10edbf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261760518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1261760518
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1007143073
Short name T462
Test name
Test status
Simulation time 490999591 ps
CPU time 11.15 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:18 PM PDT 24
Peak memory 200180 kb
Host smart-47e3335c-34a7-4097-aed1-beb71278d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007143073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1007143073
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.458734831
Short name T467
Test name
Test status
Simulation time 5934333161 ps
CPU time 73.04 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 200336 kb
Host smart-6b92ef33-8d8a-4493-8907-d688cf756d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458734831 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.458734831
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3093278487
Short name T220
Test name
Test status
Simulation time 951411556 ps
CPU time 16.39 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:23 PM PDT 24
Peak memory 200192 kb
Host smart-20a75503-4926-4aa0-a204-727e1c555dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093278487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3093278487
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2298708392
Short name T211
Test name
Test status
Simulation time 57403002 ps
CPU time 0.6 seconds
Started Jul 16 06:57:14 PM PDT 24
Finished Jul 16 06:57:16 PM PDT 24
Peak memory 196144 kb
Host smart-e2753d65-3e83-45b7-9472-a5f1c34b9584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298708392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2298708392
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.571552885
Short name T379
Test name
Test status
Simulation time 478577331 ps
CPU time 21.38 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 06:57:32 PM PDT 24
Peak memory 200224 kb
Host smart-d0fc935e-bb9f-47e8-a30f-84674e4c85d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571552885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.571552885
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1295667437
Short name T50
Test name
Test status
Simulation time 2930365722 ps
CPU time 43.03 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200240 kb
Host smart-44ff8af0-1de6-4cff-8a82-8c832c0e77d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295667437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1295667437
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4074594395
Short name T170
Test name
Test status
Simulation time 3121463837 ps
CPU time 281.6 seconds
Started Jul 16 06:57:07 PM PDT 24
Finished Jul 16 07:01:50 PM PDT 24
Peak memory 644456 kb
Host smart-9c07e2da-17dc-4f43-8195-5e89f0daf86c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074594395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4074594395
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.225341949
Short name T254
Test name
Test status
Simulation time 14985990042 ps
CPU time 55.15 seconds
Started Jul 16 06:57:07 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 200208 kb
Host smart-bf634fcb-4026-4582-8993-3b5a7135c638
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225341949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.225341949
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1544269014
Short name T188
Test name
Test status
Simulation time 504391981 ps
CPU time 6.96 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 06:57:17 PM PDT 24
Peak memory 200196 kb
Host smart-892433fd-8dae-4825-9299-a8027c57a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544269014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1544269014
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2402524580
Short name T492
Test name
Test status
Simulation time 346020815 ps
CPU time 1.85 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 200316 kb
Host smart-2584997d-e216-4e7e-805a-d21795b2e7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402524580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2402524580
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.988158045
Short name T405
Test name
Test status
Simulation time 29680436778 ps
CPU time 276.27 seconds
Started Jul 16 06:57:14 PM PDT 24
Finished Jul 16 07:01:51 PM PDT 24
Peak memory 545276 kb
Host smart-1d141caa-8184-4783-a47e-010812ed6bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988158045 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.988158045
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.301992893
Short name T352
Test name
Test status
Simulation time 29898267021 ps
CPU time 103.71 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 06:58:56 PM PDT 24
Peak memory 200308 kb
Host smart-0656f270-3982-43a5-a2f8-f528647d7983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301992893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.301992893
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2831328646
Short name T365
Test name
Test status
Simulation time 12517249 ps
CPU time 0.57 seconds
Started Jul 16 06:57:06 PM PDT 24
Finished Jul 16 06:57:09 PM PDT 24
Peak memory 196896 kb
Host smart-6e70181b-a65a-4f57-95b8-428bcda38e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831328646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2831328646
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1714493651
Short name T497
Test name
Test status
Simulation time 959920265 ps
CPU time 53.28 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 200232 kb
Host smart-ae7d1c97-a384-4773-8c9c-01fb407eaaeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714493651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1714493651
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3978164540
Short name T355
Test name
Test status
Simulation time 999837884 ps
CPU time 17.6 seconds
Started Jul 16 06:57:11 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200224 kb
Host smart-ffdc545a-a981-4da1-b7ff-0c5b040988bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978164540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3978164540
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3658998310
Short name T17
Test name
Test status
Simulation time 3437167231 ps
CPU time 548.83 seconds
Started Jul 16 06:57:10 PM PDT 24
Finished Jul 16 07:06:21 PM PDT 24
Peak memory 664172 kb
Host smart-6feffab7-b699-47a7-9c55-ec42b4d675df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658998310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3658998310
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3575881465
Short name T484
Test name
Test status
Simulation time 16789397441 ps
CPU time 192.56 seconds
Started Jul 16 06:57:08 PM PDT 24
Finished Jul 16 07:00:22 PM PDT 24
Peak memory 200360 kb
Host smart-2d68a971-dd4e-40b4-91f9-ee7ec65c953b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575881465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3575881465
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3005809703
Short name T388
Test name
Test status
Simulation time 55831462087 ps
CPU time 167.39 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:59:55 PM PDT 24
Peak memory 200400 kb
Host smart-e46213b2-babb-4e9c-9812-e04344181486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005809703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3005809703
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4078528369
Short name T383
Test name
Test status
Simulation time 1151401872 ps
CPU time 14.14 seconds
Started Jul 16 06:57:06 PM PDT 24
Finished Jul 16 06:57:22 PM PDT 24
Peak memory 200172 kb
Host smart-5b085b62-637d-4ce3-aa46-101b9fbb926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078528369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4078528369
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1022996826
Short name T457
Test name
Test status
Simulation time 138197699138 ps
CPU time 4837.85 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 08:17:51 PM PDT 24
Peak memory 841308 kb
Host smart-9ff94623-32f2-48d9-8348-edae212fff6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022996826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1022996826
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4067560532
Short name T110
Test name
Test status
Simulation time 8397422138 ps
CPU time 52.03 seconds
Started Jul 16 06:57:12 PM PDT 24
Finished Jul 16 06:58:06 PM PDT 24
Peak memory 200316 kb
Host smart-1d8d9e1d-6986-40a9-8718-a7852517ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067560532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4067560532
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3200822777
Short name T450
Test name
Test status
Simulation time 36482754 ps
CPU time 0.61 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:28 PM PDT 24
Peak memory 196124 kb
Host smart-1204be79-6965-4c1d-8801-e5336039ae28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200822777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3200822777
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.161389815
Short name T281
Test name
Test status
Simulation time 5870660690 ps
CPU time 84.75 seconds
Started Jul 16 06:57:11 PM PDT 24
Finished Jul 16 06:58:37 PM PDT 24
Peak memory 200356 kb
Host smart-73e52be5-90be-4332-8d5e-14df851db920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161389815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.161389815
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.241576930
Short name T435
Test name
Test status
Simulation time 437487628 ps
CPU time 12.17 seconds
Started Jul 16 06:57:09 PM PDT 24
Finished Jul 16 06:57:23 PM PDT 24
Peak memory 200320 kb
Host smart-917cb8d2-bd56-4312-94ec-d30e440cd192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241576930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.241576930
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2831769894
Short name T279
Test name
Test status
Simulation time 21229486312 ps
CPU time 987.62 seconds
Started Jul 16 06:57:16 PM PDT 24
Finished Jul 16 07:13:45 PM PDT 24
Peak memory 686668 kb
Host smart-294b8707-c6b4-45a6-8325-9bdf7d05b9ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831769894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2831769894
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2803744537
Short name T385
Test name
Test status
Simulation time 799426921 ps
CPU time 43.36 seconds
Started Jul 16 06:57:06 PM PDT 24
Finished Jul 16 06:57:52 PM PDT 24
Peak memory 200248 kb
Host smart-552fc8b2-5476-4937-ba32-575433aadfcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803744537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2803744537
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.17174784
Short name T67
Test name
Test status
Simulation time 1733811968 ps
CPU time 6.16 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:14 PM PDT 24
Peak memory 200316 kb
Host smart-30f8c587-4bf4-403c-87e7-4d11a6ce94ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17174784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.17174784
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.531882979
Short name T43
Test name
Test status
Simulation time 251547405 ps
CPU time 11.74 seconds
Started Jul 16 06:57:05 PM PDT 24
Finished Jul 16 06:57:19 PM PDT 24
Peak memory 200368 kb
Host smart-0c8bd87d-4dd8-4210-99b3-0b5f9e7f8b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531882979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.531882979
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3844857754
Short name T399
Test name
Test status
Simulation time 894547086 ps
CPU time 14.32 seconds
Started Jul 16 06:57:14 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200220 kb
Host smart-59690453-aad6-49c3-a4dd-3b1917c5f94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844857754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3844857754
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3008828749
Short name T439
Test name
Test status
Simulation time 40883151208 ps
CPU time 126.86 seconds
Started Jul 16 06:57:13 PM PDT 24
Finished Jul 16 06:59:21 PM PDT 24
Peak memory 200376 kb
Host smart-ec42b280-c3c6-41ba-b769-e47fd72ddbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008828749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3008828749
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.764852977
Short name T225
Test name
Test status
Simulation time 39839336 ps
CPU time 0.57 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 06:57:25 PM PDT 24
Peak memory 196752 kb
Host smart-bee2b918-c5b6-4313-a8ad-ca28e97270ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764852977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.764852977
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4019477156
Short name T401
Test name
Test status
Simulation time 6550089320 ps
CPU time 90.52 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:58:53 PM PDT 24
Peak memory 200380 kb
Host smart-331488c2-812a-4178-8f29-e66427e0509b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019477156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4019477156
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3073443545
Short name T53
Test name
Test status
Simulation time 1243270493 ps
CPU time 67.01 seconds
Started Jul 16 06:57:15 PM PDT 24
Finished Jul 16 06:58:23 PM PDT 24
Peak memory 200332 kb
Host smart-c1ccbaa4-f8bb-4b8b-ad72-9aebf89a0481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073443545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3073443545
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1972916806
Short name T162
Test name
Test status
Simulation time 7560160610 ps
CPU time 1402.21 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 07:20:46 PM PDT 24
Peak memory 783544 kb
Host smart-3230ac2f-16fc-4b28-a101-a09745d65e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972916806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1972916806
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3538468559
Short name T522
Test name
Test status
Simulation time 3973613909 ps
CPU time 26.48 seconds
Started Jul 16 06:57:24 PM PDT 24
Finished Jul 16 06:57:53 PM PDT 24
Peak memory 200348 kb
Host smart-0246581e-57f7-4d02-aab3-28460d1d871c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538468559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3538468559
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3209255540
Short name T277
Test name
Test status
Simulation time 34761365818 ps
CPU time 108.39 seconds
Started Jul 16 06:57:17 PM PDT 24
Finished Jul 16 06:59:07 PM PDT 24
Peak memory 200300 kb
Host smart-97bb0c56-864f-47e5-8c9b-8cc27ec09499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209255540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3209255540
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.581898004
Short name T345
Test name
Test status
Simulation time 5103451335 ps
CPU time 17.23 seconds
Started Jul 16 06:57:15 PM PDT 24
Finished Jul 16 06:57:34 PM PDT 24
Peak memory 200400 kb
Host smart-e8cfe1bc-e3ef-4242-957e-2aa529e0bc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581898004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.581898004
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.354915286
Short name T42
Test name
Test status
Simulation time 3643272731 ps
CPU time 84.23 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:58:45 PM PDT 24
Peak memory 200404 kb
Host smart-3535a6ea-8d0b-4ede-8db2-535034b218f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354915286 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.354915286
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1876826484
Short name T168
Test name
Test status
Simulation time 8180267157 ps
CPU time 101.09 seconds
Started Jul 16 06:57:19 PM PDT 24
Finished Jul 16 06:59:01 PM PDT 24
Peak memory 200324 kb
Host smart-196a9211-e531-484a-8f29-b29d19503300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876826484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1876826484
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.384388202
Short name T207
Test name
Test status
Simulation time 29931207 ps
CPU time 0.6 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:57:22 PM PDT 24
Peak memory 196148 kb
Host smart-539c7472-beb0-41cd-9eab-ee585c80a9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384388202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.384388202
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.305636425
Short name T169
Test name
Test status
Simulation time 665431145 ps
CPU time 37.16 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:57:59 PM PDT 24
Peak memory 200208 kb
Host smart-14e41a47-e175-4627-9ddf-c23a56fa00df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305636425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.305636425
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1600940133
Short name T515
Test name
Test status
Simulation time 605112025 ps
CPU time 32.24 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:57:53 PM PDT 24
Peak memory 200276 kb
Host smart-daa4690f-259f-4c0f-9b05-b609030f5a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600940133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1600940133
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2814948455
Short name T286
Test name
Test status
Simulation time 3782204293 ps
CPU time 300.43 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 07:02:26 PM PDT 24
Peak memory 592072 kb
Host smart-696a959a-7904-4ade-8581-1b38fb2cfb71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814948455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2814948455
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2803606847
Short name T250
Test name
Test status
Simulation time 4828531662 ps
CPU time 75.95 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 200260 kb
Host smart-dc054a04-a67c-4cad-8f7c-318df59f51b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803606847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2803606847
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3788520254
Short name T167
Test name
Test status
Simulation time 8600830105 ps
CPU time 38.84 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 200364 kb
Host smart-2c99e916-f516-4d81-9cea-3e7e1201f7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788520254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3788520254
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.977944678
Short name T240
Test name
Test status
Simulation time 407866673 ps
CPU time 5.43 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:33 PM PDT 24
Peak memory 200228 kb
Host smart-a6a6c847-5807-4bcc-9685-ca379dac6d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977944678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.977944678
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4253166960
Short name T326
Test name
Test status
Simulation time 426779324 ps
CPU time 4.7 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200136 kb
Host smart-4886033d-4b0f-4ed0-a10e-c00f5087d352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253166960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4253166960
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2931556157
Short name T488
Test name
Test status
Simulation time 9854304207 ps
CPU time 32.63 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 06:57:52 PM PDT 24
Peak memory 200272 kb
Host smart-e4631a6e-1686-4ab8-94e0-8caed5aa6b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931556157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2931556157
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2005103703
Short name T16
Test name
Test status
Simulation time 22495479 ps
CPU time 0.56 seconds
Started Jul 16 06:56:35 PM PDT 24
Finished Jul 16 06:56:36 PM PDT 24
Peak memory 195040 kb
Host smart-ced20d18-d464-4477-a985-56782331c32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005103703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2005103703
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3865677894
Short name T33
Test name
Test status
Simulation time 1495510482 ps
CPU time 88.63 seconds
Started Jul 16 06:56:32 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 200356 kb
Host smart-30375b21-ed6d-4b4a-9f7b-0051cfe04062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865677894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3865677894
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3896172931
Short name T287
Test name
Test status
Simulation time 1987602000 ps
CPU time 50.53 seconds
Started Jul 16 06:56:31 PM PDT 24
Finished Jul 16 06:57:23 PM PDT 24
Peak memory 200272 kb
Host smart-a2fe9231-e239-4d05-9b6d-01d901fc3c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896172931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3896172931
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2973664563
Short name T503
Test name
Test status
Simulation time 909620277 ps
CPU time 133.92 seconds
Started Jul 16 06:56:35 PM PDT 24
Finished Jul 16 06:58:49 PM PDT 24
Peak memory 440132 kb
Host smart-859ce73b-e262-4ffd-82d1-c55e02f5864c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973664563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2973664563
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2277701908
Short name T166
Test name
Test status
Simulation time 18106209499 ps
CPU time 71.9 seconds
Started Jul 16 06:56:30 PM PDT 24
Finished Jul 16 06:57:44 PM PDT 24
Peak memory 200332 kb
Host smart-527355d9-6d30-4e6b-b435-66a957a3d757
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277701908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2277701908
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3537529317
Short name T514
Test name
Test status
Simulation time 9283136838 ps
CPU time 123.32 seconds
Started Jul 16 06:56:34 PM PDT 24
Finished Jul 16 06:58:38 PM PDT 24
Peak memory 216672 kb
Host smart-3be3255e-8120-4f85-bb6c-3d0aba44bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537529317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3537529317
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.336077929
Short name T15
Test name
Test status
Simulation time 147015627 ps
CPU time 0.93 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 06:56:52 PM PDT 24
Peak memory 219488 kb
Host smart-1a89962b-684d-422b-a4ca-6ac13ce9b7f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336077929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.336077929
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.416112475
Short name T353
Test name
Test status
Simulation time 274319088 ps
CPU time 3.02 seconds
Started Jul 16 06:56:46 PM PDT 24
Finished Jul 16 06:56:50 PM PDT 24
Peak memory 200240 kb
Host smart-6ae4b63e-b309-42fd-9708-c6084b30d9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416112475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.416112475
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3263765791
Short name T121
Test name
Test status
Simulation time 5105318835 ps
CPU time 15.57 seconds
Started Jul 16 06:56:30 PM PDT 24
Finished Jul 16 06:56:48 PM PDT 24
Peak memory 200348 kb
Host smart-62396843-81be-494c-8717-add0a56e8799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263765791 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3263765791
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1890948447
Short name T66
Test name
Test status
Simulation time 302488448907 ps
CPU time 1480.9 seconds
Started Jul 16 06:56:29 PM PDT 24
Finished Jul 16 07:21:13 PM PDT 24
Peak memory 712752 kb
Host smart-283b08ac-3326-403e-9c37-d92a61c0c611
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890948447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1890948447
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.294937634
Short name T500
Test name
Test status
Simulation time 3815808500 ps
CPU time 44.67 seconds
Started Jul 16 06:56:35 PM PDT 24
Finished Jul 16 06:57:21 PM PDT 24
Peak memory 200320 kb
Host smart-63c9ba33-22d3-410e-81f4-a1b63b02e0ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=294937634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.294937634
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3801672121
Short name T40
Test name
Test status
Simulation time 12180700600 ps
CPU time 70.95 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 06:57:57 PM PDT 24
Peak memory 200368 kb
Host smart-f90134f0-04ef-46eb-8e67-653d5abaed51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3801672121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3801672121
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2895767712
Short name T520
Test name
Test status
Simulation time 7485392749 ps
CPU time 76.67 seconds
Started Jul 16 06:56:31 PM PDT 24
Finished Jul 16 06:57:49 PM PDT 24
Peak memory 200380 kb
Host smart-121128f3-3ebf-4e11-8b38-320feb4e731d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2895767712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2895767712
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2678116820
Short name T410
Test name
Test status
Simulation time 20421292120 ps
CPU time 578.46 seconds
Started Jul 16 06:56:39 PM PDT 24
Finished Jul 16 07:06:18 PM PDT 24
Peak memory 200340 kb
Host smart-451a2fa2-982b-4068-8131-1e93984d5846
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2678116820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2678116820
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2665926364
Short name T122
Test name
Test status
Simulation time 1426585443774 ps
CPU time 2522.26 seconds
Started Jul 16 06:56:31 PM PDT 24
Finished Jul 16 07:38:35 PM PDT 24
Peak memory 216080 kb
Host smart-a90693ce-d52d-4aa2-a821-4f55a0bfe1d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2665926364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2665926364
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2648386966
Short name T123
Test name
Test status
Simulation time 287113893427 ps
CPU time 2500.44 seconds
Started Jul 16 06:56:29 PM PDT 24
Finished Jul 16 07:38:12 PM PDT 24
Peak memory 215840 kb
Host smart-3eeb5e09-7ad7-4a9d-b731-3002afdadaaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2648386966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2648386966
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2882941905
Short name T377
Test name
Test status
Simulation time 1806293656 ps
CPU time 85.68 seconds
Started Jul 16 06:56:38 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 200308 kb
Host smart-9bbe6c63-28b5-476b-9a88-688c14c49e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882941905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2882941905
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.223710143
Short name T408
Test name
Test status
Simulation time 14905537 ps
CPU time 0.58 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 06:57:20 PM PDT 24
Peak memory 195832 kb
Host smart-d3320e6f-c5e1-479e-924e-7b72338aea50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223710143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.223710143
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1996299243
Short name T10
Test name
Test status
Simulation time 3191159137 ps
CPU time 44.92 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:58:08 PM PDT 24
Peak memory 200396 kb
Host smart-31ef9c5b-a7ee-4d92-a8cf-d6c1bdd30f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996299243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1996299243
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.891938830
Short name T306
Test name
Test status
Simulation time 25005818 ps
CPU time 1.48 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 06:57:21 PM PDT 24
Peak memory 200276 kb
Host smart-62a36831-c680-43ca-86c6-63d7aed3c1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891938830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.891938830
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1089480454
Short name T513
Test name
Test status
Simulation time 697615439 ps
CPU time 19 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 06:57:38 PM PDT 24
Peak memory 238160 kb
Host smart-1cce3846-b1ac-42a3-a3dc-6bb7e0b0e56e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089480454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1089480454
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3636938708
Short name T191
Test name
Test status
Simulation time 42874473839 ps
CPU time 191.35 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 07:00:35 PM PDT 24
Peak memory 200400 kb
Host smart-e7c73151-c21b-4c5f-9f17-993bfd75d6cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636938708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3636938708
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2695392281
Short name T149
Test name
Test status
Simulation time 74866482604 ps
CPU time 80.87 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:58:49 PM PDT 24
Peak memory 200288 kb
Host smart-21b23686-460d-432a-9904-5350943a845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695392281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2695392281
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2386967183
Short name T154
Test name
Test status
Simulation time 1094320790 ps
CPU time 4.08 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 06:57:24 PM PDT 24
Peak memory 200240 kb
Host smart-2a9f9e2c-a78f-46be-893b-54ff5e77bf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386967183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2386967183
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1585647576
Short name T381
Test name
Test status
Simulation time 14757347367 ps
CPU time 226.2 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 07:01:12 PM PDT 24
Peak memory 200372 kb
Host smart-09c3978d-84ea-4cb5-adb4-911129898b44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585647576 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1585647576
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2976366127
Short name T494
Test name
Test status
Simulation time 53102859154 ps
CPU time 88.59 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:58:51 PM PDT 24
Peak memory 200360 kb
Host smart-9c011926-f969-4392-b74b-71fea62fa66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976366127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2976366127
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2068262311
Short name T222
Test name
Test status
Simulation time 12404312 ps
CPU time 0.6 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:26 PM PDT 24
Peak memory 195176 kb
Host smart-4dda0924-afa4-4552-8051-ab5bff6cb5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068262311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2068262311
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2805332247
Short name T482
Test name
Test status
Simulation time 1224479393 ps
CPU time 66.19 seconds
Started Jul 16 06:57:27 PM PDT 24
Finished Jul 16 06:58:35 PM PDT 24
Peak memory 200348 kb
Host smart-dffb2514-753f-4647-9ee7-560e8460fff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805332247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2805332247
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1717376567
Short name T252
Test name
Test status
Simulation time 2074538941 ps
CPU time 2.15 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 06:57:27 PM PDT 24
Peak memory 200296 kb
Host smart-ba42d2ee-5714-4d4d-bba2-014f350232dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717376567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1717376567
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1378988391
Short name T459
Test name
Test status
Simulation time 1798427315 ps
CPU time 307.27 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 07:02:33 PM PDT 24
Peak memory 595712 kb
Host smart-a7a24050-9358-4b20-bdc5-6848c0518aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378988391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1378988391
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3667044713
Short name T181
Test name
Test status
Simulation time 2022151806 ps
CPU time 15.84 seconds
Started Jul 16 06:57:17 PM PDT 24
Finished Jul 16 06:57:34 PM PDT 24
Peak memory 200232 kb
Host smart-52be5aba-7764-4dcf-8cb3-61f1588d555d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667044713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3667044713
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.870931138
Short name T471
Test name
Test status
Simulation time 53835761510 ps
CPU time 194.24 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 07:00:35 PM PDT 24
Peak memory 200384 kb
Host smart-c623d893-f1ac-47eb-8810-2b9ff0420fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870931138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.870931138
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.501596444
Short name T339
Test name
Test status
Simulation time 682935562 ps
CPU time 10.89 seconds
Started Jul 16 06:57:27 PM PDT 24
Finished Jul 16 06:57:39 PM PDT 24
Peak memory 200224 kb
Host smart-65ea0d7d-caea-476e-ab41-e6498feb8c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501596444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.501596444
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3716199842
Short name T78
Test name
Test status
Simulation time 335162837353 ps
CPU time 1987.26 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 07:30:33 PM PDT 24
Peak memory 777004 kb
Host smart-403ce8ac-10eb-4205-b6d5-b2387cec52b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716199842 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3716199842
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.704049283
Short name T227
Test name
Test status
Simulation time 8256331249 ps
CPU time 25.51 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:57:49 PM PDT 24
Peak memory 200252 kb
Host smart-12271a94-7813-4992-bfaa-48c4f28ff040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704049283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.704049283
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2303056376
Short name T251
Test name
Test status
Simulation time 33180755 ps
CPU time 0.59 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:27 PM PDT 24
Peak memory 196588 kb
Host smart-6d679e79-4ea5-4884-85cd-cb0f640beef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303056376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2303056376
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1004121647
Short name T315
Test name
Test status
Simulation time 3941428865 ps
CPU time 63.07 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:58:29 PM PDT 24
Peak memory 200356 kb
Host smart-30b095b0-87d3-44c2-bc97-a83980c0d245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004121647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1004121647
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3465450814
Short name T363
Test name
Test status
Simulation time 3744388918 ps
CPU time 47.58 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:58:09 PM PDT 24
Peak memory 200392 kb
Host smart-c65ab630-5cab-44d0-8277-032fa04519c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465450814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3465450814
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4166032605
Short name T508
Test name
Test status
Simulation time 12578070585 ps
CPU time 1106.38 seconds
Started Jul 16 06:57:27 PM PDT 24
Finished Jul 16 07:15:56 PM PDT 24
Peak memory 518016 kb
Host smart-a555daed-e8f6-4c36-8b30-bb28be22c421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166032605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4166032605
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3822336377
Short name T423
Test name
Test status
Simulation time 26070035377 ps
CPU time 170.48 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 07:00:12 PM PDT 24
Peak memory 200336 kb
Host smart-0b27caf2-c51c-4894-8220-ebb08ac51af8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822336377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3822336377
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2540683340
Short name T374
Test name
Test status
Simulation time 42638694725 ps
CPU time 104.68 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:59:11 PM PDT 24
Peak memory 200520 kb
Host smart-75adf58b-3f0a-4f3c-8886-ea56ef088ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540683340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2540683340
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3377538383
Short name T507
Test name
Test status
Simulation time 690986876 ps
CPU time 3.39 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:31 PM PDT 24
Peak memory 200316 kb
Host smart-aa14babb-1e00-4a1c-9548-6a0648a1be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377538383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3377538383
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.953392458
Short name T349
Test name
Test status
Simulation time 3505821374 ps
CPU time 420.8 seconds
Started Jul 16 06:57:19 PM PDT 24
Finished Jul 16 07:04:21 PM PDT 24
Peak memory 494856 kb
Host smart-3fa21421-30c8-4bfc-a2d1-5b5eb16604d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953392458 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.953392458
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3933235479
Short name T28
Test name
Test status
Simulation time 7606991393 ps
CPU time 79.27 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 200380 kb
Host smart-b535436c-9bfd-471d-a3e8-7a72673ffac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933235479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3933235479
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.134262454
Short name T420
Test name
Test status
Simulation time 42879447 ps
CPU time 0.58 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 06:57:20 PM PDT 24
Peak memory 196128 kb
Host smart-59dce3eb-443f-4be6-bf96-3b9e89783d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134262454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.134262454
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3401312678
Short name T32
Test name
Test status
Simulation time 1335751763 ps
CPU time 49.56 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 200284 kb
Host smart-58d5716a-3f5e-48f3-bae5-4be2d30b713b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401312678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3401312678
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1999554778
Short name T323
Test name
Test status
Simulation time 34975101 ps
CPU time 1.96 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200312 kb
Host smart-e0e110ef-d861-4875-a058-f636bb8247a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999554778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1999554778
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2658862595
Short name T247
Test name
Test status
Simulation time 18539658049 ps
CPU time 247.24 seconds
Started Jul 16 06:57:17 PM PDT 24
Finished Jul 16 07:01:26 PM PDT 24
Peak memory 478644 kb
Host smart-cae307dd-2e05-4368-b577-f949ceac073b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658862595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2658862595
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1692894824
Short name T344
Test name
Test status
Simulation time 39151826461 ps
CPU time 149.61 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:59:54 PM PDT 24
Peak memory 200336 kb
Host smart-94f2fbcf-26bc-4592-92d1-afb5f8b12e78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692894824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1692894824
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1128697056
Short name T465
Test name
Test status
Simulation time 8381531956 ps
CPU time 121.39 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 06:59:26 PM PDT 24
Peak memory 216532 kb
Host smart-aa3e42a9-cd82-4b5f-a8be-b20b622dc399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128697056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1128697056
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2281756168
Short name T394
Test name
Test status
Simulation time 86375016 ps
CPU time 4.15 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200140 kb
Host smart-b3578057-e83c-4f74-b298-c37449d3765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281756168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2281756168
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1206543219
Short name T31
Test name
Test status
Simulation time 229952074266 ps
CPU time 2498.58 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 07:39:01 PM PDT 24
Peak memory 770468 kb
Host smart-a76fea3a-e617-4811-bc46-7c6f7ec2aae2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206543219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1206543219
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2736913646
Short name T524
Test name
Test status
Simulation time 2846543385 ps
CPU time 5.84 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:57:28 PM PDT 24
Peak memory 200360 kb
Host smart-d8a294c0-6e17-4bbc-8218-256f61f6b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736913646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2736913646
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1462120169
Short name T527
Test name
Test status
Simulation time 14493291 ps
CPU time 0.61 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:27 PM PDT 24
Peak memory 195052 kb
Host smart-4beb05d2-b453-4a1f-933d-f456eb5d6bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462120169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1462120169
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1443130490
Short name T145
Test name
Test status
Simulation time 367758912 ps
CPU time 21.68 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200292 kb
Host smart-48a0fe08-c273-4b82-9cb4-ae713a2d913f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443130490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1443130490
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3502510080
Short name T200
Test name
Test status
Simulation time 4488122302 ps
CPU time 13.68 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:40 PM PDT 24
Peak memory 200344 kb
Host smart-2ec296ed-5119-4077-8b04-5bc1995075b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502510080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3502510080
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3673785062
Short name T470
Test name
Test status
Simulation time 13445366251 ps
CPU time 1095.48 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 07:15:39 PM PDT 24
Peak memory 733324 kb
Host smart-a94ad8e2-0e00-40c4-ba0c-ceddc6375280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673785062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3673785062
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.4127345354
Short name T280
Test name
Test status
Simulation time 1188354989 ps
CPU time 34.81 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:57:58 PM PDT 24
Peak memory 200132 kb
Host smart-f227e791-467b-4b26-90c6-a3502bcdb4e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127345354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4127345354
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1582438449
Short name T55
Test name
Test status
Simulation time 12712742160 ps
CPU time 238.6 seconds
Started Jul 16 06:57:27 PM PDT 24
Finished Jul 16 07:01:28 PM PDT 24
Peak memory 216748 kb
Host smart-80033015-803a-46de-9d75-134aa7c70cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582438449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1582438449
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.369415708
Short name T202
Test name
Test status
Simulation time 1478542690 ps
CPU time 4.03 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200012 kb
Host smart-28c7303c-c333-416d-979f-dd08b9e947ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369415708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.369415708
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.4131963708
Short name T77
Test name
Test status
Simulation time 1688198791 ps
CPU time 6.3 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:57:29 PM PDT 24
Peak memory 200276 kb
Host smart-f8ad261d-b1f3-4f93-832b-a1ffd95081d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131963708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.4131963708
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2673210073
Short name T347
Test name
Test status
Simulation time 10396034689 ps
CPU time 129.61 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:59:35 PM PDT 24
Peak memory 200240 kb
Host smart-2fee82bc-cee6-4361-82d3-24661f881fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673210073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2673210073
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4111852149
Short name T444
Test name
Test status
Simulation time 19513542 ps
CPU time 0.59 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 196180 kb
Host smart-aa72eb3e-6f74-4298-8186-13bc35b3d5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111852149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4111852149
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1342187841
Short name T184
Test name
Test status
Simulation time 1719899411 ps
CPU time 98.18 seconds
Started Jul 16 06:57:24 PM PDT 24
Finished Jul 16 06:59:04 PM PDT 24
Peak memory 200260 kb
Host smart-6cc1893e-19d0-47b0-9914-581913fcda3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342187841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1342187841
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1323704172
Short name T38
Test name
Test status
Simulation time 5672551300 ps
CPU time 77.59 seconds
Started Jul 16 06:57:24 PM PDT 24
Finished Jul 16 06:58:44 PM PDT 24
Peak memory 208604 kb
Host smart-fc42b4cd-ccf9-4ac8-83e4-04db8c669b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323704172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1323704172
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2985285488
Short name T489
Test name
Test status
Simulation time 4676351519 ps
CPU time 470.86 seconds
Started Jul 16 06:57:24 PM PDT 24
Finished Jul 16 07:05:17 PM PDT 24
Peak memory 683592 kb
Host smart-0e95ef2b-2f43-4b54-b769-7123dcf8fdc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985285488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2985285488
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2015663536
Short name T72
Test name
Test status
Simulation time 85408498264 ps
CPU time 200.81 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 07:00:45 PM PDT 24
Peak memory 200216 kb
Host smart-9ef22625-2257-4212-b127-42b8e80a89b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015663536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2015663536
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3398391818
Short name T186
Test name
Test status
Simulation time 25591900808 ps
CPU time 74.97 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 06:58:39 PM PDT 24
Peak memory 200288 kb
Host smart-8dea110e-7458-497e-9b7b-65a30a71ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398391818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3398391818
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2543936827
Short name T526
Test name
Test status
Simulation time 134813064 ps
CPU time 6.47 seconds
Started Jul 16 06:57:24 PM PDT 24
Finished Jul 16 06:57:34 PM PDT 24
Peak memory 200292 kb
Host smart-97004e7d-1502-452c-9b19-6bea8e8509ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543936827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2543936827
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3041216233
Short name T371
Test name
Test status
Simulation time 451690138259 ps
CPU time 2828.41 seconds
Started Jul 16 06:57:24 PM PDT 24
Finished Jul 16 07:44:35 PM PDT 24
Peak memory 832108 kb
Host smart-ed92c78e-b234-4699-8266-07f2c6437442
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041216233 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3041216233
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2100382455
Short name T80
Test name
Test status
Simulation time 1295282722 ps
CPU time 54.69 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:58:20 PM PDT 24
Peak memory 200224 kb
Host smart-43f1fc3b-5764-4b72-8d3b-33e367d3c00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100382455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2100382455
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2099855910
Short name T519
Test name
Test status
Simulation time 42807564 ps
CPU time 0.59 seconds
Started Jul 16 06:57:25 PM PDT 24
Finished Jul 16 06:57:28 PM PDT 24
Peak memory 196140 kb
Host smart-53ae29b7-61e3-4b64-8b45-9133c02f0007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099855910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2099855910
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2497938951
Short name T29
Test name
Test status
Simulation time 2940105893 ps
CPU time 82.28 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 06:58:52 PM PDT 24
Peak memory 200352 kb
Host smart-6ee47de2-4631-4a81-aec3-59493e8808c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497938951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2497938951
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.755750462
Short name T261
Test name
Test status
Simulation time 13938246369 ps
CPU time 41.24 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 06:58:11 PM PDT 24
Peak memory 200408 kb
Host smart-e8f21da4-ed7f-4d07-9d46-e808d8c673d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755750462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.755750462
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.4207054897
Short name T248
Test name
Test status
Simulation time 9875101102 ps
CPU time 879.44 seconds
Started Jul 16 06:57:18 PM PDT 24
Finished Jul 16 07:11:59 PM PDT 24
Peak memory 693160 kb
Host smart-ab63c245-36af-4fb6-bc17-1cfb596384a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207054897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4207054897
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3942056385
Short name T498
Test name
Test status
Simulation time 1695800074 ps
CPU time 49.04 seconds
Started Jul 16 06:57:27 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 200280 kb
Host smart-b83ca485-4107-4cda-927d-a98506207fb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942056385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3942056385
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2303710223
Short name T143
Test name
Test status
Simulation time 29656297989 ps
CPU time 97.37 seconds
Started Jul 16 06:57:17 PM PDT 24
Finished Jul 16 06:58:56 PM PDT 24
Peak memory 200412 kb
Host smart-a77a8e30-39c3-41f7-b841-79b5997ae0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303710223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2303710223
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.36934351
Short name T36
Test name
Test status
Simulation time 189981184 ps
CPU time 1.17 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:29 PM PDT 24
Peak memory 200212 kb
Host smart-3cd1f701-899b-4ed6-99fa-ddf64ca7f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36934351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.36934351
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.556336856
Short name T82
Test name
Test status
Simulation time 43639526197 ps
CPU time 1198.25 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 07:17:20 PM PDT 24
Peak memory 700356 kb
Host smart-9221c586-a663-4b03-b73a-7e6790067662
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556336856 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.556336856
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.702898034
Short name T299
Test name
Test status
Simulation time 15438933731 ps
CPU time 78.38 seconds
Started Jul 16 06:57:21 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 200236 kb
Host smart-815eb872-bbe1-4b41-b38a-ba9abf04d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702898034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.702898034
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1647323309
Short name T302
Test name
Test status
Simulation time 11578866 ps
CPU time 0.57 seconds
Started Jul 16 06:57:29 PM PDT 24
Finished Jul 16 06:57:31 PM PDT 24
Peak memory 196816 kb
Host smart-bf155d1a-264d-4ced-9c02-9fa93e8fc619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647323309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1647323309
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2569291632
Short name T456
Test name
Test status
Simulation time 1611048443 ps
CPU time 92.91 seconds
Started Jul 16 06:57:25 PM PDT 24
Finished Jul 16 06:59:00 PM PDT 24
Peak memory 200244 kb
Host smart-2af3679a-e1c0-4235-b6b8-931e49dc848d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569291632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2569291632
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3280360625
Short name T141
Test name
Test status
Simulation time 5585584323 ps
CPU time 57.55 seconds
Started Jul 16 06:57:22 PM PDT 24
Finished Jul 16 06:58:22 PM PDT 24
Peak memory 200376 kb
Host smart-369267e0-8d4f-4536-9a13-447d940f4189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280360625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3280360625
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3913299376
Short name T419
Test name
Test status
Simulation time 6576805937 ps
CPU time 617.48 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 07:07:47 PM PDT 24
Peak memory 733216 kb
Host smart-e88170c6-735f-481d-9c93-9b09d8ae260a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913299376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3913299376
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2705511763
Short name T461
Test name
Test status
Simulation time 6618297858 ps
CPU time 42.65 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:58:08 PM PDT 24
Peak memory 200296 kb
Host smart-2022bf02-65ff-47cd-9043-dbaedbf5ef53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705511763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2705511763
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1104780319
Short name T440
Test name
Test status
Simulation time 2647844521 ps
CPU time 131.48 seconds
Started Jul 16 06:57:25 PM PDT 24
Finished Jul 16 06:59:39 PM PDT 24
Peak memory 200316 kb
Host smart-5c88f9e9-46d9-44c8-84ea-4613fd4f25d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104780319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1104780319
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3918264799
Short name T350
Test name
Test status
Simulation time 752041078 ps
CPU time 4.94 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 06:57:35 PM PDT 24
Peak memory 200344 kb
Host smart-e2944967-7b1c-46f2-b875-4e9ef9ea0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918264799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3918264799
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3629433695
Short name T316
Test name
Test status
Simulation time 7875700219 ps
CPU time 138.27 seconds
Started Jul 16 06:57:17 PM PDT 24
Finished Jul 16 06:59:37 PM PDT 24
Peak memory 200388 kb
Host smart-5fee2b7f-1d89-4e68-b4e7-fd276827a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629433695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3629433695
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3898878898
Short name T466
Test name
Test status
Simulation time 78534009 ps
CPU time 0.58 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 06:57:48 PM PDT 24
Peak memory 196220 kb
Host smart-2e8ca713-1af5-4520-89d6-9ab5a3845079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898878898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3898878898
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.31097337
Short name T271
Test name
Test status
Simulation time 50059532 ps
CPU time 2.95 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:29 PM PDT 24
Peak memory 200180 kb
Host smart-5eee22f7-280d-4655-834e-92e6014c87aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31097337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.31097337
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4209646145
Short name T477
Test name
Test status
Simulation time 16220144681 ps
CPU time 35.06 seconds
Started Jul 16 06:57:19 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 208588 kb
Host smart-51f6140f-70b3-4598-8fd2-17a14afe5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209646145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4209646145
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.896024222
Short name T380
Test name
Test status
Simulation time 3794120996 ps
CPU time 642.89 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 07:08:09 PM PDT 24
Peak memory 652260 kb
Host smart-3e91d044-bfd8-488d-880d-e0a9c2424a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896024222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.896024222
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1541926513
Short name T242
Test name
Test status
Simulation time 3357078722 ps
CPU time 29.73 seconds
Started Jul 16 06:57:23 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 200364 kb
Host smart-0baf002d-0c25-4cf6-9a5b-40156addf97b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541926513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1541926513
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3838959904
Short name T369
Test name
Test status
Simulation time 5187131507 ps
CPU time 79.7 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:58:48 PM PDT 24
Peak memory 200372 kb
Host smart-2d1c7af8-49e7-4da3-810c-7293a53c7da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838959904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3838959904
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3248260744
Short name T255
Test name
Test status
Simulation time 158513812 ps
CPU time 2.47 seconds
Started Jul 16 06:57:26 PM PDT 24
Finished Jul 16 06:57:30 PM PDT 24
Peak memory 200224 kb
Host smart-aaf85cb3-f0f1-4951-a28d-3ec6bbe7dbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248260744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3248260744
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3256730138
Short name T436
Test name
Test status
Simulation time 1013924559 ps
CPU time 60.4 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 06:58:30 PM PDT 24
Peak memory 200192 kb
Host smart-c048f42d-6ec2-4b4e-9e41-77fcb14c75c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256730138 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3256730138
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1244414728
Short name T472
Test name
Test status
Simulation time 26774485880 ps
CPU time 122.21 seconds
Started Jul 16 06:57:20 PM PDT 24
Finished Jul 16 06:59:23 PM PDT 24
Peak memory 200424 kb
Host smart-7f69335f-c4cd-4228-96a2-d0c98f4a2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244414728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1244414728
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3939065827
Short name T165
Test name
Test status
Simulation time 19648775 ps
CPU time 0.58 seconds
Started Jul 16 06:57:31 PM PDT 24
Finished Jul 16 06:57:33 PM PDT 24
Peak memory 195152 kb
Host smart-e965df7a-b157-43a2-b7da-594f21613e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939065827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3939065827
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.893177471
Short name T219
Test name
Test status
Simulation time 2670927284 ps
CPU time 102.53 seconds
Started Jul 16 06:57:30 PM PDT 24
Finished Jul 16 06:59:14 PM PDT 24
Peak memory 200268 kb
Host smart-7a0472d8-a3f4-4074-9dc7-3127cdb4a1fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893177471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.893177471
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1935053414
Short name T342
Test name
Test status
Simulation time 931888525 ps
CPU time 87.75 seconds
Started Jul 16 06:57:32 PM PDT 24
Finished Jul 16 06:59:01 PM PDT 24
Peak memory 403792 kb
Host smart-f12fb039-0b3f-45b4-a1cd-6f709376ebf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935053414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1935053414
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3165145673
Short name T201
Test name
Test status
Simulation time 2563319024 ps
CPU time 120.23 seconds
Started Jul 16 06:57:32 PM PDT 24
Finished Jul 16 06:59:33 PM PDT 24
Peak memory 200256 kb
Host smart-3985ba3b-b158-4694-ae17-ce478b0bf90d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165145673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3165145673
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.640722471
Short name T486
Test name
Test status
Simulation time 2442128783 ps
CPU time 44.69 seconds
Started Jul 16 06:57:33 PM PDT 24
Finished Jul 16 06:58:18 PM PDT 24
Peak memory 200432 kb
Host smart-609cd1eb-b6a6-490b-b4cf-e0eb0e2f23ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640722471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.640722471
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2352553258
Short name T307
Test name
Test status
Simulation time 2175722683 ps
CPU time 10.24 seconds
Started Jul 16 06:57:29 PM PDT 24
Finished Jul 16 06:57:41 PM PDT 24
Peak memory 200360 kb
Host smart-69384130-458a-4937-81ea-6066e2c21bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352553258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2352553258
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1741839546
Short name T298
Test name
Test status
Simulation time 33120267720 ps
CPU time 612.54 seconds
Started Jul 16 06:57:42 PM PDT 24
Finished Jul 16 07:07:55 PM PDT 24
Peak memory 208624 kb
Host smart-45d09d80-aee6-43ce-abe5-0c420184a4eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741839546 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1741839546
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1037013216
Short name T509
Test name
Test status
Simulation time 4435366840 ps
CPU time 55.48 seconds
Started Jul 16 06:57:40 PM PDT 24
Finished Jul 16 06:58:37 PM PDT 24
Peak memory 200292 kb
Host smart-bfeab9d8-5729-4490-b301-df46f8295439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037013216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1037013216
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3395576283
Short name T447
Test name
Test status
Simulation time 24430938 ps
CPU time 0.6 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:56:51 PM PDT 24
Peak memory 196128 kb
Host smart-d71c0d37-a395-431c-a8de-a8ec669bfbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395576283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3395576283
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3481831903
Short name T517
Test name
Test status
Simulation time 3778081436 ps
CPU time 46.28 seconds
Started Jul 16 06:56:35 PM PDT 24
Finished Jul 16 06:57:22 PM PDT 24
Peak memory 200340 kb
Host smart-8df31d28-17ab-4c56-83bf-b73eca3050dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481831903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3481831903
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2625890172
Short name T414
Test name
Test status
Simulation time 1237143955 ps
CPU time 26.6 seconds
Started Jul 16 06:56:37 PM PDT 24
Finished Jul 16 06:57:04 PM PDT 24
Peak memory 200492 kb
Host smart-287281f3-bd79-4a26-8bf4-baa8a3058b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625890172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2625890172
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.81265435
Short name T417
Test name
Test status
Simulation time 3194371835 ps
CPU time 640.79 seconds
Started Jul 16 06:56:36 PM PDT 24
Finished Jul 16 07:07:18 PM PDT 24
Peak memory 684736 kb
Host smart-2814de5c-5dcb-4199-8647-fa2be19c9840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81265435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.81265435
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3345081516
Short name T506
Test name
Test status
Simulation time 5139197709 ps
CPU time 36.18 seconds
Started Jul 16 06:56:29 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 200356 kb
Host smart-acbee4de-cab7-4926-bfbf-526a06b1fbb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345081516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3345081516
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3445813423
Short name T216
Test name
Test status
Simulation time 6583209006 ps
CPU time 74.47 seconds
Started Jul 16 06:56:30 PM PDT 24
Finished Jul 16 06:57:47 PM PDT 24
Peak memory 200416 kb
Host smart-e96e4175-472f-411e-bebe-3c2f63e9d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445813423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3445813423
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.144652590
Short name T58
Test name
Test status
Simulation time 34491602 ps
CPU time 0.79 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:56:50 PM PDT 24
Peak memory 218216 kb
Host smart-cdbfc6be-8f0f-42b4-a52c-ca9505dd0861
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144652590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.144652590
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1553853014
Short name T120
Test name
Test status
Simulation time 258716469 ps
CPU time 2.64 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 06:56:54 PM PDT 24
Peak memory 200312 kb
Host smart-7dcad581-3e20-40c8-ad1b-64cab55141ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553853014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1553853014
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1998762992
Short name T9
Test name
Test status
Simulation time 35751526989 ps
CPU time 1386.17 seconds
Started Jul 16 06:56:35 PM PDT 24
Finished Jul 16 07:19:42 PM PDT 24
Peak memory 215912 kb
Host smart-33b7e16c-d4f2-4e6b-8f56-a9d806ba48e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998762992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1998762992
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.743736902
Short name T158
Test name
Test status
Simulation time 4894825974 ps
CPU time 82.13 seconds
Started Jul 16 06:56:32 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 200420 kb
Host smart-6a62f4e4-479f-4ee2-a2c5-eacdc25b38a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=743736902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.743736902
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3039691526
Short name T275
Test name
Test status
Simulation time 6405132077 ps
CPU time 52.64 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 06:57:38 PM PDT 24
Peak memory 200368 kb
Host smart-1353ad90-d54a-4fab-bc0f-7e2941968e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3039691526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3039691526
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3807658399
Short name T396
Test name
Test status
Simulation time 11896583876 ps
CPU time 110.81 seconds
Started Jul 16 06:56:46 PM PDT 24
Finished Jul 16 06:58:37 PM PDT 24
Peak memory 200300 kb
Host smart-8d77c77d-8757-4714-be92-756b7c20ca53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3807658399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3807658399
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1134022570
Short name T304
Test name
Test status
Simulation time 206585764076 ps
CPU time 609.14 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 07:06:58 PM PDT 24
Peak memory 200332 kb
Host smart-a7f0c033-262a-47d7-b3e7-9db5d80f4e5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1134022570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1134022570
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3247372470
Short name T124
Test name
Test status
Simulation time 133105158049 ps
CPU time 2258.72 seconds
Started Jul 16 06:56:34 PM PDT 24
Finished Jul 16 07:34:14 PM PDT 24
Peak memory 215820 kb
Host smart-c799ef8f-1b67-405d-bf72-f1431cba61c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3247372470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3247372470
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1631524686
Short name T273
Test name
Test status
Simulation time 132121361667 ps
CPU time 2390.07 seconds
Started Jul 16 06:56:36 PM PDT 24
Finished Jul 16 07:36:27 PM PDT 24
Peak memory 216288 kb
Host smart-b76e6559-7293-42dd-8273-13c9e160540e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1631524686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1631524686
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1225789559
Short name T190
Test name
Test status
Simulation time 13881958691 ps
CPU time 59.73 seconds
Started Jul 16 06:56:40 PM PDT 24
Finished Jul 16 06:57:41 PM PDT 24
Peak memory 200276 kb
Host smart-4711c738-5c7f-48bc-ac86-0ec90b00ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225789559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1225789559
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.891466507
Short name T310
Test name
Test status
Simulation time 12003681 ps
CPU time 0.59 seconds
Started Jul 16 06:57:29 PM PDT 24
Finished Jul 16 06:57:31 PM PDT 24
Peak memory 196184 kb
Host smart-7b0aba5b-5974-41b2-a048-f86a576aaf0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891466507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.891466507
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2008403389
Short name T415
Test name
Test status
Simulation time 200244923 ps
CPU time 11.22 seconds
Started Jul 16 06:57:29 PM PDT 24
Finished Jul 16 06:57:42 PM PDT 24
Peak memory 200348 kb
Host smart-50883021-76e6-485b-b99b-81d697dc153d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008403389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2008403389
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.333664503
Short name T73
Test name
Test status
Simulation time 1262005662 ps
CPU time 23.15 seconds
Started Jul 16 06:57:40 PM PDT 24
Finished Jul 16 06:58:04 PM PDT 24
Peak memory 200248 kb
Host smart-17009757-fbb4-4b49-b959-67c3bb12130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333664503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.333664503
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2204541779
Short name T400
Test name
Test status
Simulation time 167232192 ps
CPU time 6.93 seconds
Started Jul 16 06:57:31 PM PDT 24
Finished Jul 16 06:57:39 PM PDT 24
Peak memory 200212 kb
Host smart-03aa786b-def8-458f-b71a-82235dd3837a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204541779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2204541779
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.37349243
Short name T510
Test name
Test status
Simulation time 2970203963 ps
CPU time 19.15 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 06:58:07 PM PDT 24
Peak memory 200180 kb
Host smart-4eaecc0d-923e-4ee6-ba7f-cbbee3fecd17
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.37349243
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3327254959
Short name T132
Test name
Test status
Simulation time 12286049690 ps
CPU time 225.66 seconds
Started Jul 16 06:57:41 PM PDT 24
Finished Jul 16 07:01:28 PM PDT 24
Peak memory 200400 kb
Host smart-6954e1e0-72ac-44b8-b93a-790d95489f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327254959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3327254959
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2229961834
Short name T295
Test name
Test status
Simulation time 206067399 ps
CPU time 8.38 seconds
Started Jul 16 06:57:30 PM PDT 24
Finished Jul 16 06:57:40 PM PDT 24
Peak memory 200364 kb
Host smart-457dd114-4725-4108-a3c6-649f904c54ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229961834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2229961834
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2248212600
Short name T512
Test name
Test status
Simulation time 76255973441 ps
CPU time 1228.24 seconds
Started Jul 16 06:57:38 PM PDT 24
Finished Jul 16 07:18:07 PM PDT 24
Peak memory 698060 kb
Host smart-6c8f6deb-e382-4551-b2f5-0a09c5e47db8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248212600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2248212600
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3117939641
Short name T185
Test name
Test status
Simulation time 1570697749 ps
CPU time 22.82 seconds
Started Jul 16 06:57:31 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 200192 kb
Host smart-b7a2dcd2-6821-4500-a953-80c56021ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117939641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3117939641
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.610415841
Short name T289
Test name
Test status
Simulation time 41411420 ps
CPU time 0.58 seconds
Started Jul 16 06:57:36 PM PDT 24
Finished Jul 16 06:57:37 PM PDT 24
Peak memory 195116 kb
Host smart-ba63395f-a34a-4b40-9002-d7693d91ed18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610415841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.610415841
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4016323391
Short name T130
Test name
Test status
Simulation time 1256045502 ps
CPU time 40.04 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 200124 kb
Host smart-6daa1ba0-66f0-4e21-acca-eb02479670f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016323391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4016323391
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.110586195
Short name T1
Test name
Test status
Simulation time 451434459 ps
CPU time 21.19 seconds
Started Jul 16 06:57:32 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 200236 kb
Host smart-a59f48bb-0326-4ff1-88e1-e9aa6b9a0c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110586195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.110586195
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2942522002
Short name T481
Test name
Test status
Simulation time 768260465 ps
CPU time 21.85 seconds
Started Jul 16 06:57:39 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 241056 kb
Host smart-0481c3c0-af25-4e26-b25e-ab3aae70d82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942522002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2942522002
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2342936487
Short name T528
Test name
Test status
Simulation time 37934887444 ps
CPU time 167.27 seconds
Started Jul 16 06:57:30 PM PDT 24
Finished Jul 16 07:00:19 PM PDT 24
Peak memory 200332 kb
Host smart-7da1779f-31e2-4865-874e-a69ae2d4ee99
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342936487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2342936487
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1283642641
Short name T223
Test name
Test status
Simulation time 1021727918 ps
CPU time 56.54 seconds
Started Jul 16 06:57:28 PM PDT 24
Finished Jul 16 06:58:27 PM PDT 24
Peak memory 200300 kb
Host smart-1bf6a5c6-72a6-41a4-9887-489982c5506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283642641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1283642641
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3971985862
Short name T263
Test name
Test status
Simulation time 2591371709 ps
CPU time 9.11 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 06:57:57 PM PDT 24
Peak memory 199740 kb
Host smart-f8594fc3-6996-421a-a67d-01f4140c3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971985862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3971985862
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2114663641
Short name T6
Test name
Test status
Simulation time 16160282331 ps
CPU time 223.52 seconds
Started Jul 16 06:57:31 PM PDT 24
Finished Jul 16 07:01:15 PM PDT 24
Peak memory 200232 kb
Host smart-724a9895-11a8-4f7e-a504-a6ed404b8388
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114663641 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2114663641
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1323295132
Short name T311
Test name
Test status
Simulation time 47184029163 ps
CPU time 112.98 seconds
Started Jul 16 06:57:39 PM PDT 24
Finished Jul 16 06:59:33 PM PDT 24
Peak memory 200136 kb
Host smart-fb609754-6421-4a65-8f74-1ba46c1de284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323295132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1323295132
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1947854247
Short name T312
Test name
Test status
Simulation time 31087377 ps
CPU time 0.58 seconds
Started Jul 16 06:57:31 PM PDT 24
Finished Jul 16 06:57:33 PM PDT 24
Peak memory 195088 kb
Host smart-259d8418-cd45-4049-bb7d-9ce1479b4148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947854247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1947854247
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1841621599
Short name T493
Test name
Test status
Simulation time 367314845 ps
CPU time 21.5 seconds
Started Jul 16 06:57:33 PM PDT 24
Finished Jul 16 06:57:55 PM PDT 24
Peak memory 200300 kb
Host smart-4778cc32-70de-4254-8342-5ebfce63b9ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841621599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1841621599
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.787878356
Short name T325
Test name
Test status
Simulation time 1555717674 ps
CPU time 28.95 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 06:58:17 PM PDT 24
Peak memory 200040 kb
Host smart-9a5671aa-51a4-4468-8211-0c2abece3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787878356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.787878356
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1616673994
Short name T46
Test name
Test status
Simulation time 2454148542 ps
CPU time 417.33 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 07:04:45 PM PDT 24
Peak memory 613244 kb
Host smart-b9cc5915-1220-4e03-8145-56be46c8e2cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616673994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1616673994
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1730359316
Short name T474
Test name
Test status
Simulation time 11230631561 ps
CPU time 162.8 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 07:00:29 PM PDT 24
Peak memory 200400 kb
Host smart-6c3e4411-04ad-4a74-8bbe-537fe1a7f0a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730359316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1730359316
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3569163858
Short name T257
Test name
Test status
Simulation time 38595069483 ps
CPU time 88.49 seconds
Started Jul 16 06:57:36 PM PDT 24
Finished Jul 16 06:59:05 PM PDT 24
Peak memory 200476 kb
Host smart-f295203e-ec66-44e4-98dd-e4604cbbea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569163858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3569163858
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.761494348
Short name T4
Test name
Test status
Simulation time 533877712 ps
CPU time 7.34 seconds
Started Jul 16 06:57:41 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200328 kb
Host smart-b256d248-1a1e-47fd-88d5-e64fdc2b6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761494348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.761494348
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3177415867
Short name T516
Test name
Test status
Simulation time 1513732950 ps
CPU time 27.04 seconds
Started Jul 16 06:57:39 PM PDT 24
Finished Jul 16 06:58:07 PM PDT 24
Peak memory 200064 kb
Host smart-23b2de09-2d00-4718-9d6e-82a89f304e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177415867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3177415867
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2418684644
Short name T249
Test name
Test status
Simulation time 24658435 ps
CPU time 0.6 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:57:45 PM PDT 24
Peak memory 195820 kb
Host smart-476ac11a-719e-4387-98dd-2164f3209695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418684644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2418684644
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3067207658
Short name T213
Test name
Test status
Simulation time 2524657558 ps
CPU time 69.7 seconds
Started Jul 16 06:57:32 PM PDT 24
Finished Jul 16 06:58:42 PM PDT 24
Peak memory 200292 kb
Host smart-e48ba089-a9ae-445a-a161-3a48634917ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067207658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3067207658
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.616133281
Short name T140
Test name
Test status
Simulation time 1274315868 ps
CPU time 19.09 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:58:06 PM PDT 24
Peak memory 200320 kb
Host smart-1dcf5c82-d944-4e10-81d1-bb087d949ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616133281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.616133281
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1313148611
Short name T320
Test name
Test status
Simulation time 7393525484 ps
CPU time 587.72 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 07:07:35 PM PDT 24
Peak memory 670036 kb
Host smart-26107901-f885-4f30-a4ef-e22b79b64974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313148611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1313148611
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.26797843
Short name T354
Test name
Test status
Simulation time 9883257694 ps
CPU time 141.43 seconds
Started Jul 16 06:57:32 PM PDT 24
Finished Jul 16 06:59:54 PM PDT 24
Peak memory 200220 kb
Host smart-2a28653f-efcd-47e8-a601-4da9b246f8f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.26797843
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1356951304
Short name T411
Test name
Test status
Simulation time 699385593 ps
CPU time 37.68 seconds
Started Jul 16 06:57:32 PM PDT 24
Finished Jul 16 06:58:11 PM PDT 24
Peak memory 200212 kb
Host smart-b0540b8b-7eeb-4dd4-8583-d4417a980f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356951304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1356951304
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2945549821
Short name T319
Test name
Test status
Simulation time 479696964 ps
CPU time 8.58 seconds
Started Jul 16 06:57:34 PM PDT 24
Finished Jul 16 06:57:44 PM PDT 24
Peak memory 200260 kb
Host smart-e48067ef-bc66-456d-ba28-ef67e3a57962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945549821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2945549821
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2031417543
Short name T449
Test name
Test status
Simulation time 41623585654 ps
CPU time 1913.5 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 07:29:41 PM PDT 24
Peak memory 716252 kb
Host smart-f4285530-954c-4dc6-bea7-adbeedd7468d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031417543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2031417543
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.799499197
Short name T390
Test name
Test status
Simulation time 1771180475 ps
CPU time 8.22 seconds
Started Jul 16 06:57:47 PM PDT 24
Finished Jul 16 06:57:57 PM PDT 24
Peak memory 200236 kb
Host smart-f09daf78-59cb-4533-bb52-9944f5b6d1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799499197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.799499197
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.4043594707
Short name T39
Test name
Test status
Simulation time 13876059 ps
CPU time 0.59 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:57:47 PM PDT 24
Peak memory 196240 kb
Host smart-79876645-b93c-4d19-b826-fc69585da792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043594707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.4043594707
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.677370741
Short name T192
Test name
Test status
Simulation time 675078711 ps
CPU time 21.09 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:58:08 PM PDT 24
Peak memory 200272 kb
Host smart-7b44d44b-1a82-45ce-9424-1c8b0d057f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677370741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.677370741
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1943555742
Short name T402
Test name
Test status
Simulation time 576876355 ps
CPU time 10.82 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:57:56 PM PDT 24
Peak memory 200292 kb
Host smart-7b85a7db-6c1a-4479-83ac-0456235a6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943555742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1943555742
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2824592215
Short name T364
Test name
Test status
Simulation time 19644073568 ps
CPU time 248.49 seconds
Started Jul 16 06:57:47 PM PDT 24
Finished Jul 16 07:01:57 PM PDT 24
Peak memory 653328 kb
Host smart-7febc7e6-a21b-4a8e-8951-3e8aeec4ecc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824592215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2824592215
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3223871657
Short name T180
Test name
Test status
Simulation time 46900575080 ps
CPU time 159.11 seconds
Started Jul 16 06:57:43 PM PDT 24
Finished Jul 16 07:00:23 PM PDT 24
Peak memory 200304 kb
Host smart-48e45fc1-f466-49bd-8cdf-7cfea7b64861
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223871657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3223871657
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2753303041
Short name T182
Test name
Test status
Simulation time 8986688372 ps
CPU time 150.36 seconds
Started Jul 16 06:57:43 PM PDT 24
Finished Jul 16 07:00:14 PM PDT 24
Peak memory 200344 kb
Host smart-d66b49eb-df0c-46aa-828d-63c96d7fc75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753303041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2753303041
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2150420066
Short name T358
Test name
Test status
Simulation time 215638993 ps
CPU time 2.69 seconds
Started Jul 16 06:57:47 PM PDT 24
Finished Jul 16 06:57:51 PM PDT 24
Peak memory 200236 kb
Host smart-32513008-c753-424f-aaac-54cc7cc34884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150420066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2150420066
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2452360096
Short name T382
Test name
Test status
Simulation time 137911522856 ps
CPU time 1953.09 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 07:30:21 PM PDT 24
Peak memory 777308 kb
Host smart-1a5032db-f80b-4a28-b313-3fa2a2b7dbcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452360096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2452360096
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3839786122
Short name T301
Test name
Test status
Simulation time 17923719711 ps
CPU time 63.7 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:58:48 PM PDT 24
Peak memory 200376 kb
Host smart-fe9abbec-5290-4926-8b9b-1dc9da2a5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839786122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3839786122
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1516656952
Short name T504
Test name
Test status
Simulation time 12533088 ps
CPU time 0.61 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:57:47 PM PDT 24
Peak memory 195780 kb
Host smart-ddc10564-04af-4ef4-bbb8-0f903cbf69c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516656952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1516656952
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.70479429
Short name T173
Test name
Test status
Simulation time 1327572227 ps
CPU time 83.19 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:59:10 PM PDT 24
Peak memory 200304 kb
Host smart-21f65f55-3722-48ae-9654-a56eafafc9ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70479429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.70479429
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3369126368
Short name T362
Test name
Test status
Simulation time 3950863734 ps
CPU time 34.01 seconds
Started Jul 16 06:57:47 PM PDT 24
Finished Jul 16 06:58:22 PM PDT 24
Peak memory 200380 kb
Host smart-1053915f-6c89-4575-b8f1-a42a86f2b058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369126368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3369126368
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3695281947
Short name T426
Test name
Test status
Simulation time 2665995463 ps
CPU time 442.34 seconds
Started Jul 16 06:57:43 PM PDT 24
Finished Jul 16 07:05:07 PM PDT 24
Peak memory 629312 kb
Host smart-fb896ad9-3df0-4025-963d-f65dc05cb761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695281947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3695281947
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1816472072
Short name T47
Test name
Test status
Simulation time 1007921517 ps
CPU time 52.85 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:58:39 PM PDT 24
Peak memory 200476 kb
Host smart-d1d63aea-95de-44f0-86a4-798f4b53a7c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816472072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1816472072
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3564902336
Short name T198
Test name
Test status
Simulation time 1909909825 ps
CPU time 110.3 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:59:37 PM PDT 24
Peak memory 200488 kb
Host smart-b6f82280-f62e-4540-8e4b-077d0a816403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564902336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3564902336
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2271753367
Short name T157
Test name
Test status
Simulation time 407238832 ps
CPU time 5.28 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:57:50 PM PDT 24
Peak memory 200316 kb
Host smart-aecc7837-e708-4c45-983d-b322279664b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271753367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2271753367
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4142375809
Short name T135
Test name
Test status
Simulation time 19453343809 ps
CPU time 1793.73 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 762796 kb
Host smart-79f5b546-0515-4784-8541-1d57f0a61ec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142375809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4142375809
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.926177948
Short name T203
Test name
Test status
Simulation time 19016990137 ps
CPU time 58.63 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:58:45 PM PDT 24
Peak memory 200324 kb
Host smart-be930f03-3c01-4772-9a30-3e655fe4070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926177948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.926177948
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1434272780
Short name T266
Test name
Test status
Simulation time 13482364 ps
CPU time 0.61 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:00 PM PDT 24
Peak memory 196872 kb
Host smart-a267a3f0-a9d3-4e41-89c1-fb8518268a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434272780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1434272780
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1725056000
Short name T148
Test name
Test status
Simulation time 8289714942 ps
CPU time 43.07 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 200392 kb
Host smart-6e96878c-2208-4bd7-9894-ba1543acaf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725056000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1725056000
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.345501883
Short name T403
Test name
Test status
Simulation time 2564873883 ps
CPU time 44.64 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:58:31 PM PDT 24
Peak memory 200356 kb
Host smart-ec381de2-4479-4940-8c45-e710fc85c00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345501883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.345501883
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2710636783
Short name T487
Test name
Test status
Simulation time 27377449186 ps
CPU time 1421.2 seconds
Started Jul 16 06:57:46 PM PDT 24
Finished Jul 16 07:21:29 PM PDT 24
Peak memory 715428 kb
Host smart-442b7042-8daf-4d70-b1fb-a346f12b26d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710636783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2710636783
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.489245786
Short name T126
Test name
Test status
Simulation time 25963969564 ps
CPU time 157.36 seconds
Started Jul 16 06:57:44 PM PDT 24
Finished Jul 16 07:00:23 PM PDT 24
Peak memory 200344 kb
Host smart-1ecb3a3b-5a97-4ba4-8965-77f857d0505a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489245786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.489245786
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3926187351
Short name T329
Test name
Test status
Simulation time 20354923727 ps
CPU time 93.07 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:59:19 PM PDT 24
Peak memory 200344 kb
Host smart-d3e4f7d7-4e9b-4b47-b444-8303873b318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926187351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3926187351
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1592529426
Short name T23
Test name
Test status
Simulation time 150586657 ps
CPU time 7.16 seconds
Started Jul 16 06:57:45 PM PDT 24
Finished Jul 16 06:57:53 PM PDT 24
Peak memory 200312 kb
Host smart-20589a8d-9d6a-4646-a3ed-32180abba913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592529426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1592529426
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2519647421
Short name T338
Test name
Test status
Simulation time 43864695491 ps
CPU time 582.38 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 07:07:42 PM PDT 24
Peak memory 200208 kb
Host smart-4d21022d-0d96-4dea-9a3e-3aa92f9226bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519647421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2519647421
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4173816663
Short name T234
Test name
Test status
Simulation time 6249006781 ps
CPU time 104.29 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:59:42 PM PDT 24
Peak memory 200360 kb
Host smart-b03341f0-2f88-49cc-85a6-84e335fd3127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173816663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4173816663
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3115722931
Short name T206
Test name
Test status
Simulation time 11124632 ps
CPU time 0.63 seconds
Started Jul 16 06:58:00 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 196220 kb
Host smart-704287a8-44ff-45d4-ae9d-84ebbee75296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115722931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3115722931
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4246118427
Short name T501
Test name
Test status
Simulation time 869170877 ps
CPU time 47.87 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 06:58:47 PM PDT 24
Peak memory 200316 kb
Host smart-c9ef906c-4bb1-4b9f-8293-7c8627bd92dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246118427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4246118427
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.750057697
Short name T214
Test name
Test status
Simulation time 5177560567 ps
CPU time 35.9 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:58:34 PM PDT 24
Peak memory 200396 kb
Host smart-d4181b0e-3390-4e23-8391-6a2cfd39489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750057697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.750057697
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.12472021
Short name T189
Test name
Test status
Simulation time 8999208755 ps
CPU time 817.19 seconds
Started Jul 16 06:58:05 PM PDT 24
Finished Jul 16 07:11:43 PM PDT 24
Peak memory 629128 kb
Host smart-1f408a34-99d9-412e-885c-976c7101ffed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12472021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.12472021
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1919990832
Short name T48
Test name
Test status
Simulation time 11378795849 ps
CPU time 179.12 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 07:01:00 PM PDT 24
Peak memory 200352 kb
Host smart-055effcc-5233-4fd8-b173-342fc477f44e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919990832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1919990832
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.353941323
Short name T264
Test name
Test status
Simulation time 7711942782 ps
CPU time 110.13 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:59:48 PM PDT 24
Peak memory 208448 kb
Host smart-9309dacc-9bd5-454f-9b16-a6bfb96d3aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353941323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.353941323
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2263666819
Short name T235
Test name
Test status
Simulation time 3077707436 ps
CPU time 10.41 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:10 PM PDT 24
Peak memory 200360 kb
Host smart-b653c8bf-6289-482d-b637-89e75da2c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263666819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2263666819
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3721411996
Short name T253
Test name
Test status
Simulation time 337723834 ps
CPU time 5.99 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:07 PM PDT 24
Peak memory 200348 kb
Host smart-e69e2bd0-c672-4694-8f06-4684dd2ecf91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721411996 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3721411996
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1230334381
Short name T83
Test name
Test status
Simulation time 5820469028 ps
CPU time 38.61 seconds
Started Jul 16 06:58:00 PM PDT 24
Finished Jul 16 06:58:40 PM PDT 24
Peak memory 200172 kb
Host smart-c2b4d2ba-f9a5-43f7-939d-926f58173c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230334381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1230334381
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3110633794
Short name T290
Test name
Test status
Simulation time 14288207 ps
CPU time 0.62 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:57:58 PM PDT 24
Peak memory 196180 kb
Host smart-39416b46-5e99-4d96-b70c-c9c5f234f87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110633794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3110633794
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1767248965
Short name T432
Test name
Test status
Simulation time 5280287043 ps
CPU time 67.65 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:59:04 PM PDT 24
Peak memory 208612 kb
Host smart-a80d7031-a5a5-49c1-9e17-dcd63298a3ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767248965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1767248965
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.993566574
Short name T210
Test name
Test status
Simulation time 5599627359 ps
CPU time 62.28 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:59:02 PM PDT 24
Peak memory 200268 kb
Host smart-5d50a818-5779-4e42-8e99-41269965b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993566574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.993566574
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.145466642
Short name T478
Test name
Test status
Simulation time 7385255623 ps
CPU time 392.08 seconds
Started Jul 16 06:58:01 PM PDT 24
Finished Jul 16 07:04:34 PM PDT 24
Peak memory 447432 kb
Host smart-0f736e88-6608-4104-91cf-9557a39ab85e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145466642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.145466642
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1170844856
Short name T336
Test name
Test status
Simulation time 1059133408 ps
CPU time 64.03 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:59:00 PM PDT 24
Peak memory 200296 kb
Host smart-7f15dac3-1584-42f1-a6b7-6ee9247721fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170844856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1170844856
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3183161346
Short name T259
Test name
Test status
Simulation time 10333692410 ps
CPU time 134.91 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 07:00:15 PM PDT 24
Peak memory 200332 kb
Host smart-8d7606eb-c174-45d7-a813-6e6db1f4c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183161346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3183161346
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1338202282
Short name T224
Test name
Test status
Simulation time 321604420 ps
CPU time 3.03 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 06:58:01 PM PDT 24
Peak memory 200260 kb
Host smart-bfb4a30b-df8a-47eb-b816-84d2dd004489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338202282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1338202282
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1652997694
Short name T21
Test name
Test status
Simulation time 13998776464 ps
CPU time 1125.53 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 07:16:44 PM PDT 24
Peak memory 699912 kb
Host smart-93714fa5-1b74-4bca-8233-a5253c63c137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652997694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1652997694
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.46063373
Short name T85
Test name
Test status
Simulation time 3029937368 ps
CPU time 41.43 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 06:58:41 PM PDT 24
Peak memory 200252 kb
Host smart-6b6a2e69-8916-4d43-98bb-76dc26889962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46063373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.46063373
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2826010714
Short name T56
Test name
Test status
Simulation time 21297634 ps
CPU time 0.59 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:01 PM PDT 24
Peak memory 196236 kb
Host smart-ca1aa3f8-5784-425c-85e9-592a32349c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826010714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2826010714
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.42243271
Short name T389
Test name
Test status
Simulation time 1036880360 ps
CPU time 13.47 seconds
Started Jul 16 06:58:00 PM PDT 24
Finished Jul 16 06:58:15 PM PDT 24
Peak memory 200252 kb
Host smart-1fb8305d-9277-4462-bf0e-f1945fe92480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42243271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.42243271
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3500447683
Short name T209
Test name
Test status
Simulation time 736563312 ps
CPU time 5.63 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 06:58:06 PM PDT 24
Peak memory 200372 kb
Host smart-d2d21814-3035-483e-8a27-4f24eee4a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500447683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3500447683
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1459505087
Short name T387
Test name
Test status
Simulation time 1604384940 ps
CPU time 275.43 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 07:02:34 PM PDT 24
Peak memory 579472 kb
Host smart-f69d553b-f14e-406c-a9fa-e452adb9ddc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459505087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1459505087
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2533049006
Short name T296
Test name
Test status
Simulation time 8059763464 ps
CPU time 141.18 seconds
Started Jul 16 06:57:58 PM PDT 24
Finished Jul 16 07:00:21 PM PDT 24
Peak memory 200268 kb
Host smart-8eaa7e86-78bb-4801-9c9d-876967b67514
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533049006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2533049006
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2668916034
Short name T330
Test name
Test status
Simulation time 120912190352 ps
CPU time 224.91 seconds
Started Jul 16 06:57:57 PM PDT 24
Finished Jul 16 07:01:44 PM PDT 24
Peak memory 216624 kb
Host smart-dec0105a-f7ce-4cac-8056-4971a15fefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668916034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2668916034
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.310302182
Short name T208
Test name
Test status
Simulation time 68272242 ps
CPU time 1.29 seconds
Started Jul 16 06:58:00 PM PDT 24
Finished Jul 16 06:58:03 PM PDT 24
Peak memory 200360 kb
Host smart-783df40d-8f10-461d-95b0-2dd9631614f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310302182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.310302182
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1433936044
Short name T228
Test name
Test status
Simulation time 31330033 ps
CPU time 0.68 seconds
Started Jul 16 06:57:59 PM PDT 24
Finished Jul 16 06:58:02 PM PDT 24
Peak memory 195920 kb
Host smart-f09e7481-32c1-45d5-8dc5-8278ff1d0b54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433936044 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1433936044
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1230752250
Short name T111
Test name
Test status
Simulation time 8248886697 ps
CPU time 134.56 seconds
Started Jul 16 06:57:56 PM PDT 24
Finished Jul 16 07:00:12 PM PDT 24
Peak memory 200324 kb
Host smart-354637dd-3cd0-4898-9ad1-e062f4b89244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230752250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1230752250
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.869754303
Short name T416
Test name
Test status
Simulation time 20681560 ps
CPU time 0.57 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 06:56:52 PM PDT 24
Peak memory 195952 kb
Host smart-8802d817-7e42-4c72-bb6d-b6335a183967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869754303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.869754303
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2736769547
Short name T26
Test name
Test status
Simulation time 1306300021 ps
CPU time 80.1 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:58:10 PM PDT 24
Peak memory 200328 kb
Host smart-54643839-c7e2-43c3-89d1-e3ff7725d4f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736769547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2736769547
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3811732468
Short name T146
Test name
Test status
Simulation time 11516367752 ps
CPU time 35.63 seconds
Started Jul 16 06:56:40 PM PDT 24
Finished Jul 16 06:57:22 PM PDT 24
Peak memory 200380 kb
Host smart-82c2994f-1797-4f89-9994-76bdd4db1f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811732468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3811732468
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2637391615
Short name T505
Test name
Test status
Simulation time 6516641088 ps
CPU time 1201.86 seconds
Started Jul 16 06:56:40 PM PDT 24
Finished Jul 16 07:16:42 PM PDT 24
Peak memory 770148 kb
Host smart-ad2e8873-5b13-40e0-8d6a-55f610e7fb65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637391615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2637391615
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3319088300
Short name T183
Test name
Test status
Simulation time 2021863052 ps
CPU time 105.78 seconds
Started Jul 16 06:56:41 PM PDT 24
Finished Jul 16 06:58:28 PM PDT 24
Peak memory 200344 kb
Host smart-8be39df0-588d-4833-9bbe-986be99e5566
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319088300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3319088300
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3379054753
Short name T69
Test name
Test status
Simulation time 7758622756 ps
CPU time 122.85 seconds
Started Jul 16 06:56:55 PM PDT 24
Finished Jul 16 06:58:59 PM PDT 24
Peak memory 200364 kb
Host smart-eb1d5a8c-ce1d-4526-8ad1-62f86df6c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379054753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3379054753
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1300690769
Short name T430
Test name
Test status
Simulation time 103419921 ps
CPU time 1.95 seconds
Started Jul 16 06:56:49 PM PDT 24
Finished Jul 16 06:56:52 PM PDT 24
Peak memory 200192 kb
Host smart-7730dd56-9ca8-40fe-bb7c-674360ad85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300690769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1300690769
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3651062081
Short name T397
Test name
Test status
Simulation time 44198916008 ps
CPU time 673.76 seconds
Started Jul 16 06:56:50 PM PDT 24
Finished Jul 16 07:08:06 PM PDT 24
Peak memory 629776 kb
Host smart-ab2df3b3-e4c8-48a9-9957-3753d415c1eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651062081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3651062081
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2765657038
Short name T495
Test name
Test status
Simulation time 4596544980 ps
CPU time 25.34 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:57:27 PM PDT 24
Peak memory 200372 kb
Host smart-00cf7f0f-2580-4f8b-a9fc-5bfea3ea0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765657038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2765657038
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3186428368
Short name T147
Test name
Test status
Simulation time 13459304 ps
CPU time 0.64 seconds
Started Jul 16 06:56:31 PM PDT 24
Finished Jul 16 06:56:33 PM PDT 24
Peak memory 196176 kb
Host smart-b5d20b58-ffd7-4330-ab48-bf257664fff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186428368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3186428368
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.946749571
Short name T433
Test name
Test status
Simulation time 1497740310 ps
CPU time 85.19 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 06:58:11 PM PDT 24
Peak memory 200360 kb
Host smart-9aef1229-e704-4334-8b82-09c688c9337e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946749571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.946749571
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3924990281
Short name T133
Test name
Test status
Simulation time 6785709897 ps
CPU time 35.25 seconds
Started Jul 16 06:56:55 PM PDT 24
Finished Jul 16 06:57:31 PM PDT 24
Peak memory 200384 kb
Host smart-22d877da-e619-421c-b301-4e6e59e1e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924990281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3924990281
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2053351617
Short name T2
Test name
Test status
Simulation time 45282638600 ps
CPU time 516.26 seconds
Started Jul 16 06:56:46 PM PDT 24
Finished Jul 16 07:05:23 PM PDT 24
Peak memory 703744 kb
Host smart-6964ff65-3d7a-47a3-a530-337333ddf912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053351617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2053351617
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3197053579
Short name T424
Test name
Test status
Simulation time 16119620673 ps
CPU time 199.84 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 07:00:05 PM PDT 24
Peak memory 200344 kb
Host smart-e4b3b19f-1c81-4ee9-ba2e-9c3fbe6a33bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197053579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3197053579
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2183786145
Short name T49
Test name
Test status
Simulation time 10430190821 ps
CPU time 184.43 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 07:00:07 PM PDT 24
Peak memory 200436 kb
Host smart-4ae00add-0923-4f8a-a9a7-45e6b691962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183786145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2183786145
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.341508606
Short name T455
Test name
Test status
Simulation time 782449234 ps
CPU time 6.75 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 06:56:53 PM PDT 24
Peak memory 200240 kb
Host smart-274ae342-ffe3-41cd-9bd2-ee16283d9d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341508606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.341508606
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3461718800
Short name T79
Test name
Test status
Simulation time 75266060075 ps
CPU time 2071.04 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 07:31:17 PM PDT 24
Peak memory 781236 kb
Host smart-bc6149f3-578b-4e12-818e-b964b7b722d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461718800 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3461718800
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1735134377
Short name T179
Test name
Test status
Simulation time 5153525804 ps
CPU time 11.91 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:57:05 PM PDT 24
Peak memory 200252 kb
Host smart-10565d6a-a939-4a94-983d-8d8e1a6cc1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735134377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1735134377
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4094586387
Short name T44
Test name
Test status
Simulation time 13519519 ps
CPU time 0.58 seconds
Started Jul 16 06:56:58 PM PDT 24
Finished Jul 16 06:56:59 PM PDT 24
Peak memory 195160 kb
Host smart-bbe4d699-eb30-42b3-b86d-8c732b91a90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094586387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4094586387
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.940855220
Short name T128
Test name
Test status
Simulation time 2510034825 ps
CPU time 34.1 seconds
Started Jul 16 06:56:33 PM PDT 24
Finished Jul 16 06:57:08 PM PDT 24
Peak memory 200400 kb
Host smart-406d8bbb-09eb-4f34-8246-26aca87d43bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940855220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.940855220
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1930827831
Short name T413
Test name
Test status
Simulation time 3291508895 ps
CPU time 58.03 seconds
Started Jul 16 06:56:32 PM PDT 24
Finished Jul 16 06:57:31 PM PDT 24
Peak memory 200392 kb
Host smart-a2d2bb1d-67ef-4075-a088-d834b76dcc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930827831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1930827831
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3349373923
Short name T511
Test name
Test status
Simulation time 14293533169 ps
CPU time 1326.43 seconds
Started Jul 16 06:56:37 PM PDT 24
Finished Jul 16 07:18:45 PM PDT 24
Peak memory 727968 kb
Host smart-304d369b-d2fb-4fa5-998d-63f4b4029431
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349373923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3349373923
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.77004292
Short name T226
Test name
Test status
Simulation time 15098536914 ps
CPU time 180.87 seconds
Started Jul 16 06:56:42 PM PDT 24
Finished Jul 16 06:59:44 PM PDT 24
Peak memory 200380 kb
Host smart-0770af2e-e67d-4232-aac3-46e455b805a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77004292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.77004292
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4058537422
Short name T446
Test name
Test status
Simulation time 2712194043 ps
CPU time 11.69 seconds
Started Jul 16 06:56:45 PM PDT 24
Finished Jul 16 06:56:58 PM PDT 24
Peak memory 200352 kb
Host smart-f0d2daa5-78a9-4db5-bd93-22990c239d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058537422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4058537422
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2219615121
Short name T41
Test name
Test status
Simulation time 4470179792 ps
CPU time 14.1 seconds
Started Jul 16 06:56:59 PM PDT 24
Finished Jul 16 06:57:14 PM PDT 24
Peak memory 200376 kb
Host smart-ba3f5072-458d-46ee-878a-a6fde4aecd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219615121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2219615121
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1588601373
Short name T74
Test name
Test status
Simulation time 185735612682 ps
CPU time 4089.2 seconds
Started Jul 16 06:56:38 PM PDT 24
Finished Jul 16 08:04:48 PM PDT 24
Peak memory 848388 kb
Host smart-83525d16-9fc1-4528-b084-f89ee11a09f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588601373 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1588601373
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.520556220
Short name T13
Test name
Test status
Simulation time 143428281234 ps
CPU time 1533.22 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 07:22:21 PM PDT 24
Peak memory 660928 kb
Host smart-844f9f72-a66e-4d70-9b1a-767b1a982246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520556220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.520556220
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3032142221
Short name T479
Test name
Test status
Simulation time 894724370 ps
CPU time 43.34 seconds
Started Jul 16 06:56:34 PM PDT 24
Finished Jul 16 06:57:18 PM PDT 24
Peak memory 200292 kb
Host smart-065efc03-bb98-43f0-9c7f-d3d96e62221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032142221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3032142221
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3777852292
Short name T241
Test name
Test status
Simulation time 39913488 ps
CPU time 0.57 seconds
Started Jul 16 06:57:00 PM PDT 24
Finished Jul 16 06:57:02 PM PDT 24
Peak memory 195860 kb
Host smart-3d56a910-2749-4d1b-b4e8-8d086787a6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777852292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3777852292
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1032166524
Short name T274
Test name
Test status
Simulation time 1545215064 ps
CPU time 87.93 seconds
Started Jul 16 06:56:57 PM PDT 24
Finished Jul 16 06:58:26 PM PDT 24
Peak memory 200300 kb
Host smart-4e1a64d5-ec22-4a0b-8d13-d29284f12eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032166524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1032166524
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1975778366
Short name T317
Test name
Test status
Simulation time 11531228890 ps
CPU time 48.6 seconds
Started Jul 16 06:56:46 PM PDT 24
Finished Jul 16 06:57:36 PM PDT 24
Peak memory 200360 kb
Host smart-45817c9b-50b2-41d4-8a35-d8694066a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975778366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1975778366
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3616571813
Short name T368
Test name
Test status
Simulation time 15079045619 ps
CPU time 592.09 seconds
Started Jul 16 06:56:55 PM PDT 24
Finished Jul 16 07:06:48 PM PDT 24
Peak memory 637344 kb
Host smart-8582d787-93a8-468b-a5af-e793abf82ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616571813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3616571813
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3482661589
Short name T45
Test name
Test status
Simulation time 2221993348 ps
CPU time 30.29 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:57:24 PM PDT 24
Peak memory 200284 kb
Host smart-4863f9c5-3a15-4f04-b83c-4485f02647e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482661589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3482661589
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.658058965
Short name T305
Test name
Test status
Simulation time 8407835122 ps
CPU time 121.57 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 06:58:50 PM PDT 24
Peak memory 200360 kb
Host smart-b5470a51-8fef-4fee-aa42-d04e09c3fed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658058965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.658058965
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3368678969
Short name T196
Test name
Test status
Simulation time 3903855560 ps
CPU time 13.32 seconds
Started Jul 16 06:56:49 PM PDT 24
Finished Jul 16 06:57:04 PM PDT 24
Peak memory 200360 kb
Host smart-b104a331-ba32-4a70-8371-909b69cc1676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368678969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3368678969
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2942584935
Short name T272
Test name
Test status
Simulation time 71654917013 ps
CPU time 1689.58 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 07:25:12 PM PDT 24
Peak memory 760996 kb
Host smart-fdb17986-d6a9-4653-afad-af82a50d9bae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942584935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2942584935
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2385003996
Short name T22
Test name
Test status
Simulation time 36779900345 ps
CPU time 1143.35 seconds
Started Jul 16 06:56:43 PM PDT 24
Finished Jul 16 07:15:47 PM PDT 24
Peak memory 697804 kb
Host smart-5de8f3a7-6dd9-4a2f-bde1-2bfdff24a1bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385003996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2385003996
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.310787985
Short name T406
Test name
Test status
Simulation time 10043492203 ps
CPU time 115.65 seconds
Started Jul 16 06:56:51 PM PDT 24
Finished Jul 16 06:58:48 PM PDT 24
Peak memory 200384 kb
Host smart-a15fdcc1-022f-4365-943f-786347523d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310787985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.310787985
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.272335951
Short name T458
Test name
Test status
Simulation time 31717723 ps
CPU time 0.59 seconds
Started Jul 16 06:57:01 PM PDT 24
Finished Jul 16 06:57:03 PM PDT 24
Peak memory 195192 kb
Host smart-d9488135-e8eb-4a56-9d60-9bbe18c9b7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272335951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.272335951
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1255536654
Short name T294
Test name
Test status
Simulation time 2771628831 ps
CPU time 84.37 seconds
Started Jul 16 06:56:54 PM PDT 24
Finished Jul 16 06:58:19 PM PDT 24
Peak memory 200212 kb
Host smart-2c5064fe-a7eb-4611-8ce4-b19b7113563f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255536654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1255536654
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3719883833
Short name T269
Test name
Test status
Simulation time 1386745570 ps
CPU time 5.38 seconds
Started Jul 16 06:56:53 PM PDT 24
Finished Jul 16 06:57:00 PM PDT 24
Peak memory 200304 kb
Host smart-4af13a54-daf1-4830-a16c-b74f8a368c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719883833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3719883833
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1137162756
Short name T194
Test name
Test status
Simulation time 7256864748 ps
CPU time 1262.18 seconds
Started Jul 16 06:56:47 PM PDT 24
Finished Jul 16 07:17:50 PM PDT 24
Peak memory 748560 kb
Host smart-d3177967-7ef5-4259-b97f-89ba938f7a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137162756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1137162756
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3900985006
Short name T142
Test name
Test status
Simulation time 1734534419 ps
CPU time 51.43 seconds
Started Jul 16 06:56:59 PM PDT 24
Finished Jul 16 06:57:51 PM PDT 24
Peak memory 200204 kb
Host smart-97574e05-cba0-4bd1-b06e-204e2a630e4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900985006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3900985006
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2911449017
Short name T131
Test name
Test status
Simulation time 2078570521 ps
CPU time 124.38 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 06:58:54 PM PDT 24
Peak memory 200324 kb
Host smart-6d8394f3-c563-408d-bb7a-a05beaef1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911449017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2911449017
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.985681834
Short name T153
Test name
Test status
Simulation time 390182979 ps
CPU time 6.49 seconds
Started Jul 16 06:56:52 PM PDT 24
Finished Jul 16 06:57:00 PM PDT 24
Peak memory 200304 kb
Host smart-2ca6eae9-1c48-4d3c-8083-5905aa7b231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985681834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.985681834
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3984902118
Short name T65
Test name
Test status
Simulation time 112060221811 ps
CPU time 2706.63 seconds
Started Jul 16 06:56:48 PM PDT 24
Finished Jul 16 07:41:57 PM PDT 24
Peak memory 785028 kb
Host smart-354d0f97-f00a-4f00-8e54-e74288a08803
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984902118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3984902118
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4015881314
Short name T144
Test name
Test status
Simulation time 16851803468 ps
CPU time 73.69 seconds
Started Jul 16 06:56:44 PM PDT 24
Finished Jul 16 06:57:59 PM PDT 24
Peak memory 200328 kb
Host smart-b84f2508-ff92-4b11-ba88-47c28cfc1c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015881314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4015881314
Directory /workspace/9.hmac_wipe_secret/latest
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