Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18497013	1			T1	9995		T4	547		T5	1376
all_values[1]	18497013	1			T1	9995		T4	547		T5	1376
all_values[2]	18497013	1			T1	9995		T4	547		T5	1376

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

257120

1

T1

2455

T6

27

T17

3468

auto[1]

55233919

1

T1

27530

T4

1641

T5

4128

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47343494

1

T1

24596

T4

1638

T5

3444

auto[1]

8147545

1

T1

5389

T4

3

T5

684

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90877	1			T6	3		T17	1734		T9	12
all_values[0]	auto[0]	auto[1]	365	1			T6	5		T9	10		T24	3
all_values[0]	auto[1]	auto[0]	18385386	1			T1	9993		T4	544		T5	1359
all_values[0]	auto[1]	auto[1]	20385	1			T1	2		T4	3		T5	17
all_values[1]	auto[0]	auto[0]	93817	1			T6	5		T9	453		T22	8
all_values[1]	auto[0]	auto[1]	230	1			T6	5		T9	9		T22	8
all_values[1]	auto[1]	auto[0]	18402590	1			T1	9995		T4	547		T5	1376
all_values[1]	auto[1]	auto[1]	376	1			T6	11		T9	15		T22	11
all_values[2]	auto[0]	auto[0]	33157	1			T1	613		T6	6		T17	448
all_values[2]	auto[0]	auto[1]	38674	1			T1	1842		T6	3		T17	1286
all_values[2]	auto[1]	auto[0]	10337667	1			T1	3995		T4	547		T5	709
all_values[2]	auto[1]	auto[1]	8087515	1			T1	3545		T5	667		T10	124107