Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138466

1

T4

4

T5

784

T10

320

auto[1]

122178

1

T1

10

T4

4

T5

284

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	99605	1			T1	2		T4	4		T5	436
len_1026_2046	6386	1			T5	11		T6	79		T7	5
len_514_1022	4070	1			T5	3		T10	50		T6	41
len_2_510	4095	1			T5	4		T10	55		T6	35
len_2056	330	1			T22	15		T25	1		T77	1
len_2048	359	1			T6	5		T7	1		T8	1
len_2040	186	1			T22	3		T79	4		T53	2
len_1032	339	1			T24	1		T22	1		T25	3
len_1024	1782	1			T5	1		T10	1		T6	5
len_1016	182	1			T10	1		T22	4		T47	1
len_520	225	1			T24	1		T22	7		T47	2
len_512	410	1			T10	1		T6	3		T9	4
len_504	469	1			T10	1		T22	8		T53	1
len_8	1031	1			T1	2		T6	53		T17	2
len_0	10853	1			T1	1		T5	79		T6	81

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

132

1

T5

1

T7

2

T31

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	54956	1			T4	2		T5	376		T10	51
auto[0]	len_1026_2046	3440	1			T5	9		T6	45		T7	5
auto[0]	len_514_1022	2409	1			T5	3		T10	50		T6	25
auto[0]	len_2_510	2445	1			T5	3		T10	55		T6	23
auto[0]	len_2056	208	1			T22	6		T77	1		T79	1
auto[0]	len_2048	200	1			T6	4		T7	1		T8	1
auto[0]	len_2040	97	1			T22	3		T79	3		T53	1
auto[0]	len_1032	155	1			T24	1		T25	1		T79	1
auto[0]	len_1024	236	1			T5	1		T10	1		T6	2
auto[0]	len_1016	93	1			T10	1		T22	3		T45	2
auto[0]	len_520	129	1			T24	1		T22	1		T47	2
auto[0]	len_512	268	1			T10	1		T6	1		T9	4
auto[0]	len_504	121	1			T10	1		T22	5		T53	1
auto[0]	len_8	43	1			T6	10		T120	2		T121	1
auto[0]	len_0	4433	1			T6	46		T7	1		T8	2
auto[1]	len_2050_plus	44649	1			T1	2		T4	2		T5	60
auto[1]	len_1026_2046	2946	1			T5	2		T6	34		T8	2
auto[1]	len_514_1022	1661	1			T6	16		T9	19		T22	8
auto[1]	len_2_510	1650	1			T5	1		T6	12		T9	16
auto[1]	len_2056	122	1			T22	9		T25	1		T79	1
auto[1]	len_2048	159	1			T6	1		T9	1		T24	3
auto[1]	len_2040	89	1			T79	1		T53	1		T122	3
auto[1]	len_1032	184	1			T22	1		T25	2		T45	2
auto[1]	len_1024	1546	1			T6	3		T9	1		T31	1
auto[1]	len_1016	89	1			T22	1		T47	1		T45	3
auto[1]	len_520	96	1			T22	6		T25	1		T79	2
auto[1]	len_512	142	1			T6	2		T22	4		T18	1
auto[1]	len_504	348	1			T22	3		T122	2		T67	4
auto[1]	len_8	988	1			T1	2		T6	43		T17	2
auto[1]	len_0	6420	1			T1	1		T5	79		T6	35

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

64

1

T5

1

T7

2

T31

2

auto[1]

len_upper

68

1

T18

3

T47

1

T13

2