Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4685591

1

T1

2395

T4

1

T5

1487

auto[1]

2982048

1

T1

2626

T4

1

T5

731

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2990901

1

T1

2628

T5

1852

T6

75387

auto[1]

4676738

1

T1

2393

T4

2

T5

366

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3565041

1

T4

1

T5

1621

T10

147903

auto[1]

4102598

1

T1

5021

T4

1

T5

597

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4672858

1

T1

1223

T5

1384

T10

147903

auto[1]

2994781

1

T1

3798

T4

2

T5

834

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6762531	1			T1	4702		T4	2		T5	2102
fifo_depth[1]	131193	1			T1	38		T5	23		T10	4844
fifo_depth[2]	106137	1			T1	47		T5	34		T10	4551
fifo_depth[3]	86878	1			T1	43		T5	17		T10	4035
fifo_depth[4]	79000	1			T1	50		T5	22		T10	3098
fifo_depth[5]	62640	1			T1	46		T5	8		T10	2349
fifo_depth[6]	51507	1			T1	44		T5	8		T10	1703
fifo_depth[7]	34112	1			T1	30		T5	2		T10	1046

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

905108

1

T1

319

T5

116

T10

22513

auto[1]

6762531

1

T1

4702

T4

2

T5

2102

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7651115

1

T1

5021

T4

2

T5

2218

auto[1]

16524

1

T6

254

T9

240

T22

818

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50485

1

T6

1501

T7

38

T8

11

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

35039

1

T5

69

T6

583

T7

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57487

1

T5

8

T6

776

T7

25

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

39070

1

T5

12

T6

942

T9

326

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

188786

1

T10

22513

T6

1564

T9

2637

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

38549

1

T6

251

T8

35

T9

1471

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44826

1

T5

15

T6

731

T7

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

50354

1

T6

1858

T7

20

T9

3535

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43057

1

T6

927

T7

35

T8

14

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

49928

1

T6

1045

T9

426

T22

559

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57427

1

T5

12

T6

1190

T7

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

49077

1

T1

319

T6

1085

T7

32

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

63857

1

T6

306

T9

1052

T22

321

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

43164

1

T6

2401

T7

8

T8

46

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50543

1

T6

379

T8

32

T9

1172

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43459

1

T6

3151

T7

19

T9

852

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

190566

1

T5

755

T6

3014

T7

697

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

204473

1

T5

429

T6

2990

T7

450

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

187394

1

T5

103

T6

7115

T7

1296

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

185786

1

T5

94

T6

5493

T7

601

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1710398

1

T5

7

T10

125390

T6

6461

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

204648

1

T4

1

T6

4548

T7

497

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

181675

1

T5

88

T6

2868

T7

684

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

195505

1

T5

41

T6

6498

T7

1263

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

437632

1

T5

103

T6

13794

T7

1137

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

481383

1

T1

4

T6

12288

T7

384

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

446528

1

T1

1223

T5

222

T6

10330

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

475569

1

T1

1082

T5

45

T6

12314

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

489770

1

T5

63

T6

6633

T17

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

453856

1

T1

2391

T5

61

T6

16869

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

472427

1

T5

8

T6

14513

T7

717

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

444921

1

T1

2

T4

1

T5

83

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

239277

1

T5

755

T6

4506

T7

735

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

238221

1

T5

498

T6

3573

T7

458

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

243395

1

T5

111

T6

7891

T7

1321

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

223287

1

T5

106

T6

6426

T7

601

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1897258

1

T5

7

T10

147903

T6

7932

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

242623

1

T4

1

T6

4799

T7

497

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

224496

1

T5

103

T6

3599

T7

691

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

244940

1

T5

41

T6

8349

T7

1283

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

480174

1

T5

103

T6

14721

T7

1172

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

531051

1

T1

4

T6

13332

T7

384

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

502850

1

T1

1223

T5

234

T6

11520

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

524222

1

T1

1401

T5

45

T6

13399

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

552857

1

T5

63

T6

6939

T17

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

495950

1

T1

2391

T5

61

T6

19209

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

522565

1

T5

8

T6

14818

T7

717

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

487949

1

T1

2

T4

1

T5

83

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1774

1

T6

9

T9

83

T22

37

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1291

1

T9

8

T44

145

T76

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1486

1

T9

13

T60

162

T123

186

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1569

1

T6

9

T22

315

T23

138

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1926

1

T6

93

T9

46

T44

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

574

1

T9

7

T22

235

T76

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2005

1

T9

6

T76

16

T124

17

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

919

1

T6

7

T9

56

T22

69

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

515

1

T9

4

T22

50

T125

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

260

1

T6

1

T22

4

T76

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1105

1

T9

1

T123

27

T125

168

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

424

1

T12

10

T46

29

T126

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

770

1

T22

10

T44

25

T123

140

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1070

1

T6

61

T22

33

T60

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

405

1

T6

74

T9

3

T22

65

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

431

1

T9

13

T23

12

T46

204

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

190566

1

T5

755

T6

3014

T7

697

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

204473

1

T5

429

T6

2990

T7

450

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

187394

1

T5

103

T6

7115

T7

1296

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

185786

1

T5

94

T6

5493

T7

601

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1710398

1

T5

7

T10

125390

T6

6461

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

204648

1

T4

1

T6

4548

T7

497

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

181675

1

T5

88

T6

2868

T7

684

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

195505

1

T5

41

T6

6498

T7

1263

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

437632

1

T5

103

T6

13794

T7

1137

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

481383

1

T1

4

T6

12288

T7

384

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

446528

1

T1

1223

T5

222

T6

10330

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

475569

1

T1

1082

T5

45

T6

12314

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

489770

1

T5

63

T6

6633

T17

3

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

453856

1

T1

2391

T5

61

T6

16869

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

472427

1

T5

8

T6

14513

T7

717

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

444921

1

T1

2

T4

1

T5

83

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4609

1

T6

89

T7

31

T8

4

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3947

1

T5

10

T6

124

T7

7

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4992

1

T6

156

T7

19

T8

20

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3947

1

T5

4

T6

13

T9

5

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

46696

1

T10

4844

T6

178

T9

13

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4524

1

T6

45

T8

24

T9

87

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4489

1

T5

4

T6

51

T7

5

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4325

1

T6

174

T7

14

T9

8

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6156

1

T6

167

T7

23

T8

7

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7013

1

T6

49

T9

3

T22

52

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6856

1

T5

5

T6

171

T7

4

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6463

1

T1

38

T6

174

T7

23

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8309

1

T6

49

T9

9

T22

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5361

1

T6

141

T7

7

T8

27

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6834

1

T6

43

T8

19

T9

6

fifo_depth[1]

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6

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5

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1

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8

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4

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6

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9

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46

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3

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62

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1

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3

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1

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1

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47

T6

178

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7

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46

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27

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1

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1

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15

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5

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4

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89

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1

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4

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71

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6

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1

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149

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19

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4

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41

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7

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1

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2

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1

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47

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20

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91

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74

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1

T10

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T6

142

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60

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1

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38

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89

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91

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20

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3

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85

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1

T6

144

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1

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4

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1

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50

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8

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219

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1

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155

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52

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49

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1

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1

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59

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2

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19

fifo_depth[5]

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1

T5

5

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74

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72

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5

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T10

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122

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39

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95

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77

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6

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41

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11

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130

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42

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21

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T10

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93

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84

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12

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249

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32

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fifo_depth[6]

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44

T6

108

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94

fifo_depth[6]

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41

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81

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52

fifo_depth[7]

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22

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T6

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74

T22

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fifo_depth[7]

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T6

55

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1

T6

66

T9

88

T22

274

fifo_depth[7]

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T6

52

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17

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14

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T22

37

fifo_depth[7]

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T6

67

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22

T22

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1

T1

30

T6

83

T17

59

fifo_depth[7]

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1

T6

15

T9

47

T22

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fifo_depth[7]

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1

T6

84

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12

T25

66

fifo_depth[7]

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14

T9

78

T22

26

fifo_depth[7]

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1

T6

171

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1

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17