Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18497013	1			T1	9995		T4	547		T5	1376
all_pins[1]	18497013	1			T1	9995		T4	547		T5	1376
all_pins[2]	18497013	1			T1	9995		T4	547		T5	1376

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47381859	1			T1	26438		T4	1637		T5	3443
values[0x1]	8109180	1			T1	3547		T4	4		T5	685
transitions[0x0=>0x1]	8108999	1			T1	3547		T4	4		T5	685
transitions[0x1=>0x0]	8109015	1			T1	3547		T4	4		T5	685

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18475767	1			T1	9993		T4	543		T5	1358
all_pins[0]	values[0x1]	21246	1			T1	2		T4	4		T5	18
all_pins[0]	transitions[0x0=>0x1]	21167	1			T1	2		T4	4		T5	18
all_pins[0]	transitions[0x1=>0x0]	8087452	1			T1	3545		T5	667		T10	124107
all_pins[1]	values[0x0]	18496594	1			T1	9995		T4	547		T5	1376
all_pins[1]	values[0x1]	419	1			T6	12		T9	20		T22	12
all_pins[1]	transitions[0x0=>0x1]	363	1			T6	11		T9	18		T22	12
all_pins[1]	transitions[0x1=>0x0]	21190	1			T1	2		T4	4		T5	18
all_pins[2]	values[0x0]	10409498	1			T1	6450		T4	547		T5	709
all_pins[2]	values[0x1]	8087515	1			T1	3545		T5	667		T10	124107
all_pins[2]	transitions[0x0=>0x1]	8087469	1			T1	3545		T5	667		T10	124107
all_pins[2]	transitions[0x1=>0x0]	373	1			T6	10		T9	18		T22	10