Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1030 1 T6 16 T9 45 T22 27
all_values[1] 1030 1 T6 16 T9 45 T22 27
all_values[2] 1030 1 T6 16 T9 45 T22 27


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T6 20 T9 53 T22 55
auto[1] 1490 1 T6 28 T9 82 T22 26


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1016 1 T6 9 T9 54 T22 26
auto[1] 2074 1 T6 39 T9 81 T22 55


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1724 1 T6 21 T9 82 T22 45
auto[1] 1366 1 T6 27 T9 53 T22 36


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 190 1 T6 1 T9 9 T22 11
all_values[0] auto[0] auto[0] auto[1] 106 1 T6 1 T9 3 T22 4
all_values[0] auto[0] auto[1] auto[0] 175 1 T9 15 T22 2 T67 3
all_values[0] auto[0] auto[1] auto[1] 112 1 T6 3 T9 5 T22 2
all_values[0] auto[1] auto[0] auto[1] 228 1 T6 4 T9 4 T22 6
all_values[0] auto[1] auto[1] auto[1] 219 1 T6 7 T9 9 T22 2
all_values[1] auto[0] auto[0] auto[0] 163 1 T6 1 T9 7 T22 2
all_values[1] auto[0] auto[0] auto[1] 146 1 T6 3 T9 4 T22 4
all_values[1] auto[0] auto[1] auto[0] 145 1 T6 1 T9 9 T22 2
all_values[1] auto[0] auto[1] auto[1] 122 1 T6 2 T9 7 T22 4
all_values[1] auto[1] auto[0] auto[1] 236 1 T6 4 T9 8 T22 9
all_values[1] auto[1] auto[1] auto[1] 218 1 T6 5 T9 10 T22 6
all_values[2] auto[0] auto[0] auto[0] 181 1 T6 2 T9 7 T22 6
all_values[2] auto[0] auto[0] auto[1] 110 1 T6 1 T9 5 T22 4
all_values[2] auto[0] auto[1] auto[0] 162 1 T6 4 T9 7 T22 3
all_values[2] auto[0] auto[1] auto[1] 112 1 T6 2 T9 4 T22 1
all_values[2] auto[1] auto[0] auto[1] 240 1 T6 3 T9 6 T22 9
all_values[2] auto[1] auto[1] auto[1] 225 1 T6 4 T9 16 T22 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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