Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4390	1			T1	1		T5	7		T6	89
sha2_none	4427	1			T1	4		T5	5		T6	105
sha2_512	7804	1			T1	2		T5	4		T6	90
sha2_384	7564	1			T4	3		T5	9		T10	386
sha2_256	6547	1			T5	1		T6	76		T7	9

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19406

1

T1

3

T4

1

T5

12

auto[1]

11722

1

T1

4

T4

2

T5

14

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11648

1

T1

5

T5

15

T6

210

auto[1]

19480

1

T1

2

T4

3

T5

11

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15958

1

T1

7

T4

2

T5

13

disabled

15170

1

T4

1

T5

13

T10

386

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4794	1			T1	1		T4	1		T5	3
key_none	7915	1			T5	4		T10	386		T6	70
key_1024	4480	1			T1	1		T4	2		T5	2
key_512	3962	1			T1	3		T5	5		T6	68
key_384	3589	1			T5	4		T6	63		T7	4
key_256	3164	1			T1	1		T5	3		T6	59
key_128	3142	1			T1	1		T5	4		T6	48

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19462

1

T1

1

T5

17

T10

386

auto[1]

11666

1

T1

6

T4

3

T5

9

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30933

1

T1

7

T4

3

T5

26

disabled

195

1

T6

5

T9

2

T33

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1679

1

T5

2

T6

32

T7

1

enabled

auto[0]

auto[0]

auto[1]

1618

1

T1

2

T6

32

T7

1

enabled

auto[0]

auto[1]

auto[0]

1603

1

T1

1

T5

3

T6

31

enabled

auto[0]

auto[1]

auto[1]

1612

1

T1

2

T5

1

T6

37

enabled

auto[1]

auto[0]

auto[0]

4382

1

T5

1

T6

29

T17

2

enabled

auto[1]

auto[0]

auto[1]

1655

1

T1

1

T5

1

T6

38

enabled

auto[1]

auto[1]

auto[0]

1775

1

T5

4

T6

44

T7

1

enabled

auto[1]

auto[1]

auto[1]

1634

1

T1

1

T4

2

T5

1

disabled

auto[0]

auto[0]

auto[0]

1366

1

T5

4

T6

19

T7

3

disabled

auto[0]

auto[0]

auto[1]

1234

1

T5

3

T6

15

T7

4

disabled

auto[0]

auto[1]

auto[0]

1293

1

T5

1

T6

22

T7

4

disabled

auto[0]

auto[1]

auto[1]

1243

1

T5

1

T6

22

T7

1

disabled

auto[1]

auto[0]

auto[0]

6124

1

T5

1

T10

386

T6

35

disabled

auto[1]

auto[0]

auto[1]

1348

1

T4

1

T6

22

T7

1

disabled

auto[1]

auto[1]

auto[0]

1240

1

T5

1

T6

24

T7

2

disabled

auto[1]

auto[1]

auto[1]

1322

1

T5

2

T6

31

T7

6

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15879

1

T1

7

T4

2

T5

13

enabled

disabled

79

1

T9

1

T33

1

T38

1

disabled

disabled

116

1

T6

5

T9

1

T33

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15054

1

T4

1

T5

13

T10

386

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1079	1			T5	1		T6	21		T8	1
key_invalid	sha2_none	937	1			T1	1		T6	24		T7	3
key_invalid	sha2_512	862	1			T5	1		T6	18		T7	2
key_invalid	sha2_384	919	1			T4	1		T5	1		T6	22
key_invalid	sha2_256	893	1			T6	17		T7	2		T17	1
key_none	sha2_invalid	571	1			T5	1		T6	13		T9	5
key_none	sha2_none	566	1			T5	1		T6	18		T7	1
key_none	sha2_512	2569	1			T5	1		T6	15		T7	1
key_none	sha2_384	2519	1			T10	386		T6	10		T7	1
key_none	sha2_256	1653	1			T5	1		T6	13		T7	2
key_1024	sha2_invalid	552	1			T6	14		T7	2		T8	1
key_1024	sha2_none	594	1			T1	1		T6	11		T9	6
key_1024	sha2_512	1774	1			T6	10		T7	2		T8	1
key_1024	sha2_384	931	1			T4	2		T5	2		T6	16
key_512	sha2_invalid	576	1			T1	1		T5	2		T6	11
key_512	sha2_none	563	1			T1	1		T5	1		T6	13
key_512	sha2_512	658	1			T1	1		T6	16		T8	1
key_512	sha2_384	1237	1			T5	2		T6	17		T7	2
key_512	sha2_256	881	1			T6	11		T7	1		T9	5
key_384	sha2_invalid	513	1			T5	1		T6	10		T7	2
key_384	sha2_none	600	1			T6	15		T8	1		T9	9
key_384	sha2_512	681	1			T6	13		T7	1		T8	1
key_384	sha2_384	637	1			T5	3		T6	20		T17	1
key_384	sha2_256	1119	1			T6	5		T7	1		T8	1
key_256	sha2_invalid	529	1			T6	11		T9	5		T22	5
key_256	sha2_none	576	1			T5	2		T6	14		T8	2
key_256	sha2_512	631	1			T1	1		T6	12		T7	1
key_256	sha2_384	646	1			T5	1		T6	9		T9	5
key_256	sha2_256	725	1			T6	13		T7	1		T8	2
key_128	sha2_invalid	547	1			T5	1		T6	8		T7	1
key_128	sha2_none	578	1			T1	1		T5	1		T6	10
key_128	sha2_512	619	1			T5	2		T6	6		T8	2
key_128	sha2_384	664	1			T6	12		T7	2		T17	1
key_128	sha2_256	679	1			T6	11		T9	5		T22	4

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

575

1

T6

6

T7

2

T9

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1079	1			T5	1		T6	21		T8	1
key_invalid	sha2_none	937	1			T1	1		T6	24		T7	3
key_invalid	sha2_512	862	1			T5	1		T6	18		T7	2
key_invalid	sha2_384	919	1			T4	1		T5	1		T6	22
key_invalid	sha2_256	893	1			T6	17		T7	2		T17	1
key_none	sha2_invalid	571	1			T5	1		T6	13		T9	5
key_none	sha2_none	566	1			T5	1		T6	18		T7	1
key_none	sha2_512	2569	1			T5	1		T6	15		T7	1
key_none	sha2_384	2519	1			T10	386		T6	10		T7	1
key_none	sha2_256	1653	1			T5	1		T6	13		T7	2
key_1024	sha2_invalid	552	1			T6	14		T7	2		T8	1
key_1024	sha2_none	594	1			T1	1		T6	11		T9	6
key_1024	sha2_512	1774	1			T6	10		T7	2		T8	1
key_1024	sha2_384	931	1			T4	2		T5	2		T6	16
key_1024	sha2_256	575	1			T6	6		T7	2		T9	2
key_512	sha2_invalid	576	1			T1	1		T5	2		T6	11
key_512	sha2_none	563	1			T1	1		T5	1		T6	13
key_512	sha2_512	658	1			T1	1		T6	16		T8	1
key_512	sha2_384	1237	1			T5	2		T6	17		T7	2
key_512	sha2_256	881	1			T6	11		T7	1		T9	5
key_384	sha2_invalid	513	1			T5	1		T6	10		T7	2
key_384	sha2_none	600	1			T6	15		T8	1		T9	9
key_384	sha2_512	681	1			T6	13		T7	1		T8	1
key_384	sha2_384	637	1			T5	3		T6	20		T17	1
key_384	sha2_256	1119	1			T6	5		T7	1		T8	1
key_256	sha2_invalid	529	1			T6	11		T9	5		T22	5
key_256	sha2_none	576	1			T5	2		T6	14		T8	2
key_256	sha2_512	631	1			T1	1		T6	12		T7	1
key_256	sha2_384	646	1			T5	1		T6	9		T9	5
key_256	sha2_256	725	1			T6	13		T7	1		T8	2
key_128	sha2_invalid	547	1			T5	1		T6	8		T7	1
key_128	sha2_none	578	1			T1	1		T5	1		T6	10
key_128	sha2_512	619	1			T5	2		T6	6		T8	2
key_128	sha2_384	664	1			T6	12		T7	2		T17	1
key_128	sha2_256	679	1			T6	11		T9	5		T22	4