Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 657
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T529 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3012981579 Jul 17 06:28:18 PM PDT 24 Jul 17 06:28:20 PM PDT 24 17774693 ps
T89 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3767116287 Jul 17 06:28:17 PM PDT 24 Jul 17 06:28:21 PM PDT 24 160689436 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1360354855 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:40 PM PDT 24 83653930 ps
T530 /workspace/coverage/cover_reg_top/12.hmac_intr_test.4255711477 Jul 17 06:29:28 PM PDT 24 Jul 17 06:29:29 PM PDT 24 43622333 ps
T531 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2529093588 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:03 PM PDT 24 18933201 ps
T532 /workspace/coverage/cover_reg_top/13.hmac_intr_test.260779000 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:39 PM PDT 24 13590129 ps
T63 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.700136319 Jul 17 06:29:48 PM PDT 24 Jul 17 06:29:50 PM PDT 24 355574598 ps
T533 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.32192133 Jul 17 06:29:15 PM PDT 24 Jul 17 06:29:18 PM PDT 24 152534580 ps
T534 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2974018793 Jul 17 06:29:03 PM PDT 24 Jul 17 06:29:06 PM PDT 24 186255451 ps
T64 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.591674466 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:55 PM PDT 24 1478234862 ps
T535 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1285421236 Jul 17 06:28:53 PM PDT 24 Jul 17 06:28:57 PM PDT 24 45636381 ps
T112 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1669473216 Jul 17 06:29:01 PM PDT 24 Jul 17 06:29:05 PM PDT 24 193742755 ps
T536 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2979517098 Jul 17 06:30:14 PM PDT 24 Jul 17 06:30:15 PM PDT 24 23185058 ps
T90 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2859429567 Jul 17 06:29:38 PM PDT 24 Jul 17 06:29:41 PM PDT 24 130058966 ps
T113 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4010684388 Jul 17 06:29:14 PM PDT 24 Jul 17 06:29:19 PM PDT 24 418842592 ps
T537 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3129480640 Jul 17 06:30:02 PM PDT 24 Jul 17 06:30:03 PM PDT 24 21442774 ps
T102 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.85236179 Jul 17 06:29:25 PM PDT 24 Jul 17 06:29:28 PM PDT 24 542357666 ps
T91 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3104240202 Jul 17 06:28:06 PM PDT 24 Jul 17 06:28:08 PM PDT 24 22906122 ps
T538 /workspace/coverage/cover_reg_top/1.hmac_intr_test.471827512 Jul 17 06:28:17 PM PDT 24 Jul 17 06:28:18 PM PDT 24 26180452 ps
T539 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1528706004 Jul 17 06:29:35 PM PDT 24 Jul 17 06:29:39 PM PDT 24 155192712 ps
T540 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1665662287 Jul 17 06:29:02 PM PDT 24 Jul 17 06:29:03 PM PDT 24 37417262 ps
T103 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3124640781 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:55 PM PDT 24 263766914 ps
T541 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2600905045 Jul 17 06:28:40 PM PDT 24 Jul 17 06:28:46 PM PDT 24 3716301901 ps
T104 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2272961830 Jul 17 06:29:26 PM PDT 24 Jul 17 06:29:28 PM PDT 24 125308939 ps
T542 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3377282436 Jul 17 06:30:03 PM PDT 24 Jul 17 06:30:04 PM PDT 24 56439140 ps
T543 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.116719933 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:39 PM PDT 24 254155334 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3565313169 Jul 17 06:28:39 PM PDT 24 Jul 17 06:28:41 PM PDT 24 36850135 ps
T544 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2388758202 Jul 17 06:29:47 PM PDT 24 Jul 17 06:29:51 PM PDT 24 498098620 ps
T114 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1036828524 Jul 17 06:29:35 PM PDT 24 Jul 17 06:29:39 PM PDT 24 299711470 ps
T545 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2910341712 Jul 17 06:29:47 PM PDT 24 Jul 17 06:29:48 PM PDT 24 34992206 ps
T116 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1140828383 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:41 PM PDT 24 210197613 ps
T93 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1373823816 Jul 17 06:29:01 PM PDT 24 Jul 17 06:29:03 PM PDT 24 180240302 ps
T546 /workspace/coverage/cover_reg_top/16.hmac_intr_test.4193442246 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:38 PM PDT 24 44827242 ps
T94 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3119776079 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:39 PM PDT 24 60807529 ps
T115 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3782055714 Jul 17 06:29:03 PM PDT 24 Jul 17 06:29:08 PM PDT 24 724908625 ps
T105 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.863924251 Jul 17 06:29:48 PM PDT 24 Jul 17 06:29:51 PM PDT 24 285529161 ps
T547 /workspace/coverage/cover_reg_top/48.hmac_intr_test.823242132 Jul 17 06:30:13 PM PDT 24 Jul 17 06:30:14 PM PDT 24 13234248 ps
T548 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1033748911 Jul 17 06:29:38 PM PDT 24 Jul 17 06:29:41 PM PDT 24 79546352 ps
T549 /workspace/coverage/cover_reg_top/21.hmac_intr_test.934345449 Jul 17 06:29:49 PM PDT 24 Jul 17 06:29:50 PM PDT 24 43301576 ps
T95 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3041405241 Jul 17 06:28:40 PM PDT 24 Jul 17 06:28:42 PM PDT 24 149767459 ps
T106 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3268861969 Jul 17 06:29:01 PM PDT 24 Jul 17 06:29:03 PM PDT 24 36210580 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1177098567 Jul 17 06:28:30 PM PDT 24 Jul 17 06:28:32 PM PDT 24 96239928 ps
T550 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3530932754 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:40 PM PDT 24 398068117 ps
T551 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.844217339 Jul 17 06:28:29 PM PDT 24 Jul 17 06:28:32 PM PDT 24 687652614 ps
T119 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1782756202 Jul 17 06:28:08 PM PDT 24 Jul 17 06:28:13 PM PDT 24 1124646108 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2495513969 Jul 17 06:28:30 PM PDT 24 Jul 17 06:28:35 PM PDT 24 925261907 ps
T552 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4147202684 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:39 PM PDT 24 72700028 ps
T553 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2120682002 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:03 PM PDT 24 30194470 ps
T554 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3644844247 Jul 17 06:30:17 PM PDT 24 Jul 17 06:30:18 PM PDT 24 19876253 ps
T555 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1090778884 Jul 17 06:30:00 PM PDT 24 Jul 17 06:30:01 PM PDT 24 13842654 ps
T556 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2889839430 Jul 17 06:29:14 PM PDT 24 Jul 17 06:29:15 PM PDT 24 20452144 ps
T557 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.658358909 Jul 17 06:29:02 PM PDT 24 Jul 17 06:29:06 PM PDT 24 499958272 ps
T558 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.760643827 Jul 17 06:29:48 PM PDT 24 Jul 17 06:29:49 PM PDT 24 119402724 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_intr_test.229108249 Jul 17 06:29:13 PM PDT 24 Jul 17 06:29:14 PM PDT 24 13286305 ps
T96 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2055755437 Jul 17 06:29:28 PM PDT 24 Jul 17 06:29:29 PM PDT 24 324164634 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.309231871 Jul 17 06:29:26 PM PDT 24 Jul 17 06:29:28 PM PDT 24 104283445 ps
T561 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3390880100 Jul 17 06:28:50 PM PDT 24 Jul 17 06:28:56 PM PDT 24 115371584 ps
T97 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1623496083 Jul 17 06:28:52 PM PDT 24 Jul 17 06:28:59 PM PDT 24 419496010 ps
T562 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3976594208 Jul 17 06:29:25 PM PDT 24 Jul 17 06:29:28 PM PDT 24 376595315 ps
T563 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3416363027 Jul 17 06:30:14 PM PDT 24 Jul 17 06:30:15 PM PDT 24 45697554 ps
T564 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1792660131 Jul 17 06:28:16 PM PDT 24 Jul 17 06:40:02 PM PDT 24 387344345950 ps
T565 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.162943845 Jul 17 06:29:14 PM PDT 24 Jul 17 06:29:16 PM PDT 24 180267192 ps
T566 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1482610110 Jul 17 06:29:26 PM PDT 24 Jul 17 06:29:27 PM PDT 24 18566567 ps
T567 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1967456793 Jul 17 06:30:00 PM PDT 24 Jul 17 06:30:01 PM PDT 24 13412453 ps
T568 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2867494410 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:38 PM PDT 24 40068987 ps
T569 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3481775534 Jul 17 06:29:38 PM PDT 24 Jul 17 06:29:41 PM PDT 24 177230877 ps
T570 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2841402998 Jul 17 06:28:39 PM PDT 24 Jul 17 06:28:42 PM PDT 24 334263156 ps
T117 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2964221849 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:39 PM PDT 24 173737639 ps
T571 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1615017378 Jul 17 06:29:49 PM PDT 24 Jul 17 06:29:50 PM PDT 24 53601488 ps
T572 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1048374274 Jul 17 06:29:01 PM PDT 24 Jul 17 06:29:04 PM PDT 24 407188071 ps
T573 /workspace/coverage/cover_reg_top/5.hmac_intr_test.230573967 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:52 PM PDT 24 28319865 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.195549760 Jul 17 06:28:17 PM PDT 24 Jul 17 06:28:28 PM PDT 24 862420448 ps
T574 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1082800767 Jul 17 06:30:13 PM PDT 24 Jul 17 06:30:15 PM PDT 24 15033945 ps
T575 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2973069768 Jul 17 06:29:15 PM PDT 24 Jul 17 06:29:18 PM PDT 24 169475427 ps
T576 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.313222424 Jul 17 06:28:29 PM PDT 24 Jul 17 06:28:30 PM PDT 24 19572331 ps
T577 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1071826792 Jul 17 06:30:00 PM PDT 24 Jul 17 06:30:02 PM PDT 24 29543676 ps
T578 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1537596997 Jul 17 06:29:02 PM PDT 24 Jul 17 06:29:03 PM PDT 24 13911816 ps
T579 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3732315255 Jul 17 06:29:48 PM PDT 24 Jul 17 06:29:50 PM PDT 24 106540798 ps
T580 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3320767551 Jul 17 06:29:39 PM PDT 24 Jul 17 06:29:41 PM PDT 24 34900479 ps
T581 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.270067539 Jul 17 06:29:27 PM PDT 24 Jul 17 06:29:31 PM PDT 24 273930382 ps
T582 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.343770228 Jul 17 06:29:13 PM PDT 24 Jul 17 06:29:15 PM PDT 24 17144482 ps
T98 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.414498650 Jul 17 06:30:15 PM PDT 24 Jul 17 06:30:17 PM PDT 24 20115557 ps
T583 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3072327030 Jul 17 06:29:01 PM PDT 24 Jul 17 06:29:03 PM PDT 24 49966100 ps
T584 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2446943015 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:03 PM PDT 24 14324444 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.938455079 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:52 PM PDT 24 35551613 ps
T586 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4217894158 Jul 17 06:29:04 PM PDT 24 Jul 17 06:29:06 PM PDT 24 190221944 ps
T587 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2183597990 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:54 PM PDT 24 385935411 ps
T588 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.545384351 Jul 17 06:28:32 PM PDT 24 Jul 17 06:28:34 PM PDT 24 60486262 ps
T589 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3173746417 Jul 17 06:29:14 PM PDT 24 Jul 17 06:29:17 PM PDT 24 46507516 ps
T590 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2552222330 Jul 17 06:29:28 PM PDT 24 Jul 17 06:29:31 PM PDT 24 151593309 ps
T591 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1989844841 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:39 PM PDT 24 46478292 ps
T592 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.953407789 Jul 17 06:29:27 PM PDT 24 Jul 17 06:29:30 PM PDT 24 69589281 ps
T593 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1347009523 Jul 17 06:28:16 PM PDT 24 Jul 17 06:28:19 PM PDT 24 286024489 ps
T594 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3058327282 Jul 17 06:28:52 PM PDT 24 Jul 17 06:28:55 PM PDT 24 191827397 ps
T595 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.373865618 Jul 17 06:29:26 PM PDT 24 Jul 17 06:29:31 PM PDT 24 1763678017 ps
T596 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2992622394 Jul 17 06:30:13 PM PDT 24 Jul 17 06:30:14 PM PDT 24 11240520 ps
T597 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.267022790 Jul 17 06:29:46 PM PDT 24 Jul 17 06:51:39 PM PDT 24 261926078511 ps
T598 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3741921026 Jul 17 06:28:19 PM PDT 24 Jul 17 06:28:23 PM PDT 24 85440903 ps
T599 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1538014285 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:42 PM PDT 24 1126994008 ps
T600 /workspace/coverage/cover_reg_top/49.hmac_intr_test.514848198 Jul 17 06:30:15 PM PDT 24 Jul 17 06:30:16 PM PDT 24 62581134 ps
T601 /workspace/coverage/cover_reg_top/2.hmac_intr_test.30287815 Jul 17 06:28:29 PM PDT 24 Jul 17 06:28:30 PM PDT 24 48123688 ps
T602 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3035006086 Jul 17 06:28:05 PM PDT 24 Jul 17 06:28:06 PM PDT 24 14531449 ps
T603 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1984142671 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:02 PM PDT 24 90069701 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2762786093 Jul 17 06:28:38 PM PDT 24 Jul 17 06:28:55 PM PDT 24 2225846711 ps
T605 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3398474747 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:38 PM PDT 24 35594134 ps
T606 /workspace/coverage/cover_reg_top/32.hmac_intr_test.992284087 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:03 PM PDT 24 67074803 ps
T607 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1565397862 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:41 PM PDT 24 50455426 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1901472697 Jul 17 06:29:36 PM PDT 24 Jul 17 06:29:39 PM PDT 24 208519889 ps
T609 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1961506894 Jul 17 06:29:02 PM PDT 24 Jul 17 06:29:03 PM PDT 24 85666555 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.769267682 Jul 17 06:29:47 PM PDT 24 Jul 17 06:29:50 PM PDT 24 63859655 ps
T611 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3470930935 Jul 17 06:30:02 PM PDT 24 Jul 17 06:30:04 PM PDT 24 118492042 ps
T612 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1445216352 Jul 17 06:28:07 PM PDT 24 Jul 17 06:28:10 PM PDT 24 303069502 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2790692336 Jul 17 06:28:32 PM PDT 24 Jul 17 06:28:36 PM PDT 24 52347145 ps
T614 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3060694163 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:53 PM PDT 24 29417905 ps
T615 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.293861730 Jul 17 06:29:03 PM PDT 24 Jul 17 06:29:05 PM PDT 24 90281645 ps
T616 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4094380898 Jul 17 06:29:47 PM PDT 24 Jul 17 06:29:51 PM PDT 24 181237797 ps
T617 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3949489144 Jul 17 06:28:50 PM PDT 24 Jul 17 06:28:55 PM PDT 24 373356194 ps
T618 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1312946396 Jul 17 06:30:14 PM PDT 24 Jul 17 06:30:16 PM PDT 24 40171701 ps
T619 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2910088406 Jul 17 06:29:14 PM PDT 24 Jul 17 06:29:18 PM PDT 24 106303663 ps
T620 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3219521026 Jul 17 06:28:29 PM PDT 24 Jul 17 06:28:31 PM PDT 24 72475582 ps
T621 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.713160415 Jul 17 06:29:37 PM PDT 24 Jul 17 06:29:40 PM PDT 24 199857776 ps
T622 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2411424774 Jul 17 06:28:53 PM PDT 24 Jul 17 06:28:54 PM PDT 24 61603256 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3434576126 Jul 17 06:29:39 PM PDT 24 Jul 17 06:29:42 PM PDT 24 822786260 ps
T624 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3620870931 Jul 17 06:28:50 PM PDT 24 Jul 17 06:28:52 PM PDT 24 22643744 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1098330927 Jul 17 06:28:30 PM PDT 24 Jul 17 06:28:37 PM PDT 24 2677954888 ps
T626 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2823326646 Jul 17 06:28:41 PM PDT 24 Jul 17 06:28:42 PM PDT 24 54719207 ps
T627 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2056007638 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:02 PM PDT 24 45743480 ps
T628 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4052418252 Jul 17 06:29:38 PM PDT 24 Jul 17 06:29:40 PM PDT 24 15568337 ps
T629 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2754245882 Jul 17 06:28:16 PM PDT 24 Jul 17 06:28:18 PM PDT 24 578743543 ps
T630 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1818018292 Jul 17 06:29:49 PM PDT 24 Jul 17 06:40:41 PM PDT 24 61498798950 ps
T631 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3407824968 Jul 17 06:29:47 PM PDT 24 Jul 17 06:29:48 PM PDT 24 294827912 ps
T632 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2061347986 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:03 PM PDT 24 47607838 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1630228160 Jul 17 06:28:32 PM PDT 24 Jul 17 06:28:39 PM PDT 24 1306715878 ps
T634 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1696468079 Jul 17 06:29:29 PM PDT 24 Jul 17 06:29:30 PM PDT 24 56016019 ps
T635 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2861784445 Jul 17 06:28:16 PM PDT 24 Jul 17 06:28:18 PM PDT 24 49601488 ps
T636 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1991627810 Jul 17 06:30:02 PM PDT 24 Jul 17 06:30:04 PM PDT 24 29982978 ps
T637 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2409153098 Jul 17 06:30:22 PM PDT 24 Jul 17 06:30:24 PM PDT 24 147125646 ps
T638 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1878366934 Jul 17 06:29:49 PM PDT 24 Jul 17 06:29:51 PM PDT 24 18473130 ps
T639 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.656010834 Jul 17 06:28:30 PM PDT 24 Jul 17 06:28:46 PM PDT 24 1184397861 ps
T640 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3290678271 Jul 17 06:28:51 PM PDT 24 Jul 17 06:28:54 PM PDT 24 580514167 ps
T641 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1604118916 Jul 17 06:28:05 PM PDT 24 Jul 17 06:28:12 PM PDT 24 1480795777 ps
T642 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1153669293 Jul 17 06:29:48 PM PDT 24 Jul 17 06:29:49 PM PDT 24 12900294 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2210820709 Jul 17 06:28:31 PM PDT 24 Jul 17 06:28:32 PM PDT 24 59475027 ps
T644 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1609226601 Jul 17 06:28:52 PM PDT 24 Jul 17 06:28:56 PM PDT 24 185421970 ps
T645 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3732594850 Jul 17 06:29:13 PM PDT 24 Jul 17 06:29:15 PM PDT 24 23309286 ps
T646 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.489083550 Jul 17 06:29:27 PM PDT 24 Jul 17 06:29:31 PM PDT 24 64380204 ps
T647 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1482299386 Jul 17 06:29:50 PM PDT 24 Jul 17 06:29:51 PM PDT 24 34742396 ps
T648 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2355372403 Jul 17 06:30:01 PM PDT 24 Jul 17 06:30:02 PM PDT 24 30451774 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3548287336 Jul 17 06:29:16 PM PDT 24 Jul 17 06:29:17 PM PDT 24 40477697 ps
T650 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2776229585 Jul 17 06:30:36 PM PDT 24 Jul 17 06:30:38 PM PDT 24 130098545 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.932299612 Jul 17 06:29:38 PM PDT 24 Jul 17 06:29:41 PM PDT 24 126510131 ps
T652 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2915354681 Jul 17 06:30:03 PM PDT 24 Jul 17 06:30:04 PM PDT 24 14040215 ps
T653 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2996702791 Jul 17 06:30:17 PM PDT 24 Jul 17 06:30:19 PM PDT 24 55587027 ps
T654 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3802122164 Jul 17 06:30:15 PM PDT 24 Jul 17 06:30:16 PM PDT 24 49886788 ps
T655 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3000058367 Jul 17 06:28:41 PM PDT 24 Jul 17 06:28:44 PM PDT 24 446049438 ps
T656 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2857400048 Jul 17 06:30:19 PM PDT 24 Jul 17 06:30:20 PM PDT 24 79825941 ps
T657 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1634509468 Jul 17 06:29:16 PM PDT 24 Jul 17 06:29:19 PM PDT 24 45349992 ps

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3623189230
Short name T6
Test name
Test status
Simulation time 127882934646 ps
CPU time 4602.53 seconds
Started Jul 17 06:31:34 PM PDT 24
Finished Jul 17 07:48:18 PM PDT 24
Peak memory 825296 kb
Host smart-52b273e9-dd4b-4bae-bec8-5c92537559b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623189230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3623189230
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2075987832
Short name T20
Test name
Test status
Simulation time 42546690105 ps
CPU time 3395.04 seconds
Started Jul 17 06:31:11 PM PDT 24
Finished Jul 17 07:27:48 PM PDT 24
Peak memory 814640 kb
Host smart-85d965cd-3d34-4ca2-abe2-2c301b1e3b5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075987832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2075987832
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1821676334
Short name T7
Test name
Test status
Simulation time 9297069556 ps
CPU time 129.51 seconds
Started Jul 17 06:36:21 PM PDT 24
Finished Jul 17 06:38:31 PM PDT 24
Peak memory 216716 kb
Host smart-e4ab72aa-e68a-4b6b-b828-811ef2445769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821676334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1821676334
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4010684388
Short name T113
Test name
Test status
Simulation time 418842592 ps
CPU time 4.23 seconds
Started Jul 17 06:29:14 PM PDT 24
Finished Jul 17 06:29:19 PM PDT 24
Peak memory 200256 kb
Host smart-d92e6335-8ff9-4362-97f3-0576e08cdeb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010684388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4010684388
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/33.hmac_stress_all.951616283
Short name T22
Test name
Test status
Simulation time 31019908161 ps
CPU time 375.2 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:40:58 PM PDT 24
Peak memory 200300 kb
Host smart-f86ea25a-2589-421a-9ba7-c56545558ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951616283 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.951616283
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_alert_test.941710626
Short name T34
Test name
Test status
Simulation time 58424889 ps
CPU time 0.6 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:09 PM PDT 24
Peak memory 196176 kb
Host smart-8da1676e-719b-40e3-83d9-580d70fcc2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941710626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.941710626
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3041405241
Short name T95
Test name
Test status
Simulation time 149767459 ps
CPU time 0.93 seconds
Started Jul 17 06:28:40 PM PDT 24
Finished Jul 17 06:28:42 PM PDT 24
Peak memory 199996 kb
Host smart-f36f7eea-0a17-4ff8-b905-c9e9df09ef92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041405241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3041405241
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.838490422
Short name T13
Test name
Test status
Simulation time 1662596212 ps
CPU time 106.65 seconds
Started Jul 17 06:30:39 PM PDT 24
Finished Jul 17 06:32:26 PM PDT 24
Peak memory 200304 kb
Host smart-f9fd3daf-12ee-4c61-ac5f-243860260cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838490422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.838490422
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1450466492
Short name T50
Test name
Test status
Simulation time 77560462 ps
CPU time 0.93 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:30:25 PM PDT 24
Peak memory 218436 kb
Host smart-73d0f96d-438b-4213-a273-636fc82f9481
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450466492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1450466492
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1067870299
Short name T9
Test name
Test status
Simulation time 10071635292 ps
CPU time 524.93 seconds
Started Jul 17 06:34:50 PM PDT 24
Finished Jul 17 06:43:36 PM PDT 24
Peak memory 216748 kb
Host smart-89f74ba5-70c5-4c29-b476-d371edabbc56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067870299 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1067870299
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all.447206980
Short name T69
Test name
Test status
Simulation time 59706880833 ps
CPU time 1615.68 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 06:57:34 PM PDT 24
Peak memory 743520 kb
Host smart-ab47b3af-b090-47cd-9ba0-b726c277113a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447206980 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.447206980
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1538014285
Short name T599
Test name
Test status
Simulation time 1126994008 ps
CPU time 4.33 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:42 PM PDT 24
Peak memory 200364 kb
Host smart-6c2cf00d-657c-436f-9d82-f9aab4db948c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538014285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1538014285
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2964221849
Short name T117
Test name
Test status
Simulation time 173737639 ps
CPU time 1.75 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200260 kb
Host smart-50c79321-01c3-4217-b3eb-7ddc878ffd34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964221849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2964221849
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1659551794
Short name T60
Test name
Test status
Simulation time 2594817030 ps
CPU time 35.05 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:33:19 PM PDT 24
Peak memory 200552 kb
Host smart-d92fc729-1f4e-43c7-95fb-c7e50df24c6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659551794 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1659551794
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3852213684
Short name T11
Test name
Test status
Simulation time 142088530126 ps
CPU time 678.78 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:42:20 PM PDT 24
Peak memory 463244 kb
Host smart-d88e5681-0f5d-4243-be5c-6b57441ffae5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852213684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3852213684
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3767116287
Short name T89
Test name
Test status
Simulation time 160689436 ps
CPU time 3.36 seconds
Started Jul 17 06:28:17 PM PDT 24
Finished Jul 17 06:28:21 PM PDT 24
Peak memory 200324 kb
Host smart-8fb38aa3-ced9-4b2d-a1c2-43f53a39b1b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767116287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3767116287
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1604118916
Short name T641
Test name
Test status
Simulation time 1480795777 ps
CPU time 5.89 seconds
Started Jul 17 06:28:05 PM PDT 24
Finished Jul 17 06:28:12 PM PDT 24
Peak memory 200340 kb
Host smart-d835dfed-2f3e-4e52-89d7-52af59d37afc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604118916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1604118916
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3104240202
Short name T91
Test name
Test status
Simulation time 22906122 ps
CPU time 0.99 seconds
Started Jul 17 06:28:06 PM PDT 24
Finished Jul 17 06:28:08 PM PDT 24
Peak memory 200060 kb
Host smart-67fb8779-65b8-46e2-b9c0-7480637fb9e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104240202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3104240202
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1792660131
Short name T564
Test name
Test status
Simulation time 387344345950 ps
CPU time 706.02 seconds
Started Jul 17 06:28:16 PM PDT 24
Finished Jul 17 06:40:02 PM PDT 24
Peak memory 216832 kb
Host smart-23b93c76-cd10-4db8-b419-33eb676965a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792660131 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1792660131
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3211534078
Short name T524
Test name
Test status
Simulation time 32589261 ps
CPU time 0.69 seconds
Started Jul 17 06:28:07 PM PDT 24
Finished Jul 17 06:28:08 PM PDT 24
Peak memory 198136 kb
Host smart-c5b70531-fe98-4466-9c06-026a341446a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211534078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3211534078
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3035006086
Short name T602
Test name
Test status
Simulation time 14531449 ps
CPU time 0.59 seconds
Started Jul 17 06:28:05 PM PDT 24
Finished Jul 17 06:28:06 PM PDT 24
Peak memory 195108 kb
Host smart-0e9b882b-8701-492b-bc28-83b3c67c6161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035006086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3035006086
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1347009523
Short name T593
Test name
Test status
Simulation time 286024489 ps
CPU time 2.28 seconds
Started Jul 17 06:28:16 PM PDT 24
Finished Jul 17 06:28:19 PM PDT 24
Peak memory 200296 kb
Host smart-c4c83ef0-22f9-4a78-a19b-f817ed9849b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347009523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1347009523
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1445216352
Short name T612
Test name
Test status
Simulation time 303069502 ps
CPU time 3.07 seconds
Started Jul 17 06:28:07 PM PDT 24
Finished Jul 17 06:28:10 PM PDT 24
Peak memory 200344 kb
Host smart-81abce4c-cc3f-4a8d-9621-0097f65a32c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445216352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1445216352
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1782756202
Short name T119
Test name
Test status
Simulation time 1124646108 ps
CPU time 4.06 seconds
Started Jul 17 06:28:08 PM PDT 24
Finished Jul 17 06:28:13 PM PDT 24
Peak memory 200244 kb
Host smart-5ce2ef8d-073c-4d99-a73d-9ab64cffdda6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782756202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1782756202
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1630228160
Short name T633
Test name
Test status
Simulation time 1306715878 ps
CPU time 6.04 seconds
Started Jul 17 06:28:32 PM PDT 24
Finished Jul 17 06:28:39 PM PDT 24
Peak memory 200248 kb
Host smart-9cdefc36-b1e2-4529-9eda-63533910985a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630228160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1630228160
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.195549760
Short name T99
Test name
Test status
Simulation time 862420448 ps
CPU time 10.27 seconds
Started Jul 17 06:28:17 PM PDT 24
Finished Jul 17 06:28:28 PM PDT 24
Peak memory 200292 kb
Host smart-e1540e5d-e1bb-4c58-a780-5643269e8c59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195549760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.195549760
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2754245882
Short name T629
Test name
Test status
Simulation time 578743543 ps
CPU time 1.07 seconds
Started Jul 17 06:28:16 PM PDT 24
Finished Jul 17 06:28:18 PM PDT 24
Peak memory 200104 kb
Host smart-feb9259c-9697-48f3-85f8-ab112d4d6657
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754245882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2754245882
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2790692336
Short name T613
Test name
Test status
Simulation time 52347145 ps
CPU time 3.35 seconds
Started Jul 17 06:28:32 PM PDT 24
Finished Jul 17 06:28:36 PM PDT 24
Peak memory 216632 kb
Host smart-05bcf0e8-8e76-4837-ae61-265b0e31442d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790692336 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2790692336
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3012981579
Short name T529
Test name
Test status
Simulation time 17774693 ps
CPU time 0.74 seconds
Started Jul 17 06:28:18 PM PDT 24
Finished Jul 17 06:28:20 PM PDT 24
Peak memory 198252 kb
Host smart-b1e7ab53-dc47-4304-8aeb-ecf987f8e3a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012981579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3012981579
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.471827512
Short name T538
Test name
Test status
Simulation time 26180452 ps
CPU time 0.59 seconds
Started Jul 17 06:28:17 PM PDT 24
Finished Jul 17 06:28:18 PM PDT 24
Peak memory 195364 kb
Host smart-50782135-374d-438b-a177-313d8c0414b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471827512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.471827512
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1177098567
Short name T107
Test name
Test status
Simulation time 96239928 ps
CPU time 1.24 seconds
Started Jul 17 06:28:30 PM PDT 24
Finished Jul 17 06:28:32 PM PDT 24
Peak memory 200276 kb
Host smart-3978814f-d498-46e7-bc5d-4433bab2435a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177098567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1177098567
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3741921026
Short name T598
Test name
Test status
Simulation time 85440903 ps
CPU time 3.44 seconds
Started Jul 17 06:28:19 PM PDT 24
Finished Jul 17 06:28:23 PM PDT 24
Peak memory 200308 kb
Host smart-295003d6-bcb8-4ca9-8558-b1b2a8cecf50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741921026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3741921026
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2861784445
Short name T635
Test name
Test status
Simulation time 49601488 ps
CPU time 1.83 seconds
Started Jul 17 06:28:16 PM PDT 24
Finished Jul 17 06:28:18 PM PDT 24
Peak memory 200280 kb
Host smart-3e6cee2f-a428-43fb-bd8f-cf1a190af712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861784445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2861784445
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.953407789
Short name T592
Test name
Test status
Simulation time 69589281 ps
CPU time 1.97 seconds
Started Jul 17 06:29:27 PM PDT 24
Finished Jul 17 06:29:30 PM PDT 24
Peak memory 200288 kb
Host smart-230b7e99-c0f3-4ed7-af86-4bb7de12c9f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953407789 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.953407789
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.343770228
Short name T582
Test name
Test status
Simulation time 17144482 ps
CPU time 0.83 seconds
Started Jul 17 06:29:13 PM PDT 24
Finished Jul 17 06:29:15 PM PDT 24
Peak memory 200076 kb
Host smart-ae8e6931-b5b5-4f7b-a8cb-12d20dbd045e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343770228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.343770228
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2889839430
Short name T556
Test name
Test status
Simulation time 20452144 ps
CPU time 0.6 seconds
Started Jul 17 06:29:14 PM PDT 24
Finished Jul 17 06:29:15 PM PDT 24
Peak memory 195184 kb
Host smart-6927c185-8a74-41a0-a9f5-a4c8cc369cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889839430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2889839430
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.85236179
Short name T102
Test name
Test status
Simulation time 542357666 ps
CPU time 2.25 seconds
Started Jul 17 06:29:25 PM PDT 24
Finished Jul 17 06:29:28 PM PDT 24
Peak memory 200324 kb
Host smart-de197863-708a-45f8-86d5-ec5c6903d909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85236179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_
outstanding.85236179
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2973069768
Short name T575
Test name
Test status
Simulation time 169475427 ps
CPU time 2.24 seconds
Started Jul 17 06:29:15 PM PDT 24
Finished Jul 17 06:29:18 PM PDT 24
Peak memory 200360 kb
Host smart-1288c6ad-9eb5-43b3-b0fe-c9140114124c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973069768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2973069768
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3546149829
Short name T62
Test name
Test status
Simulation time 152305600 ps
CPU time 3.12 seconds
Started Jul 17 06:29:13 PM PDT 24
Finished Jul 17 06:29:17 PM PDT 24
Peak memory 200288 kb
Host smart-3f3dba5a-ae95-4fa2-b99d-0e913d40e90f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546149829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3546149829
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3976594208
Short name T562
Test name
Test status
Simulation time 376595315 ps
CPU time 1.87 seconds
Started Jul 17 06:29:25 PM PDT 24
Finished Jul 17 06:29:28 PM PDT 24
Peak memory 200248 kb
Host smart-b7badd20-5dee-40ac-8ed9-8648019dc5fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976594208 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3976594208
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1482610110
Short name T566
Test name
Test status
Simulation time 18566567 ps
CPU time 0.81 seconds
Started Jul 17 06:29:26 PM PDT 24
Finished Jul 17 06:29:27 PM PDT 24
Peak memory 199868 kb
Host smart-d5415fc1-4512-487a-b698-c2875d45245e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482610110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1482610110
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1696468079
Short name T634
Test name
Test status
Simulation time 56016019 ps
CPU time 0.63 seconds
Started Jul 17 06:29:29 PM PDT 24
Finished Jul 17 06:29:30 PM PDT 24
Peak memory 195348 kb
Host smart-33f68d83-90b5-4954-99fa-2c4794bba304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696468079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1696468079
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2272961830
Short name T104
Test name
Test status
Simulation time 125308939 ps
CPU time 1.71 seconds
Started Jul 17 06:29:26 PM PDT 24
Finished Jul 17 06:29:28 PM PDT 24
Peak memory 200292 kb
Host smart-42d2d767-1518-4cc4-aad9-a89abea5e351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272961830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2272961830
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.489083550
Short name T646
Test name
Test status
Simulation time 64380204 ps
CPU time 3.18 seconds
Started Jul 17 06:29:27 PM PDT 24
Finished Jul 17 06:29:31 PM PDT 24
Peak memory 200284 kb
Host smart-4167faa2-a11c-4856-9f4f-51b915ceb703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489083550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.489083550
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.373865618
Short name T595
Test name
Test status
Simulation time 1763678017 ps
CPU time 4.48 seconds
Started Jul 17 06:29:26 PM PDT 24
Finished Jul 17 06:29:31 PM PDT 24
Peak memory 200272 kb
Host smart-a0ba84b2-414c-45c8-a63d-204cbabe339d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373865618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.373865618
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4144456628
Short name T526
Test name
Test status
Simulation time 82922179 ps
CPU time 2.76 seconds
Started Jul 17 06:29:25 PM PDT 24
Finished Jul 17 06:29:28 PM PDT 24
Peak memory 208444 kb
Host smart-54d4a3ce-e0e0-4e96-879c-130b8ef6b8ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144456628 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4144456628
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2055755437
Short name T96
Test name
Test status
Simulation time 324164634 ps
CPU time 0.96 seconds
Started Jul 17 06:29:28 PM PDT 24
Finished Jul 17 06:29:29 PM PDT 24
Peak memory 200116 kb
Host smart-4135cffc-887b-49de-8d9d-f57c2cd5d86e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055755437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2055755437
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.4255711477
Short name T530
Test name
Test status
Simulation time 43622333 ps
CPU time 0.59 seconds
Started Jul 17 06:29:28 PM PDT 24
Finished Jul 17 06:29:29 PM PDT 24
Peak memory 195088 kb
Host smart-e630442c-61dd-4c4b-beb3-8cbdacc12cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255711477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.4255711477
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2552222330
Short name T590
Test name
Test status
Simulation time 151593309 ps
CPU time 2.44 seconds
Started Jul 17 06:29:28 PM PDT 24
Finished Jul 17 06:29:31 PM PDT 24
Peak memory 200272 kb
Host smart-3e800db1-3dac-4590-9182-829bcf00b61e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552222330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2552222330
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.270067539
Short name T581
Test name
Test status
Simulation time 273930382 ps
CPU time 3.7 seconds
Started Jul 17 06:29:27 PM PDT 24
Finished Jul 17 06:29:31 PM PDT 24
Peak memory 200296 kb
Host smart-06ca5cfe-4c2f-4e9f-950d-d6916f06b579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270067539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.270067539
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.309231871
Short name T560
Test name
Test status
Simulation time 104283445 ps
CPU time 1.74 seconds
Started Jul 17 06:29:26 PM PDT 24
Finished Jul 17 06:29:28 PM PDT 24
Peak memory 200504 kb
Host smart-a24d2d76-f6d9-45bc-9abe-c193d60aa05d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309231871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.309231871
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3530932754
Short name T550
Test name
Test status
Simulation time 398068117 ps
CPU time 2.56 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:40 PM PDT 24
Peak memory 200336 kb
Host smart-2d010491-4039-435e-84ce-94fa9475856b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530932754 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3530932754
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3320767551
Short name T580
Test name
Test status
Simulation time 34900479 ps
CPU time 0.69 seconds
Started Jul 17 06:29:39 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 198192 kb
Host smart-89ae608f-c220-49e7-bf4f-df68de118316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320767551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3320767551
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.260779000
Short name T532
Test name
Test status
Simulation time 13590129 ps
CPU time 0.58 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 195228 kb
Host smart-e741e2b7-6860-4a4c-820f-dd75342b1813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260779000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.260779000
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1360354855
Short name T101
Test name
Test status
Simulation time 83653930 ps
CPU time 1.87 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:40 PM PDT 24
Peak memory 200284 kb
Host smart-b7da89da-4f5b-40a6-8a7e-223509d36146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360354855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1360354855
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1901472697
Short name T608
Test name
Test status
Simulation time 208519889 ps
CPU time 1.77 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200292 kb
Host smart-803f9e9c-6d2b-4c9e-93a2-fd6a47d78f82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901472697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1901472697
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4147202684
Short name T552
Test name
Test status
Simulation time 72700028 ps
CPU time 1.25 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200308 kb
Host smart-7100544a-2c6e-403e-8e8c-841074fb36b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147202684 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4147202684
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3398474747
Short name T605
Test name
Test status
Simulation time 35594134 ps
CPU time 0.95 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:38 PM PDT 24
Peak memory 200076 kb
Host smart-a36a8cac-b6d5-4bc7-bfb2-4d73a62cb58d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398474747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3398474747
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4052418252
Short name T628
Test name
Test status
Simulation time 15568337 ps
CPU time 0.57 seconds
Started Jul 17 06:29:38 PM PDT 24
Finished Jul 17 06:29:40 PM PDT 24
Peak memory 195236 kb
Host smart-34593a88-9e84-4df1-8f37-03d6594845e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052418252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4052418252
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3434576126
Short name T623
Test name
Test status
Simulation time 822786260 ps
CPU time 2.16 seconds
Started Jul 17 06:29:39 PM PDT 24
Finished Jul 17 06:29:42 PM PDT 24
Peak memory 200252 kb
Host smart-fd07f7cc-d1c5-4913-b748-7809ed6c0db7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434576126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3434576126
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.932299612
Short name T651
Test name
Test status
Simulation time 126510131 ps
CPU time 2.29 seconds
Started Jul 17 06:29:38 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 200296 kb
Host smart-2ec56b66-af8a-476f-a9b1-9a33d7a2c690
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932299612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.932299612
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.116719933
Short name T543
Test name
Test status
Simulation time 254155334 ps
CPU time 1.94 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200356 kb
Host smart-45742370-df79-4bc8-a5f0-d47a7277c33b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116719933 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.116719933
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2859429567
Short name T90
Test name
Test status
Simulation time 130058966 ps
CPU time 0.97 seconds
Started Jul 17 06:29:38 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 200060 kb
Host smart-fdd18c7a-3c2e-445d-ad54-0f79f223f7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859429567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2859429567
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2867494410
Short name T568
Test name
Test status
Simulation time 40068987 ps
CPU time 0.57 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:38 PM PDT 24
Peak memory 195164 kb
Host smart-b97de457-201b-4449-a1c0-176ef12899fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867494410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2867494410
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.713160415
Short name T621
Test name
Test status
Simulation time 199857776 ps
CPU time 2.36 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:40 PM PDT 24
Peak memory 200236 kb
Host smart-bd31155e-4822-4434-8af6-7c98c334866e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713160415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.713160415
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1033748911
Short name T548
Test name
Test status
Simulation time 79546352 ps
CPU time 2.36 seconds
Started Jul 17 06:29:38 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 200308 kb
Host smart-06ad2e5d-f680-4320-8d52-d4129ebcabc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033748911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1033748911
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3481775534
Short name T569
Test name
Test status
Simulation time 177230877 ps
CPU time 1.78 seconds
Started Jul 17 06:29:38 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 200284 kb
Host smart-71d44e16-a6b3-43f0-a674-e89223719e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481775534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3481775534
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1565397862
Short name T607
Test name
Test status
Simulation time 50455426 ps
CPU time 3.32 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 208492 kb
Host smart-ef88ad0f-67d5-4f2c-89da-208f4c9bf6bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565397862 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1565397862
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3119776079
Short name T94
Test name
Test status
Simulation time 60807529 ps
CPU time 0.72 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 198260 kb
Host smart-396604d5-d57d-47d5-b38c-9511dc157934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119776079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3119776079
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.4193442246
Short name T546
Test name
Test status
Simulation time 44827242 ps
CPU time 0.6 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:38 PM PDT 24
Peak memory 195116 kb
Host smart-db444cab-f5eb-4ddd-a541-6aaa64bd41a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193442246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.4193442246
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1989844841
Short name T591
Test name
Test status
Simulation time 46478292 ps
CPU time 2.11 seconds
Started Jul 17 06:29:36 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200284 kb
Host smart-1721f816-6e42-4224-b31e-27c6693c27d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989844841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1989844841
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1528706004
Short name T539
Test name
Test status
Simulation time 155192712 ps
CPU time 3.87 seconds
Started Jul 17 06:29:35 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200304 kb
Host smart-bf4e0168-6594-4217-ad61-64e2b9aa0b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528706004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1528706004
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1036828524
Short name T114
Test name
Test status
Simulation time 299711470 ps
CPU time 3.06 seconds
Started Jul 17 06:29:35 PM PDT 24
Finished Jul 17 06:29:39 PM PDT 24
Peak memory 200284 kb
Host smart-b8903833-2092-48f8-945a-ba3b05f44d53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036828524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1036828524
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1818018292
Short name T630
Test name
Test status
Simulation time 61498798950 ps
CPU time 651.26 seconds
Started Jul 17 06:29:49 PM PDT 24
Finished Jul 17 06:40:41 PM PDT 24
Peak memory 216672 kb
Host smart-2daf2f65-5866-4d36-85da-56a256bb5ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818018292 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1818018292
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1878366934
Short name T638
Test name
Test status
Simulation time 18473130 ps
CPU time 0.72 seconds
Started Jul 17 06:29:49 PM PDT 24
Finished Jul 17 06:29:51 PM PDT 24
Peak memory 198156 kb
Host smart-89f02e14-e8ce-4a2b-8d07-d6030889b6cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878366934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1878366934
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2910341712
Short name T545
Test name
Test status
Simulation time 34992206 ps
CPU time 0.59 seconds
Started Jul 17 06:29:47 PM PDT 24
Finished Jul 17 06:29:48 PM PDT 24
Peak memory 195232 kb
Host smart-6db0020a-946f-46cf-aa53-a5851a84f962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910341712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2910341712
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2776229585
Short name T650
Test name
Test status
Simulation time 130098545 ps
CPU time 1.5 seconds
Started Jul 17 06:30:36 PM PDT 24
Finished Jul 17 06:30:38 PM PDT 24
Peak memory 199860 kb
Host smart-948f6e0a-5e81-4c06-b5da-1ce81f896d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776229585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2776229585
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3149115146
Short name T66
Test name
Test status
Simulation time 495627814 ps
CPU time 2.52 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 200248 kb
Host smart-56f545dd-acaa-4991-a7f9-f7067f64f16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149115146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3149115146
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1140828383
Short name T116
Test name
Test status
Simulation time 210197613 ps
CPU time 2.11 seconds
Started Jul 17 06:29:37 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 200292 kb
Host smart-6873444b-580d-499e-9a1e-848b5311a120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140828383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1140828383
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3732315255
Short name T579
Test name
Test status
Simulation time 106540798 ps
CPU time 1.14 seconds
Started Jul 17 06:29:48 PM PDT 24
Finished Jul 17 06:29:50 PM PDT 24
Peak memory 200120 kb
Host smart-7b72e5fb-ae36-47e3-bf22-35ed43463682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732315255 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3732315255
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.760643827
Short name T558
Test name
Test status
Simulation time 119402724 ps
CPU time 0.72 seconds
Started Jul 17 06:29:48 PM PDT 24
Finished Jul 17 06:29:49 PM PDT 24
Peak memory 198084 kb
Host smart-5cf51b79-b5ec-42d2-9097-4c98b1a8a253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760643827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.760643827
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1153669293
Short name T642
Test name
Test status
Simulation time 12900294 ps
CPU time 0.58 seconds
Started Jul 17 06:29:48 PM PDT 24
Finished Jul 17 06:29:49 PM PDT 24
Peak memory 195152 kb
Host smart-2a560924-ddcb-4385-aa97-30a82f0ba2e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153669293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1153669293
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1957207236
Short name T100
Test name
Test status
Simulation time 164998711 ps
CPU time 2.2 seconds
Started Jul 17 06:29:48 PM PDT 24
Finished Jul 17 06:29:51 PM PDT 24
Peak memory 200312 kb
Host smart-c722f2e7-2d08-4e70-b6b0-98da090ac089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957207236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1957207236
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.769267682
Short name T610
Test name
Test status
Simulation time 63859655 ps
CPU time 2.04 seconds
Started Jul 17 06:29:47 PM PDT 24
Finished Jul 17 06:29:50 PM PDT 24
Peak memory 200276 kb
Host smart-a2550424-b72b-498f-a7c4-ab364bade240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769267682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.769267682
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.700136319
Short name T63
Test name
Test status
Simulation time 355574598 ps
CPU time 1.79 seconds
Started Jul 17 06:29:48 PM PDT 24
Finished Jul 17 06:29:50 PM PDT 24
Peak memory 200296 kb
Host smart-5f210194-1a8e-43db-af50-70bb59ed5e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700136319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.700136319
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.267022790
Short name T597
Test name
Test status
Simulation time 261926078511 ps
CPU time 1312.07 seconds
Started Jul 17 06:29:46 PM PDT 24
Finished Jul 17 06:51:39 PM PDT 24
Peak memory 226088 kb
Host smart-1c3caa76-e550-4e2f-8b69-4b244573207e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267022790 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.267022790
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3407824968
Short name T631
Test name
Test status
Simulation time 294827912 ps
CPU time 0.72 seconds
Started Jul 17 06:29:47 PM PDT 24
Finished Jul 17 06:29:48 PM PDT 24
Peak memory 198256 kb
Host smart-9a33e029-2bcd-4e1e-9417-1cd257bf9488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407824968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3407824968
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1482299386
Short name T647
Test name
Test status
Simulation time 34742396 ps
CPU time 0.59 seconds
Started Jul 17 06:29:50 PM PDT 24
Finished Jul 17 06:29:51 PM PDT 24
Peak memory 195152 kb
Host smart-78ed18c6-2d4a-4a72-a7d7-970a4dee7d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482299386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1482299386
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.863924251
Short name T105
Test name
Test status
Simulation time 285529161 ps
CPU time 1.71 seconds
Started Jul 17 06:29:48 PM PDT 24
Finished Jul 17 06:29:51 PM PDT 24
Peak memory 200292 kb
Host smart-ad0abf32-289a-4973-9901-7c99315fee8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863924251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.863924251
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2388758202
Short name T544
Test name
Test status
Simulation time 498098620 ps
CPU time 3.23 seconds
Started Jul 17 06:29:47 PM PDT 24
Finished Jul 17 06:29:51 PM PDT 24
Peak memory 200296 kb
Host smart-1c5995e7-730b-4171-a926-f8ed0deeeb8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388758202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2388758202
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4094380898
Short name T616
Test name
Test status
Simulation time 181237797 ps
CPU time 2.83 seconds
Started Jul 17 06:29:47 PM PDT 24
Finished Jul 17 06:29:51 PM PDT 24
Peak memory 200280 kb
Host smart-f7cb8ffd-700e-401f-9c9c-968a38cdacc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094380898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4094380898
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1098330927
Short name T625
Test name
Test status
Simulation time 2677954888 ps
CPU time 6.09 seconds
Started Jul 17 06:28:30 PM PDT 24
Finished Jul 17 06:28:37 PM PDT 24
Peak memory 200396 kb
Host smart-c0480d72-6c21-444c-81aa-49cccbe40713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098330927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1098330927
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.656010834
Short name T639
Test name
Test status
Simulation time 1184397861 ps
CPU time 15.06 seconds
Started Jul 17 06:28:30 PM PDT 24
Finished Jul 17 06:28:46 PM PDT 24
Peak memory 199376 kb
Host smart-03ced99e-e0aa-4e85-a8d6-efdc5b4aff72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656010834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.656010834
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2210820709
Short name T643
Test name
Test status
Simulation time 59475027 ps
CPU time 0.77 seconds
Started Jul 17 06:28:31 PM PDT 24
Finished Jul 17 06:28:32 PM PDT 24
Peak memory 197908 kb
Host smart-9a452ac0-1083-46e3-8879-2d1d8f2ad041
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210820709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2210820709
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3219521026
Short name T620
Test name
Test status
Simulation time 72475582 ps
CPU time 1.78 seconds
Started Jul 17 06:28:29 PM PDT 24
Finished Jul 17 06:28:31 PM PDT 24
Peak memory 200340 kb
Host smart-7d4eb4b9-036c-4375-b03a-549f695d7c59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219521026 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3219521026
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.313222424
Short name T576
Test name
Test status
Simulation time 19572331 ps
CPU time 0.69 seconds
Started Jul 17 06:28:29 PM PDT 24
Finished Jul 17 06:28:30 PM PDT 24
Peak memory 198256 kb
Host smart-12da66a3-71f9-4ae5-93f5-7e019705b7cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313222424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.313222424
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.30287815
Short name T601
Test name
Test status
Simulation time 48123688 ps
CPU time 0.61 seconds
Started Jul 17 06:28:29 PM PDT 24
Finished Jul 17 06:28:30 PM PDT 24
Peak memory 195176 kb
Host smart-64c850ca-98f4-4c82-b66e-23656cc3e8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.30287815
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.844217339
Short name T551
Test name
Test status
Simulation time 687652614 ps
CPU time 2.7 seconds
Started Jul 17 06:28:29 PM PDT 24
Finished Jul 17 06:28:32 PM PDT 24
Peak memory 200136 kb
Host smart-c709e898-bfc5-45c5-a63a-2a39dfca352a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844217339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.844217339
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.545384351
Short name T588
Test name
Test status
Simulation time 60486262 ps
CPU time 1.49 seconds
Started Jul 17 06:28:32 PM PDT 24
Finished Jul 17 06:28:34 PM PDT 24
Peak memory 200192 kb
Host smart-c5dd74e2-deb2-4666-afe9-fea138b1be16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545384351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.545384351
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2495513969
Short name T118
Test name
Test status
Simulation time 925261907 ps
CPU time 4.42 seconds
Started Jul 17 06:28:30 PM PDT 24
Finished Jul 17 06:28:35 PM PDT 24
Peak memory 200296 kb
Host smart-143288bb-b8b5-42b3-b449-1410369149d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495513969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2495513969
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1615017378
Short name T571
Test name
Test status
Simulation time 53601488 ps
CPU time 0.61 seconds
Started Jul 17 06:29:49 PM PDT 24
Finished Jul 17 06:29:50 PM PDT 24
Peak memory 195224 kb
Host smart-3807ce4d-7af8-4b93-a823-0e1046f15bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615017378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1615017378
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.934345449
Short name T549
Test name
Test status
Simulation time 43301576 ps
CPU time 0.58 seconds
Started Jul 17 06:29:49 PM PDT 24
Finished Jul 17 06:29:50 PM PDT 24
Peak memory 195316 kb
Host smart-1ce4232c-3fd9-4343-872e-b1122f805d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934345449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.934345449
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1090778884
Short name T555
Test name
Test status
Simulation time 13842654 ps
CPU time 0.6 seconds
Started Jul 17 06:30:00 PM PDT 24
Finished Jul 17 06:30:01 PM PDT 24
Peak memory 195080 kb
Host smart-3879c544-17d3-4e96-b3dd-8d988d55947b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090778884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1090778884
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2446943015
Short name T584
Test name
Test status
Simulation time 14324444 ps
CPU time 0.62 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195304 kb
Host smart-c0a4eca4-c83a-44be-a932-3390de8ff425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446943015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2446943015
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3377282436
Short name T542
Test name
Test status
Simulation time 56439140 ps
CPU time 0.64 seconds
Started Jul 17 06:30:03 PM PDT 24
Finished Jul 17 06:30:04 PM PDT 24
Peak memory 195188 kb
Host smart-169e2c37-7e4e-4732-943d-b64d60b9280f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377282436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3377282436
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1967456793
Short name T567
Test name
Test status
Simulation time 13412453 ps
CPU time 0.6 seconds
Started Jul 17 06:30:00 PM PDT 24
Finished Jul 17 06:30:01 PM PDT 24
Peak memory 195176 kb
Host smart-1e0fe2e9-9d9b-483e-8ce1-aafde01a6a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967456793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1967456793
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1984142671
Short name T603
Test name
Test status
Simulation time 90069701 ps
CPU time 0.63 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:02 PM PDT 24
Peak memory 195472 kb
Host smart-2b70d2b3-2e02-43f5-a6c3-6ecd8b479d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984142671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1984142671
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1071826792
Short name T577
Test name
Test status
Simulation time 29543676 ps
CPU time 0.62 seconds
Started Jul 17 06:30:00 PM PDT 24
Finished Jul 17 06:30:02 PM PDT 24
Peak memory 195324 kb
Host smart-2b707e9e-749b-4e2f-9ca9-db68669e0b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071826792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1071826792
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1991627810
Short name T636
Test name
Test status
Simulation time 29982978 ps
CPU time 0.59 seconds
Started Jul 17 06:30:02 PM PDT 24
Finished Jul 17 06:30:04 PM PDT 24
Peak memory 195096 kb
Host smart-54700ffe-97e7-4a03-b83a-0821b4447515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991627810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1991627810
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2120682002
Short name T553
Test name
Test status
Simulation time 30194470 ps
CPU time 0.63 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195388 kb
Host smart-d0694a94-aa1d-4c19-9c2d-0a272cd999b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120682002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2120682002
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2600905045
Short name T541
Test name
Test status
Simulation time 3716301901 ps
CPU time 6.03 seconds
Started Jul 17 06:28:40 PM PDT 24
Finished Jul 17 06:28:46 PM PDT 24
Peak memory 200396 kb
Host smart-d526af13-364e-4a63-bdf5-ba6b71b790ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600905045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2600905045
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2762786093
Short name T604
Test name
Test status
Simulation time 2225846711 ps
CPU time 15.72 seconds
Started Jul 17 06:28:38 PM PDT 24
Finished Jul 17 06:28:55 PM PDT 24
Peak memory 199488 kb
Host smart-1209f30b-a4b8-4aae-bd0e-69cf151dcae6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762786093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2762786093
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3565313169
Short name T92
Test name
Test status
Simulation time 36850135 ps
CPU time 0.97 seconds
Started Jul 17 06:28:39 PM PDT 24
Finished Jul 17 06:28:41 PM PDT 24
Peak memory 199864 kb
Host smart-c60cee20-3437-4a3f-9abc-d6111948bada
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565313169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3565313169
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.458557690
Short name T527
Test name
Test status
Simulation time 540768368 ps
CPU time 2.48 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:54 PM PDT 24
Peak memory 200292 kb
Host smart-811e67e6-3390-416c-83a8-318d5cf19f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458557690 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.458557690
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2823326646
Short name T626
Test name
Test status
Simulation time 54719207 ps
CPU time 0.61 seconds
Started Jul 17 06:28:41 PM PDT 24
Finished Jul 17 06:28:42 PM PDT 24
Peak memory 195400 kb
Host smart-675a8bd6-a24e-43cd-a05e-e8054dc098e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823326646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2823326646
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3620870931
Short name T624
Test name
Test status
Simulation time 22643744 ps
CPU time 1.11 seconds
Started Jul 17 06:28:50 PM PDT 24
Finished Jul 17 06:28:52 PM PDT 24
Peak memory 198988 kb
Host smart-5dfb481f-9c1f-4478-af5a-8858029303ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620870931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3620870931
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3000058367
Short name T655
Test name
Test status
Simulation time 446049438 ps
CPU time 2.24 seconds
Started Jul 17 06:28:41 PM PDT 24
Finished Jul 17 06:28:44 PM PDT 24
Peak memory 200376 kb
Host smart-bfaa6b0c-83a3-4884-a453-27e4230f9643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000058367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3000058367
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2841402998
Short name T570
Test name
Test status
Simulation time 334263156 ps
CPU time 1.97 seconds
Started Jul 17 06:28:39 PM PDT 24
Finished Jul 17 06:28:42 PM PDT 24
Peak memory 200276 kb
Host smart-d5996d3c-345c-43e1-9c2b-6110f4c2ae8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841402998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2841402998
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2061347986
Short name T632
Test name
Test status
Simulation time 47607838 ps
CPU time 0.66 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195276 kb
Host smart-424d499d-5f3f-4cdd-9723-bc6bab8dd2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061347986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2061347986
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2355372403
Short name T648
Test name
Test status
Simulation time 30451774 ps
CPU time 0.69 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:02 PM PDT 24
Peak memory 195288 kb
Host smart-4c679521-c12b-4215-bfac-5a4075fca4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355372403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2355372403
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.992284087
Short name T606
Test name
Test status
Simulation time 67074803 ps
CPU time 0.64 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195348 kb
Host smart-ff0d0a0f-2611-41d8-aa6a-0261289c39a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992284087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.992284087
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2915354681
Short name T652
Test name
Test status
Simulation time 14040215 ps
CPU time 0.59 seconds
Started Jul 17 06:30:03 PM PDT 24
Finished Jul 17 06:30:04 PM PDT 24
Peak memory 195104 kb
Host smart-7c41ff66-cc8e-4712-9ba9-466f53f4462a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915354681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2915354681
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2056007638
Short name T627
Test name
Test status
Simulation time 45743480 ps
CPU time 0.63 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:02 PM PDT 24
Peak memory 195176 kb
Host smart-858437b3-ec1e-420d-8f18-56c636a332d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056007638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2056007638
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2529093588
Short name T531
Test name
Test status
Simulation time 18933201 ps
CPU time 0.65 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195244 kb
Host smart-0ad0ac06-a7b8-4284-a5b0-ce3d025e009d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529093588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2529093588
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3129480640
Short name T537
Test name
Test status
Simulation time 21442774 ps
CPU time 0.61 seconds
Started Jul 17 06:30:02 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195148 kb
Host smart-0beaf0b8-cc9d-407d-bf72-c950b5f663b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129480640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3129480640
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1257958531
Short name T528
Test name
Test status
Simulation time 49071413 ps
CPU time 0.68 seconds
Started Jul 17 06:30:01 PM PDT 24
Finished Jul 17 06:30:03 PM PDT 24
Peak memory 195208 kb
Host smart-c92508ab-5cdd-4be8-8570-a2970214b46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257958531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1257958531
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3470930935
Short name T611
Test name
Test status
Simulation time 118492042 ps
CPU time 0.63 seconds
Started Jul 17 06:30:02 PM PDT 24
Finished Jul 17 06:30:04 PM PDT 24
Peak memory 195308 kb
Host smart-bdb3380f-9517-4272-b421-a182bd320571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470930935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3470930935
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2979517098
Short name T536
Test name
Test status
Simulation time 23185058 ps
CPU time 0.6 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 06:30:15 PM PDT 24
Peak memory 195128 kb
Host smart-4f6fccf3-2f18-46db-91f4-4d38605eb3d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979517098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2979517098
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1623496083
Short name T97
Test name
Test status
Simulation time 419496010 ps
CPU time 5.63 seconds
Started Jul 17 06:28:52 PM PDT 24
Finished Jul 17 06:28:59 PM PDT 24
Peak memory 200284 kb
Host smart-26fcced0-22fb-474c-a787-aa229d427e44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623496083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1623496083
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3390880100
Short name T561
Test name
Test status
Simulation time 115371584 ps
CPU time 5.55 seconds
Started Jul 17 06:28:50 PM PDT 24
Finished Jul 17 06:28:56 PM PDT 24
Peak memory 200344 kb
Host smart-dc9dd275-866b-405e-b4c3-56051ddb7590
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390880100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3390880100
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.938455079
Short name T585
Test name
Test status
Simulation time 35551613 ps
CPU time 1.02 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:52 PM PDT 24
Peak memory 199944 kb
Host smart-fd6516b5-b695-47d8-a669-65cf0461134b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938455079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.938455079
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1285421236
Short name T535
Test name
Test status
Simulation time 45636381 ps
CPU time 2.91 seconds
Started Jul 17 06:28:53 PM PDT 24
Finished Jul 17 06:28:57 PM PDT 24
Peak memory 216048 kb
Host smart-c1156a98-a654-46c8-ba49-6ca4e53aa093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285421236 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1285421236
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2609679653
Short name T525
Test name
Test status
Simulation time 36232711 ps
CPU time 0.97 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:53 PM PDT 24
Peak memory 199920 kb
Host smart-0e8ab0b9-06fa-478f-b327-6c5b36f00c5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609679653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2609679653
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2411424774
Short name T622
Test name
Test status
Simulation time 61603256 ps
CPU time 0.58 seconds
Started Jul 17 06:28:53 PM PDT 24
Finished Jul 17 06:28:54 PM PDT 24
Peak memory 195332 kb
Host smart-36d1ddc9-7f5c-4b42-a629-c03da1c2385f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411424774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2411424774
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2183597990
Short name T587
Test name
Test status
Simulation time 385935411 ps
CPU time 1.78 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:54 PM PDT 24
Peak memory 200300 kb
Host smart-049ad139-ce6f-474f-be00-e3380d526656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183597990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2183597990
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3058327282
Short name T594
Test name
Test status
Simulation time 191827397 ps
CPU time 1.48 seconds
Started Jul 17 06:28:52 PM PDT 24
Finished Jul 17 06:28:55 PM PDT 24
Peak memory 200292 kb
Host smart-8c411e10-b4be-4d6f-b844-b5a67a3f0cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058327282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3058327282
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.591674466
Short name T64
Test name
Test status
Simulation time 1478234862 ps
CPU time 2.84 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:55 PM PDT 24
Peak memory 200292 kb
Host smart-3c8842ce-5d8d-404f-8b1f-5505279f4aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591674466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.591674466
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3416363027
Short name T563
Test name
Test status
Simulation time 45697554 ps
CPU time 0.6 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 06:30:15 PM PDT 24
Peak memory 195188 kb
Host smart-186c7b9f-b5bc-4ac0-988e-c35295aaa300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416363027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3416363027
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1312946396
Short name T618
Test name
Test status
Simulation time 40171701 ps
CPU time 0.58 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 06:30:16 PM PDT 24
Peak memory 195276 kb
Host smart-72404f88-27e8-4dcd-b9d9-d0b4c26719ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312946396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1312946396
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2992622394
Short name T596
Test name
Test status
Simulation time 11240520 ps
CPU time 0.57 seconds
Started Jul 17 06:30:13 PM PDT 24
Finished Jul 17 06:30:14 PM PDT 24
Peak memory 195124 kb
Host smart-236cd367-2c3f-434b-8171-735dbfb5a1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992622394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2992622394
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2857400048
Short name T656
Test name
Test status
Simulation time 79825941 ps
CPU time 0.6 seconds
Started Jul 17 06:30:19 PM PDT 24
Finished Jul 17 06:30:20 PM PDT 24
Peak memory 195088 kb
Host smart-528cdc3f-7dd9-4075-9976-b8a182b20d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857400048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2857400048
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3644844247
Short name T554
Test name
Test status
Simulation time 19876253 ps
CPU time 0.59 seconds
Started Jul 17 06:30:17 PM PDT 24
Finished Jul 17 06:30:18 PM PDT 24
Peak memory 195132 kb
Host smart-09fb536c-c889-46c3-8e0d-99fe5bb8456c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644844247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3644844247
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3802122164
Short name T654
Test name
Test status
Simulation time 49886788 ps
CPU time 0.63 seconds
Started Jul 17 06:30:15 PM PDT 24
Finished Jul 17 06:30:16 PM PDT 24
Peak memory 195448 kb
Host smart-c211a436-3eda-40c1-b7ef-9a83bece51f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802122164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3802122164
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2996702791
Short name T653
Test name
Test status
Simulation time 55587027 ps
CPU time 0.64 seconds
Started Jul 17 06:30:17 PM PDT 24
Finished Jul 17 06:30:19 PM PDT 24
Peak memory 195180 kb
Host smart-085b1b8d-c445-4b85-b54f-00ca480966e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996702791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2996702791
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1082800767
Short name T574
Test name
Test status
Simulation time 15033945 ps
CPU time 0.61 seconds
Started Jul 17 06:30:13 PM PDT 24
Finished Jul 17 06:30:15 PM PDT 24
Peak memory 195340 kb
Host smart-b7094513-61df-48a1-9c60-6929c99157b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082800767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1082800767
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.823242132
Short name T547
Test name
Test status
Simulation time 13234248 ps
CPU time 0.61 seconds
Started Jul 17 06:30:13 PM PDT 24
Finished Jul 17 06:30:14 PM PDT 24
Peak memory 195124 kb
Host smart-ec673673-c178-4293-8897-8461ddd2b905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823242132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.823242132
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.514848198
Short name T600
Test name
Test status
Simulation time 62581134 ps
CPU time 0.61 seconds
Started Jul 17 06:30:15 PM PDT 24
Finished Jul 17 06:30:16 PM PDT 24
Peak memory 195196 kb
Host smart-4edf6843-9f01-4d4c-8730-0068be7513ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514848198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.514848198
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3290678271
Short name T640
Test name
Test status
Simulation time 580514167 ps
CPU time 1.83 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:54 PM PDT 24
Peak memory 200308 kb
Host smart-2a3319c4-c369-4acc-ac67-5f0961ffbfea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290678271 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3290678271
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3060694163
Short name T614
Test name
Test status
Simulation time 29417905 ps
CPU time 0.83 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:53 PM PDT 24
Peak memory 198960 kb
Host smart-9cf9d9f5-2c27-4a71-b7e0-2a30f912ce9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060694163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3060694163
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.230573967
Short name T573
Test name
Test status
Simulation time 28319865 ps
CPU time 0.57 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:52 PM PDT 24
Peak memory 195160 kb
Host smart-e0c09ebf-7788-4d81-b705-e9d2481d1c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230573967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.230573967
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3124640781
Short name T103
Test name
Test status
Simulation time 263766914 ps
CPU time 2.36 seconds
Started Jul 17 06:28:51 PM PDT 24
Finished Jul 17 06:28:55 PM PDT 24
Peak memory 200256 kb
Host smart-b1fed5f3-8acb-4a00-a40d-a44c36aa27e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124640781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3124640781
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3949489144
Short name T617
Test name
Test status
Simulation time 373356194 ps
CPU time 3.81 seconds
Started Jul 17 06:28:50 PM PDT 24
Finished Jul 17 06:28:55 PM PDT 24
Peak memory 200272 kb
Host smart-ff0763da-76f2-48bf-8dec-968612db3f54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949489144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3949489144
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1609226601
Short name T644
Test name
Test status
Simulation time 185421970 ps
CPU time 3 seconds
Started Jul 17 06:28:52 PM PDT 24
Finished Jul 17 06:28:56 PM PDT 24
Peak memory 200240 kb
Host smart-750784c3-ab9d-4bb0-9979-04d476a4bf02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609226601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1609226601
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1048374274
Short name T572
Test name
Test status
Simulation time 407188071 ps
CPU time 2.34 seconds
Started Jul 17 06:29:01 PM PDT 24
Finished Jul 17 06:29:04 PM PDT 24
Peak memory 200420 kb
Host smart-21caacd9-9567-4312-9022-baa744a4f61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048374274 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1048374274
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1373823816
Short name T93
Test name
Test status
Simulation time 180240302 ps
CPU time 1.07 seconds
Started Jul 17 06:29:01 PM PDT 24
Finished Jul 17 06:29:03 PM PDT 24
Peak memory 199812 kb
Host smart-eeb2fc90-8637-427b-95b7-ce72e8593cda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373823816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1373823816
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1665662287
Short name T540
Test name
Test status
Simulation time 37417262 ps
CPU time 0.57 seconds
Started Jul 17 06:29:02 PM PDT 24
Finished Jul 17 06:29:03 PM PDT 24
Peak memory 195152 kb
Host smart-db42a6fb-2b01-4c9b-b1b7-45a4971804a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665662287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1665662287
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3072327030
Short name T583
Test name
Test status
Simulation time 49966100 ps
CPU time 1.23 seconds
Started Jul 17 06:29:01 PM PDT 24
Finished Jul 17 06:29:03 PM PDT 24
Peak memory 200224 kb
Host smart-d4211a50-dcfb-4e70-9910-1e29657eac71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072327030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3072327030
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4217894158
Short name T586
Test name
Test status
Simulation time 190221944 ps
CPU time 1.27 seconds
Started Jul 17 06:29:04 PM PDT 24
Finished Jul 17 06:29:06 PM PDT 24
Peak memory 200252 kb
Host smart-aea7671c-8416-488c-a51d-9c149c142794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217894158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4217894158
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3782055714
Short name T115
Test name
Test status
Simulation time 724908625 ps
CPU time 3.98 seconds
Started Jul 17 06:29:03 PM PDT 24
Finished Jul 17 06:29:08 PM PDT 24
Peak memory 200284 kb
Host smart-cc45e5b2-79c9-474b-b2d1-76221617b797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782055714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3782055714
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.293861730
Short name T615
Test name
Test status
Simulation time 90281645 ps
CPU time 1.21 seconds
Started Jul 17 06:29:03 PM PDT 24
Finished Jul 17 06:29:05 PM PDT 24
Peak memory 200196 kb
Host smart-b3a68fdb-567e-4d90-8aad-5b2ad4e28be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293861730 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.293861730
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3268861969
Short name T106
Test name
Test status
Simulation time 36210580 ps
CPU time 0.71 seconds
Started Jul 17 06:29:01 PM PDT 24
Finished Jul 17 06:29:03 PM PDT 24
Peak memory 198412 kb
Host smart-fa1b49c0-339d-4c38-aa34-f1b0089eda76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268861969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3268861969
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1537596997
Short name T578
Test name
Test status
Simulation time 13911816 ps
CPU time 0.58 seconds
Started Jul 17 06:29:02 PM PDT 24
Finished Jul 17 06:29:03 PM PDT 24
Peak memory 195284 kb
Host smart-54bb8c8a-923f-4838-b6cf-ae2891e1f0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537596997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1537596997
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1961506894
Short name T609
Test name
Test status
Simulation time 85666555 ps
CPU time 1.14 seconds
Started Jul 17 06:29:02 PM PDT 24
Finished Jul 17 06:29:03 PM PDT 24
Peak memory 198764 kb
Host smart-13a93b10-4e1f-45fe-83fa-63cc50b7ac4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961506894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1961506894
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.658358909
Short name T557
Test name
Test status
Simulation time 499958272 ps
CPU time 3.18 seconds
Started Jul 17 06:29:02 PM PDT 24
Finished Jul 17 06:29:06 PM PDT 24
Peak memory 200296 kb
Host smart-28883312-a058-43f4-8e8b-01c427d30a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658358909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.658358909
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1669473216
Short name T112
Test name
Test status
Simulation time 193742755 ps
CPU time 3.42 seconds
Started Jul 17 06:29:01 PM PDT 24
Finished Jul 17 06:29:05 PM PDT 24
Peak memory 200352 kb
Host smart-92bc1581-e0b5-438a-bfe2-284c5cdbd411
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669473216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1669473216
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.32192133
Short name T533
Test name
Test status
Simulation time 152534580 ps
CPU time 2.72 seconds
Started Jul 17 06:29:15 PM PDT 24
Finished Jul 17 06:29:18 PM PDT 24
Peak memory 200328 kb
Host smart-bbd03fa6-639d-454a-ad08-ca8e44be10b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192133 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.32192133
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.414498650
Short name T98
Test name
Test status
Simulation time 20115557 ps
CPU time 0.72 seconds
Started Jul 17 06:30:15 PM PDT 24
Finished Jul 17 06:30:17 PM PDT 24
Peak memory 196948 kb
Host smart-47787c94-3fa8-4fe8-9f61-c7896188b59d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414498650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.414498650
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.229108249
Short name T559
Test name
Test status
Simulation time 13286305 ps
CPU time 0.59 seconds
Started Jul 17 06:29:13 PM PDT 24
Finished Jul 17 06:29:14 PM PDT 24
Peak memory 195228 kb
Host smart-fdc2da73-abb5-485b-b705-2a778a8d00b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229108249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.229108249
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3173746417
Short name T589
Test name
Test status
Simulation time 46507516 ps
CPU time 2.28 seconds
Started Jul 17 06:29:14 PM PDT 24
Finished Jul 17 06:29:17 PM PDT 24
Peak memory 200304 kb
Host smart-fa5afe81-15d4-42cf-a45b-e6d6f4717dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173746417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3173746417
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2974018793
Short name T534
Test name
Test status
Simulation time 186255451 ps
CPU time 1.23 seconds
Started Jul 17 06:29:03 PM PDT 24
Finished Jul 17 06:29:06 PM PDT 24
Peak memory 200308 kb
Host smart-364cf5ce-f318-4e71-84e4-87c03cf4ceec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974018793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2974018793
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1634509468
Short name T657
Test name
Test status
Simulation time 45349992 ps
CPU time 3.16 seconds
Started Jul 17 06:29:16 PM PDT 24
Finished Jul 17 06:29:19 PM PDT 24
Peak memory 200404 kb
Host smart-43fcd54d-9ada-4686-941d-6e7af9d904ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634509468 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1634509468
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3732594850
Short name T645
Test name
Test status
Simulation time 23309286 ps
CPU time 0.85 seconds
Started Jul 17 06:29:13 PM PDT 24
Finished Jul 17 06:29:15 PM PDT 24
Peak memory 199948 kb
Host smart-fdbc719d-06cc-4266-b905-78ab1ecc2373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732594850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3732594850
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3548287336
Short name T649
Test name
Test status
Simulation time 40477697 ps
CPU time 0.61 seconds
Started Jul 17 06:29:16 PM PDT 24
Finished Jul 17 06:29:17 PM PDT 24
Peak memory 195172 kb
Host smart-cf00d341-3277-46f2-b921-bcc95f988e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548287336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3548287336
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2409153098
Short name T637
Test name
Test status
Simulation time 147125646 ps
CPU time 1.53 seconds
Started Jul 17 06:30:22 PM PDT 24
Finished Jul 17 06:30:24 PM PDT 24
Peak memory 200080 kb
Host smart-95f89a85-4179-46ac-83b0-10fac82bb193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409153098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2409153098
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2910088406
Short name T619
Test name
Test status
Simulation time 106303663 ps
CPU time 2.82 seconds
Started Jul 17 06:29:14 PM PDT 24
Finished Jul 17 06:29:18 PM PDT 24
Peak memory 200304 kb
Host smart-dd446393-393d-4c2e-81cc-df8d9f21201c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910088406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2910088406
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.162943845
Short name T565
Test name
Test status
Simulation time 180267192 ps
CPU time 1.76 seconds
Started Jul 17 06:29:14 PM PDT 24
Finished Jul 17 06:29:16 PM PDT 24
Peak memory 200228 kb
Host smart-139675c2-4fe8-4c6d-a260-003480004242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162943845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.162943845
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2144466727
Short name T457
Test name
Test status
Simulation time 21314473 ps
CPU time 0.6 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 06:30:27 PM PDT 24
Peak memory 196760 kb
Host smart-a457aaf5-0b13-4efc-9ca1-b0c54f66f6ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144466727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2144466727
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3829492207
Short name T486
Test name
Test status
Simulation time 1978178003 ps
CPU time 31.27 seconds
Started Jul 17 06:30:15 PM PDT 24
Finished Jul 17 06:30:47 PM PDT 24
Peak memory 200224 kb
Host smart-94a309bd-ba57-44d5-9be3-0e29b836d58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829492207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3829492207
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3672230586
Short name T465
Test name
Test status
Simulation time 1167723409 ps
CPU time 31.27 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 06:30:46 PM PDT 24
Peak memory 200280 kb
Host smart-00fa36be-639f-456a-9f72-330e3fa4d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672230586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3672230586
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.199374440
Short name T1
Test name
Test status
Simulation time 848889979 ps
CPU time 144.46 seconds
Started Jul 17 06:30:13 PM PDT 24
Finished Jul 17 06:32:38 PM PDT 24
Peak memory 437972 kb
Host smart-3d2232eb-264b-4d5c-a85c-ebd41e5ad360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199374440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.199374440
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2418704014
Short name T332
Test name
Test status
Simulation time 31564159691 ps
CPU time 147.5 seconds
Started Jul 17 06:30:18 PM PDT 24
Finished Jul 17 06:32:46 PM PDT 24
Peak memory 200300 kb
Host smart-878dce1a-e6f4-4204-83c9-c8296e6c1cc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418704014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2418704014
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.832031670
Short name T345
Test name
Test status
Simulation time 1439724688 ps
CPU time 73.38 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 06:31:29 PM PDT 24
Peak memory 200176 kb
Host smart-c8315ce0-47b8-4089-a7bd-87a3d9c3864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832031670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.832031670
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2340832960
Short name T475
Test name
Test status
Simulation time 475850237 ps
CPU time 8.54 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 06:30:23 PM PDT 24
Peak memory 200316 kb
Host smart-df12736e-d97a-4772-abff-6aa572ab5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340832960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2340832960
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2343686701
Short name T68
Test name
Test status
Simulation time 2534417154 ps
CPU time 8.48 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:30:34 PM PDT 24
Peak memory 200392 kb
Host smart-39972a2d-fb15-4ec5-827e-546d8094e328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343686701 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2343686701
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2079807207
Short name T19
Test name
Test status
Simulation time 66147381752 ps
CPU time 3299.5 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 07:25:27 PM PDT 24
Peak memory 826596 kb
Host smart-b7cc292c-eb62-4b02-b35b-caecb083ebf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079807207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2079807207
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.898259307
Short name T230
Test name
Test status
Simulation time 9034438758 ps
CPU time 74.48 seconds
Started Jul 17 06:30:28 PM PDT 24
Finished Jul 17 06:31:43 PM PDT 24
Peak memory 200196 kb
Host smart-1e399b46-b500-4b1a-8c07-54d29ee5cc22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=898259307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.898259307
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.4260072119
Short name T233
Test name
Test status
Simulation time 13558766442 ps
CPU time 61.5 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:31:28 PM PDT 24
Peak memory 200356 kb
Host smart-7b7f6748-2b99-43c8-bd5b-7b3e766cecc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4260072119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4260072119
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1477690060
Short name T338
Test name
Test status
Simulation time 13337601442 ps
CPU time 124.04 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:32:31 PM PDT 24
Peak memory 200348 kb
Host smart-eb3096c0-97e5-43cf-99c1-8fe74ef7747c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1477690060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1477690060
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.743769704
Short name T141
Test name
Test status
Simulation time 138390428372 ps
CPU time 605.77 seconds
Started Jul 17 06:30:19 PM PDT 24
Finished Jul 17 06:40:25 PM PDT 24
Peak memory 200256 kb
Host smart-965740ca-7c3b-4791-a252-b3974e5618e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=743769704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.743769704
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.751554135
Short name T121
Test name
Test status
Simulation time 1075172461426 ps
CPU time 2526.91 seconds
Started Jul 17 06:30:17 PM PDT 24
Finished Jul 17 07:12:24 PM PDT 24
Peak memory 215772 kb
Host smart-3756a6e8-a926-4509-b247-08c958c2d0ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=751554135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.751554135
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1829664917
Short name T160
Test name
Test status
Simulation time 78594946379 ps
CPU time 2023.13 seconds
Started Jul 17 06:30:14 PM PDT 24
Finished Jul 17 07:03:59 PM PDT 24
Peak memory 215952 kb
Host smart-ee1735bd-33c1-484e-9e2a-9a91ea6bdc06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1829664917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1829664917
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1727479411
Short name T239
Test name
Test status
Simulation time 441904022 ps
CPU time 23.27 seconds
Started Jul 17 06:30:13 PM PDT 24
Finished Jul 17 06:30:37 PM PDT 24
Peak memory 200276 kb
Host smart-c3171577-3730-4aaa-a064-d224b829588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727479411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1727479411
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.196602654
Short name T462
Test name
Test status
Simulation time 35349976 ps
CPU time 0.6 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:30:28 PM PDT 24
Peak memory 196108 kb
Host smart-12a673c8-4bc3-4678-8ca5-4f8403c9a6f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196602654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.196602654
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3483408663
Short name T218
Test name
Test status
Simulation time 1466363072 ps
CPU time 41.84 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 06:31:07 PM PDT 24
Peak memory 200284 kb
Host smart-ec5cf087-083c-477e-9ae4-1b5534107a3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483408663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3483408663
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.635599839
Short name T432
Test name
Test status
Simulation time 1503196805 ps
CPU time 30.55 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:30:56 PM PDT 24
Peak memory 200240 kb
Host smart-2af81200-2d01-441e-980a-c64e86b4dbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635599839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.635599839
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2881717553
Short name T321
Test name
Test status
Simulation time 3240728870 ps
CPU time 175.49 seconds
Started Jul 17 06:30:23 PM PDT 24
Finished Jul 17 06:33:20 PM PDT 24
Peak memory 627348 kb
Host smart-0860a9e8-0045-4e2e-8119-61e400e321de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881717553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2881717553
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4082744321
Short name T425
Test name
Test status
Simulation time 146970197102 ps
CPU time 233.61 seconds
Started Jul 17 06:30:23 PM PDT 24
Finished Jul 17 06:34:17 PM PDT 24
Peak memory 200268 kb
Host smart-1ec827a2-6e07-4cc0-aa61-aec7945dca31
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082744321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4082744321
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2929809957
Short name T156
Test name
Test status
Simulation time 11123203351 ps
CPU time 207.56 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:33:55 PM PDT 24
Peak memory 200412 kb
Host smart-8ccd8cae-4649-4f2a-857f-7c3a356d590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929809957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2929809957
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1007888682
Short name T52
Test name
Test status
Simulation time 82537600 ps
CPU time 1.03 seconds
Started Jul 17 06:30:27 PM PDT 24
Finished Jul 17 06:30:29 PM PDT 24
Peak memory 219376 kb
Host smart-40d2b618-8cd4-4935-a2f2-a9b9aec98d8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007888682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1007888682
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2492081928
Short name T351
Test name
Test status
Simulation time 135539797 ps
CPU time 6.33 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:30:33 PM PDT 24
Peak memory 200332 kb
Host smart-56db4d73-c4f0-4053-95f7-5e09d2da9937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492081928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2492081928
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1892292166
Short name T23
Test name
Test status
Simulation time 78328911327 ps
CPU time 1446.03 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:54:34 PM PDT 24
Peak memory 529208 kb
Host smart-aa3129e8-208f-4a16-981d-6261e5a4cb55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892292166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1892292166
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.390790761
Short name T12
Test name
Test status
Simulation time 471024702302 ps
CPU time 3864.75 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 07:34:51 PM PDT 24
Peak memory 809860 kb
Host smart-8fe2af6d-d95b-4bec-9751-3c12bc385bae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390790761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.390790761
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3905542757
Short name T354
Test name
Test status
Simulation time 3212555546 ps
CPU time 55.56 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 06:31:22 PM PDT 24
Peak memory 200228 kb
Host smart-1a12b459-60fc-417b-a6ba-94c60ba19c92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3905542757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3905542757
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3464028377
Short name T416
Test name
Test status
Simulation time 3483679800 ps
CPU time 55.03 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 06:31:21 PM PDT 24
Peak memory 200356 kb
Host smart-fc4b017b-0cbc-4399-96eb-c1138f4dd019
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3464028377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3464028377
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2614427766
Short name T78
Test name
Test status
Simulation time 8745552126 ps
CPU time 139.53 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:32:44 PM PDT 24
Peak memory 200344 kb
Host smart-5e247d97-12be-42de-b9ba-c7307c577ce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2614427766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2614427766
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2871823041
Short name T267
Test name
Test status
Simulation time 28425883554 ps
CPU time 559.63 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:39:45 PM PDT 24
Peak memory 200284 kb
Host smart-c025067d-da28-4556-a52f-3d4e4586160a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2871823041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2871823041
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1553288125
Short name T499
Test name
Test status
Simulation time 139304223826 ps
CPU time 2533.6 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 07:12:40 PM PDT 24
Peak memory 216208 kb
Host smart-ebb41645-a328-4ee0-9091-381e00ed0868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1553288125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1553288125
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4263384334
Short name T315
Test name
Test status
Simulation time 82345758898 ps
CPU time 2154.98 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 215876 kb
Host smart-5a120f15-dace-4d83-8e13-3a7daa8af948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4263384334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4263384334
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3938026360
Short name T380
Test name
Test status
Simulation time 89913599537 ps
CPU time 120.84 seconds
Started Jul 17 06:30:27 PM PDT 24
Finished Jul 17 06:32:29 PM PDT 24
Peak memory 200352 kb
Host smart-f5dccf46-cc65-4a3b-a00f-359a2179cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938026360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3938026360
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1319124310
Short name T377
Test name
Test status
Simulation time 153432934 ps
CPU time 0.59 seconds
Started Jul 17 06:31:49 PM PDT 24
Finished Jul 17 06:31:50 PM PDT 24
Peak memory 195412 kb
Host smart-8b52c16e-6aa5-4677-8157-2fef16840c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319124310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1319124310
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3494935430
Short name T383
Test name
Test status
Simulation time 676208687 ps
CPU time 36.51 seconds
Started Jul 17 06:31:49 PM PDT 24
Finished Jul 17 06:32:26 PM PDT 24
Peak memory 200204 kb
Host smart-306483e6-9901-482e-9d40-55d4fa52d4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494935430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3494935430
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2215880621
Short name T488
Test name
Test status
Simulation time 86744118 ps
CPU time 1.68 seconds
Started Jul 17 06:31:43 PM PDT 24
Finished Jul 17 06:31:45 PM PDT 24
Peak memory 200308 kb
Host smart-121444c7-7592-4939-a787-59551b25f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215880621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2215880621
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1351894717
Short name T478
Test name
Test status
Simulation time 6258612573 ps
CPU time 1003.83 seconds
Started Jul 17 06:31:42 PM PDT 24
Finished Jul 17 06:48:26 PM PDT 24
Peak memory 687064 kb
Host smart-9c112f12-61e2-494a-8186-3cb19ef494c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351894717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1351894717
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3885177874
Short name T522
Test name
Test status
Simulation time 31588514250 ps
CPU time 98.03 seconds
Started Jul 17 06:31:43 PM PDT 24
Finished Jul 17 06:33:21 PM PDT 24
Peak memory 200344 kb
Host smart-53324cb4-2178-4ce5-bb79-8bc402938ef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885177874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3885177874
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2790075206
Short name T373
Test name
Test status
Simulation time 2873966624 ps
CPU time 171.03 seconds
Started Jul 17 06:31:42 PM PDT 24
Finished Jul 17 06:34:34 PM PDT 24
Peak memory 200364 kb
Host smart-a568252e-6460-4e0e-b32c-84bc32947b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790075206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2790075206
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3515716174
Short name T266
Test name
Test status
Simulation time 3110583230 ps
CPU time 10.9 seconds
Started Jul 17 06:31:50 PM PDT 24
Finished Jul 17 06:32:01 PM PDT 24
Peak memory 200340 kb
Host smart-8f34fc44-c064-4ba0-9bc6-a71302ddc0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515716174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3515716174
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2390324613
Short name T446
Test name
Test status
Simulation time 64217857733 ps
CPU time 685.17 seconds
Started Jul 17 06:31:49 PM PDT 24
Finished Jul 17 06:43:15 PM PDT 24
Peak memory 199932 kb
Host smart-d81d663e-f333-48f1-a5bb-53b9e2e1cf2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390324613 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2390324613
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3850991282
Short name T484
Test name
Test status
Simulation time 7246355151 ps
CPU time 27.68 seconds
Started Jul 17 06:31:42 PM PDT 24
Finished Jul 17 06:32:11 PM PDT 24
Peak memory 200544 kb
Host smart-c9680e70-43c0-4688-8c12-a649fcf8deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850991282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3850991282
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3106341985
Short name T154
Test name
Test status
Simulation time 21120989 ps
CPU time 0.57 seconds
Started Jul 17 06:31:55 PM PDT 24
Finished Jul 17 06:31:56 PM PDT 24
Peak memory 195836 kb
Host smart-dedd0bf7-23dc-45b4-82b8-227bd74766c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106341985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3106341985
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2812256764
Short name T158
Test name
Test status
Simulation time 1427569503 ps
CPU time 43.42 seconds
Started Jul 17 06:31:55 PM PDT 24
Finished Jul 17 06:32:40 PM PDT 24
Peak memory 200228 kb
Host smart-f0c54e88-334e-4368-b1fb-2b79b0e0a899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812256764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2812256764
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2318174218
Short name T123
Test name
Test status
Simulation time 3653221939 ps
CPU time 76.27 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 06:33:11 PM PDT 24
Peak memory 216752 kb
Host smart-23d7a46b-a85a-44e2-b9fa-f62edfeaa93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318174218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2318174218
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2266397546
Short name T272
Test name
Test status
Simulation time 4470871460 ps
CPU time 183.27 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 06:34:59 PM PDT 24
Peak memory 370832 kb
Host smart-6b05c0c0-64db-4b14-a7a1-c192ddb666b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266397546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2266397546
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4063638039
Short name T414
Test name
Test status
Simulation time 7391472920 ps
CPU time 119.8 seconds
Started Jul 17 06:31:55 PM PDT 24
Finished Jul 17 06:33:56 PM PDT 24
Peak memory 200316 kb
Host smart-9c373014-40d8-43fa-a97d-cc6ff56e0c97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063638039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4063638039
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3948848984
Short name T32
Test name
Test status
Simulation time 4894033613 ps
CPU time 161.59 seconds
Started Jul 17 06:31:53 PM PDT 24
Finished Jul 17 06:34:36 PM PDT 24
Peak memory 200288 kb
Host smart-1a0c87e9-cc7a-4bff-88c6-9d3bd1742f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948848984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3948848984
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3236179577
Short name T495
Test name
Test status
Simulation time 44927140 ps
CPU time 2.03 seconds
Started Jul 17 06:31:41 PM PDT 24
Finished Jul 17 06:31:44 PM PDT 24
Peak memory 200340 kb
Host smart-10bfc826-4b0b-488c-b2b6-09f31b35e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236179577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3236179577
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2845397096
Short name T72
Test name
Test status
Simulation time 2423074480813 ps
CPU time 3195.86 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 07:25:11 PM PDT 24
Peak memory 740204 kb
Host smart-bb65a6cc-6b86-41b3-80b6-3ea5c060776b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845397096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2845397096
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4006626386
Short name T523
Test name
Test status
Simulation time 3724289414 ps
CPU time 73.13 seconds
Started Jul 17 06:31:55 PM PDT 24
Finished Jul 17 06:33:09 PM PDT 24
Peak memory 200396 kb
Host smart-3f6fa92b-1287-4b51-ac57-0fd285b38065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006626386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4006626386
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1342098152
Short name T56
Test name
Test status
Simulation time 12941860 ps
CPU time 0.62 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:09 PM PDT 24
Peak memory 196188 kb
Host smart-ccd84efd-5471-4a7a-9f9c-2427c6c5ad99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342098152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1342098152
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3218752257
Short name T477
Test name
Test status
Simulation time 1010769835 ps
CPU time 57.45 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 06:32:53 PM PDT 24
Peak memory 200352 kb
Host smart-d39a7213-1329-41a8-8c82-b990ea005ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218752257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3218752257
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1094641028
Short name T245
Test name
Test status
Simulation time 1451058123 ps
CPU time 85.31 seconds
Started Jul 17 06:32:06 PM PDT 24
Finished Jul 17 06:33:32 PM PDT 24
Peak memory 200284 kb
Host smart-76a73cc7-7e73-4641-a232-f9273124100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094641028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1094641028
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4031396105
Short name T169
Test name
Test status
Simulation time 6847627041 ps
CPU time 365.43 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 06:38:01 PM PDT 24
Peak memory 598660 kb
Host smart-6533bfcd-19cc-47c1-8cef-f1aeeacde025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031396105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4031396105
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.4055173786
Short name T278
Test name
Test status
Simulation time 238292137859 ps
CPU time 152.16 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:34:40 PM PDT 24
Peak memory 200332 kb
Host smart-7d731047-8e84-4f02-a203-fd2e394731e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055173786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.4055173786
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.835630997
Short name T306
Test name
Test status
Simulation time 4624601888 ps
CPU time 127.91 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 06:34:02 PM PDT 24
Peak memory 200352 kb
Host smart-9ea1fe64-b3f2-419f-8ed1-fc5e37e7476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835630997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.835630997
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1742010776
Short name T79
Test name
Test status
Simulation time 3821159846 ps
CPU time 12.76 seconds
Started Jul 17 06:31:54 PM PDT 24
Finished Jul 17 06:32:07 PM PDT 24
Peak memory 200292 kb
Host smart-1bad814f-f0b1-44ed-84e6-64debd3728d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742010776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1742010776
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.728068140
Short name T421
Test name
Test status
Simulation time 2264889899 ps
CPU time 120.94 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:34:08 PM PDT 24
Peak memory 200324 kb
Host smart-86e6cc0b-3b28-4c1c-b4a8-25dd040950fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728068140 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.728068140
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1819479529
Short name T344
Test name
Test status
Simulation time 3143527634 ps
CPU time 49.49 seconds
Started Jul 17 06:32:06 PM PDT 24
Finished Jul 17 06:32:56 PM PDT 24
Peak memory 200336 kb
Host smart-99d89bff-6c0d-4d3e-9a4a-dbdb4ebc6b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819479529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1819479529
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3677400008
Short name T423
Test name
Test status
Simulation time 4603981692 ps
CPU time 65.7 seconds
Started Jul 17 06:32:08 PM PDT 24
Finished Jul 17 06:33:15 PM PDT 24
Peak memory 200352 kb
Host smart-d5da6a85-1b75-4cf3-8ed7-ea2bab9ff6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677400008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3677400008
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3192936226
Short name T275
Test name
Test status
Simulation time 5942987082 ps
CPU time 50.95 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:59 PM PDT 24
Peak memory 200596 kb
Host smart-d19ff159-a313-4120-8ac0-c0d1892c59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192936226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3192936226
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.521270086
Short name T74
Test name
Test status
Simulation time 400009246 ps
CPU time 38.44 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:46 PM PDT 24
Peak memory 237764 kb
Host smart-eb54f8d1-80f3-4612-8b07-e0524ef5d292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521270086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.521270086
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3333567591
Short name T305
Test name
Test status
Simulation time 39312268871 ps
CPU time 40.52 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:49 PM PDT 24
Peak memory 200344 kb
Host smart-8bb4e0a5-d67f-443b-8aa5-24111a4aef82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333567591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3333567591
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.710967860
Short name T513
Test name
Test status
Simulation time 2590052364 ps
CPU time 152.71 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:34:41 PM PDT 24
Peak memory 200372 kb
Host smart-9cd34417-dd5b-4dc4-8f3f-85d2e5fa0fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710967860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.710967860
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3841212324
Short name T350
Test name
Test status
Simulation time 1087859276 ps
CPU time 15.29 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:23 PM PDT 24
Peak memory 200240 kb
Host smart-f951d0f8-10f8-4573-97f4-f478da282629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841212324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3841212324
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1130412580
Short name T225
Test name
Test status
Simulation time 2536678650 ps
CPU time 36.64 seconds
Started Jul 17 06:32:08 PM PDT 24
Finished Jul 17 06:32:46 PM PDT 24
Peak memory 200372 kb
Host smart-6153c902-e0b4-4bfd-8563-cd0cb06f465c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130412580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1130412580
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1159073368
Short name T382
Test name
Test status
Simulation time 1192031596 ps
CPU time 55.95 seconds
Started Jul 17 06:32:08 PM PDT 24
Finished Jul 17 06:33:05 PM PDT 24
Peak memory 200304 kb
Host smart-e6dd6696-2f52-47ac-9566-1a6fb959faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159073368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1159073368
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3746943576
Short name T171
Test name
Test status
Simulation time 14088604 ps
CPU time 0.56 seconds
Started Jul 17 06:32:22 PM PDT 24
Finished Jul 17 06:32:23 PM PDT 24
Peak memory 195152 kb
Host smart-778ae5cd-485c-4670-9a9b-778b238055c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746943576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3746943576
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3229859235
Short name T261
Test name
Test status
Simulation time 647078152 ps
CPU time 37.11 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:45 PM PDT 24
Peak memory 200292 kb
Host smart-e05853b7-9372-4286-9a93-21abd387c140
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229859235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3229859235
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.495298417
Short name T422
Test name
Test status
Simulation time 5634180344 ps
CPU time 41.12 seconds
Started Jul 17 06:32:20 PM PDT 24
Finished Jul 17 06:33:02 PM PDT 24
Peak memory 208456 kb
Host smart-1f8bcb2d-174f-4b22-91f4-1bcf84deb35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495298417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.495298417
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.743963379
Short name T406
Test name
Test status
Simulation time 4023989486 ps
CPU time 193.68 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:35:22 PM PDT 24
Peak memory 626892 kb
Host smart-04d6d6ce-f4e4-43db-ae61-c96fc0c5c607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743963379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.743963379
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4201218697
Short name T302
Test name
Test status
Simulation time 2624301907 ps
CPU time 40.08 seconds
Started Jul 17 06:32:20 PM PDT 24
Finished Jul 17 06:33:00 PM PDT 24
Peak memory 200368 kb
Host smart-e2edaf7e-27f5-47e6-af41-04951217c9e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201218697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4201218697
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.22649735
Short name T188
Test name
Test status
Simulation time 6217757122 ps
CPU time 20.57 seconds
Started Jul 17 06:32:07 PM PDT 24
Finished Jul 17 06:32:29 PM PDT 24
Peak memory 200396 kb
Host smart-845f7bca-7aa2-47cf-8b6e-8a75be9c1015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22649735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.22649735
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3689456608
Short name T519
Test name
Test status
Simulation time 3583204107 ps
CPU time 11.64 seconds
Started Jul 17 06:32:08 PM PDT 24
Finished Jul 17 06:32:21 PM PDT 24
Peak memory 200316 kb
Host smart-2077c4cd-ef25-4e17-aa65-74ba6f6c8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689456608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3689456608
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.374417434
Short name T70
Test name
Test status
Simulation time 38083438659 ps
CPU time 1192.49 seconds
Started Jul 17 06:32:21 PM PDT 24
Finished Jul 17 06:52:14 PM PDT 24
Peak memory 702528 kb
Host smart-29fc4b3c-5029-4fa8-803f-e59968094c32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374417434 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.374417434
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2087627080
Short name T444
Test name
Test status
Simulation time 2845945573 ps
CPU time 35.08 seconds
Started Jul 17 06:32:21 PM PDT 24
Finished Jul 17 06:32:56 PM PDT 24
Peak memory 200356 kb
Host smart-eaec39c5-eda4-4154-a72b-584fc7d7b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087627080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2087627080
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3258351590
Short name T282
Test name
Test status
Simulation time 16331046 ps
CPU time 0.58 seconds
Started Jul 17 06:32:32 PM PDT 24
Finished Jul 17 06:32:34 PM PDT 24
Peak memory 195824 kb
Host smart-a27b3f2d-1818-4e9a-ba0d-21b0d012db3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258351590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3258351590
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3869399280
Short name T320
Test name
Test status
Simulation time 5214720659 ps
CPU time 81.55 seconds
Started Jul 17 06:32:20 PM PDT 24
Finished Jul 17 06:33:43 PM PDT 24
Peak memory 200420 kb
Host smart-d046cf0c-1475-48e2-b74a-9043a1c385ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869399280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3869399280
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2366028164
Short name T288
Test name
Test status
Simulation time 9086965183 ps
CPU time 47.75 seconds
Started Jul 17 06:32:32 PM PDT 24
Finished Jul 17 06:33:20 PM PDT 24
Peak memory 200292 kb
Host smart-ef485147-1c19-4fe9-811f-a7e4159ebeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366028164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2366028164
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1881076842
Short name T137
Test name
Test status
Simulation time 220045157 ps
CPU time 22.31 seconds
Started Jul 17 06:32:21 PM PDT 24
Finished Jul 17 06:32:44 PM PDT 24
Peak memory 243424 kb
Host smart-c62b3a1b-08ae-481a-a024-003371665ccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881076842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1881076842
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1664537630
Short name T314
Test name
Test status
Simulation time 27531270516 ps
CPU time 155.21 seconds
Started Jul 17 06:32:32 PM PDT 24
Finished Jul 17 06:35:08 PM PDT 24
Peak memory 200376 kb
Host smart-50267579-46d2-4a08-bc28-2c96864febb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664537630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1664537630
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4292827989
Short name T148
Test name
Test status
Simulation time 6936872367 ps
CPU time 128.13 seconds
Started Jul 17 06:32:21 PM PDT 24
Finished Jul 17 06:34:29 PM PDT 24
Peak memory 216588 kb
Host smart-3aced3c6-d7f2-474b-9c6b-7803dc2e4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292827989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4292827989
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1518105038
Short name T461
Test name
Test status
Simulation time 125195526 ps
CPU time 2.49 seconds
Started Jul 17 06:32:21 PM PDT 24
Finished Jul 17 06:32:24 PM PDT 24
Peak memory 200196 kb
Host smart-6699530e-8e32-49f4-89d0-3be4f15ed4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518105038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1518105038
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1959530676
Short name T328
Test name
Test status
Simulation time 167683807511 ps
CPU time 3347.82 seconds
Started Jul 17 06:32:33 PM PDT 24
Finished Jul 17 07:28:21 PM PDT 24
Peak memory 817900 kb
Host smart-99e7a960-5dc4-490a-b687-2e35a8663b1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959530676 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1959530676
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1013152386
Short name T517
Test name
Test status
Simulation time 10785970114 ps
CPU time 133.34 seconds
Started Jul 17 06:32:33 PM PDT 24
Finished Jul 17 06:34:47 PM PDT 24
Peak memory 200344 kb
Host smart-5e2d34d1-b364-4413-822f-eaa20c4490c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013152386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1013152386
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.944849945
Short name T396
Test name
Test status
Simulation time 14866943 ps
CPU time 0.61 seconds
Started Jul 17 06:32:32 PM PDT 24
Finished Jul 17 06:32:33 PM PDT 24
Peak memory 196188 kb
Host smart-2a9f21d2-ce9d-4756-867c-45b3c53465a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944849945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.944849945
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.776971261
Short name T4
Test name
Test status
Simulation time 142658738 ps
CPU time 4.48 seconds
Started Jul 17 06:32:31 PM PDT 24
Finished Jul 17 06:32:36 PM PDT 24
Peak memory 200252 kb
Host smart-6381daaf-b9d2-4e07-9e47-2ded64586d91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776971261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.776971261
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.727409886
Short name T209
Test name
Test status
Simulation time 926784028 ps
CPU time 44.04 seconds
Started Jul 17 06:32:33 PM PDT 24
Finished Jul 17 06:33:18 PM PDT 24
Peak memory 200296 kb
Host smart-53e53f6e-bcb2-4026-b845-48b2eb9bde60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727409886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.727409886
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2205072302
Short name T193
Test name
Test status
Simulation time 851473885 ps
CPU time 27.52 seconds
Started Jul 17 06:32:31 PM PDT 24
Finished Jul 17 06:32:59 PM PDT 24
Peak memory 249908 kb
Host smart-0d7f0b5e-bde5-49c8-aa14-6eb92487def5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205072302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2205072302
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2790539497
Short name T322
Test name
Test status
Simulation time 735506662 ps
CPU time 12.53 seconds
Started Jul 17 06:32:34 PM PDT 24
Finished Jul 17 06:32:47 PM PDT 24
Peak memory 200268 kb
Host smart-c00a2a6d-df7b-483a-bba4-e5c2e3ddbffa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790539497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2790539497
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3877952516
Short name T407
Test name
Test status
Simulation time 4582375020 ps
CPU time 75 seconds
Started Jul 17 06:32:32 PM PDT 24
Finished Jul 17 06:33:48 PM PDT 24
Peak memory 200384 kb
Host smart-0dacbbc7-fad0-4413-ae75-02548c951d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877952516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3877952516
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3196167872
Short name T221
Test name
Test status
Simulation time 179138742 ps
CPU time 2.69 seconds
Started Jul 17 06:32:31 PM PDT 24
Finished Jul 17 06:32:35 PM PDT 24
Peak memory 200360 kb
Host smart-9438004e-b37a-4a9d-a600-cb6042e91129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196167872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3196167872
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.179649603
Short name T124
Test name
Test status
Simulation time 7625501078 ps
CPU time 448.72 seconds
Started Jul 17 06:32:32 PM PDT 24
Finished Jul 17 06:40:01 PM PDT 24
Peak memory 208548 kb
Host smart-00f90978-0061-409c-9b64-115f4af5f384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179649603 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.179649603
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2689846482
Short name T450
Test name
Test status
Simulation time 8931012177 ps
CPU time 104.24 seconds
Started Jul 17 06:32:33 PM PDT 24
Finished Jul 17 06:34:18 PM PDT 24
Peak memory 200348 kb
Host smart-4db7ee26-2d60-4ae1-b85e-47248a1b6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689846482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2689846482
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3017452641
Short name T2
Test name
Test status
Simulation time 29773634 ps
CPU time 0.59 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:32:44 PM PDT 24
Peak memory 196864 kb
Host smart-5433d23c-7622-4823-be1f-15530f66e806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017452641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3017452641
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.564212100
Short name T304
Test name
Test status
Simulation time 4351355230 ps
CPU time 69.43 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:33:53 PM PDT 24
Peak memory 200412 kb
Host smart-9ec478a8-d8f8-4da1-b522-33632802a86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564212100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.564212100
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.225112246
Short name T518
Test name
Test status
Simulation time 102590268 ps
CPU time 2.41 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:32:46 PM PDT 24
Peak memory 200340 kb
Host smart-c8b3cd80-b69d-485d-bffd-e9b18ff7f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225112246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.225112246
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.649360799
Short name T182
Test name
Test status
Simulation time 8675725778 ps
CPU time 722.49 seconds
Started Jul 17 06:32:44 PM PDT 24
Finished Jul 17 06:44:48 PM PDT 24
Peak memory 636940 kb
Host smart-d01a5e1c-a977-4db7-b938-540f1d92ff22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649360799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.649360799
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.112934182
Short name T140
Test name
Test status
Simulation time 13180689064 ps
CPU time 79.13 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:34:02 PM PDT 24
Peak memory 200340 kb
Host smart-a5c0da7a-23cf-4234-bcf9-efd433b4aa52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112934182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.112934182
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.312199481
Short name T8
Test name
Test status
Simulation time 10306825991 ps
CPU time 97.45 seconds
Started Jul 17 06:32:44 PM PDT 24
Finished Jul 17 06:34:22 PM PDT 24
Peak memory 200352 kb
Host smart-64df2e97-48ce-40ca-9eb1-e452d0739547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312199481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.312199481
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3651877652
Short name T167
Test name
Test status
Simulation time 99591743 ps
CPU time 4.76 seconds
Started Jul 17 06:32:33 PM PDT 24
Finished Jul 17 06:32:39 PM PDT 24
Peak memory 200152 kb
Host smart-c6bbb357-4eee-4fc9-93d8-5230f16d4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651877652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3651877652
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3607461730
Short name T408
Test name
Test status
Simulation time 3052213036 ps
CPU time 142.1 seconds
Started Jul 17 06:32:44 PM PDT 24
Finished Jul 17 06:35:07 PM PDT 24
Peak memory 200268 kb
Host smart-62cf4f9d-0ddd-4173-8c7f-39638dac0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607461730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3607461730
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3475415145
Short name T480
Test name
Test status
Simulation time 72309113 ps
CPU time 0.61 seconds
Started Jul 17 06:32:54 PM PDT 24
Finished Jul 17 06:32:56 PM PDT 24
Peak memory 196116 kb
Host smart-d2be6829-b402-4a56-b4f7-da7f1d4c7921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475415145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3475415145
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2295867790
Short name T196
Test name
Test status
Simulation time 1050685225 ps
CPU time 32.58 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:33:17 PM PDT 24
Peak memory 200264 kb
Host smart-dd2fff05-986b-4ac2-9f89-a08cd030eb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295867790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2295867790
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1469430893
Short name T46
Test name
Test status
Simulation time 1419786093 ps
CPU time 59.9 seconds
Started Jul 17 06:32:57 PM PDT 24
Finished Jul 17 06:33:58 PM PDT 24
Peak memory 200308 kb
Host smart-c942f29c-1495-49cd-83f1-f8af368e2072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469430893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1469430893
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.717930934
Short name T271
Test name
Test status
Simulation time 41882173957 ps
CPU time 1679.53 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 07:00:44 PM PDT 24
Peak memory 746628 kb
Host smart-6fe78a9b-5299-48fd-9317-49a957b2938e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717930934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.717930934
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.655542211
Short name T319
Test name
Test status
Simulation time 354160786 ps
CPU time 19.28 seconds
Started Jul 17 06:32:53 PM PDT 24
Finished Jul 17 06:33:14 PM PDT 24
Peak memory 200284 kb
Host smart-28c0d62c-6a91-46d3-8192-3294638bcfa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655542211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.655542211
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.753417299
Short name T255
Test name
Test status
Simulation time 7057815257 ps
CPU time 129.72 seconds
Started Jul 17 06:32:43 PM PDT 24
Finished Jul 17 06:34:53 PM PDT 24
Peak memory 200384 kb
Host smart-243288b2-5c0d-4f45-87af-3ca4a5d31162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753417299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.753417299
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2656439846
Short name T392
Test name
Test status
Simulation time 754041676 ps
CPU time 9.37 seconds
Started Jul 17 06:32:42 PM PDT 24
Finished Jul 17 06:32:52 PM PDT 24
Peak memory 200292 kb
Host smart-1bac85c2-2840-4233-bf38-bdfd1f9d8636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656439846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2656439846
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2157696778
Short name T330
Test name
Test status
Simulation time 533908002584 ps
CPU time 1119.26 seconds
Started Jul 17 06:32:54 PM PDT 24
Finished Jul 17 06:51:35 PM PDT 24
Peak memory 680996 kb
Host smart-1254fa54-535c-4d7e-9ee2-5dc3ff265c16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157696778 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2157696778
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1117919333
Short name T253
Test name
Test status
Simulation time 3590627035 ps
CPU time 49.2 seconds
Started Jul 17 06:32:54 PM PDT 24
Finished Jul 17 06:33:44 PM PDT 24
Peak memory 200288 kb
Host smart-04ae842d-7802-444e-aff9-ac20e33c9685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117919333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1117919333
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2062844910
Short name T75
Test name
Test status
Simulation time 11308310 ps
CPU time 0.58 seconds
Started Jul 17 06:33:06 PM PDT 24
Finished Jul 17 06:33:07 PM PDT 24
Peak memory 196104 kb
Host smart-3cf148f4-b425-4380-97d0-ad6697c3f4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062844910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2062844910
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.419090230
Short name T409
Test name
Test status
Simulation time 2414460344 ps
CPU time 68.04 seconds
Started Jul 17 06:32:54 PM PDT 24
Finished Jul 17 06:34:03 PM PDT 24
Peak memory 200588 kb
Host smart-cb99dee9-b6b0-48dc-9dc1-c0e1fc1721df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419090230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.419090230
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2183987063
Short name T232
Test name
Test status
Simulation time 8874289384 ps
CPU time 33.76 seconds
Started Jul 17 06:32:55 PM PDT 24
Finished Jul 17 06:33:30 PM PDT 24
Peak memory 200320 kb
Host smart-694b50a8-c2cf-4f3f-aac9-8351cbb9997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183987063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2183987063
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3701855828
Short name T501
Test name
Test status
Simulation time 1275057041 ps
CPU time 226.16 seconds
Started Jul 17 06:32:57 PM PDT 24
Finished Jul 17 06:36:44 PM PDT 24
Peak memory 633612 kb
Host smart-88bad2c5-7c8e-4f13-9d03-4a06eca793c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701855828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3701855828
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4241944
Short name T289
Test name
Test status
Simulation time 22594917115 ps
CPU time 87.22 seconds
Started Jul 17 06:33:07 PM PDT 24
Finished Jul 17 06:34:35 PM PDT 24
Peak memory 200296 kb
Host smart-3d95394a-5ef8-4796-918b-b0da595ee9f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4241944
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.427506200
Short name T291
Test name
Test status
Simulation time 3354814356 ps
CPU time 46.24 seconds
Started Jul 17 06:32:55 PM PDT 24
Finished Jul 17 06:33:43 PM PDT 24
Peak memory 200372 kb
Host smart-3fa0433d-30f7-45c1-8f20-7a5c986e15fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427506200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.427506200
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.611874226
Short name T177
Test name
Test status
Simulation time 260700625 ps
CPU time 10.88 seconds
Started Jul 17 06:32:58 PM PDT 24
Finished Jul 17 06:33:09 PM PDT 24
Peak memory 200292 kb
Host smart-e66dcc7f-b2d2-4ea2-b429-5385ac9490fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611874226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.611874226
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3532269444
Short name T111
Test name
Test status
Simulation time 45887185418 ps
CPU time 628.5 seconds
Started Jul 17 06:33:05 PM PDT 24
Finished Jul 17 06:43:34 PM PDT 24
Peak memory 450568 kb
Host smart-3df7947b-de45-4f10-aba8-ae8e0f9f5a74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532269444 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3532269444
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1088344206
Short name T467
Test name
Test status
Simulation time 2389306487 ps
CPU time 35.37 seconds
Started Jul 17 06:33:03 PM PDT 24
Finished Jul 17 06:33:39 PM PDT 24
Peak memory 200252 kb
Host smart-f4cdd83b-a42b-45b4-9366-c7a66190fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088344206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1088344206
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3542950304
Short name T82
Test name
Test status
Simulation time 11337028 ps
CPU time 0.58 seconds
Started Jul 17 06:30:39 PM PDT 24
Finished Jul 17 06:30:41 PM PDT 24
Peak memory 195820 kb
Host smart-8e776116-73a5-4b51-82a9-50cec0b39626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542950304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3542950304
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3605187682
Short name T157
Test name
Test status
Simulation time 4143878586 ps
CPU time 19.22 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:30:44 PM PDT 24
Peak memory 200340 kb
Host smart-07ad9a2d-2113-4d63-b3d3-beb4f36f3fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605187682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3605187682
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1822804134
Short name T372
Test name
Test status
Simulation time 3312747927 ps
CPU time 28.58 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 06:30:55 PM PDT 24
Peak memory 200196 kb
Host smart-d32af52b-b9ef-430c-851d-ebbbf92ec3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822804134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1822804134
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3230902750
Short name T249
Test name
Test status
Simulation time 1488691958 ps
CPU time 261.4 seconds
Started Jul 17 06:30:24 PM PDT 24
Finished Jul 17 06:34:46 PM PDT 24
Peak memory 452912 kb
Host smart-d38d3778-2eac-46ad-8136-2a390c6deb37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230902750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3230902750
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1154427005
Short name T58
Test name
Test status
Simulation time 8053519268 ps
CPU time 94.45 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:32:02 PM PDT 24
Peak memory 200340 kb
Host smart-f0e55e58-c6d1-45c0-9ac2-29195b73c30c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154427005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1154427005
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2583584921
Short name T303
Test name
Test status
Simulation time 21395123859 ps
CPU time 198.69 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:33:46 PM PDT 24
Peak memory 200368 kb
Host smart-880bddc7-a046-41f9-9ee7-9f7f99dcc53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583584921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2583584921
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1402781542
Short name T48
Test name
Test status
Simulation time 52321676 ps
CPU time 0.9 seconds
Started Jul 17 06:30:49 PM PDT 24
Finished Jul 17 06:30:50 PM PDT 24
Peak memory 218256 kb
Host smart-45ec105e-476e-4f53-ba31-dcc1678bbbe9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402781542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1402781542
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.162299095
Short name T473
Test name
Test status
Simulation time 1651669480 ps
CPU time 9.49 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:30:37 PM PDT 24
Peak memory 200292 kb
Host smart-ed350d7d-3dc6-4b30-8bb7-5386e0f499ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162299095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.162299095
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.162304370
Short name T21
Test name
Test status
Simulation time 63424362445 ps
CPU time 5043.95 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 07:54:44 PM PDT 24
Peak memory 817160 kb
Host smart-b9cb20a2-6379-4b23-8461-a3dfc32f4e31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162304370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.162304370
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3576835639
Short name T300
Test name
Test status
Simulation time 6423059384 ps
CPU time 63.63 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 06:31:43 PM PDT 24
Peak memory 200380 kb
Host smart-7e014692-a148-457b-b587-df6945fe6efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3576835639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3576835639
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2686551534
Short name T349
Test name
Test status
Simulation time 27044606885 ps
CPU time 113.87 seconds
Started Jul 17 06:30:39 PM PDT 24
Finished Jul 17 06:32:34 PM PDT 24
Peak memory 200340 kb
Host smart-c4651baa-0691-472c-a998-4d6373414e53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2686551534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2686551534
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1170843386
Short name T260
Test name
Test status
Simulation time 6636907813 ps
CPU time 133.69 seconds
Started Jul 17 06:30:39 PM PDT 24
Finished Jul 17 06:32:53 PM PDT 24
Peak memory 200360 kb
Host smart-1f774ca9-d250-4d8a-9c70-5f8674a75540
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1170843386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1170843386
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2063196916
Short name T215
Test name
Test status
Simulation time 45815253876 ps
CPU time 605.4 seconds
Started Jul 17 06:30:26 PM PDT 24
Finished Jul 17 06:40:33 PM PDT 24
Peak memory 200356 kb
Host smart-e350553d-7fd3-4245-ac85-81b3c552c808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2063196916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2063196916
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3930342501
Short name T226
Test name
Test status
Simulation time 551845958718 ps
CPU time 2234.05 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 07:07:53 PM PDT 24
Peak memory 215816 kb
Host smart-77686030-eb87-42cc-a202-837b65da7985
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3930342501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3930342501
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.833097311
Short name T503
Test name
Test status
Simulation time 553895163153 ps
CPU time 2436.04 seconds
Started Jul 17 06:30:40 PM PDT 24
Finished Jul 17 07:11:18 PM PDT 24
Peak memory 216116 kb
Host smart-85d45652-edc2-46c6-85d5-dd6a1cd82401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=833097311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.833097311
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.594779742
Short name T487
Test name
Test status
Simulation time 1850806874 ps
CPU time 48.27 seconds
Started Jul 17 06:30:25 PM PDT 24
Finished Jul 17 06:31:14 PM PDT 24
Peak memory 200336 kb
Host smart-288a51b3-7c3a-4557-9f1a-e3f8fe1f5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594779742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.594779742
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.494775189
Short name T367
Test name
Test status
Simulation time 14958977 ps
CPU time 0.58 seconds
Started Jul 17 06:33:14 PM PDT 24
Finished Jul 17 06:33:16 PM PDT 24
Peak memory 195176 kb
Host smart-84ded8bd-6cf3-4d2c-8e84-13c2b48d79de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494775189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.494775189
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1144083505
Short name T212
Test name
Test status
Simulation time 1948175200 ps
CPU time 57.56 seconds
Started Jul 17 06:33:14 PM PDT 24
Finished Jul 17 06:34:13 PM PDT 24
Peak memory 200304 kb
Host smart-2870882c-d1ba-4464-882d-6699809d8798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144083505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1144083505
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2139276708
Short name T454
Test name
Test status
Simulation time 1084192300 ps
CPU time 15.2 seconds
Started Jul 17 06:33:15 PM PDT 24
Finished Jul 17 06:33:31 PM PDT 24
Peak memory 200292 kb
Host smart-006952a7-993e-4e7a-aeaa-de24b4ae1cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139276708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2139276708
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1474616090
Short name T492
Test name
Test status
Simulation time 1464455966 ps
CPU time 235.64 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:37:12 PM PDT 24
Peak memory 418940 kb
Host smart-5679db07-16cd-4c72-add9-e655c5241ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474616090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1474616090
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3565532666
Short name T471
Test name
Test status
Simulation time 8284612129 ps
CPU time 147.89 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:35:44 PM PDT 24
Peak memory 200388 kb
Host smart-b4370661-b9bd-4659-ae4b-ec0d3e9d83ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565532666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3565532666
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1216972869
Short name T347
Test name
Test status
Simulation time 10813862035 ps
CPU time 164.44 seconds
Started Jul 17 06:33:09 PM PDT 24
Finished Jul 17 06:35:54 PM PDT 24
Peak memory 208488 kb
Host smart-0bd5f9f5-18d2-421f-b308-6acfb6678670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216972869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1216972869
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3943660795
Short name T243
Test name
Test status
Simulation time 1355710387 ps
CPU time 14.25 seconds
Started Jul 17 06:33:06 PM PDT 24
Finished Jul 17 06:33:21 PM PDT 24
Peak memory 200296 kb
Host smart-f56b1084-1a78-41bc-a77a-5b1834074a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943660795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3943660795
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1927457265
Short name T73
Test name
Test status
Simulation time 69914417174 ps
CPU time 879.11 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:47:56 PM PDT 24
Peak memory 325364 kb
Host smart-4bf77196-e6b8-4e76-ac87-e2548718880a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927457265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1927457265
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3767407897
Short name T195
Test name
Test status
Simulation time 6292387324 ps
CPU time 78.36 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:34:35 PM PDT 24
Peak memory 200372 kb
Host smart-8b9e5cff-974e-47b2-87fa-fda8a96e3ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767407897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3767407897
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3943386908
Short name T166
Test name
Test status
Simulation time 16236349 ps
CPU time 0.66 seconds
Started Jul 17 06:33:17 PM PDT 24
Finished Jul 17 06:33:18 PM PDT 24
Peak memory 196112 kb
Host smart-43ce4171-b36e-40a7-9882-1a7bf1897620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943386908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3943386908
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.124150166
Short name T131
Test name
Test status
Simulation time 359980733 ps
CPU time 18.79 seconds
Started Jul 17 06:33:15 PM PDT 24
Finished Jul 17 06:33:35 PM PDT 24
Peak memory 200336 kb
Host smart-3794cca1-a77f-4d70-a49c-a6c88587086f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124150166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.124150166
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1077471620
Short name T220
Test name
Test status
Simulation time 4347809078 ps
CPU time 55.8 seconds
Started Jul 17 06:33:15 PM PDT 24
Finished Jul 17 06:34:11 PM PDT 24
Peak memory 216572 kb
Host smart-8948a612-ee2e-476c-a0ad-dbac4f7e170f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077471620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1077471620
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1231088866
Short name T258
Test name
Test status
Simulation time 13796512471 ps
CPU time 193.57 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:36:31 PM PDT 24
Peak memory 620056 kb
Host smart-4c2a87a8-f65d-4053-b415-084148086885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231088866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1231088866
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.819011675
Short name T33
Test name
Test status
Simulation time 51392946138 ps
CPU time 234.72 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:37:11 PM PDT 24
Peak memory 200348 kb
Host smart-0fbd30fc-6733-45f5-a329-e88151b3a63f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819011675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.819011675
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.670537227
Short name T276
Test name
Test status
Simulation time 4246653859 ps
CPU time 66.8 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:34:23 PM PDT 24
Peak memory 200376 kb
Host smart-a4c4b435-d191-43e9-93a6-8f68f478c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670537227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.670537227
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2899536882
Short name T296
Test name
Test status
Simulation time 824953400 ps
CPU time 7.19 seconds
Started Jul 17 06:33:15 PM PDT 24
Finished Jul 17 06:33:22 PM PDT 24
Peak memory 200304 kb
Host smart-250d3e4a-c5ea-4e45-93b2-edd9e814c8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899536882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2899536882
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.402221454
Short name T244
Test name
Test status
Simulation time 3376774056 ps
CPU time 37.91 seconds
Started Jul 17 06:33:14 PM PDT 24
Finished Jul 17 06:33:53 PM PDT 24
Peak memory 200596 kb
Host smart-06a5c3e7-9b81-443a-b99c-1a180b52819a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402221454 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.402221454
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2555167938
Short name T298
Test name
Test status
Simulation time 5767779875 ps
CPU time 66.93 seconds
Started Jul 17 06:33:16 PM PDT 24
Finished Jul 17 06:34:24 PM PDT 24
Peak memory 200252 kb
Host smart-06d06c38-bc6e-45dd-8c71-3bf8c47ec2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555167938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2555167938
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2950408671
Short name T3
Test name
Test status
Simulation time 49756857 ps
CPU time 0.59 seconds
Started Jul 17 06:33:30 PM PDT 24
Finished Jul 17 06:33:32 PM PDT 24
Peak memory 196176 kb
Host smart-5b05cba9-7f28-422c-a097-b1b4a8571d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950408671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2950408671
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1395097755
Short name T203
Test name
Test status
Simulation time 1031066286 ps
CPU time 61.83 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:34:32 PM PDT 24
Peak memory 200344 kb
Host smart-0fda2201-95bf-4b73-b28a-7b44b13d7e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395097755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1395097755
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.27878105
Short name T410
Test name
Test status
Simulation time 8522693844 ps
CPU time 39.17 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:34:10 PM PDT 24
Peak memory 216740 kb
Host smart-ad2e9637-532a-4379-b73e-5c886c2eb7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27878105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.27878105
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.214852029
Short name T411
Test name
Test status
Simulation time 5086914172 ps
CPU time 916.02 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:48:46 PM PDT 24
Peak memory 682332 kb
Host smart-f0573e6b-d95c-42b5-a359-e077bc9df952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214852029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.214852029
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2587085641
Short name T228
Test name
Test status
Simulation time 14442722597 ps
CPU time 192.38 seconds
Started Jul 17 06:33:30 PM PDT 24
Finished Jul 17 06:36:43 PM PDT 24
Peak memory 200328 kb
Host smart-d13b5f66-0435-459c-9a84-c3eef62493b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587085641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2587085641
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1071308058
Short name T178
Test name
Test status
Simulation time 9556110434 ps
CPU time 118.18 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:35:28 PM PDT 24
Peak memory 208564 kb
Host smart-4eeda9ed-0297-469c-ba3a-1d4b9c20a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071308058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1071308058
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2066059640
Short name T279
Test name
Test status
Simulation time 1204574359 ps
CPU time 14.34 seconds
Started Jul 17 06:33:28 PM PDT 24
Finished Jul 17 06:33:43 PM PDT 24
Peak memory 200284 kb
Host smart-608394ff-0119-4a32-bf4d-fd4b950b669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066059640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2066059640
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1652666666
Short name T26
Test name
Test status
Simulation time 7639812797 ps
CPU time 443.11 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:40:53 PM PDT 24
Peak memory 200344 kb
Host smart-01c26f83-f495-4508-af65-eb1113039e28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652666666 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1652666666
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2114347178
Short name T88
Test name
Test status
Simulation time 9353809645 ps
CPU time 124.71 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:35:35 PM PDT 24
Peak memory 200368 kb
Host smart-1489c31c-5a34-44a9-9bfb-5ff1d1236e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114347178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2114347178
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.362297530
Short name T390
Test name
Test status
Simulation time 170835027 ps
CPU time 0.63 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:33:31 PM PDT 24
Peak memory 196180 kb
Host smart-0344d921-f4f0-4bfe-a51d-a3a438b4f57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362297530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.362297530
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.588060771
Short name T30
Test name
Test status
Simulation time 287089685 ps
CPU time 16.22 seconds
Started Jul 17 06:33:28 PM PDT 24
Finished Jul 17 06:33:45 PM PDT 24
Peak memory 200320 kb
Host smart-e6e6b816-55ae-46cc-b720-061ad813fedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588060771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.588060771
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2690256265
Short name T427
Test name
Test status
Simulation time 3330106956 ps
CPU time 22.38 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:33:53 PM PDT 24
Peak memory 200356 kb
Host smart-57346bfb-13d4-4181-b6a9-0aaa1dd0c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690256265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2690256265
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4007672342
Short name T206
Test name
Test status
Simulation time 2186041476 ps
CPU time 24.32 seconds
Started Jul 17 06:33:30 PM PDT 24
Finished Jul 17 06:33:55 PM PDT 24
Peak memory 236820 kb
Host smart-457369ef-3163-4685-825f-931cb4b73f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007672342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4007672342
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.342937511
Short name T187
Test name
Test status
Simulation time 11130100658 ps
CPU time 212.34 seconds
Started Jul 17 06:33:30 PM PDT 24
Finished Jul 17 06:37:03 PM PDT 24
Peak memory 200264 kb
Host smart-ff22f956-2cda-47a7-88ac-47b205a5807a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342937511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.342937511
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2009911826
Short name T336
Test name
Test status
Simulation time 4052037761 ps
CPU time 78.65 seconds
Started Jul 17 06:33:30 PM PDT 24
Finished Jul 17 06:34:50 PM PDT 24
Peak memory 200384 kb
Host smart-a07a30ac-b678-4af7-9e27-247eda88f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009911826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2009911826
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3333496081
Short name T214
Test name
Test status
Simulation time 2228173628 ps
CPU time 16.51 seconds
Started Jul 17 06:33:28 PM PDT 24
Finished Jul 17 06:33:45 PM PDT 24
Peak memory 200316 kb
Host smart-d42902f5-8dfd-4339-be25-8a3c7d81b6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333496081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3333496081
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2940938148
Short name T71
Test name
Test status
Simulation time 22238847626 ps
CPU time 98.92 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:35:09 PM PDT 24
Peak memory 216904 kb
Host smart-8ac0d1e2-4113-4ca8-9bad-57833a8490ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940938148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2940938148
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3663588140
Short name T389
Test name
Test status
Simulation time 22421703082 ps
CPU time 77.11 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:34:47 PM PDT 24
Peak memory 200276 kb
Host smart-b1453a23-bb2b-4f3c-9039-d9a8dba92e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663588140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3663588140
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.460693012
Short name T385
Test name
Test status
Simulation time 33327480 ps
CPU time 0.6 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:33:42 PM PDT 24
Peak memory 195856 kb
Host smart-a675b407-131c-4b6b-9f63-7799d2f33c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460693012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.460693012
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2612411758
Short name T417
Test name
Test status
Simulation time 17338586105 ps
CPU time 59.77 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:34:42 PM PDT 24
Peak memory 200360 kb
Host smart-b9f407ae-f478-4cf7-8871-d154fe134b72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612411758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2612411758
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3635706183
Short name T44
Test name
Test status
Simulation time 1744297576 ps
CPU time 22.21 seconds
Started Jul 17 06:33:43 PM PDT 24
Finished Jul 17 06:34:06 PM PDT 24
Peak memory 200272 kb
Host smart-fda8ef7b-01c8-4fc2-a74c-e28b3a0fb3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635706183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3635706183
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.312459547
Short name T237
Test name
Test status
Simulation time 26461094980 ps
CPU time 1391.21 seconds
Started Jul 17 06:33:42 PM PDT 24
Finished Jul 17 06:56:54 PM PDT 24
Peak memory 772940 kb
Host smart-198bd7b7-d368-4284-b6ab-1f79d5dd2296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312459547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.312459547
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.399190109
Short name T412
Test name
Test status
Simulation time 5727394357 ps
CPU time 98.41 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:35:20 PM PDT 24
Peak memory 200388 kb
Host smart-38c1be44-6ab6-402f-a992-b3bbccbd6107
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399190109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.399190109
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.790500337
Short name T472
Test name
Test status
Simulation time 11350206983 ps
CPU time 121.4 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:35:43 PM PDT 24
Peak memory 200632 kb
Host smart-de91eff7-3b8d-4124-8d5f-f2d72315f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790500337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.790500337
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3099317138
Short name T53
Test name
Test status
Simulation time 15414687367 ps
CPU time 13.29 seconds
Started Jul 17 06:33:29 PM PDT 24
Finished Jul 17 06:33:44 PM PDT 24
Peak memory 200316 kb
Host smart-e9a15586-d13a-4e2f-a8ff-d16399cc569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099317138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3099317138
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.538006811
Short name T489
Test name
Test status
Simulation time 228954513136 ps
CPU time 1060.31 seconds
Started Jul 17 06:33:40 PM PDT 24
Finished Jul 17 06:51:22 PM PDT 24
Peak memory 681476 kb
Host smart-4c570caf-3998-42d8-aeb1-3ebeee463b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538006811 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.538006811
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1593219879
Short name T216
Test name
Test status
Simulation time 1550511888 ps
CPU time 20.36 seconds
Started Jul 17 06:33:40 PM PDT 24
Finished Jul 17 06:34:01 PM PDT 24
Peak memory 200340 kb
Host smart-3784a436-5d86-4b3a-bfdd-c4de18cae108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593219879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1593219879
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3974770893
Short name T36
Test name
Test status
Simulation time 64914706 ps
CPU time 0.62 seconds
Started Jul 17 06:33:52 PM PDT 24
Finished Jul 17 06:33:54 PM PDT 24
Peak memory 196088 kb
Host smart-2fedc80b-9a0c-4341-bae8-931578ba02dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974770893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3974770893
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1331912158
Short name T29
Test name
Test status
Simulation time 1558061963 ps
CPU time 103.87 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:35:26 PM PDT 24
Peak memory 200316 kb
Host smart-63db608a-be1a-43d9-b2c2-2f02ed3677e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331912158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1331912158
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2469272823
Short name T424
Test name
Test status
Simulation time 286140240 ps
CPU time 4.17 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:33:46 PM PDT 24
Peak memory 200224 kb
Host smart-ca5ff745-498b-4c48-a0fe-b4bd99b67853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469272823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2469272823
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3179052029
Short name T504
Test name
Test status
Simulation time 1214630177 ps
CPU time 274.03 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:38:16 PM PDT 24
Peak memory 627624 kb
Host smart-f88668c3-0785-45f8-bd2f-55d178e88bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179052029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3179052029
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.64583425
Short name T199
Test name
Test status
Simulation time 21129422722 ps
CPU time 73.76 seconds
Started Jul 17 06:33:43 PM PDT 24
Finished Jul 17 06:34:58 PM PDT 24
Peak memory 200168 kb
Host smart-9b4216fc-b74f-421a-a61d-7fa4c20ed1b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64583425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.64583425
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1311205519
Short name T147
Test name
Test status
Simulation time 26729268423 ps
CPU time 92.64 seconds
Started Jul 17 06:33:40 PM PDT 24
Finished Jul 17 06:35:13 PM PDT 24
Peak memory 200392 kb
Host smart-ed7bb155-ef47-40af-b980-625a7eb20424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311205519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1311205519
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1983917555
Short name T252
Test name
Test status
Simulation time 558640066 ps
CPU time 5.74 seconds
Started Jul 17 06:33:41 PM PDT 24
Finished Jul 17 06:33:48 PM PDT 24
Peak memory 200232 kb
Host smart-66f5d6ff-534c-4cd4-804a-4b137f7b84e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983917555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1983917555
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2852603912
Short name T348
Test name
Test status
Simulation time 4592652903 ps
CPU time 716.52 seconds
Started Jul 17 06:33:52 PM PDT 24
Finished Jul 17 06:45:49 PM PDT 24
Peak memory 699720 kb
Host smart-9e4f1235-5025-40f4-b983-daa038e28cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852603912 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2852603912
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1974078948
Short name T143
Test name
Test status
Simulation time 228886275 ps
CPU time 13.54 seconds
Started Jul 17 06:33:50 PM PDT 24
Finished Jul 17 06:34:04 PM PDT 24
Peak memory 200224 kb
Host smart-a50771b1-d9fa-40fb-885f-94653e158f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974078948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1974078948
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1272409162
Short name T318
Test name
Test status
Simulation time 16278126 ps
CPU time 0.59 seconds
Started Jul 17 06:33:50 PM PDT 24
Finished Jul 17 06:33:51 PM PDT 24
Peak memory 195816 kb
Host smart-acb4e548-17a2-414b-94f1-5fcedcac5a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272409162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1272409162
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.945195513
Short name T339
Test name
Test status
Simulation time 1674570794 ps
CPU time 93.52 seconds
Started Jul 17 06:33:50 PM PDT 24
Finished Jul 17 06:35:25 PM PDT 24
Peak memory 200276 kb
Host smart-f79e1119-1c47-4563-85b1-ed2b437bdb2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945195513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.945195513
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2610888001
Short name T295
Test name
Test status
Simulation time 9462199249 ps
CPU time 83.65 seconds
Started Jul 17 06:33:49 PM PDT 24
Finished Jul 17 06:35:13 PM PDT 24
Peak memory 216748 kb
Host smart-1b91c7be-7e11-4eac-b292-6d0943c69976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610888001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2610888001
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1900625254
Short name T162
Test name
Test status
Simulation time 194015144 ps
CPU time 14.32 seconds
Started Jul 17 06:33:51 PM PDT 24
Finished Jul 17 06:34:06 PM PDT 24
Peak memory 230856 kb
Host smart-fd9eade8-d4f7-4a88-badc-a8659fe2a582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900625254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1900625254
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.797936013
Short name T419
Test name
Test status
Simulation time 236427761 ps
CPU time 4.86 seconds
Started Jul 17 06:33:52 PM PDT 24
Finished Jul 17 06:33:57 PM PDT 24
Peak memory 200068 kb
Host smart-05cb2ba1-dba5-4627-ab11-af940a30517b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797936013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.797936013
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.932498763
Short name T312
Test name
Test status
Simulation time 1028891819 ps
CPU time 66.2 seconds
Started Jul 17 06:33:52 PM PDT 24
Finished Jul 17 06:34:58 PM PDT 24
Peak memory 200356 kb
Host smart-84544715-5382-47c5-9023-da03aa514525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932498763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.932498763
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1000387637
Short name T122
Test name
Test status
Simulation time 756673151 ps
CPU time 9.18 seconds
Started Jul 17 06:33:50 PM PDT 24
Finished Jul 17 06:34:00 PM PDT 24
Peak memory 200296 kb
Host smart-88861d2e-f083-4917-897b-35579732177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000387637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1000387637
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2279714290
Short name T440
Test name
Test status
Simulation time 12638324572 ps
CPU time 438.11 seconds
Started Jul 17 06:33:50 PM PDT 24
Finished Jul 17 06:41:09 PM PDT 24
Peak memory 662016 kb
Host smart-10d8849e-67ce-4cce-9565-df533cd67ae5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279714290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2279714290
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.998303697
Short name T110
Test name
Test status
Simulation time 7402208032 ps
CPU time 68.89 seconds
Started Jul 17 06:33:50 PM PDT 24
Finished Jul 17 06:35:00 PM PDT 24
Peak memory 200408 kb
Host smart-dcf34ab9-308f-4f96-b74e-efff7ee3d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998303697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.998303697
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.488733331
Short name T364
Test name
Test status
Simulation time 11999655 ps
CPU time 0.57 seconds
Started Jul 17 06:33:59 PM PDT 24
Finished Jul 17 06:34:00 PM PDT 24
Peak memory 195124 kb
Host smart-0203ee0d-b24c-430e-8395-1b8d96e760dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488733331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.488733331
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2280693989
Short name T331
Test name
Test status
Simulation time 815954255 ps
CPU time 49.9 seconds
Started Jul 17 06:34:01 PM PDT 24
Finished Jul 17 06:34:51 PM PDT 24
Peak memory 200336 kb
Host smart-ee4d00ea-6588-4b7d-91eb-5be7dc3b7e62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280693989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2280693989
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.4017143391
Short name T429
Test name
Test status
Simulation time 2217724776 ps
CPU time 40.64 seconds
Started Jul 17 06:34:03 PM PDT 24
Finished Jul 17 06:34:44 PM PDT 24
Peak memory 200332 kb
Host smart-50b9a50f-907e-4795-857b-1cb91778d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017143391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4017143391
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.4085879838
Short name T460
Test name
Test status
Simulation time 3334191609 ps
CPU time 159.43 seconds
Started Jul 17 06:34:02 PM PDT 24
Finished Jul 17 06:36:42 PM PDT 24
Peak memory 437468 kb
Host smart-427a786e-34e1-4953-a718-bbdb264034e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085879838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.4085879838
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2157072187
Short name T395
Test name
Test status
Simulation time 807146024 ps
CPU time 42.87 seconds
Started Jul 17 06:34:03 PM PDT 24
Finished Jul 17 06:34:47 PM PDT 24
Peak memory 199928 kb
Host smart-588e44b3-548d-4006-b616-34135bf6b968
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157072187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2157072187
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3944584353
Short name T482
Test name
Test status
Simulation time 4114509170 ps
CPU time 115.89 seconds
Started Jul 17 06:34:01 PM PDT 24
Finished Jul 17 06:35:57 PM PDT 24
Peak memory 200380 kb
Host smart-369a3143-c7a6-404c-93bc-56834b4620df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944584353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3944584353
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2819550761
Short name T205
Test name
Test status
Simulation time 851972476 ps
CPU time 3.55 seconds
Started Jul 17 06:34:03 PM PDT 24
Finished Jul 17 06:34:07 PM PDT 24
Peak memory 200340 kb
Host smart-46bc6a47-de18-4b57-a54a-1185027d5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819550761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2819550761
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3985075213
Short name T45
Test name
Test status
Simulation time 326360133101 ps
CPU time 4140.52 seconds
Started Jul 17 06:34:01 PM PDT 24
Finished Jul 17 07:43:02 PM PDT 24
Peak memory 830492 kb
Host smart-f185ff93-d576-42d7-bd63-f237b5ca08b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985075213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3985075213
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.268208658
Short name T268
Test name
Test status
Simulation time 5066191014 ps
CPU time 84.28 seconds
Started Jul 17 06:34:03 PM PDT 24
Finished Jul 17 06:35:28 PM PDT 24
Peak memory 200044 kb
Host smart-0f008054-6d36-4ec9-8a24-1cd8cfe3744e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268208658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.268208658
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2687724953
Short name T365
Test name
Test status
Simulation time 29484244 ps
CPU time 0.56 seconds
Started Jul 17 06:34:11 PM PDT 24
Finished Jul 17 06:34:12 PM PDT 24
Peak memory 195096 kb
Host smart-409c2eb2-2deb-4890-a107-b803f3057e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687724953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2687724953
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.500326926
Short name T401
Test name
Test status
Simulation time 55048994 ps
CPU time 3.09 seconds
Started Jul 17 06:34:02 PM PDT 24
Finished Jul 17 06:34:06 PM PDT 24
Peak memory 200456 kb
Host smart-490b48ae-9cd1-44c5-a3bb-925a5de425b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500326926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.500326926
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1172736158
Short name T285
Test name
Test status
Simulation time 2508870039 ps
CPU time 33.45 seconds
Started Jul 17 06:34:01 PM PDT 24
Finished Jul 17 06:34:35 PM PDT 24
Peak memory 200344 kb
Host smart-ec66bb5d-6780-4245-bbfc-51eb12264846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172736158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1172736158
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.186000671
Short name T515
Test name
Test status
Simulation time 10375065680 ps
CPU time 516 seconds
Started Jul 17 06:34:03 PM PDT 24
Finished Jul 17 06:42:39 PM PDT 24
Peak memory 484852 kb
Host smart-acc5a9fe-3d39-423e-b5b7-dfb977849a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186000671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.186000671
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4097465049
Short name T399
Test name
Test status
Simulation time 9384454532 ps
CPU time 123.22 seconds
Started Jul 17 06:34:02 PM PDT 24
Finished Jul 17 06:36:06 PM PDT 24
Peak memory 200332 kb
Host smart-eb50ffe3-f07f-4e31-9b73-d890037d0bbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097465049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4097465049
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3720867480
Short name T402
Test name
Test status
Simulation time 24098527257 ps
CPU time 107.28 seconds
Started Jul 17 06:34:02 PM PDT 24
Finished Jul 17 06:35:50 PM PDT 24
Peak memory 216500 kb
Host smart-f98f2b5b-9d34-42b0-814b-5d3c4acc4a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720867480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3720867480
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1943256437
Short name T434
Test name
Test status
Simulation time 930904297 ps
CPU time 3.1 seconds
Started Jul 17 06:34:02 PM PDT 24
Finished Jul 17 06:34:06 PM PDT 24
Peak memory 200192 kb
Host smart-74030558-3a22-44dd-9c69-9900e05f22df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943256437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1943256437
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4093632436
Short name T125
Test name
Test status
Simulation time 36356892991 ps
CPU time 2367.32 seconds
Started Jul 17 06:34:01 PM PDT 24
Finished Jul 17 07:13:29 PM PDT 24
Peak memory 700696 kb
Host smart-754279e0-1697-45ef-b442-5c95b0579020
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093632436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4093632436
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1139697329
Short name T235
Test name
Test status
Simulation time 23160176486 ps
CPU time 104.85 seconds
Started Jul 17 06:34:01 PM PDT 24
Finished Jul 17 06:35:47 PM PDT 24
Peak memory 200344 kb
Host smart-ef7d11cc-9b26-4246-8509-3fd40b6981b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139697329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1139697329
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1479538307
Short name T133
Test name
Test status
Simulation time 21138690 ps
CPU time 0.57 seconds
Started Jul 17 06:34:11 PM PDT 24
Finished Jul 17 06:34:12 PM PDT 24
Peak memory 195812 kb
Host smart-87e389b6-3855-4243-96a1-8fcabe9a36ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479538307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1479538307
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1839758562
Short name T55
Test name
Test status
Simulation time 1631547345 ps
CPU time 105.19 seconds
Started Jul 17 06:34:11 PM PDT 24
Finished Jul 17 06:35:57 PM PDT 24
Peak memory 200352 kb
Host smart-0a95c874-def8-4156-9cba-6832cace5612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839758562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1839758562
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1967160733
Short name T309
Test name
Test status
Simulation time 1340096852 ps
CPU time 20.72 seconds
Started Jul 17 06:34:13 PM PDT 24
Finished Jul 17 06:34:34 PM PDT 24
Peak memory 200244 kb
Host smart-dce2e789-4cc6-4d7a-b4a3-28eedd2281ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967160733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1967160733
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4155327643
Short name T204
Test name
Test status
Simulation time 936452895 ps
CPU time 104.43 seconds
Started Jul 17 06:34:11 PM PDT 24
Finished Jul 17 06:35:56 PM PDT 24
Peak memory 324120 kb
Host smart-3d0fce5a-6dfc-4311-b296-a1f41a9169d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155327643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4155327643
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1557044457
Short name T273
Test name
Test status
Simulation time 2121803245 ps
CPU time 135.57 seconds
Started Jul 17 06:34:12 PM PDT 24
Finished Jul 17 06:36:28 PM PDT 24
Peak memory 200292 kb
Host smart-5b04ec1d-319e-4cf8-9023-c2d0fa0b47a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557044457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1557044457
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1481698168
Short name T397
Test name
Test status
Simulation time 9054184801 ps
CPU time 30.9 seconds
Started Jul 17 06:34:13 PM PDT 24
Finished Jul 17 06:34:44 PM PDT 24
Peak memory 200292 kb
Host smart-e7baa9f4-955c-4f98-9147-72503e890a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481698168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1481698168
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3936611874
Short name T287
Test name
Test status
Simulation time 5098719714 ps
CPU time 14.75 seconds
Started Jul 17 06:34:10 PM PDT 24
Finished Jul 17 06:34:25 PM PDT 24
Peak memory 200332 kb
Host smart-793c991d-2ee6-4f53-8359-737c94f44173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936611874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3936611874
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.641282764
Short name T174
Test name
Test status
Simulation time 1433832664 ps
CPU time 16.95 seconds
Started Jul 17 06:34:11 PM PDT 24
Finished Jul 17 06:34:28 PM PDT 24
Peak memory 200288 kb
Host smart-06f800ef-d159-4692-a404-a18d1dc6f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641282764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.641282764
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1398947374
Short name T39
Test name
Test status
Simulation time 48677466 ps
CPU time 0.62 seconds
Started Jul 17 06:30:46 PM PDT 24
Finished Jul 17 06:30:48 PM PDT 24
Peak memory 196176 kb
Host smart-6ebbefd0-fb84-4fda-a6bd-286917c2b18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398947374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1398947374
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1849537385
Short name T448
Test name
Test status
Simulation time 10995617006 ps
CPU time 770.01 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 06:43:29 PM PDT 24
Peak memory 708640 kb
Host smart-ee385b84-345e-4c94-b043-3d36c3e5a4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849537385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1849537385
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.409809059
Short name T130
Test name
Test status
Simulation time 1699823586 ps
CPU time 7.56 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 06:30:46 PM PDT 24
Peak memory 200144 kb
Host smart-55403aa6-609f-40d5-8d49-6dfd9998f180
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409809059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.409809059
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1738003800
Short name T181
Test name
Test status
Simulation time 861286943 ps
CPU time 12.01 seconds
Started Jul 17 06:30:39 PM PDT 24
Finished Jul 17 06:30:53 PM PDT 24
Peak memory 200296 kb
Host smart-19b849c0-6d8d-43e2-9eb6-df7261428a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738003800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1738003800
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.752050970
Short name T51
Test name
Test status
Simulation time 98157439 ps
CPU time 0.99 seconds
Started Jul 17 06:30:49 PM PDT 24
Finished Jul 17 06:30:50 PM PDT 24
Peak memory 218164 kb
Host smart-922808e0-63fb-4683-ba22-401e941ec291
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752050970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.752050970
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4237933182
Short name T428
Test name
Test status
Simulation time 85947140 ps
CPU time 1.28 seconds
Started Jul 17 06:30:39 PM PDT 24
Finished Jul 17 06:30:41 PM PDT 24
Peak memory 200348 kb
Host smart-b2a1b425-1f93-4790-92de-47051e7c5448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237933182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4237933182
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1238799612
Short name T86
Test name
Test status
Simulation time 26830504815 ps
CPU time 783.8 seconds
Started Jul 17 06:30:53 PM PDT 24
Finished Jul 17 06:43:58 PM PDT 24
Peak memory 444312 kb
Host smart-82b3bec5-7df8-44ca-b9d0-eb2f6905981f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238799612 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1238799612
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1676524096
Short name T28
Test name
Test status
Simulation time 118033452858 ps
CPU time 6356.58 seconds
Started Jul 17 06:30:48 PM PDT 24
Finished Jul 17 08:16:46 PM PDT 24
Peak memory 883708 kb
Host smart-b1bd5690-85a9-4d2e-977f-8dc3dceed257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676524096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1676524096
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.535742141
Short name T42
Test name
Test status
Simulation time 24947508885 ps
CPU time 44.44 seconds
Started Jul 17 06:30:38 PM PDT 24
Finished Jul 17 06:31:24 PM PDT 24
Peak memory 200352 kb
Host smart-b1093507-0977-433a-bf54-39f582bb2a1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=535742141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.535742141
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3204439859
Short name T274
Test name
Test status
Simulation time 20185820175 ps
CPU time 59.27 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:31:48 PM PDT 24
Peak memory 200328 kb
Host smart-4a6c69cf-40f9-4934-aca5-9b1872495d8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3204439859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3204439859
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.619963093
Short name T507
Test name
Test status
Simulation time 16640869949 ps
CPU time 130.04 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:32:58 PM PDT 24
Peak memory 200348 kb
Host smart-72562578-ff34-411d-9674-0588f503d10d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=619963093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.619963093
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2504945590
Short name T120
Test name
Test status
Simulation time 51904844732 ps
CPU time 688.79 seconds
Started Jul 17 06:30:37 PM PDT 24
Finished Jul 17 06:42:06 PM PDT 24
Peak memory 200332 kb
Host smart-e9c68d70-170d-4e99-ba5b-934d4a034cf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2504945590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2504945590
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2482750178
Short name T146
Test name
Test status
Simulation time 886507008002 ps
CPU time 2382.37 seconds
Started Jul 17 06:30:48 PM PDT 24
Finished Jul 17 07:10:31 PM PDT 24
Peak memory 216540 kb
Host smart-2f4700f4-93cd-45d9-a879-2e7ac51a7d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2482750178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2482750178
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.309286478
Short name T463
Test name
Test status
Simulation time 39474260755 ps
CPU time 2236.17 seconds
Started Jul 17 06:30:46 PM PDT 24
Finished Jul 17 07:08:03 PM PDT 24
Peak memory 215896 kb
Host smart-ce5c8619-107c-4ba6-ad81-3d57eea5add6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=309286478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.309286478
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.955431613
Short name T109
Test name
Test status
Simulation time 42544155565 ps
CPU time 148.62 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:33:17 PM PDT 24
Peak memory 200208 kb
Host smart-b14e7a67-6efc-418c-906c-5c52cc1b3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955431613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.955431613
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1452414765
Short name T219
Test name
Test status
Simulation time 12626983 ps
CPU time 0.58 seconds
Started Jul 17 06:34:28 PM PDT 24
Finished Jul 17 06:34:29 PM PDT 24
Peak memory 195856 kb
Host smart-7b26c472-221a-4c0b-8d11-8ec95d37d82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452414765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1452414765
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.471398980
Short name T418
Test name
Test status
Simulation time 1910937433 ps
CPU time 59.18 seconds
Started Jul 17 06:34:26 PM PDT 24
Finished Jul 17 06:35:26 PM PDT 24
Peak memory 200352 kb
Host smart-a897e1de-c735-4025-9e85-5252b1623672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471398980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.471398980
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1379791012
Short name T189
Test name
Test status
Simulation time 1067883975 ps
CPU time 21.89 seconds
Started Jul 17 06:34:28 PM PDT 24
Finished Jul 17 06:34:50 PM PDT 24
Peak memory 200228 kb
Host smart-ef606ccb-40e8-49ea-a1da-10d42a09989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379791012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1379791012
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3754511499
Short name T35
Test name
Test status
Simulation time 1581081078 ps
CPU time 332.75 seconds
Started Jul 17 06:34:27 PM PDT 24
Finished Jul 17 06:40:00 PM PDT 24
Peak memory 580000 kb
Host smart-30457345-0bac-4887-b05e-8f49ce54ae78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754511499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3754511499
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3619568437
Short name T248
Test name
Test status
Simulation time 9874380521 ps
CPU time 73.58 seconds
Started Jul 17 06:34:27 PM PDT 24
Finished Jul 17 06:35:41 PM PDT 24
Peak memory 200332 kb
Host smart-c3f4fb4c-8ecf-4545-9a49-9841e106bbd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619568437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3619568437
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.4289984688
Short name T387
Test name
Test status
Simulation time 3628142475 ps
CPU time 45.78 seconds
Started Jul 17 06:34:28 PM PDT 24
Finished Jul 17 06:35:14 PM PDT 24
Peak memory 200324 kb
Host smart-289fa1a1-3a68-4d22-942e-833df8bf239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289984688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.4289984688
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2886098913
Short name T129
Test name
Test status
Simulation time 298832069 ps
CPU time 3.47 seconds
Started Jul 17 06:34:11 PM PDT 24
Finished Jul 17 06:34:15 PM PDT 24
Peak memory 200356 kb
Host smart-c9b76003-84f4-4d0d-afa6-9eb624eb03ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886098913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2886098913
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3267081166
Short name T505
Test name
Test status
Simulation time 294938216666 ps
CPU time 3076.07 seconds
Started Jul 17 06:34:28 PM PDT 24
Finished Jul 17 07:25:45 PM PDT 24
Peak memory 815948 kb
Host smart-f5f4cb2b-affc-4123-8172-1d27f36286e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267081166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3267081166
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.410466626
Short name T54
Test name
Test status
Simulation time 1332224588 ps
CPU time 60.84 seconds
Started Jul 17 06:34:27 PM PDT 24
Finished Jul 17 06:35:28 PM PDT 24
Peak memory 200148 kb
Host smart-60bce849-0f00-4d42-885e-5294fb094b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410466626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.410466626
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1275925861
Short name T265
Test name
Test status
Simulation time 29994250 ps
CPU time 0.56 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:34:43 PM PDT 24
Peak memory 194936 kb
Host smart-ecf62c95-dd3b-424a-bc72-a17af668c819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275925861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1275925861
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3783656458
Short name T18
Test name
Test status
Simulation time 922600295 ps
CPU time 55.95 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:35:39 PM PDT 24
Peak memory 200300 kb
Host smart-39fbc99d-48bc-4ccb-8e9a-2f839f873d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783656458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3783656458
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.928408878
Short name T41
Test name
Test status
Simulation time 5313212815 ps
CPU time 36.98 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:35:19 PM PDT 24
Peak memory 200444 kb
Host smart-1539b661-5400-4386-bfc3-765cdd5caa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928408878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.928408878
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1433083769
Short name T108
Test name
Test status
Simulation time 1299629380 ps
CPU time 285.68 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:39:29 PM PDT 24
Peak memory 653980 kb
Host smart-891ddb19-beec-49ba-88fd-9b486a8947b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433083769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1433083769
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3482769934
Short name T451
Test name
Test status
Simulation time 5475441151 ps
CPU time 85.8 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:36:08 PM PDT 24
Peak memory 200372 kb
Host smart-38edade2-9a83-46f1-953e-53b8e06d7fc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482769934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3482769934
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3574539238
Short name T388
Test name
Test status
Simulation time 1399798312 ps
CPU time 76.63 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:35:58 PM PDT 24
Peak memory 200256 kb
Host smart-d51172e5-28d4-459a-b177-fd25dfe3e862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574539238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3574539238
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.368926174
Short name T210
Test name
Test status
Simulation time 329920878 ps
CPU time 15.01 seconds
Started Jul 17 06:34:29 PM PDT 24
Finished Jul 17 06:34:44 PM PDT 24
Peak memory 200312 kb
Host smart-519272f7-1535-4af9-8f2a-f999d0fc5d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368926174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.368926174
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2724073018
Short name T490
Test name
Test status
Simulation time 116105917313 ps
CPU time 2157.76 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 07:10:39 PM PDT 24
Peak memory 759000 kb
Host smart-3c56deab-4eaa-4a89-8429-4832ae7fd2ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724073018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2724073018
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2609140426
Short name T292
Test name
Test status
Simulation time 197992058 ps
CPU time 10.98 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:34:54 PM PDT 24
Peak memory 200312 kb
Host smart-df329485-7493-45a1-bbb0-8966491c8991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609140426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2609140426
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1115845202
Short name T134
Test name
Test status
Simulation time 115879308 ps
CPU time 0.58 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:34:42 PM PDT 24
Peak memory 195104 kb
Host smart-5442d004-d31c-4173-8106-e8714cf0b9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115845202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1115845202
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2920536359
Short name T447
Test name
Test status
Simulation time 1411335057 ps
CPU time 85.59 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:36:06 PM PDT 24
Peak memory 200236 kb
Host smart-9e0b64f7-acda-47b5-98c3-c5584a9f0864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920536359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2920536359
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3380114524
Short name T430
Test name
Test status
Simulation time 514968296 ps
CPU time 7.95 seconds
Started Jul 17 06:34:39 PM PDT 24
Finished Jul 17 06:34:48 PM PDT 24
Peak memory 200244 kb
Host smart-91a8e6c1-3d45-4bff-8773-6c2ea4c0b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380114524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3380114524
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2340928016
Short name T173
Test name
Test status
Simulation time 5476967510 ps
CPU time 1050.7 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:52:11 PM PDT 24
Peak memory 740068 kb
Host smart-7f0b09b9-abe9-4602-a2d3-9b5f76f7fe10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340928016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2340928016
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2941577408
Short name T132
Test name
Test status
Simulation time 1523828179 ps
CPU time 29.84 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:35:11 PM PDT 24
Peak memory 200316 kb
Host smart-12c4c81c-adf0-4576-8115-fb5f6c422dac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941577408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2941577408
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2183694305
Short name T374
Test name
Test status
Simulation time 931528174 ps
CPU time 54.1 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:35:37 PM PDT 24
Peak memory 200232 kb
Host smart-02e6027c-5af7-42d2-a523-01485bbb910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183694305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2183694305
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3350745933
Short name T257
Test name
Test status
Simulation time 462934612 ps
CPU time 7.23 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:34:50 PM PDT 24
Peak memory 200340 kb
Host smart-4141685f-2d61-4890-8bad-269b9e266173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350745933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3350745933
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2203660472
Short name T87
Test name
Test status
Simulation time 21260191037 ps
CPU time 1672.46 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 700560 kb
Host smart-459f9467-1239-49f4-9af8-d59e43c412ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203660472 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2203660472
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1893330610
Short name T259
Test name
Test status
Simulation time 2548925967 ps
CPU time 130.7 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:36:53 PM PDT 24
Peak memory 200316 kb
Host smart-9a968dd9-51df-4b02-a2b1-be91736d932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893330610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1893330610
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1326081432
Short name T453
Test name
Test status
Simulation time 37130994 ps
CPU time 0.57 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:34:44 PM PDT 24
Peak memory 195844 kb
Host smart-e9becfc3-5de9-40b8-85d4-46d84a578466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326081432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1326081432
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3476659184
Short name T474
Test name
Test status
Simulation time 4223689865 ps
CPU time 26.97 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:35:10 PM PDT 24
Peak memory 200392 kb
Host smart-737ad15b-dd10-4638-a78d-4729449254ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3476659184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3476659184
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.194091536
Short name T207
Test name
Test status
Simulation time 21364398697 ps
CPU time 65.11 seconds
Started Jul 17 06:34:39 PM PDT 24
Finished Jul 17 06:35:45 PM PDT 24
Peak memory 200360 kb
Host smart-6aabea17-8779-4795-82fc-cf6f311b5447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194091536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.194091536
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4248372840
Short name T149
Test name
Test status
Simulation time 6478237269 ps
CPU time 1334.6 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:56:57 PM PDT 24
Peak memory 772096 kb
Host smart-c46f0bca-6f18-4e74-b5e9-33b21db1d11d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248372840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4248372840
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1342440759
Short name T184
Test name
Test status
Simulation time 1378062508 ps
CPU time 25.53 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:35:08 PM PDT 24
Peak memory 200252 kb
Host smart-5a0a5331-d430-429b-b15f-127452f3f10f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342440759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1342440759
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4134971091
Short name T164
Test name
Test status
Simulation time 5165219873 ps
CPU time 63.36 seconds
Started Jul 17 06:34:43 PM PDT 24
Finished Jul 17 06:35:47 PM PDT 24
Peak memory 200336 kb
Host smart-3df22230-4e10-4f02-8429-4eb3b21f7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134971091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4134971091
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3826743286
Short name T135
Test name
Test status
Simulation time 132975072 ps
CPU time 6.5 seconds
Started Jul 17 06:34:40 PM PDT 24
Finished Jul 17 06:34:48 PM PDT 24
Peak memory 200292 kb
Host smart-eedf369a-dab3-4144-b3ed-1154cf9cbf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826743286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3826743286
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2471668616
Short name T443
Test name
Test status
Simulation time 9587146872 ps
CPU time 136.83 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:37:00 PM PDT 24
Peak memory 200376 kb
Host smart-cf9587b5-7e1f-4590-996c-862094184162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471668616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2471668616
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.984267772
Short name T61
Test name
Test status
Simulation time 13986852 ps
CPU time 0.56 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:34:42 PM PDT 24
Peak memory 195992 kb
Host smart-ab279652-3433-43cc-8377-5258dcf233c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984267772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.984267772
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1996845171
Short name T299
Test name
Test status
Simulation time 95902877 ps
CPU time 5.26 seconds
Started Jul 17 06:34:39 PM PDT 24
Finished Jul 17 06:34:46 PM PDT 24
Peak memory 200108 kb
Host smart-336a21bd-3d82-4f57-9d5d-99faf81db741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996845171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1996845171
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.707616787
Short name T464
Test name
Test status
Simulation time 562374813 ps
CPU time 5.35 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:34:49 PM PDT 24
Peak memory 200300 kb
Host smart-4feff174-d358-4ec4-973a-a1c2ab2f8969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707616787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.707616787
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1550073445
Short name T172
Test name
Test status
Simulation time 4435981850 ps
CPU time 880.72 seconds
Started Jul 17 06:34:44 PM PDT 24
Finished Jul 17 06:49:25 PM PDT 24
Peak memory 722440 kb
Host smart-82505679-6676-40fc-940c-cedbd1cb76f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550073445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1550073445
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.200985725
Short name T222
Test name
Test status
Simulation time 13130443013 ps
CPU time 230.49 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:38:34 PM PDT 24
Peak memory 200340 kb
Host smart-aa3bc6a4-527e-403a-9b8e-462345db1fcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200985725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.200985725
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.397354206
Short name T356
Test name
Test status
Simulation time 3320620786 ps
CPU time 182.53 seconds
Started Jul 17 06:34:42 PM PDT 24
Finished Jul 17 06:37:46 PM PDT 24
Peak memory 200432 kb
Host smart-3f94414c-9561-48c0-9136-0d90a2a73501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397354206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.397354206
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3155772830
Short name T213
Test name
Test status
Simulation time 208504583 ps
CPU time 1.57 seconds
Started Jul 17 06:34:39 PM PDT 24
Finished Jul 17 06:34:41 PM PDT 24
Peak memory 200232 kb
Host smart-302986c5-f294-4636-9730-5c3536c1256c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155772830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3155772830
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3387405462
Short name T25
Test name
Test status
Simulation time 17525428751 ps
CPU time 1655.72 seconds
Started Jul 17 06:34:43 PM PDT 24
Finished Jul 17 07:02:20 PM PDT 24
Peak memory 705580 kb
Host smart-c2ecc894-e796-42f9-ba27-d36c5f67e002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387405462 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3387405462
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1930831943
Short name T384
Test name
Test status
Simulation time 28066601564 ps
CPU time 99.02 seconds
Started Jul 17 06:34:41 PM PDT 24
Finished Jul 17 06:36:21 PM PDT 24
Peak memory 200352 kb
Host smart-0b3603ab-8716-46f4-9050-5abc36bc1fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930831943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1930831943
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2582652786
Short name T370
Test name
Test status
Simulation time 34573656 ps
CPU time 0.6 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:34:53 PM PDT 24
Peak memory 196864 kb
Host smart-7c0f8544-28f3-4f33-aadf-f032b9a2ac31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582652786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2582652786
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3598689529
Short name T14
Test name
Test status
Simulation time 626685446 ps
CPU time 37.55 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:35:31 PM PDT 24
Peak memory 200272 kb
Host smart-e6941398-9025-4688-a0cf-c22276f4a1f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598689529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3598689529
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1306267882
Short name T398
Test name
Test status
Simulation time 4608437432 ps
CPU time 40.15 seconds
Started Jul 17 06:34:53 PM PDT 24
Finished Jul 17 06:35:34 PM PDT 24
Peak memory 216764 kb
Host smart-da38eeff-85e2-41c2-bb1f-e2ce5e3c1a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306267882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1306267882
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3279706728
Short name T311
Test name
Test status
Simulation time 8613480042 ps
CPU time 659.51 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:45:52 PM PDT 24
Peak memory 634028 kb
Host smart-48b6f0ad-4126-4853-82ba-bb7e6bb1948d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279706728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3279706728
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2669741967
Short name T386
Test name
Test status
Simulation time 11330892682 ps
CPU time 57.28 seconds
Started Jul 17 06:34:51 PM PDT 24
Finished Jul 17 06:35:49 PM PDT 24
Peak memory 200268 kb
Host smart-b226ae6c-0a43-4bda-bacc-b2b2e2df04ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669741967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2669741967
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1421153457
Short name T176
Test name
Test status
Simulation time 19524390278 ps
CPU time 92.11 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:36:25 PM PDT 24
Peak memory 200580 kb
Host smart-1f2cef8c-d3e6-4f09-8d91-bc3231b933c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421153457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1421153457
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.875682587
Short name T459
Test name
Test status
Simulation time 827883696 ps
CPU time 7.17 seconds
Started Jul 17 06:34:51 PM PDT 24
Finished Jul 17 06:34:59 PM PDT 24
Peak memory 200292 kb
Host smart-307c413f-7408-4fb5-8b07-5e1935467803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875682587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.875682587
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3040894855
Short name T381
Test name
Test status
Simulation time 120707388584 ps
CPU time 1546.02 seconds
Started Jul 17 06:34:54 PM PDT 24
Finished Jul 17 07:00:41 PM PDT 24
Peak memory 719332 kb
Host smart-bf2d90f3-5a7a-4778-9e7d-c61c49a23646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040894855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3040894855
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.917540107
Short name T159
Test name
Test status
Simulation time 977439477 ps
CPU time 39.22 seconds
Started Jul 17 06:34:53 PM PDT 24
Finished Jul 17 06:35:34 PM PDT 24
Peak memory 200296 kb
Host smart-3a533245-f413-41ec-be4c-87b09180984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917540107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.917540107
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2275216572
Short name T415
Test name
Test status
Simulation time 11805153 ps
CPU time 0.54 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:34:54 PM PDT 24
Peak memory 196176 kb
Host smart-0e7588f9-5504-4c2e-98ba-3e9a397e9058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275216572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2275216572
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.232453947
Short name T43
Test name
Test status
Simulation time 155198790 ps
CPU time 9.44 seconds
Started Jul 17 06:34:53 PM PDT 24
Finished Jul 17 06:35:03 PM PDT 24
Peak memory 200276 kb
Host smart-52476681-17ec-482a-9f5a-720457152a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232453947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.232453947
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3761297022
Short name T323
Test name
Test status
Simulation time 1629418289 ps
CPU time 42.38 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:35:35 PM PDT 24
Peak memory 200304 kb
Host smart-f18ccabd-3088-4287-875b-04838063f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761297022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3761297022
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2397741955
Short name T127
Test name
Test status
Simulation time 2482965709 ps
CPU time 215.3 seconds
Started Jul 17 06:34:53 PM PDT 24
Finished Jul 17 06:38:29 PM PDT 24
Peak memory 440320 kb
Host smart-463ec076-dd09-4135-82fe-2b2d13f693af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397741955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2397741955
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3445634566
Short name T316
Test name
Test status
Simulation time 37352691653 ps
CPU time 127.03 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:37:00 PM PDT 24
Peak memory 200332 kb
Host smart-c61c0fb2-95d9-41d0-a5a8-dc77023a46c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445634566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3445634566
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1035665147
Short name T284
Test name
Test status
Simulation time 61715584253 ps
CPU time 167.13 seconds
Started Jul 17 06:34:51 PM PDT 24
Finished Jul 17 06:37:39 PM PDT 24
Peak memory 200344 kb
Host smart-4d973ae2-7218-4a7a-acb5-dbaa8e5807ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035665147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1035665147
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.240507388
Short name T458
Test name
Test status
Simulation time 3491885268 ps
CPU time 11.99 seconds
Started Jul 17 06:34:51 PM PDT 24
Finished Jul 17 06:35:04 PM PDT 24
Peak memory 200368 kb
Host smart-c44d48de-d4d4-4019-8ae6-c9b22062f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240507388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.240507388
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3195243078
Short name T340
Test name
Test status
Simulation time 4784175563 ps
CPU time 72.04 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:36:05 PM PDT 24
Peak memory 200276 kb
Host smart-1a4c1604-3a60-4d6f-b02d-1a9da57cb1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195243078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3195243078
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.995004658
Short name T310
Test name
Test status
Simulation time 14421665 ps
CPU time 0.55 seconds
Started Jul 17 06:35:03 PM PDT 24
Finished Jul 17 06:35:04 PM PDT 24
Peak memory 195084 kb
Host smart-aa78ffa4-81ca-4b2e-89c0-de18aa54d24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995004658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.995004658
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.405577751
Short name T180
Test name
Test status
Simulation time 5564606383 ps
CPU time 88.01 seconds
Started Jul 17 06:34:52 PM PDT 24
Finished Jul 17 06:36:21 PM PDT 24
Peak memory 200348 kb
Host smart-02c70421-d16c-4df0-870f-fca39ff48d85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405577751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.405577751
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1647097493
Short name T293
Test name
Test status
Simulation time 2942963288 ps
CPU time 10.32 seconds
Started Jul 17 06:35:01 PM PDT 24
Finished Jul 17 06:35:12 PM PDT 24
Peak memory 200252 kb
Host smart-33da1a1e-8173-4938-af17-0d293d989991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647097493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1647097493
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.842145964
Short name T270
Test name
Test status
Simulation time 10402749660 ps
CPU time 1183.35 seconds
Started Jul 17 06:35:05 PM PDT 24
Finished Jul 17 06:54:49 PM PDT 24
Peak memory 758872 kb
Host smart-2913de37-66ae-4d8f-ae28-15b0ddba27de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842145964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.842145964
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3324226595
Short name T435
Test name
Test status
Simulation time 14813927088 ps
CPU time 214.87 seconds
Started Jul 17 06:35:01 PM PDT 24
Finished Jul 17 06:38:37 PM PDT 24
Peak memory 200328 kb
Host smart-5ab1b72a-fe2c-4b85-b776-03f2a6ee447d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324226595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3324226595
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.907958875
Short name T479
Test name
Test status
Simulation time 18738453234 ps
CPU time 161.15 seconds
Started Jul 17 06:34:55 PM PDT 24
Finished Jul 17 06:37:37 PM PDT 24
Peak memory 200368 kb
Host smart-e674dc58-dbde-43b8-9b9c-3a4037ca1e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907958875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.907958875
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1810374691
Short name T481
Test name
Test status
Simulation time 78565629 ps
CPU time 1.97 seconds
Started Jul 17 06:34:54 PM PDT 24
Finished Jul 17 06:34:57 PM PDT 24
Peak memory 200300 kb
Host smart-423c7a1f-e149-43d5-bb4f-31cc0387485f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810374691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1810374691
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2622320297
Short name T361
Test name
Test status
Simulation time 26869345061 ps
CPU time 154.32 seconds
Started Jul 17 06:35:01 PM PDT 24
Finished Jul 17 06:37:36 PM PDT 24
Peak memory 216708 kb
Host smart-659f3012-5eb3-413d-9908-facdba2269e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622320297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2622320297
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1749621660
Short name T254
Test name
Test status
Simulation time 22692051299 ps
CPU time 113.48 seconds
Started Jul 17 06:35:04 PM PDT 24
Finished Jul 17 06:36:58 PM PDT 24
Peak memory 200400 kb
Host smart-0429d6e1-ae02-49de-811b-d1f0bb07be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749621660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1749621660
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2736743479
Short name T264
Test name
Test status
Simulation time 38821362 ps
CPU time 0.57 seconds
Started Jul 17 06:35:16 PM PDT 24
Finished Jul 17 06:35:17 PM PDT 24
Peak memory 195152 kb
Host smart-387b6bb5-e238-48ce-bb14-727b30fff9a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736743479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2736743479
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2679282626
Short name T366
Test name
Test status
Simulation time 1566902875 ps
CPU time 9.3 seconds
Started Jul 17 06:35:13 PM PDT 24
Finished Jul 17 06:35:23 PM PDT 24
Peak memory 200308 kb
Host smart-309b2b0c-f51c-4c4d-823c-926f2c10b6ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679282626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2679282626
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1306868423
Short name T128
Test name
Test status
Simulation time 6677111488 ps
CPU time 33.47 seconds
Started Jul 17 06:35:14 PM PDT 24
Finished Jul 17 06:35:48 PM PDT 24
Peak memory 200404 kb
Host smart-37521ec9-5688-49a8-a2d5-79d2e263a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306868423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1306868423
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.505156692
Short name T441
Test name
Test status
Simulation time 8895303834 ps
CPU time 380.76 seconds
Started Jul 17 06:35:14 PM PDT 24
Finished Jul 17 06:41:35 PM PDT 24
Peak memory 510104 kb
Host smart-25dfe095-11c6-4e86-bc8a-6e8b94ab21dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505156692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.505156692
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1087557078
Short name T405
Test name
Test status
Simulation time 8413556558 ps
CPU time 157.43 seconds
Started Jul 17 06:37:59 PM PDT 24
Finished Jul 17 06:40:37 PM PDT 24
Peak memory 200252 kb
Host smart-05259156-b86d-4941-9649-0d369e90ac9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087557078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1087557078
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3581552851
Short name T144
Test name
Test status
Simulation time 45322356142 ps
CPU time 150.04 seconds
Started Jul 17 06:35:14 PM PDT 24
Finished Jul 17 06:37:44 PM PDT 24
Peak memory 200380 kb
Host smart-342369b5-0a46-4f66-95c8-4c8bb035544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581552851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3581552851
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2601869876
Short name T152
Test name
Test status
Simulation time 789012477 ps
CPU time 14.68 seconds
Started Jul 17 06:35:02 PM PDT 24
Finished Jul 17 06:35:18 PM PDT 24
Peak memory 200260 kb
Host smart-37e6a5cc-42f9-410a-8531-ad3b9fe6f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601869876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2601869876
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2745470814
Short name T47
Test name
Test status
Simulation time 19245707343 ps
CPU time 803.23 seconds
Started Jul 17 06:35:15 PM PDT 24
Finished Jul 17 06:48:39 PM PDT 24
Peak memory 716340 kb
Host smart-9810dd5c-026d-4372-8a7a-b00c930527c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745470814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2745470814
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.157364656
Short name T510
Test name
Test status
Simulation time 8531483298 ps
CPU time 90.1 seconds
Started Jul 17 06:35:14 PM PDT 24
Finished Jul 17 06:36:45 PM PDT 24
Peak memory 200376 kb
Host smart-8c72adc7-806e-42d6-a0c8-cb04607a79b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157364656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.157364656
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1713804048
Short name T491
Test name
Test status
Simulation time 13149885 ps
CPU time 0.58 seconds
Started Jul 17 06:35:28 PM PDT 24
Finished Jul 17 06:35:29 PM PDT 24
Peak memory 196200 kb
Host smart-11a061dc-1666-491c-8db1-2ee227cc354a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713804048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1713804048
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.227964037
Short name T200
Test name
Test status
Simulation time 1695168375 ps
CPU time 97.69 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:37:03 PM PDT 24
Peak memory 200352 kb
Host smart-4f753ebd-3c18-4ec5-8840-4f29bb65d640
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227964037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.227964037
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3367455183
Short name T355
Test name
Test status
Simulation time 1290143589 ps
CPU time 35.46 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:36:01 PM PDT 24
Peak memory 200256 kb
Host smart-5f7e8d68-d88e-4619-b249-9d4e49595f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367455183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3367455183
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1455437508
Short name T224
Test name
Test status
Simulation time 4320180200 ps
CPU time 862.53 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:49:48 PM PDT 24
Peak memory 738192 kb
Host smart-4c89225c-1f52-430e-add6-308ddc8d31cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455437508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1455437508
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3227966165
Short name T420
Test name
Test status
Simulation time 8221141978 ps
CPU time 123.21 seconds
Started Jul 17 06:35:26 PM PDT 24
Finished Jul 17 06:37:30 PM PDT 24
Peak memory 200352 kb
Host smart-6324ee00-546e-4279-8368-9991db204734
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227966165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3227966165
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.638497404
Short name T240
Test name
Test status
Simulation time 10722251171 ps
CPU time 142.79 seconds
Started Jul 17 06:35:24 PM PDT 24
Finished Jul 17 06:37:48 PM PDT 24
Peak memory 200356 kb
Host smart-7e8d1019-178b-44af-a8fe-1ff552538399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638497404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.638497404
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3774044043
Short name T242
Test name
Test status
Simulation time 97620108 ps
CPU time 2.03 seconds
Started Jul 17 06:35:14 PM PDT 24
Finished Jul 17 06:35:17 PM PDT 24
Peak memory 200228 kb
Host smart-ce2e9c12-1afe-48cc-a4b3-0eecc4f2319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774044043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3774044043
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1624246194
Short name T286
Test name
Test status
Simulation time 76796158799 ps
CPU time 920.93 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:50:47 PM PDT 24
Peak memory 200328 kb
Host smart-a4e01488-bfef-4fed-a793-13416327f8c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624246194 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1624246194
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4078571002
Short name T290
Test name
Test status
Simulation time 76759119212 ps
CPU time 92.93 seconds
Started Jul 17 06:35:23 PM PDT 24
Finished Jul 17 06:36:56 PM PDT 24
Peak memory 200364 kb
Host smart-8abcab9e-20f3-49f7-bed6-300d8b234c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078571002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4078571002
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.348527840
Short name T16
Test name
Test status
Simulation time 24663069 ps
CPU time 0.59 seconds
Started Jul 17 06:31:02 PM PDT 24
Finished Jul 17 06:31:03 PM PDT 24
Peak memory 195844 kb
Host smart-769e3f90-7b6d-439e-a8dc-b8781e11d223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348527840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.348527840
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1329852320
Short name T198
Test name
Test status
Simulation time 469807791 ps
CPU time 28.55 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:31:17 PM PDT 24
Peak memory 200332 kb
Host smart-fb3f7b37-5d29-4c3c-94d2-d3a2c8284931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329852320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1329852320
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.571923806
Short name T168
Test name
Test status
Simulation time 594981479 ps
CPU time 7.9 seconds
Started Jul 17 06:30:46 PM PDT 24
Finished Jul 17 06:30:55 PM PDT 24
Peak memory 200340 kb
Host smart-a7df4a6b-bb3a-40bf-8fd9-710151a50054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571923806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.571923806
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1155167969
Short name T496
Test name
Test status
Simulation time 4933957416 ps
CPU time 1064.9 seconds
Started Jul 17 06:30:48 PM PDT 24
Finished Jul 17 06:48:34 PM PDT 24
Peak memory 741856 kb
Host smart-6ec01727-0161-48bf-b76f-62a71dcbd16a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155167969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1155167969
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3565442079
Short name T229
Test name
Test status
Simulation time 7601627469 ps
CPU time 51.36 seconds
Started Jul 17 06:30:48 PM PDT 24
Finished Jul 17 06:31:40 PM PDT 24
Peak memory 200256 kb
Host smart-544d8298-a2f8-4680-9542-60308814a535
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565442079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3565442079
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3986225530
Short name T511
Test name
Test status
Simulation time 9489019232 ps
CPU time 138.36 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:33:06 PM PDT 24
Peak memory 208564 kb
Host smart-0d3c0b2c-fe90-4a9a-bead-a21466c8ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986225530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3986225530
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2374317330
Short name T49
Test name
Test status
Simulation time 75663193 ps
CPU time 0.99 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:31:02 PM PDT 24
Peak memory 219348 kb
Host smart-7a263884-61c2-46b8-b2ef-4b3b465ca39e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374317330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2374317330
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2565584735
Short name T165
Test name
Test status
Simulation time 135432413 ps
CPU time 3.38 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:30:51 PM PDT 24
Peak memory 200352 kb
Host smart-1d642954-66df-4f3b-909a-29eb0726a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565584735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2565584735
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1562125379
Short name T333
Test name
Test status
Simulation time 17850082705 ps
CPU time 118.19 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:32:59 PM PDT 24
Peak memory 208620 kb
Host smart-8443c5af-b24a-4297-9baf-6f2838113023
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562125379 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1562125379
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3381781738
Short name T65
Test name
Test status
Simulation time 28257930767 ps
CPU time 363.69 seconds
Started Jul 17 06:31:02 PM PDT 24
Finished Jul 17 06:37:06 PM PDT 24
Peak memory 452888 kb
Host smart-8d91cb4d-87b5-4ecb-97d7-6a73098fe0ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381781738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3381781738
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.65291290
Short name T236
Test name
Test status
Simulation time 30109061209 ps
CPU time 46.47 seconds
Started Jul 17 06:30:46 PM PDT 24
Finished Jul 17 06:31:33 PM PDT 24
Peak memory 200348 kb
Host smart-49418441-2029-496d-a7b5-f61401f725c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=65291290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.65291290
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2512846322
Short name T269
Test name
Test status
Simulation time 5543839773 ps
CPU time 70.22 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:31:58 PM PDT 24
Peak memory 200408 kb
Host smart-6f3abd6b-8736-4abf-a6ec-e61c658271e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2512846322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2512846322
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.4036927727
Short name T307
Test name
Test status
Simulation time 4700022905 ps
CPU time 82.82 seconds
Started Jul 17 06:30:48 PM PDT 24
Finished Jul 17 06:32:12 PM PDT 24
Peak memory 200276 kb
Host smart-34dd3ef7-5348-45bf-bf02-69c0a36d35ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4036927727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.4036927727
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2378930027
Short name T449
Test name
Test status
Simulation time 56495680761 ps
CPU time 679.69 seconds
Started Jul 17 06:30:46 PM PDT 24
Finished Jul 17 06:42:07 PM PDT 24
Peak memory 200292 kb
Host smart-5385bd4c-52ef-420b-836c-a7da67905623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2378930027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2378930027
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1189754471
Short name T10
Test name
Test status
Simulation time 49087272377 ps
CPU time 2087.43 seconds
Started Jul 17 06:30:59 PM PDT 24
Finished Jul 17 07:05:47 PM PDT 24
Peak memory 216016 kb
Host smart-9a3da55f-b8b3-4236-97b9-db440ffdd93a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1189754471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1189754471
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2128259481
Short name T403
Test name
Test status
Simulation time 274909105895 ps
CPU time 2452.7 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 07:11:41 PM PDT 24
Peak memory 215828 kb
Host smart-e5c4680b-660a-49d8-80c3-f9c9aed33541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2128259481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2128259481
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1216802141
Short name T217
Test name
Test status
Simulation time 1239431640 ps
CPU time 17.9 seconds
Started Jul 17 06:30:47 PM PDT 24
Finished Jul 17 06:31:05 PM PDT 24
Peak memory 200288 kb
Host smart-1f3bb973-1476-448d-9534-faa50ced39d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216802141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1216802141
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2026965585
Short name T520
Test name
Test status
Simulation time 60387255 ps
CPU time 0.58 seconds
Started Jul 17 06:35:27 PM PDT 24
Finished Jul 17 06:35:28 PM PDT 24
Peak memory 195840 kb
Host smart-73e5b318-1b75-47f9-af9f-6519cef72438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026965585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2026965585
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.650785999
Short name T262
Test name
Test status
Simulation time 254272589 ps
CPU time 7.99 seconds
Started Jul 17 06:35:24 PM PDT 24
Finished Jul 17 06:35:32 PM PDT 24
Peak memory 200440 kb
Host smart-b4bea142-9354-40f6-b746-6399aca64124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650785999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.650785999
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1834484517
Short name T413
Test name
Test status
Simulation time 2479562248 ps
CPU time 45.23 seconds
Started Jul 17 06:35:27 PM PDT 24
Finished Jul 17 06:36:13 PM PDT 24
Peak memory 200360 kb
Host smart-80d6c250-adca-473c-a842-a578f7b087c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834484517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1834484517
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3454722420
Short name T493
Test name
Test status
Simulation time 3036253498 ps
CPU time 131.4 seconds
Started Jul 17 06:35:27 PM PDT 24
Finished Jul 17 06:37:39 PM PDT 24
Peak memory 565808 kb
Host smart-5e72535c-2140-4099-bd9f-ec2f9bb7b932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454722420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3454722420
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.334685687
Short name T223
Test name
Test status
Simulation time 9839530573 ps
CPU time 138.23 seconds
Started Jul 17 06:35:24 PM PDT 24
Finished Jul 17 06:37:43 PM PDT 24
Peak memory 200188 kb
Host smart-c26c40f2-cf59-4c28-978f-338025201704
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334685687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.334685687
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3346305842
Short name T358
Test name
Test status
Simulation time 56549701721 ps
CPU time 237.87 seconds
Started Jul 17 06:35:24 PM PDT 24
Finished Jul 17 06:39:23 PM PDT 24
Peak memory 200556 kb
Host smart-c82f6098-4056-4450-af17-d6b824ef0f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346305842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3346305842
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.549990079
Short name T313
Test name
Test status
Simulation time 842511314 ps
CPU time 4.34 seconds
Started Jul 17 06:35:27 PM PDT 24
Finished Jul 17 06:35:32 PM PDT 24
Peak memory 200208 kb
Host smart-4b7fbfe5-82c5-4be6-90b0-bc5821364e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549990079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.549990079
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1649881955
Short name T84
Test name
Test status
Simulation time 46355021862 ps
CPU time 496.44 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:43:42 PM PDT 24
Peak memory 200356 kb
Host smart-6a3c4db7-bb26-44d0-ba8e-d8a4af4c246d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649881955 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1649881955
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2538324666
Short name T483
Test name
Test status
Simulation time 89971447247 ps
CPU time 89.84 seconds
Started Jul 17 06:35:24 PM PDT 24
Finished Jul 17 06:36:54 PM PDT 24
Peak memory 200420 kb
Host smart-4e8cbfe8-7698-4666-b483-0d3e3a16045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538324666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2538324666
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.4223485993
Short name T197
Test name
Test status
Simulation time 10874590 ps
CPU time 0.55 seconds
Started Jul 17 06:35:35 PM PDT 24
Finished Jul 17 06:35:36 PM PDT 24
Peak memory 195084 kb
Host smart-a0ae5424-d3b2-471a-9ef7-c352b0620d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223485993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.4223485993
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1927036820
Short name T250
Test name
Test status
Simulation time 1087138744 ps
CPU time 66.49 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:36:32 PM PDT 24
Peak memory 200216 kb
Host smart-9b7b8339-6c22-4b32-b715-1128688e3058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927036820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1927036820
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.580542926
Short name T5
Test name
Test status
Simulation time 9616915337 ps
CPU time 30.86 seconds
Started Jul 17 06:35:37 PM PDT 24
Finished Jul 17 06:36:08 PM PDT 24
Peak memory 216736 kb
Host smart-1277fddd-6869-4bc4-9ad5-4f74455fdf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580542926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.580542926
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.185800881
Short name T138
Test name
Test status
Simulation time 3270891399 ps
CPU time 553.02 seconds
Started Jul 17 06:35:36 PM PDT 24
Finished Jul 17 06:44:50 PM PDT 24
Peak memory 514528 kb
Host smart-1988a9d1-b023-46ff-aa78-920298bc2a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185800881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.185800881
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3829283812
Short name T498
Test name
Test status
Simulation time 8295148268 ps
CPU time 117.79 seconds
Started Jul 17 06:35:38 PM PDT 24
Finished Jul 17 06:37:37 PM PDT 24
Peak memory 200316 kb
Host smart-9413d2b4-a2f8-4853-b637-fe22d0f073d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829283812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3829283812
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4041705812
Short name T404
Test name
Test status
Simulation time 7679825895 ps
CPU time 114.62 seconds
Started Jul 17 06:35:25 PM PDT 24
Finished Jul 17 06:37:21 PM PDT 24
Peak memory 200268 kb
Host smart-49ebe968-dcba-430c-92af-8d609d6e9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041705812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4041705812
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1362506900
Short name T77
Test name
Test status
Simulation time 158674362 ps
CPU time 3.22 seconds
Started Jul 17 06:35:29 PM PDT 24
Finished Jul 17 06:35:32 PM PDT 24
Peak memory 200288 kb
Host smart-a1054bef-72a0-427a-bbee-bf7e3534d3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362506900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1362506900
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3764077949
Short name T442
Test name
Test status
Simulation time 8921812307 ps
CPU time 536.25 seconds
Started Jul 17 06:35:41 PM PDT 24
Finished Jul 17 06:44:38 PM PDT 24
Peak memory 465304 kb
Host smart-ecaa6f7f-ec4f-4751-83e8-7718317dc258
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764077949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3764077949
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2277566477
Short name T469
Test name
Test status
Simulation time 7442326251 ps
CPU time 97.82 seconds
Started Jul 17 06:35:41 PM PDT 24
Finished Jul 17 06:37:20 PM PDT 24
Peak memory 200276 kb
Host smart-182fdaa5-82bb-42c8-8d15-7eb791a05987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277566477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2277566477
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3727871914
Short name T470
Test name
Test status
Simulation time 13781578 ps
CPU time 0.6 seconds
Started Jul 17 06:35:37 PM PDT 24
Finished Jul 17 06:35:38 PM PDT 24
Peak memory 195164 kb
Host smart-994fa0b1-162a-4f0e-8123-1f227c6152c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727871914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3727871914
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2752916546
Short name T27
Test name
Test status
Simulation time 1388774802 ps
CPU time 40.4 seconds
Started Jul 17 06:35:38 PM PDT 24
Finished Jul 17 06:36:19 PM PDT 24
Peak memory 200212 kb
Host smart-bb7637bf-52f7-4564-a713-9b90db58321e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752916546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2752916546
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.353083697
Short name T359
Test name
Test status
Simulation time 1384002103 ps
CPU time 5.85 seconds
Started Jul 17 06:35:41 PM PDT 24
Finished Jul 17 06:35:47 PM PDT 24
Peak memory 200216 kb
Host smart-0af7a405-c0d7-4f64-a040-9e5ad1e3d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353083697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.353083697
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2320608788
Short name T508
Test name
Test status
Simulation time 152757126 ps
CPU time 13.65 seconds
Started Jul 17 06:35:38 PM PDT 24
Finished Jul 17 06:35:53 PM PDT 24
Peak memory 227692 kb
Host smart-a1e5f3e6-2421-4ba1-8a12-c94eb68fd1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320608788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2320608788
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3667201897
Short name T334
Test name
Test status
Simulation time 1677203054 ps
CPU time 46.96 seconds
Started Jul 17 06:35:41 PM PDT 24
Finished Jul 17 06:36:28 PM PDT 24
Peak memory 200192 kb
Host smart-8cf51d14-930f-4388-a376-19bab508d589
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667201897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3667201897
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2775620306
Short name T150
Test name
Test status
Simulation time 11261225171 ps
CPU time 197.36 seconds
Started Jul 17 06:35:38 PM PDT 24
Finished Jul 17 06:38:56 PM PDT 24
Peak memory 200416 kb
Host smart-83d63d58-04b6-4f35-a544-ca47ad7ff329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775620306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2775620306
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2417528610
Short name T439
Test name
Test status
Simulation time 589000937 ps
CPU time 9.5 seconds
Started Jul 17 06:35:38 PM PDT 24
Finished Jul 17 06:35:48 PM PDT 24
Peak memory 200232 kb
Host smart-c1276b1c-8026-44bb-8b52-c78af2fa3700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417528610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2417528610
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2506011255
Short name T190
Test name
Test status
Simulation time 14626610321 ps
CPU time 190.17 seconds
Started Jul 17 06:35:37 PM PDT 24
Finished Jul 17 06:38:48 PM PDT 24
Peak memory 200656 kb
Host smart-cbaa067f-3ce1-4bf0-8a6d-231528eed037
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506011255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2506011255
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.45568865
Short name T81
Test name
Test status
Simulation time 4912440401 ps
CPU time 115.99 seconds
Started Jul 17 06:35:36 PM PDT 24
Finished Jul 17 06:37:33 PM PDT 24
Peak memory 200372 kb
Host smart-f80a8a57-cc79-4412-8fec-e2f1df52b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45568865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.45568865
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3596490206
Short name T183
Test name
Test status
Simulation time 44996321 ps
CPU time 0.56 seconds
Started Jul 17 06:35:56 PM PDT 24
Finished Jul 17 06:35:58 PM PDT 24
Peak memory 195152 kb
Host smart-0b84e416-df18-4026-a1d9-6a99def72a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596490206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3596490206
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3928912117
Short name T238
Test name
Test status
Simulation time 5303079029 ps
CPU time 82.46 seconds
Started Jul 17 06:35:48 PM PDT 24
Finished Jul 17 06:37:11 PM PDT 24
Peak memory 200416 kb
Host smart-fd25b46c-9048-4286-a6db-9041c303f916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928912117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3928912117
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1375431600
Short name T155
Test name
Test status
Simulation time 5119686020 ps
CPU time 60.27 seconds
Started Jul 17 06:35:47 PM PDT 24
Finished Jul 17 06:36:48 PM PDT 24
Peak memory 200368 kb
Host smart-62ef85a7-883a-489e-8097-43819e1b7d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375431600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1375431600
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4251119750
Short name T151
Test name
Test status
Simulation time 13546246848 ps
CPU time 471.8 seconds
Started Jul 17 06:35:47 PM PDT 24
Finished Jul 17 06:43:40 PM PDT 24
Peak memory 479532 kb
Host smart-baa492f8-2035-44d9-8fb6-4be3ca55c0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251119750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4251119750
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.993797599
Short name T468
Test name
Test status
Simulation time 9374625742 ps
CPU time 94.5 seconds
Started Jul 17 06:35:48 PM PDT 24
Finished Jul 17 06:37:23 PM PDT 24
Peak memory 200316 kb
Host smart-d711d543-1c1b-43ea-bc5c-23e76d1c3af3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993797599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.993797599
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1842669332
Short name T281
Test name
Test status
Simulation time 51687726815 ps
CPU time 131.2 seconds
Started Jul 17 06:35:35 PM PDT 24
Finished Jul 17 06:37:47 PM PDT 24
Peak memory 216816 kb
Host smart-99280a4a-1f7d-4afc-90a0-1ac72f835201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842669332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1842669332
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1047954035
Short name T227
Test name
Test status
Simulation time 3281115631 ps
CPU time 8.83 seconds
Started Jul 17 06:35:36 PM PDT 24
Finished Jul 17 06:35:46 PM PDT 24
Peak memory 200356 kb
Host smart-2695808b-074b-4114-8692-ff7d01e93386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047954035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1047954035
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3803157406
Short name T400
Test name
Test status
Simulation time 40515149231 ps
CPU time 2234.54 seconds
Started Jul 17 06:35:56 PM PDT 24
Finished Jul 17 07:13:12 PM PDT 24
Peak memory 776636 kb
Host smart-a731ebcc-a489-4493-94ea-b4345306fc78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803157406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3803157406
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.258097578
Short name T326
Test name
Test status
Simulation time 10940938329 ps
CPU time 51.4 seconds
Started Jul 17 06:35:47 PM PDT 24
Finished Jul 17 06:36:39 PM PDT 24
Peak memory 200344 kb
Host smart-87039c7d-b46b-4bc6-9e46-f5779006c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258097578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.258097578
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.954790313
Short name T394
Test name
Test status
Simulation time 60050365 ps
CPU time 0.57 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:36:00 PM PDT 24
Peak memory 196852 kb
Host smart-36ec3bbd-ad1a-4a12-9c0c-fb32f34cacbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954790313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.954790313
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2771401032
Short name T280
Test name
Test status
Simulation time 329151056 ps
CPU time 20.23 seconds
Started Jul 17 06:35:45 PM PDT 24
Finished Jul 17 06:36:06 PM PDT 24
Peak memory 200264 kb
Host smart-901196e5-7c82-4fdd-973a-2b338d1679bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771401032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2771401032
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2894023823
Short name T76
Test name
Test status
Simulation time 1025921511 ps
CPU time 20.27 seconds
Started Jul 17 06:35:56 PM PDT 24
Finished Jul 17 06:36:17 PM PDT 24
Peak memory 200340 kb
Host smart-a67c87fa-8108-4527-b8da-d57158ad4d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894023823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2894023823
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3089964296
Short name T247
Test name
Test status
Simulation time 3178268443 ps
CPU time 263.09 seconds
Started Jul 17 06:35:55 PM PDT 24
Finished Jul 17 06:40:19 PM PDT 24
Peak memory 620980 kb
Host smart-6a5dba53-74d3-404f-be55-5b36df7de531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089964296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3089964296
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2085627381
Short name T40
Test name
Test status
Simulation time 6177903303 ps
CPU time 77.9 seconds
Started Jul 17 06:35:56 PM PDT 24
Finished Jul 17 06:37:15 PM PDT 24
Peak memory 200336 kb
Host smart-2b813084-e0ca-41a0-bec2-e05b9e721beb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085627381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2085627381
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1752684793
Short name T329
Test name
Test status
Simulation time 1619731146 ps
CPU time 52.05 seconds
Started Jul 17 06:35:45 PM PDT 24
Finished Jul 17 06:36:38 PM PDT 24
Peak memory 200224 kb
Host smart-cdf4512a-53a7-431f-aabd-d90b23e7d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752684793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1752684793
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3304262924
Short name T337
Test name
Test status
Simulation time 5790151202 ps
CPU time 8.49 seconds
Started Jul 17 06:35:56 PM PDT 24
Finished Jul 17 06:36:05 PM PDT 24
Peak memory 200360 kb
Host smart-f0da9dbf-fd5a-4552-b227-b2a264fadfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304262924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3304262924
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1349944680
Short name T126
Test name
Test status
Simulation time 18433202278 ps
CPU time 332.77 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:41:32 PM PDT 24
Peak memory 216708 kb
Host smart-080b9b92-510e-4843-b0d8-f9d739f16767
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349944680 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1349944680
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3901722210
Short name T371
Test name
Test status
Simulation time 16870749 ps
CPU time 0.89 seconds
Started Jul 17 06:36:00 PM PDT 24
Finished Jul 17 06:36:01 PM PDT 24
Peak memory 199396 kb
Host smart-b33ac844-aa6e-4961-a5e6-b49d1520d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901722210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3901722210
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3636580177
Short name T80
Test name
Test status
Simulation time 45482812 ps
CPU time 0.58 seconds
Started Jul 17 06:35:57 PM PDT 24
Finished Jul 17 06:35:58 PM PDT 24
Peak memory 195084 kb
Host smart-c4d59e40-6f5a-4e22-b295-60513a6643d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636580177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3636580177
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.845195488
Short name T194
Test name
Test status
Simulation time 2721627657 ps
CPU time 45.5 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:36:45 PM PDT 24
Peak memory 200288 kb
Host smart-ecc9fac6-2612-4fbe-9d58-210fd76cb10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845195488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.845195488
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.116410315
Short name T445
Test name
Test status
Simulation time 67300077 ps
CPU time 3.76 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:36:04 PM PDT 24
Peak memory 200276 kb
Host smart-926258e0-2f6c-4f40-b225-2b8817e95ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116410315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.116410315
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2809724817
Short name T185
Test name
Test status
Simulation time 13428448265 ps
CPU time 213.81 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:39:34 PM PDT 24
Peak memory 638280 kb
Host smart-13d08dd2-00dc-44d5-8df7-b6b5f2dbc74c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809724817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2809724817
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1777324510
Short name T357
Test name
Test status
Simulation time 2330874893 ps
CPU time 15.88 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:36:16 PM PDT 24
Peak memory 200296 kb
Host smart-f6cfe50d-a791-495a-bc04-562480bc7b26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777324510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1777324510
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1544263678
Short name T497
Test name
Test status
Simulation time 58033676336 ps
CPU time 212.26 seconds
Started Jul 17 06:35:59 PM PDT 24
Finished Jul 17 06:39:32 PM PDT 24
Peak memory 200372 kb
Host smart-09692f04-4c66-4d80-8584-1a29c36d1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544263678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1544263678
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.152011182
Short name T145
Test name
Test status
Simulation time 878200888 ps
CPU time 13.08 seconds
Started Jul 17 06:35:57 PM PDT 24
Finished Jul 17 06:36:11 PM PDT 24
Peak memory 200184 kb
Host smart-73fdee23-0029-47f6-8131-b603c0a7aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152011182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.152011182
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2853567297
Short name T327
Test name
Test status
Simulation time 308580349997 ps
CPU time 203.34 seconds
Started Jul 17 06:36:02 PM PDT 24
Finished Jul 17 06:39:25 PM PDT 24
Peak memory 208552 kb
Host smart-2183014c-30fa-400c-b94b-9975cfb6d9d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853567297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2853567297
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3256827453
Short name T476
Test name
Test status
Simulation time 12131232255 ps
CPU time 11.6 seconds
Started Jul 17 06:35:58 PM PDT 24
Finished Jul 17 06:36:10 PM PDT 24
Peak memory 200356 kb
Host smart-58f890ee-3a5b-4b0a-af07-8a662ad149d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256827453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3256827453
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3956161982
Short name T297
Test name
Test status
Simulation time 13433960 ps
CPU time 0.61 seconds
Started Jul 17 06:36:11 PM PDT 24
Finished Jul 17 06:36:12 PM PDT 24
Peak memory 196080 kb
Host smart-b1cdd909-15ab-4663-a1ea-55e7a91d336c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956161982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3956161982
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.614483277
Short name T506
Test name
Test status
Simulation time 2779500511 ps
CPU time 40.86 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 06:36:52 PM PDT 24
Peak memory 200336 kb
Host smart-59b2ef7b-5839-4272-99a8-9c4a4b93fec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614483277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.614483277
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.861837366
Short name T341
Test name
Test status
Simulation time 615895944 ps
CPU time 12.18 seconds
Started Jul 17 06:36:12 PM PDT 24
Finished Jul 17 06:36:25 PM PDT 24
Peak memory 200292 kb
Host smart-4dde2dba-2e1f-43db-a6b7-24b1ad64e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861837366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.861837366
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.706221165
Short name T317
Test name
Test status
Simulation time 3656018633 ps
CPU time 550.72 seconds
Started Jul 17 06:36:11 PM PDT 24
Finished Jul 17 06:45:23 PM PDT 24
Peak memory 518132 kb
Host smart-2a27aaf2-b14c-4bdf-9684-5a1cb189ed62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706221165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.706221165
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1829319047
Short name T192
Test name
Test status
Simulation time 3972425828 ps
CPU time 223.07 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 06:39:54 PM PDT 24
Peak memory 200352 kb
Host smart-84b60f4e-0f30-416c-8dac-5aebb19ce369
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829319047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1829319047
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3941304079
Short name T436
Test name
Test status
Simulation time 916496486 ps
CPU time 13.94 seconds
Started Jul 17 06:35:58 PM PDT 24
Finished Jul 17 06:36:13 PM PDT 24
Peak memory 200280 kb
Host smart-36f58c53-aa62-4d74-b896-4cdb583609a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941304079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3941304079
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2602410706
Short name T256
Test name
Test status
Simulation time 4495875018 ps
CPU time 13.05 seconds
Started Jul 17 06:36:00 PM PDT 24
Finished Jul 17 06:36:13 PM PDT 24
Peak memory 200276 kb
Host smart-46b21464-6c4e-4c93-8069-f33c09b0135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602410706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2602410706
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2316600406
Short name T455
Test name
Test status
Simulation time 109392661731 ps
CPU time 2261.66 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 07:13:53 PM PDT 24
Peak memory 737024 kb
Host smart-537e4e6d-0a8a-4d0e-8546-da1f2e8b5272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316600406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2316600406
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2752112062
Short name T59
Test name
Test status
Simulation time 20209933378 ps
CPU time 65.25 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 06:37:17 PM PDT 24
Peak memory 200356 kb
Host smart-7857e46f-1d7f-4a4c-9623-18ee37c2745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752112062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2752112062
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3060647225
Short name T346
Test name
Test status
Simulation time 23656709 ps
CPU time 0.62 seconds
Started Jul 17 06:36:23 PM PDT 24
Finished Jul 17 06:36:24 PM PDT 24
Peak memory 195840 kb
Host smart-72c3d70b-45f8-4f1b-ac49-d7b6e23fc469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060647225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3060647225
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1701412174
Short name T142
Test name
Test status
Simulation time 745698428 ps
CPU time 42.41 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 06:36:53 PM PDT 24
Peak memory 200268 kb
Host smart-1ae38c69-200e-42b5-b0bc-0dfa5c3030c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701412174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1701412174
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3507009000
Short name T175
Test name
Test status
Simulation time 332827922 ps
CPU time 17.67 seconds
Started Jul 17 06:36:09 PM PDT 24
Finished Jul 17 06:36:28 PM PDT 24
Peak memory 200336 kb
Host smart-566a3ad6-4d49-46fb-83a0-e265c22fccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507009000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3507009000
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2663806327
Short name T246
Test name
Test status
Simulation time 4704174885 ps
CPU time 813.75 seconds
Started Jul 17 06:36:11 PM PDT 24
Finished Jul 17 06:49:46 PM PDT 24
Peak memory 521620 kb
Host smart-2fa539ba-2e89-438e-9350-d7a59b83ca29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663806327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2663806327
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4041089208
Short name T241
Test name
Test status
Simulation time 2020423052 ps
CPU time 21.42 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 06:36:32 PM PDT 24
Peak memory 200224 kb
Host smart-142dd12a-3ba2-4bd1-b5be-8841a960ccad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041089208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4041089208
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.671727568
Short name T202
Test name
Test status
Simulation time 16379699461 ps
CPU time 58.99 seconds
Started Jul 17 06:36:09 PM PDT 24
Finished Jul 17 06:37:09 PM PDT 24
Peak memory 200308 kb
Host smart-e7e0995a-1ea8-4b3a-8135-b9aab32f86ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671727568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.671727568
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3421863013
Short name T393
Test name
Test status
Simulation time 128314788 ps
CPU time 5.6 seconds
Started Jul 17 06:36:10 PM PDT 24
Finished Jul 17 06:36:17 PM PDT 24
Peak memory 200316 kb
Host smart-c725d97c-8a61-491e-bfb3-0b9aa0d1c4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421863013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3421863013
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2084238062
Short name T512
Test name
Test status
Simulation time 32545030086 ps
CPU time 1220.89 seconds
Started Jul 17 06:36:22 PM PDT 24
Finished Jul 17 06:56:43 PM PDT 24
Peak memory 734312 kb
Host smart-67e10ea5-9811-462d-952f-a3cab15ca981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084238062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2084238062
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2486218274
Short name T363
Test name
Test status
Simulation time 6963014158 ps
CPU time 60.12 seconds
Started Jul 17 06:36:25 PM PDT 24
Finished Jul 17 06:37:26 PM PDT 24
Peak memory 200392 kb
Host smart-25799219-e992-426f-b6a4-ac7a82619891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486218274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2486218274
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.964725562
Short name T514
Test name
Test status
Simulation time 15924739 ps
CPU time 0.6 seconds
Started Jul 17 06:36:22 PM PDT 24
Finished Jul 17 06:36:23 PM PDT 24
Peak memory 196200 kb
Host smart-48a6c677-1bb9-4c82-86df-aa039e69dfd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964725562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.964725562
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2282825688
Short name T136
Test name
Test status
Simulation time 2396202974 ps
CPU time 75.96 seconds
Started Jul 17 06:36:22 PM PDT 24
Finished Jul 17 06:37:38 PM PDT 24
Peak memory 200336 kb
Host smart-8fb770c4-fd79-4d62-ba42-517488a0ff96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282825688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2282825688
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3467016474
Short name T369
Test name
Test status
Simulation time 66046719 ps
CPU time 3.41 seconds
Started Jul 17 06:36:20 PM PDT 24
Finished Jul 17 06:36:24 PM PDT 24
Peak memory 200568 kb
Host smart-970f6f67-5e17-45cd-9db0-7bca562a9741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467016474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3467016474
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3322072311
Short name T186
Test name
Test status
Simulation time 260853388 ps
CPU time 28.57 seconds
Started Jul 17 06:36:22 PM PDT 24
Finished Jul 17 06:36:51 PM PDT 24
Peak memory 234552 kb
Host smart-a40d0417-b3da-4d0f-a984-4f00247d8124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322072311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3322072311
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.783017929
Short name T161
Test name
Test status
Simulation time 1179248639 ps
CPU time 65.68 seconds
Started Jul 17 06:36:20 PM PDT 24
Finished Jul 17 06:37:27 PM PDT 24
Peak memory 200280 kb
Host smart-70d4056a-5fad-482c-8b19-d1b093a6706c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783017929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.783017929
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_smoke.1140853501
Short name T301
Test name
Test status
Simulation time 144935992 ps
CPU time 2.86 seconds
Started Jul 17 06:36:20 PM PDT 24
Finished Jul 17 06:36:23 PM PDT 24
Peak memory 200260 kb
Host smart-4481f497-e3b1-4a26-a882-0d0d6f25dc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140853501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1140853501
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3431957185
Short name T234
Test name
Test status
Simulation time 65166330255 ps
CPU time 567.79 seconds
Started Jul 17 06:36:23 PM PDT 24
Finished Jul 17 06:45:52 PM PDT 24
Peak memory 200284 kb
Host smart-ea5e9e00-f78c-4d9c-a2f5-e235c4deefb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431957185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3431957185
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2536578517
Short name T500
Test name
Test status
Simulation time 11360209283 ps
CPU time 138.95 seconds
Started Jul 17 06:36:23 PM PDT 24
Finished Jul 17 06:38:43 PM PDT 24
Peak memory 200412 kb
Host smart-eebea3dc-0151-4357-a49e-aaa8fb3bfb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536578517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2536578517
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1211241668
Short name T456
Test name
Test status
Simulation time 50507645 ps
CPU time 0.58 seconds
Started Jul 17 06:36:31 PM PDT 24
Finished Jul 17 06:36:32 PM PDT 24
Peak memory 195152 kb
Host smart-b607b93d-012d-4862-a599-3ec00d3cb887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211241668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1211241668
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3106968143
Short name T362
Test name
Test status
Simulation time 1268414953 ps
CPU time 79.94 seconds
Started Jul 17 06:36:43 PM PDT 24
Finished Jul 17 06:38:04 PM PDT 24
Peak memory 200200 kb
Host smart-1a3d939a-d76d-48d7-aecf-9853b591d855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106968143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3106968143
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2606530040
Short name T509
Test name
Test status
Simulation time 5008574260 ps
CPU time 4.05 seconds
Started Jul 17 06:36:20 PM PDT 24
Finished Jul 17 06:36:24 PM PDT 24
Peak memory 200336 kb
Host smart-9e0c420b-7bf3-46b1-9634-607efc7fec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606530040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2606530040
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4108539769
Short name T17
Test name
Test status
Simulation time 5098322750 ps
CPU time 233.34 seconds
Started Jul 17 06:36:23 PM PDT 24
Finished Jul 17 06:40:17 PM PDT 24
Peak memory 643164 kb
Host smart-fe9cf83d-5d85-410e-a170-32ad2c72cdd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108539769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4108539769
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3667339191
Short name T335
Test name
Test status
Simulation time 1883839661 ps
CPU time 99.81 seconds
Started Jul 17 06:36:22 PM PDT 24
Finished Jul 17 06:38:03 PM PDT 24
Peak memory 200312 kb
Host smart-9add0a19-44dc-44cf-8047-95886ae84057
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667339191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3667339191
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1353998989
Short name T294
Test name
Test status
Simulation time 13153790478 ps
CPU time 113.17 seconds
Started Jul 17 06:36:24 PM PDT 24
Finished Jul 17 06:38:17 PM PDT 24
Peak memory 200308 kb
Host smart-8e350f75-5ff0-4ff5-b13e-f181d0a8abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353998989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1353998989
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1635904775
Short name T379
Test name
Test status
Simulation time 558580834 ps
CPU time 3.91 seconds
Started Jul 17 06:36:20 PM PDT 24
Finished Jul 17 06:36:25 PM PDT 24
Peak memory 200288 kb
Host smart-799257e2-24bd-442e-b1d4-6d927abf827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635904775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1635904775
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1962886383
Short name T391
Test name
Test status
Simulation time 114465253085 ps
CPU time 2652.96 seconds
Started Jul 17 06:36:21 PM PDT 24
Finished Jul 17 07:20:35 PM PDT 24
Peak memory 797332 kb
Host smart-3ae4533e-fde8-472c-ab95-98a4b87b7827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962886383 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1962886383
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.891273397
Short name T163
Test name
Test status
Simulation time 1185452728 ps
CPU time 64.52 seconds
Started Jul 17 06:36:20 PM PDT 24
Finished Jul 17 06:37:26 PM PDT 24
Peak memory 200264 kb
Host smart-ec1fa874-0294-4cb1-918e-a1298febd840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891273397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.891273397
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3547844783
Short name T324
Test name
Test status
Simulation time 15456091 ps
CPU time 0.58 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:31:01 PM PDT 24
Peak memory 195132 kb
Host smart-7196c853-6594-4ecf-99ef-64e1f98f1d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547844783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3547844783
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1314889141
Short name T431
Test name
Test status
Simulation time 1093356280 ps
CPU time 56.08 seconds
Started Jul 17 06:31:01 PM PDT 24
Finished Jul 17 06:31:58 PM PDT 24
Peak memory 200300 kb
Host smart-7b769ea7-d152-4fad-896b-6709c7ceaeeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314889141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1314889141
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.600756394
Short name T201
Test name
Test status
Simulation time 404786064 ps
CPU time 21.47 seconds
Started Jul 17 06:31:01 PM PDT 24
Finished Jul 17 06:31:24 PM PDT 24
Peak memory 200312 kb
Host smart-cf4fe734-e336-4e0d-acbf-a997a53cc7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600756394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.600756394
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1056748319
Short name T191
Test name
Test status
Simulation time 13819537878 ps
CPU time 138.34 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:33:20 PM PDT 24
Peak memory 421184 kb
Host smart-1a02c081-99e0-4659-bb00-9a7c03526087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056748319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1056748319
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2648598105
Short name T438
Test name
Test status
Simulation time 14748898472 ps
CPU time 202.21 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:34:22 PM PDT 24
Peak memory 200252 kb
Host smart-92588e61-a4ae-478d-94bd-cf470d59693d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648598105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2648598105
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3828850757
Short name T179
Test name
Test status
Simulation time 14463727949 ps
CPU time 89.46 seconds
Started Jul 17 06:30:59 PM PDT 24
Finished Jul 17 06:32:29 PM PDT 24
Peak memory 200644 kb
Host smart-74a945d0-ecb3-437c-9b31-1f048097f719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828850757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3828850757
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3223073506
Short name T426
Test name
Test status
Simulation time 3303534664 ps
CPU time 12.99 seconds
Started Jul 17 06:31:01 PM PDT 24
Finished Jul 17 06:31:15 PM PDT 24
Peak memory 200272 kb
Host smart-5b2db0a9-3925-42fb-a792-90850931f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223073506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3223073506
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3730701005
Short name T67
Test name
Test status
Simulation time 147112485520 ps
CPU time 3419.69 seconds
Started Jul 17 06:31:01 PM PDT 24
Finished Jul 17 07:28:02 PM PDT 24
Peak memory 792320 kb
Host smart-76184433-c752-4d7f-9dba-048b346692d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730701005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3730701005
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.284843154
Short name T485
Test name
Test status
Simulation time 30442412423 ps
CPU time 98.19 seconds
Started Jul 17 06:31:01 PM PDT 24
Finished Jul 17 06:32:40 PM PDT 24
Peak memory 200352 kb
Host smart-da005c32-6178-41d4-ae77-9b8adcda8a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284843154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.284843154
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2913378617
Short name T360
Test name
Test status
Simulation time 58724261 ps
CPU time 0.59 seconds
Started Jul 17 06:31:11 PM PDT 24
Finished Jul 17 06:31:13 PM PDT 24
Peak memory 196800 kb
Host smart-686389d3-4b6a-4db5-991e-68272ea3e605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913378617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2913378617
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.929661062
Short name T452
Test name
Test status
Simulation time 623260237 ps
CPU time 21.48 seconds
Started Jul 17 06:30:58 PM PDT 24
Finished Jul 17 06:31:20 PM PDT 24
Peak memory 200272 kb
Host smart-cdc0e232-d17e-4090-8a8a-50c2610cbfa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929661062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.929661062
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.102456154
Short name T57
Test name
Test status
Simulation time 3627660535 ps
CPU time 51.9 seconds
Started Jul 17 06:31:01 PM PDT 24
Finished Jul 17 06:31:54 PM PDT 24
Peak memory 200296 kb
Host smart-c618f79b-b3a3-4a7b-bf09-49c524260bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102456154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.102456154
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.560784348
Short name T231
Test name
Test status
Simulation time 10252048517 ps
CPU time 1028.27 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:48:09 PM PDT 24
Peak memory 711008 kb
Host smart-810eecbd-1a25-4fdf-8e97-0864268471bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560784348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.560784348
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1601539982
Short name T38
Test name
Test status
Simulation time 27212715152 ps
CPU time 91.85 seconds
Started Jul 17 06:31:03 PM PDT 24
Finished Jul 17 06:32:35 PM PDT 24
Peak memory 200236 kb
Host smart-163a67e8-cd09-4827-8095-4b86aad22a40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601539982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1601539982
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.18315692
Short name T31
Test name
Test status
Simulation time 14494340004 ps
CPU time 126.46 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:33:07 PM PDT 24
Peak memory 200412 kb
Host smart-67da7926-f1d8-4e87-acb3-7b2a229c2813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18315692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.18315692
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1941372369
Short name T170
Test name
Test status
Simulation time 1621923322 ps
CPU time 14.5 seconds
Started Jul 17 06:31:00 PM PDT 24
Finished Jul 17 06:31:16 PM PDT 24
Peak memory 200248 kb
Host smart-8c995b1f-73d5-42f9-97bb-ad87996c374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941372369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1941372369
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.101587284
Short name T283
Test name
Test status
Simulation time 46724374349 ps
CPU time 1778.19 seconds
Started Jul 17 06:31:13 PM PDT 24
Finished Jul 17 07:00:52 PM PDT 24
Peak memory 710352 kb
Host smart-0fb6bbb5-1bd9-4f50-9d74-c5140bdb4ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101587284 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.101587284
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2803618210
Short name T466
Test name
Test status
Simulation time 7860992992 ps
CPU time 143.08 seconds
Started Jul 17 06:31:12 PM PDT 24
Finished Jul 17 06:33:37 PM PDT 24
Peak memory 200352 kb
Host smart-c4415e10-9ca5-4bde-975c-86016198cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803618210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2803618210
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2146041401
Short name T263
Test name
Test status
Simulation time 13562932 ps
CPU time 0.6 seconds
Started Jul 17 06:31:28 PM PDT 24
Finished Jul 17 06:31:29 PM PDT 24
Peak memory 195168 kb
Host smart-5834847f-eda7-4832-9ce8-d4d654c57a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146041401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2146041401
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1420124384
Short name T352
Test name
Test status
Simulation time 936171821 ps
CPU time 57.66 seconds
Started Jul 17 06:31:12 PM PDT 24
Finished Jul 17 06:32:11 PM PDT 24
Peak memory 200240 kb
Host smart-44c516e5-0107-4b1b-a3b1-ea348706c58d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420124384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1420124384
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1200267046
Short name T251
Test name
Test status
Simulation time 2333333849 ps
CPU time 31.43 seconds
Started Jul 17 06:31:10 PM PDT 24
Finished Jul 17 06:31:42 PM PDT 24
Peak memory 200264 kb
Host smart-ec274656-9398-4477-9e43-a18bf1261c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200267046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1200267046
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.983740462
Short name T277
Test name
Test status
Simulation time 6439896124 ps
CPU time 1146.73 seconds
Started Jul 17 06:31:13 PM PDT 24
Finished Jul 17 06:50:21 PM PDT 24
Peak memory 729648 kb
Host smart-29bf8ee3-ff10-4056-98bf-85e5afd76b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983740462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.983740462
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1579037426
Short name T437
Test name
Test status
Simulation time 12384220515 ps
CPU time 143.1 seconds
Started Jul 17 06:31:14 PM PDT 24
Finished Jul 17 06:33:37 PM PDT 24
Peak memory 200396 kb
Host smart-fc9887a1-7546-43c8-b82b-69443086c62f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579037426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1579037426
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2958168274
Short name T494
Test name
Test status
Simulation time 9300437409 ps
CPU time 83.28 seconds
Started Jul 17 06:31:12 PM PDT 24
Finished Jul 17 06:32:36 PM PDT 24
Peak memory 200476 kb
Host smart-0b42699c-8fbc-4b0e-8e38-76ff65e6a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958168274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2958168274
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3627191917
Short name T433
Test name
Test status
Simulation time 389415331 ps
CPU time 6.68 seconds
Started Jul 17 06:31:13 PM PDT 24
Finished Jul 17 06:31:21 PM PDT 24
Peak memory 200292 kb
Host smart-b4b021e1-a539-4ef2-a7cf-064bad306e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627191917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3627191917
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3314031372
Short name T208
Test name
Test status
Simulation time 32984620333 ps
CPU time 1221.35 seconds
Started Jul 17 06:31:12 PM PDT 24
Finished Jul 17 06:51:35 PM PDT 24
Peak memory 691764 kb
Host smart-d2007ad4-9fe8-4bd0-afcc-5a10c5d8fd26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314031372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3314031372
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4203216815
Short name T83
Test name
Test status
Simulation time 1738601224 ps
CPU time 101.99 seconds
Started Jul 17 06:31:12 PM PDT 24
Finished Jul 17 06:32:55 PM PDT 24
Peak memory 200336 kb
Host smart-609f8634-db1d-4804-8fde-9d1397c3b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203216815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4203216815
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4102587953
Short name T37
Test name
Test status
Simulation time 12235335 ps
CPU time 0.58 seconds
Started Jul 17 06:31:32 PM PDT 24
Finished Jul 17 06:31:34 PM PDT 24
Peak memory 195060 kb
Host smart-96d0efdb-951c-43af-b28e-f21b6ac18b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102587953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4102587953
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2530508954
Short name T342
Test name
Test status
Simulation time 1598651488 ps
CPU time 17.3 seconds
Started Jul 17 06:31:21 PM PDT 24
Finished Jul 17 06:31:39 PM PDT 24
Peak memory 200328 kb
Host smart-daf3bc44-dc62-4a90-8b2c-eb0cc6492aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530508954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2530508954
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3564844095
Short name T502
Test name
Test status
Simulation time 3651007254 ps
CPU time 50.7 seconds
Started Jul 17 06:31:28 PM PDT 24
Finished Jul 17 06:32:19 PM PDT 24
Peak memory 200416 kb
Host smart-eb9ac713-89bd-47de-a837-d97488352620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564844095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3564844095
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3252428930
Short name T378
Test name
Test status
Simulation time 12012337637 ps
CPU time 592.45 seconds
Started Jul 17 06:31:22 PM PDT 24
Finished Jul 17 06:41:15 PM PDT 24
Peak memory 684380 kb
Host smart-614d7d15-edc4-4cc9-952a-8521502bc3dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252428930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3252428930
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1308509812
Short name T375
Test name
Test status
Simulation time 31918270962 ps
CPU time 102.03 seconds
Started Jul 17 06:31:21 PM PDT 24
Finished Jul 17 06:33:03 PM PDT 24
Peak memory 200280 kb
Host smart-c5535e49-3a16-4606-9cb6-e5c80b3f747c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308509812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1308509812
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1830448756
Short name T353
Test name
Test status
Simulation time 425954550 ps
CPU time 9.09 seconds
Started Jul 17 06:31:21 PM PDT 24
Finished Jul 17 06:31:30 PM PDT 24
Peak memory 200240 kb
Host smart-920ae532-23ea-4fdd-ab7a-554e541988dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830448756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1830448756
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1005634601
Short name T24
Test name
Test status
Simulation time 139024572 ps
CPU time 2.16 seconds
Started Jul 17 06:31:19 PM PDT 24
Finished Jul 17 06:31:22 PM PDT 24
Peak memory 200292 kb
Host smart-21424b32-152d-44d4-8fed-7528a6c93390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005634601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1005634601
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.493463620
Short name T85
Test name
Test status
Simulation time 45434016581 ps
CPU time 1013.41 seconds
Started Jul 17 06:31:31 PM PDT 24
Finished Jul 17 06:48:25 PM PDT 24
Peak memory 704908 kb
Host smart-4aa545ad-4a24-42d3-bb10-98a011b54d67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493463620 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.493463620
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1185574197
Short name T15
Test name
Test status
Simulation time 22213041860 ps
CPU time 341.28 seconds
Started Jul 17 06:31:32 PM PDT 24
Finished Jul 17 06:37:13 PM PDT 24
Peak memory 208628 kb
Host smart-5db0c839-6fb2-4e2e-bd67-67cf18b5bf59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185574197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1185574197
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3201462145
Short name T343
Test name
Test status
Simulation time 4372431482 ps
CPU time 74.18 seconds
Started Jul 17 06:31:22 PM PDT 24
Finished Jul 17 06:32:37 PM PDT 24
Peak memory 200364 kb
Host smart-e89d2446-c14a-43d2-9d68-052c0f70ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201462145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3201462145
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4068464873
Short name T308
Test name
Test status
Simulation time 80270183 ps
CPU time 0.58 seconds
Started Jul 17 06:31:33 PM PDT 24
Finished Jul 17 06:31:34 PM PDT 24
Peak memory 196204 kb
Host smart-36e315b1-52a4-431a-9564-7d28caa08b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068464873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4068464873
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1828352760
Short name T211
Test name
Test status
Simulation time 3126993449 ps
CPU time 92.71 seconds
Started Jul 17 06:31:33 PM PDT 24
Finished Jul 17 06:33:06 PM PDT 24
Peak memory 216472 kb
Host smart-8e5c53eb-ec04-4436-a332-4ab421bb26f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828352760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1828352760
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3055578422
Short name T368
Test name
Test status
Simulation time 5029700283 ps
CPU time 47.92 seconds
Started Jul 17 06:31:34 PM PDT 24
Finished Jul 17 06:32:22 PM PDT 24
Peak memory 200212 kb
Host smart-1dec6206-b5d2-49fc-9a30-73e60e87b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055578422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3055578422
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1305418844
Short name T153
Test name
Test status
Simulation time 2833061228 ps
CPU time 415.3 seconds
Started Jul 17 06:31:32 PM PDT 24
Finished Jul 17 06:38:28 PM PDT 24
Peak memory 618528 kb
Host smart-d9838ece-d1f2-40c8-8d8c-17e4001ccd74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305418844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1305418844
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.211022657
Short name T376
Test name
Test status
Simulation time 5117420497 ps
CPU time 100.63 seconds
Started Jul 17 06:31:32 PM PDT 24
Finished Jul 17 06:33:13 PM PDT 24
Peak memory 200264 kb
Host smart-1e157a8c-9b8f-42e7-8d6f-d16d4a941747
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211022657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.211022657
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.556507249
Short name T325
Test name
Test status
Simulation time 3044920845 ps
CPU time 178.07 seconds
Started Jul 17 06:31:37 PM PDT 24
Finished Jul 17 06:34:35 PM PDT 24
Peak memory 200312 kb
Host smart-418c881e-f1e3-4921-a6b0-18ed4b294fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556507249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.556507249
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.728217278
Short name T516
Test name
Test status
Simulation time 122314005 ps
CPU time 1.88 seconds
Started Jul 17 06:31:37 PM PDT 24
Finished Jul 17 06:31:39 PM PDT 24
Peak memory 200240 kb
Host smart-f664a312-3ce8-4f2a-9392-c0d70d9ab6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728217278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.728217278
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3106558828
Short name T521
Test name
Test status
Simulation time 82826351442 ps
CPU time 374.53 seconds
Started Jul 17 06:31:32 PM PDT 24
Finished Jul 17 06:37:48 PM PDT 24
Peak memory 208492 kb
Host smart-4b54d3ac-5ade-42f5-984e-2e016adb764d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106558828 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3106558828
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1951764704
Short name T139
Test name
Test status
Simulation time 9898072249 ps
CPU time 138.12 seconds
Started Jul 17 06:31:32 PM PDT 24
Finished Jul 17 06:33:50 PM PDT 24
Peak memory 200396 kb
Host smart-d2c1e704-df27-439d-a518-c5a414b615d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951764704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1951764704
Directory /workspace/9.hmac_wipe_secret/latest
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