Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18872823	1			T1	171193		T2	20572		T3	454048
all_values[1]	18872823	1			T1	171193		T2	20572		T3	454048
all_values[2]	18872823	1			T1	171193		T2	20572		T3	454048

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337144

1

T1

689

T4

193

T9

792

auto[1]

56281325

1

T1

512890

T2

61716

T3

136214

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48112442

1

T1

439571

T2

55162

T3

120281

auto[1]

8506027

1

T1

74008

T2

6554

T3

159325

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	130418	1			T1	1		T23	6752		T27	3
all_values[0]	auto[0]	auto[1]	399	1			T23	5		T118	2		T42	2
all_values[0]	auto[1]	auto[0]	18721819	1			T1	171009		T2	20545		T3	453662
all_values[0]	auto[1]	auto[1]	20187	1			T1	183		T2	27		T3	386
all_values[1]	auto[0]	auto[0]	111175	1			T1	3		T9	396		T16	25
all_values[1]	auto[0]	auto[1]	201	1			T1	2		T23	1		T7	1
all_values[1]	auto[1]	auto[0]	18761173	1			T1	171186		T2	20572		T3	454048
all_values[1]	auto[1]	auto[1]	274	1			T1	2		T15	1		T23	3
all_values[2]	auto[0]	auto[0]	46522	1			T1	174		T4	193		T9	224
all_values[2]	auto[0]	auto[1]	48429	1			T1	509		T9	172		T23	544
all_values[2]	auto[1]	auto[0]	10341335	1			T1	97198		T2	14045		T3	295109
all_values[2]	auto[1]	auto[1]	8436537	1			T1	73312		T2	6527		T3	158939