Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132461

1

T1

1952

T2

38

T3

360

auto[1]

125486

1

T1

3836

T2

18

T4

32

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	97968	1			T1	2505		T2	21		T3	65
len_1026_2046	5846	1			T1	46		T3	1		T4	1
len_514_1022	3377	1			T1	23		T2	2		T3	49
len_2_510	2990	1			T1	12		T2	2		T3	58
len_2056	160	1			T1	4		T28	1		T51	2
len_2048	324	1			T1	3		T6	1		T15	2
len_2040	477	1			T16	1		T130	1		T66	1
len_1032	170	1			T1	3		T16	2		T28	3
len_1024	1771	1			T1	6		T3	1		T4	2
len_1016	219	1			T1	2		T3	1		T16	4
len_520	160	1			T3	1		T26	1		T28	2
len_512	375	1			T3	2		T15	3		T16	1
len_504	203	1			T1	5		T16	1		T26	2
len_8	1521	1			T1	17		T23	16		T26	1
len_0	13411	1			T1	268		T2	3		T3	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

122

1

T4

1

T6

2

T27

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	52087	1			T1	773		T2	16		T3	65
auto[0]	len_1026_2046	2835	1			T1	31		T3	1		T4	1
auto[0]	len_514_1022	1992	1			T1	14		T3	49		T15	14
auto[0]	len_2_510	2095	1			T1	6		T2	2		T3	58
auto[0]	len_2056	92	1			T1	3		T28	1		T119	3
auto[0]	len_2048	174	1			T1	1		T6	1		T15	2
auto[0]	len_2040	79	1			T16	1		T130	1		T131	5
auto[0]	len_1032	69	1			T1	3		T28	1		T66	2
auto[0]	len_1024	255	1			T1	4		T3	1		T4	1
auto[0]	len_1016	130	1			T3	1		T16	4		T26	1
auto[0]	len_520	91	1			T3	1		T26	1		T130	1
auto[0]	len_512	221	1			T3	2		T15	3		T16	1
auto[0]	len_504	97	1			T1	2		T26	2		T28	2
auto[0]	len_8	60	1			T26	1		T66	2		T132	2
auto[0]	len_0	5952	1			T1	139		T2	1		T3	2
auto[1]	len_2050_plus	45881	1			T1	1732		T2	5		T4	15
auto[1]	len_1026_2046	3011	1			T1	15		T5	7		T15	8
auto[1]	len_514_1022	1385	1			T1	9		T2	2		T5	1
auto[1]	len_2_510	895	1			T1	6		T5	1		T15	2
auto[1]	len_2056	68	1			T1	1		T51	2		T66	2
auto[1]	len_2048	150	1			T1	2		T28	2		T7	1
auto[1]	len_2040	398	1			T66	1		T131	1		T133	1
auto[1]	len_1032	101	1			T16	2		T28	2		T66	1
auto[1]	len_1024	1516	1			T1	2		T4	1		T5	1
auto[1]	len_1016	89	1			T1	2		T28	1		T119	2
auto[1]	len_520	69	1			T28	2		T130	1		T119	2
auto[1]	len_512	154	1			T130	6		T7	2		T66	3
auto[1]	len_504	106	1			T1	3		T16	1		T28	1
auto[1]	len_8	1461	1			T1	17		T23	16		T27	9
auto[1]	len_0	7459	1			T1	129		T2	2		T5	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

74

1

T4

1

T134

2

T135

2

auto[1]

len_upper

48

1

T6

2

T27

2

T57

1