Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4696391 1 T1 44009 T2 4341 T3 147443
auto[1] 2887429 1 T1 38549 T2 5844 T4 22


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2959636 1 T1 38798 T2 4184 T4 23
auto[1] 4624184 1 T1 43760 T2 6001 T3 147443


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3380344 1 T1 24770 T2 7225 T3 147443
auto[1] 4203476 1 T1 57788 T2 2960 T4 20


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4644502 1 T1 46036 T2 5125 T3 147443
auto[1] 2939318 1 T1 36522 T2 5060 T4 15


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6902798 1 T1 81720 T2 8727 T3 126503
fifo_depth[1] 120343 1 T1 595 T2 224 T3 4719
fifo_depth[2] 89145 1 T1 159 T2 237 T3 4536
fifo_depth[3] 68796 1 T1 43 T2 214 T3 3900
fifo_depth[4] 60367 1 T1 25 T2 229 T3 2722
fifo_depth[5] 47509 1 T1 7 T2 199 T3 2018
fifo_depth[6] 37945 1 T1 6 T2 142 T3 1415
fifo_depth[7] 25067 1 T1 2 T2 112 T3 901


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 681022 1 T1 838 T2 1458 T3 20940
auto[1] 6902798 1 T1 81720 T2 8727 T3 126503


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7573642 1 T1 82558 T2 10185 T3 147443
auto[1] 10178 1 T15 219 T19 10 T17 55


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 37131 1 T1 43 T2 98 T4 1
auto[0] auto[0] auto[0] auto[0] auto[1] 26418 1 T1 25 T5 25 T9 1
auto[0] auto[0] auto[0] auto[1] auto[0] 29723 1 T1 65 T2 274 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] 27386 1 T1 19 T2 140 T4 1
auto[0] auto[0] auto[1] auto[0] auto[0] 159737 1 T1 32 T2 244 T3 20940
auto[0] auto[0] auto[1] auto[0] auto[1] 27260 1 T1 30 T2 135 T5 23
auto[0] auto[0] auto[1] auto[1] auto[0] 29635 1 T1 28 T4 3 T6 1
auto[0] auto[0] auto[1] auto[1] auto[1] 31714 1 T1 105 T2 381 T4 1
auto[0] auto[1] auto[0] auto[0] auto[0] 35052 1 T1 27 T4 2 T5 3
auto[0] auto[1] auto[0] auto[0] auto[1] 43480 1 T1 58 T2 79 T15 195
auto[0] auto[1] auto[0] auto[1] auto[0] 35479 1 T1 26 T15 298 T23 120
auto[0] auto[1] auto[0] auto[1] auto[1] 42142 1 T1 47 T2 82 T4 1
auto[0] auto[1] auto[1] auto[0] auto[0] 51904 1 T1 128 T5 2 T14 967
auto[0] auto[1] auto[1] auto[0] auto[1] 34482 1 T1 62 T5 4 T23 176
auto[0] auto[1] auto[1] auto[1] auto[0] 34065 1 T1 46 T2 25 T16 2
auto[0] auto[1] auto[1] auto[1] auto[1] 35414 1 T1 97 T5 84 T6 1
auto[1] auto[0] auto[0] auto[0] auto[0] 184519 1 T1 4979 T2 384 T4 1
auto[1] auto[0] auto[0] auto[0] auto[1] 191720 1 T1 1780 T4 1 T5 1857
auto[1] auto[0] auto[0] auto[1] auto[0] 162941 1 T1 3164 T2 1269 T4 2
auto[1] auto[0] auto[0] auto[1] auto[1] 190103 1 T1 2781 T2 317 T4 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1737695 1 T1 3115 T2 866 T3 126503
auto[1] auto[0] auto[1] auto[0] auto[1] 169658 1 T1 1991 T2 997 T4 1
auto[1] auto[0] auto[1] auto[1] auto[0] 191470 1 T1 1388 T2 790 T4 1
auto[1] auto[0] auto[1] auto[1] auto[1] 183234 1 T1 5225 T2 1330 T4 2
auto[1] auto[1] auto[0] auto[0] auto[0] 434795 1 T1 4763 T2 41 T4 2
auto[1] auto[1] auto[0] auto[0] auto[1] 530216 1 T1 7664 T2 948 T4 3
auto[1] auto[1] auto[0] auto[1] auto[0] 510672 1 T1 9826 T2 257 T4 4
auto[1] auto[1] auto[0] auto[1] auto[1] 477859 1 T1 3531 T2 295 T4 3
auto[1] auto[1] auto[1] auto[0] auto[0] 558279 1 T1 14139 T2 549 T4 2
auto[1] auto[1] auto[1] auto[0] auto[1] 474045 1 T1 5173 T4 1 T5 1051
auto[1] auto[1] auto[1] auto[1] auto[0] 451405 1 T1 4267 T2 328 T4 2
auto[1] auto[1] auto[1] auto[1] auto[1] 454187 1 T1 7934 T2 356 T5 2848


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 220377 1 T1 5022 T2 482 T4 2
auto[0] auto[0] auto[0] auto[0] auto[1] 217605 1 T1 1805 T4 1 T5 1882
auto[0] auto[0] auto[0] auto[1] auto[0] 192218 1 T1 3229 T2 1543 T4 3
auto[0] auto[0] auto[0] auto[1] auto[1] 217197 1 T1 2800 T2 457 T4 2
auto[0] auto[0] auto[1] auto[0] auto[0] 1895268 1 T1 3147 T2 1110 T3 147443
auto[0] auto[0] auto[1] auto[0] auto[1] 196260 1 T1 2021 T2 1132 T4 1
auto[0] auto[0] auto[1] auto[1] auto[0] 220476 1 T1 1416 T2 790 T4 4
auto[0] auto[0] auto[1] auto[1] auto[1] 214236 1 T1 5330 T2 1711 T4 3
auto[0] auto[1] auto[0] auto[0] auto[0] 469729 1 T1 4790 T2 41 T4 4
auto[0] auto[1] auto[0] auto[0] auto[1] 573043 1 T1 7722 T2 1027 T4 3
auto[0] auto[1] auto[0] auto[1] auto[0] 545811 1 T1 9852 T2 257 T4 4
auto[0] auto[1] auto[0] auto[1] auto[1] 519313 1 T1 3578 T2 377 T4 4
auto[0] auto[1] auto[1] auto[0] auto[0] 610000 1 T1 14267 T2 549 T4 2
auto[0] auto[1] auto[1] auto[0] auto[1] 507723 1 T1 5235 T4 1 T5 1055
auto[0] auto[1] auto[1] auto[1] auto[0] 485001 1 T1 4313 T2 353 T4 2
auto[0] auto[1] auto[1] auto[1] auto[1] 489385 1 T1 8031 T2 356 T5 2932
auto[1] auto[0] auto[0] auto[0] auto[0] 1273 1 T15 91 T139 31 T140 12
auto[1] auto[0] auto[0] auto[0] auto[1] 533 1 T40 116 T139 1 T141 3
auto[1] auto[0] auto[0] auto[1] auto[0] 446 1 T15 123 T139 2 T140 96
auto[1] auto[0] auto[0] auto[1] auto[1] 292 1 T40 9 T10 15 T142 143
auto[1] auto[0] auto[1] auto[0] auto[0] 2164 1 T40 24 T139 38 T141 41
auto[1] auto[0] auto[1] auto[0] auto[1] 658 1 T40 33 T139 354 T140 26
auto[1] auto[0] auto[1] auto[1] auto[0] 629 1 T19 7 T40 358 T140 4
auto[1] auto[0] auto[1] auto[1] auto[1] 712 1 T40 41 T139 249 T10 3
auto[1] auto[1] auto[0] auto[0] auto[0] 118 1 T40 1 T139 25 T140 3
auto[1] auto[1] auto[0] auto[0] auto[1] 653 1 T141 4 T10 129 T142 110
auto[1] auto[1] auto[0] auto[1] auto[0] 340 1 T15 1 T140 4 T141 1
auto[1] auto[1] auto[0] auto[1] auto[1] 688 1 T139 43 T10 5 T143 1
auto[1] auto[1] auto[1] auto[0] auto[0] 183 1 T15 3 T17 1 T141 12
auto[1] auto[1] auto[1] auto[0] auto[1] 804 1 T139 6 T140 59 T141 89
auto[1] auto[1] auto[1] auto[1] auto[0] 469 1 T19 3 T40 3 T140 10
auto[1] auto[1] auto[1] auto[1] auto[1] 216 1 T15 1 T17 54 T140 5


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 184519 1 T1 4979 T2 384 T4 1
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 191720 1 T1 1780 T4 1 T5 1857
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 162941 1 T1 3164 T2 1269 T4 2
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 190103 1 T1 2781 T2 317 T4 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1737695 1 T1 3115 T2 866 T3 126503
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 169658 1 T1 1991 T2 997 T4 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 191470 1 T1 1388 T2 790 T4 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 183234 1 T1 5225 T2 1330 T4 2
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 434795 1 T1 4763 T2 41 T4 2
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 530216 1 T1 7664 T2 948 T4 3
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 510672 1 T1 9826 T2 257 T4 4
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 477859 1 T1 3531 T2 295 T4 3
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 558279 1 T1 14139 T2 549 T4 2
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 474045 1 T1 5173 T4 1 T5 1051
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 451405 1 T1 4267 T2 328 T4 2
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 454187 1 T1 7934 T2 356 T5 2848
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4011 1 T1 34 T2 12 T5 34
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3679 1 T1 15 T5 16 T15 3
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3422 1 T1 40 T2 51 T4 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3576 1 T1 16 T2 28 T9 1
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 43859 1 T1 21 T2 30 T3 4719
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3259 1 T1 27 T2 17 T5 18
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3856 1 T1 14 T15 3 T23 72
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3381 1 T1 61 T2 54 T15 6
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 5075 1 T1 19 T4 1 T5 1
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7008 1 T1 41 T2 16 T15 3
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6372 1 T1 21 T15 2 T23 70
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6226 1 T1 33 T2 11 T9 1
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8653 1 T1 100 T5 1 T14 206
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5815 1 T1 46 T5 2 T23 118
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6287 1 T1 27 T2 5 T23 5
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5864 1 T1 80 T5 67 T23 51
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2735 1 T1 7 T2 12 T5 8
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2751 1 T1 4 T5 7 T15 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2512 1 T1 13 T2 54 T15 3
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2637 1 T1 3 T2 24 T15 38
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 29911 1 T1 5 T2 49 T3 4536
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2607 1 T1 2 T2 20 T5 5
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2939 1 T1 4 T15 2 T23 28
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2782 1 T1 25 T2 56 T23 16
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 4191 1 T1 4 T5 1 T6 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5500 1 T1 12 T2 8 T15 11
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4814 1 T1 5 T15 4 T23 39
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4858 1 T1 12 T2 12 T15 8
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6770 1 T1 22 T5 1 T14 209
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4678 1 T1 13 T5 2 T23 48
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4896 1 T1 11 T2 2 T16 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4564 1 T1 17 T5 14 T15 4
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2085 1 T1 1 T2 21 T15 3
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1964 1 T1 2 T5 2 T9 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1924 1 T1 5 T2 43 T15 2
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1767 1 T2 22 T15 34 T23 5
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 21667 1 T1 1 T2 29 T3 3900
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1800 1 T1 1 T2 18 T23 5
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2226 1 T1 6 T4 1 T23 14
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1944 1 T1 11 T2 49 T15 6
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3397 1 T1 3 T5 1 T23 17
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4698 1 T1 2 T2 19 T15 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3846 1 T23 3 T27 63 T136 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4152 1 T1 1 T2 10 T15 9
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5549 1 T1 6 T14 190 T23 4
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3946 1 T1 1 T23 7 T25 18
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4186 1 T1 3 T2 3 T16 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3645 1 T5 3 T23 12 T136 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2088 1 T1 1 T2 15 T4 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2066 1 T1 2 T134 5 T129 14
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1884 1 T1 5 T2 44 T15 12
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1595 1 T2 25 T15 35 T23 8
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 15432 1 T1 4 T2 38 T3 2722
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1857 1 T2 19 T9 1 T23 4
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2071 1 T1 1 T15 2 T23 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2121 1 T1 4 T2 62 T15 38
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 3374 1 T1 1 T4 1 T23 7
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4258 1 T1 2 T2 10 T15 11
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3460 1 T15 2 T23 4 T27 54
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3965 1 T2 16 T15 13 T23 6
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5162 1 T14 156 T15 2 T23 2
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3626 1 T1 2 T23 2 T25 24
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3659 1 T1 3 T23 5 T118 31
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3749 1 T15 2 T136 3 T129 10
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1561 1 T2 8 T15 2 T135 36
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1469 1 T1 1 T129 10 T135 6
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1402 1 T1 1 T2 40 T15 3
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1205 1 T2 18 T15 14 T23 2
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 11073 1 T1 1 T2 31 T3 2018
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1271 1 T2 20 T25 2 T134 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1622 1 T1 2 T4 1 T15 4
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1474 1 T1 2 T2 55 T15 6
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2822 1 T23 1 T27 5 T144 3
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3776 1 T2 12 T15 2 T23 18
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 2941 1 T27 39 T135 10 T42 122
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3391 1 T2 9 T15 11 T23 2
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4334 1 T14 122 T135 1 T145 10
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3108 1 T23 1 T25 8 T135 34
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3223 1 T2 6 T23 7 T118 21
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2837 1 T129 4 T135 24 T42 58
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1464 1 T2 7 T15 2 T23 5
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1331 1 T134 4 T129 6 T135 6
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1170 1 T1 1 T2 22 T6 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 949 1 T2 15 T15 1 T23 5
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7341 1 T2 28 T3 1415 T25 11
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1105 1 T2 9 T144 3 T135 33
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1306 1 T1 1 T6 1 T15 2
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1391 1 T1 2 T2 38 T134 14
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2426 1 T23 1 T27 8 T144 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3106 1 T1 1 T2 11 T15 16
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2355 1 T15 3 T27 45 T135 14
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2765 1 T2 11 T15 9 T27 10
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3457 1 T14 58 T15 6 T145 5
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2427 1 T25 3 T135 34 T7 3
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2693 1 T1 1 T2 1 T23 4
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2659 1 T15 3 T136 1 T135 12
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 821 1 T2 12 T15 4 T135 10
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 785 1 T1 1 T129 4 T135 5
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 722 1 T2 16 T15 2 T7 5
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 631 1 T2 5 T23 2 T135 6
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4652 1 T2 17 T3 901 T15 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 754 1 T2 19 T144 3 T135 22
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 832 1 T15 2 T53 11 T55 9
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 916 1 T2 29 T6 1 T15 5
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1785 1 T9 1 T27 6 T144 2
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2120 1 T2 2 T15 3 T23 3
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1597 1 T27 39 T135 12 T42 79
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1924 1 T2 8 T6 1 T15 10
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2503 1 T14 20 T135 2 T145 5
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1638 1 T135 15 T7 4 T42 79
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1794 1 T1 1 T2 4 T23 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1593 1 T135 11 T42 26 T55 2

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