Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18872823	1			T1	171193		T2	20572		T3	454048
all_pins[1]	18872823	1			T1	171193		T2	20572		T3	454048
all_pins[2]	18872823	1			T1	171193		T2	20572		T3	454048

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48160589	1			T1	440076		T2	55160		T3	120281
values[0x1]	8457880	1			T1	73503		T2	6556		T3	159325
transitions[0x0=>0x1]	8457689	1			T1	73497		T2	6556		T3	159325
transitions[0x1=>0x0]	8457704	1			T1	73497		T2	6556		T3	159325

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18851781	1			T1	171004		T2	20543		T3	453662
all_pins[0]	values[0x1]	21042	1			T1	189		T2	29		T3	386
all_pins[0]	transitions[0x0=>0x1]	20961	1			T1	186		T2	29		T3	386
all_pins[0]	transitions[0x1=>0x0]	8436471	1			T1	73309		T2	6527		T3	158939
all_pins[1]	values[0x0]	18872522	1			T1	171191		T2	20572		T3	454048
all_pins[1]	values[0x1]	301	1			T1	2		T15	2		T23	3
all_pins[1]	transitions[0x0=>0x1]	249	1			T15	2		T23	2		T66	2
all_pins[1]	transitions[0x1=>0x0]	20990	1			T1	187		T2	29		T3	386
all_pins[2]	values[0x0]	10436286	1			T1	97881		T2	14045		T3	295109
all_pins[2]	values[0x1]	8436537	1			T1	73312		T2	6527		T3	158939
all_pins[2]	transitions[0x0=>0x1]	8436479	1			T1	73311		T2	6527		T3	158939
all_pins[2]	transitions[0x1=>0x0]	243	1			T1	1		T15	2		T23	3