Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 969 1 T1 7 T23 8 T7 4
all_values[1] 969 1 T1 7 T23 8 T7 4
all_values[2] 969 1 T1 7 T23 8 T7 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1462 1 T1 5 T23 12 T7 1
auto[1] 1445 1 T1 16 T23 12 T7 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1076 1 T1 5 T23 6 T7 2
auto[1] 1831 1 T1 16 T23 18 T7 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1693 1 T1 11 T23 13 T7 7
auto[1] 1214 1 T1 10 T23 11 T7 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 182 1 T23 2 T66 2 T67 2
all_values[0] auto[0] auto[0] auto[1] 110 1 T68 4 T70 1 T119 2
all_values[0] auto[0] auto[1] auto[0] 174 1 T1 1 T23 1 T66 3
all_values[0] auto[0] auto[1] auto[1] 93 1 T1 2 T23 2 T7 2
all_values[0] auto[1] auto[0] auto[1] 204 1 T23 3 T67 3 T68 1
all_values[0] auto[1] auto[1] auto[1] 206 1 T1 4 T7 2 T66 2
all_values[1] auto[0] auto[0] auto[0] 168 1 T23 1 T67 4 T68 2
all_values[1] auto[0] auto[0] auto[1] 125 1 T1 2 T23 1 T66 1
all_values[1] auto[0] auto[1] auto[0] 164 1 T7 2 T66 2 T67 3
all_values[1] auto[0] auto[1] auto[1] 113 1 T1 1 T23 2 T7 1
all_values[1] auto[1] auto[0] auto[1] 199 1 T1 1 T66 2 T68 1
all_values[1] auto[1] auto[1] auto[1] 200 1 T1 3 T23 4 T7 1
all_values[2] auto[0] auto[0] auto[0] 178 1 T1 2 T23 1 T66 1
all_values[2] auto[0] auto[0] auto[1] 93 1 T23 2 T66 1 T67 2
all_values[2] auto[0] auto[1] auto[0] 210 1 T1 2 T23 1 T67 1
all_values[2] auto[0] auto[1] auto[1] 83 1 T1 1 T7 2 T66 1
all_values[2] auto[1] auto[0] auto[1] 203 1 T23 2 T7 1 T66 2
all_values[2] auto[1] auto[1] auto[1] 202 1 T1 2 T23 2 T7 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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