Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4476	1			T1	63		T2	11		T4	9
sha2_none	4264	1			T1	50		T2	5		T4	6
sha2_512	7886	1			T1	82		T2	8		T4	8
sha2_384	7636	1			T1	75		T2	10		T3	386
sha2_256	6562	1			T1	66		T2	6		T4	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19413

1

T1

151

T2

16

T3

386

auto[1]

11787

1

T1

190

T2

24

T4

23

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11751

1

T1

158

T2

19

T4

24

auto[1]

19449

1

T1

183

T2

21

T3

386

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16218

1

T1

201

T2

16

T4

21

disabled

14982

1

T1

140

T2

24

T3

386

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4748	1			T1	66		T2	2		T4	9
key_none	7893	1			T1	48		T2	4		T3	386
key_1024	4486	1			T1	34		T2	8		T4	5
key_512	4004	1			T1	47		T2	8		T4	11
key_384	3540	1			T1	34		T2	5		T4	3
key_256	3300	1			T1	59		T2	7		T4	4
key_128	3156	1			T1	53		T2	5		T4	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19506

1

T1

185

T2

17

T3

386

auto[1]

11694

1

T1

156

T2

23

T4

17

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30977

1

T1

340

T2

40

T3

386

disabled

223

1

T1

1

T23

3

T25

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1661

1

T1

18

T2

1

T4

4

enabled

auto[0]

auto[0]

auto[1]

1705

1

T1

19

T2

6

T4

4

enabled

auto[0]

auto[1]

auto[0]

1707

1

T1

27

T2

1

T4

4

enabled

auto[0]

auto[1]

auto[1]

1660

1

T1

20

T2

2

T4

4

enabled

auto[1]

auto[0]

auto[0]

4437

1

T1

27

T2

1

T4

2

enabled

auto[1]

auto[0]

auto[1]

1630

1

T1

20

T4

1

T5

5

enabled

auto[1]

auto[1]

auto[0]

1817

1

T1

43

T2

2

T4

2

enabled

auto[1]

auto[1]

auto[1]

1601

1

T1

27

T2

3

T5

7

disabled

auto[0]

auto[0]

auto[0]

1245

1

T1

24

T2

2

T4

2

disabled

auto[0]

auto[0]

auto[1]

1303

1

T1

16

T4

1

T5

2

disabled

auto[0]

auto[1]

auto[0]

1215

1

T1

16

T2

4

T4

3

disabled

auto[0]

auto[1]

auto[1]

1255

1

T1

18

T2

3

T4

2

disabled

auto[1]

auto[0]

auto[0]

6168

1

T1

14

T2

3

T3

386

disabled

auto[1]

auto[0]

auto[1]

1264

1

T1

13

T2

3

T4

2

disabled

auto[1]

auto[1]

auto[0]

1256

1

T1

16

T2

3

T4

5

disabled

auto[1]

auto[1]

auto[1]

1276

1

T1

23

T2

6

T4

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16135

1

T1

201

T2

16

T4

21

enabled

disabled

83

1

T23

2

T25

1

T129

1

disabled

disabled

140

1

T1

1

T23

1

T25

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14842

1

T1

139

T2

24

T3

386

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1190	1			T1	21		T5	2		T6	3
key_invalid	sha2_none	853	1			T1	11		T4	2		T5	1
key_invalid	sha2_512	855	1			T1	12		T2	1		T4	1
key_invalid	sha2_384	883	1			T1	14		T2	1		T4	5
key_invalid	sha2_256	877	1			T1	8		T4	1		T5	1
key_none	sha2_invalid	538	1			T1	8		T2	1		T4	2
key_none	sha2_none	564	1			T1	6		T5	3		T6	3
key_none	sha2_512	2574	1			T1	13		T2	1		T5	3
key_none	sha2_384	2578	1			T1	12		T2	2		T3	386
key_none	sha2_256	1589	1			T1	6		T5	1		T15	3
key_1024	sha2_invalid	556	1			T1	4		T2	4		T6	2
key_1024	sha2_none	551	1			T1	6		T2	1		T5	2
key_1024	sha2_512	1776	1			T1	11		T2	2		T4	2
key_1024	sha2_384	949	1			T1	8		T2	1		T4	2
key_512	sha2_invalid	565	1			T1	6		T2	2		T4	4
key_512	sha2_none	545	1			T1	7		T2	1		T4	2
key_512	sha2_512	670	1			T1	13		T5	2		T9	2
key_512	sha2_384	1276	1			T1	13		T2	3		T4	2
key_512	sha2_256	893	1			T1	7		T2	2		T4	3
key_384	sha2_invalid	514	1			T1	5		T2	1		T5	2
key_384	sha2_none	609	1			T1	7		T2	1		T4	1
key_384	sha2_512	643	1			T1	9		T2	1		T4	2
key_384	sha2_384	629	1			T1	8		T2	1		T5	1
key_384	sha2_256	1106	1			T1	5		T2	1		T5	1
key_256	sha2_invalid	562	1			T1	11		T2	1		T4	1
key_256	sha2_none	550	1			T1	5		T2	1		T5	1
key_256	sha2_512	673	1			T1	12		T2	2		T4	2
key_256	sha2_384	651	1			T1	9		T2	2		T5	3
key_256	sha2_256	813	1			T1	22		T2	1		T4	1
key_128	sha2_invalid	534	1			T1	8		T2	2		T4	2
key_128	sha2_none	574	1			T1	8		T2	1		T4	1
key_128	sha2_512	687	1			T1	12		T2	1		T4	1
key_128	sha2_384	656	1			T1	11		T6	2		T23	7
key_128	sha2_256	665	1			T1	13		T2	1		T4	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

607

1

T1

5

T4

1

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1190	1			T1	21		T5	2		T6	3
key_invalid	sha2_none	853	1			T1	11		T4	2		T5	1
key_invalid	sha2_512	855	1			T1	12		T2	1		T4	1
key_invalid	sha2_384	883	1			T1	14		T2	1		T4	5
key_invalid	sha2_256	877	1			T1	8		T4	1		T5	1
key_none	sha2_invalid	538	1			T1	8		T2	1		T4	2
key_none	sha2_none	564	1			T1	6		T5	3		T6	3
key_none	sha2_512	2574	1			T1	13		T2	1		T5	3
key_none	sha2_384	2578	1			T1	12		T2	2		T3	386
key_none	sha2_256	1589	1			T1	6		T5	1		T15	3
key_1024	sha2_invalid	556	1			T1	4		T2	4		T6	2
key_1024	sha2_none	551	1			T1	6		T2	1		T5	2
key_1024	sha2_512	1776	1			T1	11		T2	2		T4	2
key_1024	sha2_384	949	1			T1	8		T2	1		T4	2
key_1024	sha2_256	607	1			T1	5		T4	1		T5	1
key_512	sha2_invalid	565	1			T1	6		T2	2		T4	4
key_512	sha2_none	545	1			T1	7		T2	1		T4	2
key_512	sha2_512	670	1			T1	13		T5	2		T9	2
key_512	sha2_384	1276	1			T1	13		T2	3		T4	2
key_512	sha2_256	893	1			T1	7		T2	2		T4	3
key_384	sha2_invalid	514	1			T1	5		T2	1		T5	2
key_384	sha2_none	609	1			T1	7		T2	1		T4	1
key_384	sha2_512	643	1			T1	9		T2	1		T4	2
key_384	sha2_384	629	1			T1	8		T2	1		T5	1
key_384	sha2_256	1106	1			T1	5		T2	1		T5	1
key_256	sha2_invalid	562	1			T1	11		T2	1		T4	1
key_256	sha2_none	550	1			T1	5		T2	1		T5	1
key_256	sha2_512	673	1			T1	12		T2	2		T4	2
key_256	sha2_384	651	1			T1	9		T2	2		T5	3
key_256	sha2_256	813	1			T1	22		T2	1		T4	1
key_128	sha2_invalid	534	1			T1	8		T2	2		T4	2
key_128	sha2_none	574	1			T1	8		T2	1		T4	1
key_128	sha2_512	687	1			T1	12		T2	1		T4	1
key_128	sha2_384	656	1			T1	11		T6	2		T23	7
key_128	sha2_256	665	1			T1	13		T2	1		T4	1