Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 659
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T536 /workspace/coverage/cover_reg_top/6.hmac_intr_test.654449225 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:33 PM PDT 24 43224984 ps
T537 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4107921561 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:12 PM PDT 24 66434904 ps
T538 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3806715287 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 41987316 ps
T539 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3191905037 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:32 PM PDT 24 24924569 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.306611077 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:38 PM PDT 24 35342348 ps
T103 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.943816659 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:17 PM PDT 24 267469599 ps
T104 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2591180701 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:38 PM PDT 24 157151541 ps
T105 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1862559766 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:37 PM PDT 24 706117099 ps
T540 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3574682322 Jul 18 06:45:24 PM PDT 24 Jul 18 06:45:31 PM PDT 24 69552864 ps
T60 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4002890802 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:18 PM PDT 24 1479255537 ps
T61 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3139913798 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:15 PM PDT 24 153120890 ps
T106 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.63560504 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:15 PM PDT 24 90763263 ps
T107 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3989463930 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:10 PM PDT 24 109982126 ps
T541 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.515448770 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:40 PM PDT 24 277861344 ps
T108 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2113088654 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:34 PM PDT 24 14852140 ps
T542 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4050058095 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:14 PM PDT 24 38584108 ps
T543 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1167715415 Jul 18 06:46:04 PM PDT 24 Jul 18 07:02:07 PM PDT 24 90264823623 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.683071893 Jul 18 06:45:30 PM PDT 24 Jul 18 06:45:38 PM PDT 24 62846197 ps
T120 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3607050719 Jul 18 06:45:12 PM PDT 24 Jul 18 06:45:22 PM PDT 24 428389613 ps
T545 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4209468435 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:34 PM PDT 24 72703867 ps
T546 /workspace/coverage/cover_reg_top/7.hmac_intr_test.703095156 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:34 PM PDT 24 16401546 ps
T547 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1917725597 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 80414201 ps
T548 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1556635260 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:14 PM PDT 24 18391804 ps
T549 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3955970279 Jul 18 06:45:12 PM PDT 24 Jul 18 06:45:18 PM PDT 24 18819657 ps
T550 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2414227157 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:16 PM PDT 24 34359955 ps
T109 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2514406377 Jul 18 06:46:09 PM PDT 24 Jul 18 06:46:18 PM PDT 24 41823644 ps
T87 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3268992199 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:37 PM PDT 24 202729594 ps
T125 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3124432505 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:34 PM PDT 24 161204216 ps
T88 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3720445438 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:08 PM PDT 24 27742905 ps
T551 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3606007178 Jul 18 06:46:04 PM PDT 24 Jul 18 06:46:07 PM PDT 24 12904674 ps
T552 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.949756430 Jul 18 06:45:24 PM PDT 24 Jul 18 06:45:29 PM PDT 24 839617214 ps
T553 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3634939572 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:10 PM PDT 24 13710759 ps
T123 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1815605902 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:28 PM PDT 24 304270129 ps
T89 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.467449448 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:37 PM PDT 24 69512477 ps
T554 /workspace/coverage/cover_reg_top/38.hmac_intr_test.926555369 Jul 18 06:46:12 PM PDT 24 Jul 18 06:46:20 PM PDT 24 22931963 ps
T555 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3759769379 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:37 PM PDT 24 212308930 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1738194827 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:34 PM PDT 24 81760158 ps
T556 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2862691524 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 10793387 ps
T557 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2077362718 Jul 18 06:46:09 PM PDT 24 Jul 18 06:46:19 PM PDT 24 122383304 ps
T558 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2812205114 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:12 PM PDT 24 17081831 ps
T559 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1561987548 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:11 PM PDT 24 14961380 ps
T560 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3075922649 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:14 PM PDT 24 48052907 ps
T561 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.138948995 Jul 18 06:45:19 PM PDT 24 Jul 18 06:45:27 PM PDT 24 155076688 ps
T110 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2892497483 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:34 PM PDT 24 29368781 ps
T562 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4027232081 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:09 PM PDT 24 17312537 ps
T121 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3676768518 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:10 PM PDT 24 637060353 ps
T563 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.104913857 Jul 18 06:45:25 PM PDT 24 Jul 18 06:45:30 PM PDT 24 1038069215 ps
T564 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2238778402 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 98863104 ps
T565 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2388814515 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:20 PM PDT 24 102389330 ps
T566 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3335002259 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:15 PM PDT 24 86626109 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3313112341 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:11 PM PDT 24 32302812 ps
T567 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1363941521 Jul 18 06:45:24 PM PDT 24 Jul 18 06:45:30 PM PDT 24 58551577 ps
T568 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1308557803 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:12 PM PDT 24 14816406 ps
T124 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.273524267 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:11 PM PDT 24 289793804 ps
T569 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2923271909 Jul 18 06:45:25 PM PDT 24 Jul 18 06:45:30 PM PDT 24 67754733 ps
T570 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3291097514 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:38 PM PDT 24 283142861 ps
T571 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2886509674 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:33 PM PDT 24 338281898 ps
T572 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1904457025 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:19 PM PDT 24 30603682 ps
T573 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3270037457 Jul 18 06:45:19 PM PDT 24 Jul 18 06:45:29 PM PDT 24 362185192 ps
T574 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2942513684 Jul 18 06:54:09 PM PDT 24 Jul 18 06:54:20 PM PDT 24 63378438 ps
T92 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3080766491 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:13 PM PDT 24 67064885 ps
T93 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3661903660 Jul 18 06:45:33 PM PDT 24 Jul 18 06:45:38 PM PDT 24 154648397 ps
T575 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2205634350 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:37 PM PDT 24 78129698 ps
T128 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2564467878 Jul 18 06:45:17 PM PDT 24 Jul 18 06:45:23 PM PDT 24 85625330 ps
T576 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3584178849 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:12 PM PDT 24 14935420 ps
T577 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.152697826 Jul 18 06:45:26 PM PDT 24 Jul 18 06:47:53 PM PDT 24 14449516981 ps
T122 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.126527865 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:21 PM PDT 24 123341376 ps
T578 /workspace/coverage/cover_reg_top/30.hmac_intr_test.908882521 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:11 PM PDT 24 16094905 ps
T579 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3422893267 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:21 PM PDT 24 209631623 ps
T580 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2900897892 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:39 PM PDT 24 970565108 ps
T581 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1985187115 Jul 18 06:45:25 PM PDT 24 Jul 18 06:45:29 PM PDT 24 65404034 ps
T582 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3979863836 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:33 PM PDT 24 46777569 ps
T583 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1401436436 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:14 PM PDT 24 271857341 ps
T584 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3862260961 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:12 PM PDT 24 18959683 ps
T585 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3065078546 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:12 PM PDT 24 64180133 ps
T586 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2111415131 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:31 PM PDT 24 80428229 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1693672014 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:35 PM PDT 24 1038715251 ps
T587 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4116436474 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:37 PM PDT 24 104084140 ps
T588 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3482346267 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 32481657 ps
T589 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1963472453 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:16 PM PDT 24 351146972 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2124168344 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:17 PM PDT 24 68108028 ps
T591 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2430128806 Jul 18 06:46:20 PM PDT 24 Jul 18 06:46:23 PM PDT 24 30688436 ps
T592 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1503051739 Jul 18 06:45:12 PM PDT 24 Jul 18 06:45:19 PM PDT 24 33148012 ps
T593 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2387748588 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:30 PM PDT 24 27885087 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2303564218 Jul 18 06:45:19 PM PDT 24 Jul 18 06:45:24 PM PDT 24 17639943 ps
T594 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1706495202 Jul 18 06:45:24 PM PDT 24 Jul 18 06:45:28 PM PDT 24 88064747 ps
T595 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3663707677 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:11 PM PDT 24 189047414 ps
T596 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2500490525 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:18 PM PDT 24 30045427 ps
T597 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.302790365 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:11 PM PDT 24 113728915 ps
T598 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4079253987 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:37 PM PDT 24 1207510871 ps
T599 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1515192884 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:11 PM PDT 24 52266626 ps
T600 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3849072441 Jul 18 06:46:09 PM PDT 24 Jul 18 06:46:20 PM PDT 24 205684547 ps
T601 /workspace/coverage/cover_reg_top/47.hmac_intr_test.645146508 Jul 18 06:46:20 PM PDT 24 Jul 18 06:46:23 PM PDT 24 14283070 ps
T602 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2857784805 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:34 PM PDT 24 38820788 ps
T603 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4178157670 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:11 PM PDT 24 102908706 ps
T604 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4104896067 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:19 PM PDT 24 113191640 ps
T605 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1769830033 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:19 PM PDT 24 28912714 ps
T606 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2526303472 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:15 PM PDT 24 15187114 ps
T607 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1750837007 Jul 18 06:45:25 PM PDT 24 Jul 18 06:45:32 PM PDT 24 158671523 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.506710078 Jul 18 06:46:04 PM PDT 24 Jul 18 06:46:09 PM PDT 24 457290493 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3831646688 Jul 18 06:45:32 PM PDT 24 Jul 18 06:45:38 PM PDT 24 69466750 ps
T610 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2675377144 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:37 PM PDT 24 1650235651 ps
T611 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2730560765 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:31 PM PDT 24 72396410 ps
T126 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1298385703 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:15 PM PDT 24 92907185 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2895142684 Jul 18 06:45:09 PM PDT 24 Jul 18 06:45:23 PM PDT 24 2955072724 ps
T612 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2411766362 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:30 PM PDT 24 127084053 ps
T613 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3587346996 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:20 PM PDT 24 179080703 ps
T614 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2137406305 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:16 PM PDT 24 310795180 ps
T615 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1783078884 Jul 18 06:46:08 PM PDT 24 Jul 18 06:53:56 PM PDT 24 62617188826 ps
T616 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4130008782 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 63077498 ps
T97 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1591089895 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:34 PM PDT 24 20236617 ps
T98 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1936828587 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:12 PM PDT 24 25848999 ps
T99 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3349659161 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:36 PM PDT 24 35220859 ps
T617 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4257712373 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:39 PM PDT 24 208134337 ps
T618 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4118431066 Jul 18 06:46:03 PM PDT 24 Jul 18 06:46:06 PM PDT 24 168890617 ps
T619 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3188280074 Jul 18 06:45:19 PM PDT 24 Jul 18 06:45:24 PM PDT 24 61757803 ps
T620 /workspace/coverage/cover_reg_top/48.hmac_intr_test.312142716 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 11142931 ps
T621 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3052016254 Jul 18 06:46:09 PM PDT 24 Jul 18 06:46:17 PM PDT 24 72462591 ps
T622 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1583466198 Jul 18 06:46:06 PM PDT 24 Jul 18 06:46:11 PM PDT 24 58163157 ps
T100 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2776594280 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:41 PM PDT 24 414757613 ps
T127 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3689663842 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:18 PM PDT 24 265923317 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3669910022 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:37 PM PDT 24 50000921 ps
T624 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3506702482 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:38 PM PDT 24 112055426 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3200299480 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:41 PM PDT 24 452190120 ps
T626 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1483030170 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:14 PM PDT 24 19961017 ps
T627 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3836227164 Jul 18 06:46:07 PM PDT 24 Jul 18 07:02:04 PM PDT 24 205781896386 ps
T628 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3358301782 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:21 PM PDT 24 169840935 ps
T629 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3041112261 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:19 PM PDT 24 201330472 ps
T630 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3617959685 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:33 PM PDT 24 30146006 ps
T631 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3897564489 Jul 18 06:45:32 PM PDT 24 Jul 18 06:45:39 PM PDT 24 409710409 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3512929632 Jul 18 06:46:07 PM PDT 24 Jul 18 06:46:14 PM PDT 24 71407400 ps
T101 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1141130227 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:34 PM PDT 24 19055378 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1758819894 Jul 18 06:45:25 PM PDT 24 Jul 18 06:45:30 PM PDT 24 28029098 ps
T634 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3326107551 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:30 PM PDT 24 13130474 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.5843073 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:09 PM PDT 24 198696498 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1746145259 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:11 PM PDT 24 200313562 ps
T637 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3808698005 Jul 18 06:46:04 PM PDT 24 Jul 18 06:46:06 PM PDT 24 40668529 ps
T638 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3921688676 Jul 18 06:46:12 PM PDT 24 Jul 18 06:46:19 PM PDT 24 101217930 ps
T639 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4158797306 Jul 18 06:45:26 PM PDT 24 Jul 18 06:45:35 PM PDT 24 132365947 ps
T640 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3564805712 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:36 PM PDT 24 124667529 ps
T641 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3849895650 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:08 PM PDT 24 11060372 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2538967991 Jul 18 06:45:30 PM PDT 24 Jul 18 06:45:51 PM PDT 24 390225653 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3953388597 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:40 PM PDT 24 210319885 ps
T644 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.157729442 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:17 PM PDT 24 53709022 ps
T645 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2656857342 Jul 18 06:45:28 PM PDT 24 Jul 18 06:45:35 PM PDT 24 21594702 ps
T646 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.715952733 Jul 18 06:46:04 PM PDT 24 Jul 18 06:46:07 PM PDT 24 143945436 ps
T647 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1614093347 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:27 PM PDT 24 12396278 ps
T648 /workspace/coverage/cover_reg_top/11.hmac_intr_test.128849981 Jul 18 06:45:58 PM PDT 24 Jul 18 06:46:01 PM PDT 24 32747820 ps
T649 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2075557503 Jul 18 06:46:05 PM PDT 24 Jul 18 06:46:08 PM PDT 24 17944268 ps
T650 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.425005272 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:16 PM PDT 24 190504871 ps
T651 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.809207643 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:15 PM PDT 24 303145360 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1238013404 Jul 18 06:45:31 PM PDT 24 Jul 18 06:45:38 PM PDT 24 363092534 ps
T653 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1358724638 Jul 18 06:45:29 PM PDT 24 Jul 18 06:45:38 PM PDT 24 247718327 ps
T654 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3888043994 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:33 PM PDT 24 98602959 ps
T655 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4233398888 Jul 18 06:46:10 PM PDT 24 Jul 18 06:46:18 PM PDT 24 19013474 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_intr_test.380156249 Jul 18 06:45:19 PM PDT 24 Jul 18 06:45:24 PM PDT 24 26104452 ps
T657 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3618242234 Jul 18 06:45:27 PM PDT 24 Jul 18 06:45:33 PM PDT 24 31172440 ps
T658 /workspace/coverage/cover_reg_top/32.hmac_intr_test.5962652 Jul 18 06:46:11 PM PDT 24 Jul 18 06:46:18 PM PDT 24 17070259 ps
T659 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1422305337 Jul 18 06:46:08 PM PDT 24 Jul 18 06:46:15 PM PDT 24 59732025 ps

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.443513950
Short name T1
Test name
Test status
Simulation time 219393921504 ps
CPU time 2181.57 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 06:12:41 PM PDT 24
Peak memory 706216 kb
Host smart-b6ee849c-c4a0-4962-aa91-70efce998cc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443513950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.443513950
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1985856117
Short name T27
Test name
Test status
Simulation time 2330803787 ps
CPU time 342.74 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:42:51 PM PDT 24
Peak memory 662648 kb
Host smart-ca1d85a0-5d68-4742-9754-d9720b8e257a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985856117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1985856117
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3660406490
Short name T10
Test name
Test status
Simulation time 1437747471282 ps
CPU time 10632.7 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 08:33:57 PM PDT 24
Peak memory 960884 kb
Host smart-e6671098-3f34-4833-a1d9-f1c3bb0475ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660406490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3660406490
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2876903977
Short name T135
Test name
Test status
Simulation time 5405445515 ps
CPU time 156.61 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:39:31 PM PDT 24
Peak memory 200312 kb
Host smart-838351c1-c38f-46fa-8254-e9ce5256980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876903977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2876903977
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1741864087
Short name T12
Test name
Test status
Simulation time 143584949170 ps
CPU time 4681.38 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 06:54:38 PM PDT 24
Peak memory 870984 kb
Host smart-b3e65028-5c05-4bea-adcb-7da3f361c0ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741864087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1741864087
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4002890802
Short name T60
Test name
Test status
Simulation time 1479255537 ps
CPU time 3.12 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 199580 kb
Host smart-c68e55aa-e36d-45d5-bd00-d12e35053d91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002890802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4002890802
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2882490519
Short name T23
Test name
Test status
Simulation time 40812720658 ps
CPU time 1505.5 seconds
Started Jul 18 05:36:36 PM PDT 24
Finished Jul 18 06:01:44 PM PDT 24
Peak memory 551960 kb
Host smart-0b5d4cba-4b09-4f92-a831-dfd9d761cbd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882490519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2882490519
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.245710564
Short name T47
Test name
Test status
Simulation time 564288743 ps
CPU time 0.96 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:41 PM PDT 24
Peak memory 219588 kb
Host smart-eccc797d-c969-4f7a-b168-593f3ac318e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245710564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.245710564
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/48.hmac_stress_all.994876042
Short name T67
Test name
Test status
Simulation time 84969693010 ps
CPU time 1298.83 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:58:56 PM PDT 24
Peak memory 464704 kb
Host smart-d514a252-4425-49f4-be98-56a3432d00dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994876042 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.994876042
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.257876032
Short name T17
Test name
Test status
Simulation time 1532720783 ps
CPU time 18.59 seconds
Started Jul 18 05:37:27 PM PDT 24
Finished Jul 18 05:37:49 PM PDT 24
Peak memory 200256 kb
Host smart-accc8ade-53fe-4ed3-83a6-93e0d2af2063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257876032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.257876032
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_smoke.2102212776
Short name T16
Test name
Test status
Simulation time 4047624429 ps
CPU time 9.87 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:37:16 PM PDT 24
Peak memory 200244 kb
Host smart-1c18ca69-e499-43d7-9cbe-24e34f25855c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102212776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2102212776
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3720445438
Short name T88
Test name
Test status
Simulation time 27742905 ps
CPU time 0.86 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:08 PM PDT 24
Peak memory 199324 kb
Host smart-8faebf5b-5d8a-461c-8055-7bd4fec7592a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720445438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3720445438
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3139913798
Short name T61
Test name
Test status
Simulation time 153120890 ps
CPU time 3.17 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 199740 kb
Host smart-538ff443-67e3-4bb8-945b-859065c63bed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139913798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3139913798
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2338037823
Short name T32
Test name
Test status
Simulation time 19996020 ps
CPU time 0.61 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:00 PM PDT 24
Peak memory 195720 kb
Host smart-035a7d3c-888a-4a1d-8301-e3f406535eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338037823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2338037823
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3182675692
Short name T140
Test name
Test status
Simulation time 2385796871 ps
CPU time 61.5 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:38:00 PM PDT 24
Peak memory 200284 kb
Host smart-3aa26e92-1e6f-42e6-86cc-745a3c1b9a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182675692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3182675692
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3607050719
Short name T120
Test name
Test status
Simulation time 428389613 ps
CPU time 4.14 seconds
Started Jul 18 06:45:12 PM PDT 24
Finished Jul 18 06:45:22 PM PDT 24
Peak memory 199748 kb
Host smart-4a8d0411-b465-49f9-8d09-88efe52b1e11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607050719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3607050719
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1298385703
Short name T126
Test name
Test status
Simulation time 92907185 ps
CPU time 3.04 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 199748 kb
Host smart-238d75b5-466f-4396-b03c-68eb2bc7e2e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298385703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1298385703
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2895142684
Short name T96
Test name
Test status
Simulation time 2955072724 ps
CPU time 8.51 seconds
Started Jul 18 06:45:09 PM PDT 24
Finished Jul 18 06:45:23 PM PDT 24
Peak memory 199780 kb
Host smart-15d8e875-d989-4593-8fd3-0b44f9e66027
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895142684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2895142684
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3270037457
Short name T573
Test name
Test status
Simulation time 362185192 ps
CPU time 5.8 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:29 PM PDT 24
Peak memory 199792 kb
Host smart-1d672a7a-c804-42bd-ad14-5787af7516c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270037457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3270037457
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3955970279
Short name T549
Test name
Test status
Simulation time 18819657 ps
CPU time 0.86 seconds
Started Jul 18 06:45:12 PM PDT 24
Finished Jul 18 06:45:18 PM PDT 24
Peak memory 198792 kb
Host smart-a38c39b6-0b07-4d56-8848-d940ea7d3055
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955970279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3955970279
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2726397089
Short name T533
Test name
Test status
Simulation time 195614688 ps
CPU time 2.38 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:25 PM PDT 24
Peak memory 199804 kb
Host smart-feea6733-6e1c-4d45-990e-3d6ceaee9269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726397089 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2726397089
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2303564218
Short name T95
Test name
Test status
Simulation time 17639943 ps
CPU time 0.89 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:24 PM PDT 24
Peak memory 199396 kb
Host smart-c780a4ca-b8de-4b1b-b840-f162939dd000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303564218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2303564218
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.380156249
Short name T656
Test name
Test status
Simulation time 26104452 ps
CPU time 0.57 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:24 PM PDT 24
Peak memory 194680 kb
Host smart-5421cb8b-45d5-4c70-b84f-58622a41a666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380156249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.380156249
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3188280074
Short name T619
Test name
Test status
Simulation time 61757803 ps
CPU time 1.19 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:24 PM PDT 24
Peak memory 199596 kb
Host smart-ddb3c5e2-8c72-478e-84bf-f2ae7c6e61b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188280074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3188280074
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.138948995
Short name T561
Test name
Test status
Simulation time 155076688 ps
CPU time 3.57 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:27 PM PDT 24
Peak memory 199800 kb
Host smart-b0d57ed6-1c3e-45f0-b788-7313eb28e8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138948995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.138948995
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.683071893
Short name T544
Test name
Test status
Simulation time 62846197 ps
CPU time 2.93 seconds
Started Jul 18 06:45:30 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 198564 kb
Host smart-ea9c1b15-237f-43fb-9c6c-9cca68ec5a17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683071893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.683071893
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2776594280
Short name T100
Test name
Test status
Simulation time 414757613 ps
CPU time 9.67 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:41 PM PDT 24
Peak memory 198792 kb
Host smart-203960fa-431f-4ab6-92cc-0ef6d42b77f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776594280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2776594280
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1738194827
Short name T90
Test name
Test status
Simulation time 81760158 ps
CPU time 0.97 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 199528 kb
Host smart-0d9d1ee6-6c90-4a0c-8b14-f6f5a6d66da7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738194827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1738194827
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.152697826
Short name T577
Test name
Test status
Simulation time 14449516981 ps
CPU time 142.45 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 215524 kb
Host smart-0b0c0c85-ac23-4e96-98b4-d426c973718f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152697826 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.152697826
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3661903660
Short name T93
Test name
Test status
Simulation time 154648397 ps
CPU time 1.01 seconds
Started Jul 18 06:45:33 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199516 kb
Host smart-54815992-888e-4059-9e9b-44f45a7950e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661903660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3661903660
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1985187115
Short name T581
Test name
Test status
Simulation time 65404034 ps
CPU time 0.58 seconds
Started Jul 18 06:45:25 PM PDT 24
Finished Jul 18 06:45:29 PM PDT 24
Peak memory 194648 kb
Host smart-bfa3f01b-dac9-418c-a70a-95e4db47e763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985187115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1985187115
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.104913857
Short name T563
Test name
Test status
Simulation time 1038069215 ps
CPU time 2.24 seconds
Started Jul 18 06:45:25 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 199712 kb
Host smart-afd541bc-cd51-4d5d-9800-a4cee1672ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104913857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.104913857
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1503051739
Short name T592
Test name
Test status
Simulation time 33148012 ps
CPU time 1.72 seconds
Started Jul 18 06:45:12 PM PDT 24
Finished Jul 18 06:45:19 PM PDT 24
Peak memory 199756 kb
Host smart-2759ab22-cbe3-4352-b16e-bae1bc298952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503051739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1503051739
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2886509674
Short name T571
Test name
Test status
Simulation time 338281898 ps
CPU time 1.75 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:33 PM PDT 24
Peak memory 199796 kb
Host smart-e878a661-c9f7-4e6d-8d77-4dee340dd088
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886509674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2886509674
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4107921561
Short name T537
Test name
Test status
Simulation time 66434904 ps
CPU time 1.2 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 199556 kb
Host smart-b969c615-ecae-454e-9b72-fe7a139f5740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107921561 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4107921561
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3313112341
Short name T91
Test name
Test status
Simulation time 32302812 ps
CPU time 0.94 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 199576 kb
Host smart-68498180-c1df-4f4d-9293-8a74e48e4680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313112341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3313112341
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3606007178
Short name T551
Test name
Test status
Simulation time 12904674 ps
CPU time 0.58 seconds
Started Jul 18 06:46:04 PM PDT 24
Finished Jul 18 06:46:07 PM PDT 24
Peak memory 194576 kb
Host smart-0c8d79d7-e47a-4b7c-acd4-4f3315fe91a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606007178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3606007178
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.5843073
Short name T635
Test name
Test status
Simulation time 198696498 ps
CPU time 1.2 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:09 PM PDT 24
Peak memory 198304 kb
Host smart-5c2404dc-0ec6-44db-8476-0def8d40f7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5843073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_o
utstanding.5843073
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.302790365
Short name T597
Test name
Test status
Simulation time 113728915 ps
CPU time 2.21 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 199748 kb
Host smart-de118ec0-b38d-42c9-ade6-6ad5b7314f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302790365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.302790365
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3676768518
Short name T121
Test name
Test status
Simulation time 637060353 ps
CPU time 2.94 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:10 PM PDT 24
Peak memory 199744 kb
Host smart-c8c9356f-a5ae-45b6-a6f5-48f84d1de799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676768518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3676768518
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.425005272
Short name T650
Test name
Test status
Simulation time 190504871 ps
CPU time 1.33 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:16 PM PDT 24
Peak memory 199768 kb
Host smart-9d1ee799-8758-43e0-9f75-fed453583a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425005272 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.425005272
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1422305337
Short name T659
Test name
Test status
Simulation time 59732025 ps
CPU time 0.98 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 199476 kb
Host smart-28c95b04-31bf-4f45-b3d2-667dcde7d510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422305337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1422305337
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.128849981
Short name T648
Test name
Test status
Simulation time 32747820 ps
CPU time 0.58 seconds
Started Jul 18 06:45:58 PM PDT 24
Finished Jul 18 06:46:01 PM PDT 24
Peak memory 194752 kb
Host smart-98ff3f33-bbd5-415e-b999-080f6ea4fbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128849981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.128849981
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2514406377
Short name T109
Test name
Test status
Simulation time 41823644 ps
CPU time 1.12 seconds
Started Jul 18 06:46:09 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 199772 kb
Host smart-dc0b688e-3b02-446b-8832-2817c6f41354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514406377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2514406377
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.715952733
Short name T646
Test name
Test status
Simulation time 143945436 ps
CPU time 1.66 seconds
Started Jul 18 06:46:04 PM PDT 24
Finished Jul 18 06:46:07 PM PDT 24
Peak memory 199736 kb
Host smart-e8aad9c7-df42-4e1c-baf6-df0066b8ff2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715952733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.715952733
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3836227164
Short name T627
Test name
Test status
Simulation time 205781896386 ps
CPU time 950.73 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 07:02:04 PM PDT 24
Peak memory 216224 kb
Host smart-90e7c97c-8445-4760-bb3e-df17dec21ebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836227164 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3836227164
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2075557503
Short name T649
Test name
Test status
Simulation time 17944268 ps
CPU time 0.84 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:08 PM PDT 24
Peak memory 199560 kb
Host smart-6396c70c-c91e-4cd1-b0ca-897671b63b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075557503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2075557503
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2812205114
Short name T558
Test name
Test status
Simulation time 17081831 ps
CPU time 0.62 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 194604 kb
Host smart-251b9633-af25-47fd-b8b7-46b0cffc42f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812205114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2812205114
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3989463930
Short name T107
Test name
Test status
Simulation time 109982126 ps
CPU time 2.34 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:10 PM PDT 24
Peak memory 199720 kb
Host smart-322dbd35-abb6-4086-85b7-4f819e18286d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989463930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3989463930
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3663707677
Short name T595
Test name
Test status
Simulation time 189047414 ps
CPU time 2.19 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 199668 kb
Host smart-97d496e0-1fab-47ab-b556-10364bb5e2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663707677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3663707677
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1401436436
Short name T583
Test name
Test status
Simulation time 271857341 ps
CPU time 4.3 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:14 PM PDT 24
Peak memory 199752 kb
Host smart-6d9dccf2-03ee-4d5e-98a2-5c12cbecd900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401436436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1401436436
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2124168344
Short name T590
Test name
Test status
Simulation time 68108028 ps
CPU time 2.17 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:17 PM PDT 24
Peak memory 207904 kb
Host smart-a8eb24d5-e903-404d-acf0-354b732df20e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124168344 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2124168344
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1515192884
Short name T599
Test name
Test status
Simulation time 52266626 ps
CPU time 0.57 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 194612 kb
Host smart-27cb6edb-61cc-4839-a157-9d89825b269c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515192884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1515192884
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2137406305
Short name T614
Test name
Test status
Simulation time 310795180 ps
CPU time 1.84 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:16 PM PDT 24
Peak memory 199740 kb
Host smart-7411428b-8fd6-4531-968a-aa326a0de964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137406305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2137406305
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.506710078
Short name T608
Test name
Test status
Simulation time 457290493 ps
CPU time 3.39 seconds
Started Jul 18 06:46:04 PM PDT 24
Finished Jul 18 06:46:09 PM PDT 24
Peak memory 199860 kb
Host smart-4d057aa6-00aa-4e84-a7bb-9ac0fabc6d35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506710078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.506710078
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3512929632
Short name T632
Test name
Test status
Simulation time 71407400 ps
CPU time 1.28 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:14 PM PDT 24
Peak memory 199572 kb
Host smart-e4d4e531-ae47-40ff-bc28-539bc2feb609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512929632 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3512929632
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4130008782
Short name T616
Test name
Test status
Simulation time 63077498 ps
CPU time 0.93 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 199564 kb
Host smart-4203e77a-89be-4939-a532-1afd1338ea0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130008782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4130008782
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1583466198
Short name T622
Test name
Test status
Simulation time 58163157 ps
CPU time 0.56 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 194708 kb
Host smart-daffa1f2-a231-4883-8d95-b2c52da37ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583466198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1583466198
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4118431066
Short name T618
Test name
Test status
Simulation time 168890617 ps
CPU time 2.28 seconds
Started Jul 18 06:46:03 PM PDT 24
Finished Jul 18 06:46:06 PM PDT 24
Peak memory 199744 kb
Host smart-b2cc95fb-1cae-4acd-9758-f3e59e79a494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118431066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4118431066
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1963472453
Short name T589
Test name
Test status
Simulation time 351146972 ps
CPU time 1.52 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:16 PM PDT 24
Peak memory 199744 kb
Host smart-3e0de09e-1f36-4755-bd35-ba3e11560350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963472453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1963472453
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3689663842
Short name T127
Test name
Test status
Simulation time 265923317 ps
CPU time 4.2 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 199776 kb
Host smart-c6a474f3-1c6c-4943-b1b7-bc263ac67b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689663842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3689663842
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2077362718
Short name T557
Test name
Test status
Simulation time 122383304 ps
CPU time 2.22 seconds
Started Jul 18 06:46:09 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 199784 kb
Host smart-c9ca71d1-a157-46ef-ba57-342ad7a2556b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077362718 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2077362718
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.809207643
Short name T651
Test name
Test status
Simulation time 303145360 ps
CPU time 0.91 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 199388 kb
Host smart-d4d75f6e-9db9-44b3-a1e9-e39a8f78e0b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809207643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.809207643
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3584178849
Short name T576
Test name
Test status
Simulation time 14935420 ps
CPU time 0.61 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 194616 kb
Host smart-5466d90e-09fd-4eaf-a093-25b77f0a1d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584178849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3584178849
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.943816659
Short name T103
Test name
Test status
Simulation time 267469599 ps
CPU time 2.23 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:17 PM PDT 24
Peak memory 199704 kb
Host smart-1aa2462d-f9d0-4195-a78c-02515818a9fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943816659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.943816659
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.157729442
Short name T644
Test name
Test status
Simulation time 53709022 ps
CPU time 1.45 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:17 PM PDT 24
Peak memory 199724 kb
Host smart-0af9d290-5283-4a3b-a4cc-dc24d0da1d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157729442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.157729442
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1783078884
Short name T615
Test name
Test status
Simulation time 62617188826 ps
CPU time 459.93 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:53:56 PM PDT 24
Peak memory 215400 kb
Host smart-659277df-56b5-4871-970d-105196b050f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783078884 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1783078884
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3080766491
Short name T92
Test name
Test status
Simulation time 67064885 ps
CPU time 0.71 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:13 PM PDT 24
Peak memory 197676 kb
Host smart-74626ff1-a2dd-414f-8c4a-c6d128919d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080766491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3080766491
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1917725597
Short name T547
Test name
Test status
Simulation time 80414201 ps
CPU time 0.6 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194608 kb
Host smart-6d22a33b-27ef-4286-bb61-4e7207fc66a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917725597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1917725597
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3808698005
Short name T637
Test name
Test status
Simulation time 40668529 ps
CPU time 1.07 seconds
Started Jul 18 06:46:04 PM PDT 24
Finished Jul 18 06:46:06 PM PDT 24
Peak memory 199536 kb
Host smart-3c0f56b0-13ba-4293-ba44-d4302f72602b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808698005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3808698005
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1746145259
Short name T636
Test name
Test status
Simulation time 200313562 ps
CPU time 1.99 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 199760 kb
Host smart-17cd1d47-7bf4-4b44-a312-2c283a9d3e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746145259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1746145259
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.273524267
Short name T124
Test name
Test status
Simulation time 289793804 ps
CPU time 2.85 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 199760 kb
Host smart-a504e1c3-04f4-4d50-82e6-ce0e442ca610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273524267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.273524267
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3041112261
Short name T629
Test name
Test status
Simulation time 201330472 ps
CPU time 1.48 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 199948 kb
Host smart-1f236879-f5cd-4937-a9c5-3f3960c29a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041112261 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3041112261
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4104896067
Short name T604
Test name
Test status
Simulation time 113191640 ps
CPU time 0.71 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 197736 kb
Host smart-7a8e939a-7e39-4526-8395-de490fb38319
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104896067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.4104896067
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2862691524
Short name T556
Test name
Test status
Simulation time 10793387 ps
CPU time 0.6 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194572 kb
Host smart-ea77f63c-19ae-4249-ae86-0d4f3dcc8863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862691524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2862691524
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2388814515
Short name T565
Test name
Test status
Simulation time 102389330 ps
CPU time 1.78 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:20 PM PDT 24
Peak memory 199508 kb
Host smart-a216261f-8ecb-475b-99c9-539255f3fc52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388814515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2388814515
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3849072441
Short name T600
Test name
Test status
Simulation time 205684547 ps
CPU time 4.05 seconds
Started Jul 18 06:46:09 PM PDT 24
Finished Jul 18 06:46:20 PM PDT 24
Peak memory 199756 kb
Host smart-c1ba2e4c-2997-43a8-8ff6-8d0130ead2db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849072441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3849072441
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3950400660
Short name T59
Test name
Test status
Simulation time 126409138 ps
CPU time 3.78 seconds
Started Jul 18 06:46:09 PM PDT 24
Finished Jul 18 06:46:20 PM PDT 24
Peak memory 199800 kb
Host smart-b8ba5418-d3fa-4227-b7ce-e1e277e1b191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950400660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3950400660
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3065078546
Short name T585
Test name
Test status
Simulation time 64180133 ps
CPU time 1.11 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 199640 kb
Host smart-772db5cc-00bb-407d-9972-26b8bcb0293f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065078546 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3065078546
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1769830033
Short name T605
Test name
Test status
Simulation time 28912714 ps
CPU time 0.82 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 199020 kb
Host smart-70c53cf4-affb-430a-ada5-856ec472c947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769830033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1769830033
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.513845672
Short name T531
Test name
Test status
Simulation time 14658606 ps
CPU time 0.6 seconds
Started Jul 18 06:46:13 PM PDT 24
Finished Jul 18 06:46:20 PM PDT 24
Peak memory 194584 kb
Host smart-2cd94f90-660f-498a-bdeb-bcb6f9519ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513845672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.513845672
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3587346996
Short name T613
Test name
Test status
Simulation time 179080703 ps
CPU time 2.28 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:20 PM PDT 24
Peak memory 198564 kb
Host smart-24707a77-7826-4166-a9c6-496a87befa46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587346996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3587346996
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3422893267
Short name T579
Test name
Test status
Simulation time 209631623 ps
CPU time 3.75 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:21 PM PDT 24
Peak memory 199764 kb
Host smart-5b9fbd2e-9212-4e88-b1ed-10d0976fa078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422893267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3422893267
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3358301782
Short name T628
Test name
Test status
Simulation time 169840935 ps
CPU time 3.07 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:21 PM PDT 24
Peak memory 199712 kb
Host smart-dcf7095c-c184-4d0a-a309-5cf10499c3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358301782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3358301782
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1091558955
Short name T532
Test name
Test status
Simulation time 233096322489 ps
CPU time 848.9 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 07:00:24 PM PDT 24
Peak memory 216220 kb
Host smart-b9ff0e18-8565-43b6-8726-cf028aca2bf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091558955 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1091558955
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1936828587
Short name T98
Test name
Test status
Simulation time 25848999 ps
CPU time 0.73 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 197780 kb
Host smart-fa9452d9-fba0-4936-8ae8-caa93d52a737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936828587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1936828587
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1483030170
Short name T626
Test name
Test status
Simulation time 19961017 ps
CPU time 0.59 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:14 PM PDT 24
Peak memory 194612 kb
Host smart-39341239-b86d-45c8-bc3e-589d10ba2256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483030170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1483030170
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.63560504
Short name T106
Test name
Test status
Simulation time 90763263 ps
CPU time 1.15 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 199732 kb
Host smart-95a81744-c255-4e5f-ad79-18fdc3e3e67b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63560504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_
outstanding.63560504
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2942513684
Short name T574
Test name
Test status
Simulation time 63378438 ps
CPU time 3.2 seconds
Started Jul 18 06:54:09 PM PDT 24
Finished Jul 18 06:54:20 PM PDT 24
Peak memory 199784 kb
Host smart-cb729432-4ad4-4189-ab4c-3489e2a2920c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942513684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2942513684
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.126527865
Short name T122
Test name
Test status
Simulation time 123341376 ps
CPU time 2.84 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:21 PM PDT 24
Peak memory 198696 kb
Host smart-a6cc8b0d-612d-4e69-81a8-68edfc9c6a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126527865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.126527865
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3759769379
Short name T555
Test name
Test status
Simulation time 212308930 ps
CPU time 5.11 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 199712 kb
Host smart-fd4b83d8-c370-4ddf-b201-5983c228410d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759769379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3759769379
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2538967991
Short name T642
Test name
Test status
Simulation time 390225653 ps
CPU time 15.39 seconds
Started Jul 18 06:45:30 PM PDT 24
Finished Jul 18 06:45:51 PM PDT 24
Peak memory 199728 kb
Host smart-f51f8f07-86db-4b6d-9378-d9a2e8127406
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538967991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2538967991
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1758819894
Short name T633
Test name
Test status
Simulation time 28029098 ps
CPU time 0.87 seconds
Started Jul 18 06:45:25 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 198956 kb
Host smart-42788312-6e3a-49f1-a656-9f87e6944bca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758819894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1758819894
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1706495202
Short name T594
Test name
Test status
Simulation time 88064747 ps
CPU time 1.35 seconds
Started Jul 18 06:45:24 PM PDT 24
Finished Jul 18 06:45:28 PM PDT 24
Peak memory 199808 kb
Host smart-50a5276f-2e8e-4d2c-ab75-9b0bd36e4014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706495202 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1706495202
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2111415131
Short name T586
Test name
Test status
Simulation time 80428229 ps
CPU time 0.7 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:31 PM PDT 24
Peak memory 197264 kb
Host smart-ef8b1fa9-f3c4-4c36-b250-e86b4b6640c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111415131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2111415131
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3618242234
Short name T657
Test name
Test status
Simulation time 31172440 ps
CPU time 0.56 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:33 PM PDT 24
Peak memory 194604 kb
Host smart-3fecb886-8291-474a-9c25-9cb601d281ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618242234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3618242234
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2591180701
Short name T104
Test name
Test status
Simulation time 157151541 ps
CPU time 2.41 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199616 kb
Host smart-1a690ce5-9bd9-4c9f-bfda-38678c2eb19e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591180701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2591180701
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3574682322
Short name T540
Test name
Test status
Simulation time 69552864 ps
CPU time 3.62 seconds
Started Jul 18 06:45:24 PM PDT 24
Finished Jul 18 06:45:31 PM PDT 24
Peak memory 199756 kb
Host smart-8d01aa75-e9d6-42b7-992f-c9a9bac1b96c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574682322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3574682322
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3124432505
Short name T125
Test name
Test status
Simulation time 161204216 ps
CPU time 3.04 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 199708 kb
Host smart-d1415787-8160-4185-b94a-91219c09a858
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124432505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3124432505
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3806715287
Short name T538
Test name
Test status
Simulation time 41987316 ps
CPU time 0.59 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194684 kb
Host smart-8558c95d-0ec5-42e5-a33f-1d67b32aa344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806715287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3806715287
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1904457025
Short name T572
Test name
Test status
Simulation time 30603682 ps
CPU time 0.65 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 194864 kb
Host smart-2a6d6760-900a-44a3-90d6-20046ffd3c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904457025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1904457025
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1308557803
Short name T568
Test name
Test status
Simulation time 14816406 ps
CPU time 0.63 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 194656 kb
Host smart-3a5572ec-f4db-48f6-86f7-e7051853917c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308557803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1308557803
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3849895650
Short name T641
Test name
Test status
Simulation time 11060372 ps
CPU time 0.55 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:08 PM PDT 24
Peak memory 194648 kb
Host smart-b6e6a1db-8da7-4567-b0b8-679c86094dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849895650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3849895650
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3634939572
Short name T553
Test name
Test status
Simulation time 13710759 ps
CPU time 0.61 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:10 PM PDT 24
Peak memory 194624 kb
Host smart-2ea1e470-a0b6-405d-9252-6b944c821aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634939572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3634939572
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4178157670
Short name T603
Test name
Test status
Simulation time 102908706 ps
CPU time 0.6 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 194696 kb
Host smart-f2d68ac7-94f2-4abc-a222-8ab36f27db25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178157670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4178157670
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2414227157
Short name T550
Test name
Test status
Simulation time 34359955 ps
CPU time 0.63 seconds
Started Jul 18 06:46:08 PM PDT 24
Finished Jul 18 06:46:16 PM PDT 24
Peak memory 194644 kb
Host smart-92c5e01f-98f9-4660-a677-165cc468555d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414227157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2414227157
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3075922649
Short name T560
Test name
Test status
Simulation time 48052907 ps
CPU time 0.63 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:14 PM PDT 24
Peak memory 194616 kb
Host smart-39073d48-af1d-46c5-a26c-b3143fcf6bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075922649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3075922649
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4233398888
Short name T655
Test name
Test status
Simulation time 19013474 ps
CPU time 0.62 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194692 kb
Host smart-788dc90f-9f97-437d-a592-376ed16ed5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233398888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4233398888
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3052016254
Short name T621
Test name
Test status
Simulation time 72462591 ps
CPU time 0.55 seconds
Started Jul 18 06:46:09 PM PDT 24
Finished Jul 18 06:46:17 PM PDT 24
Peak memory 194628 kb
Host smart-d130f6c9-bea7-4fa8-b379-f7d1451caf40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052016254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3052016254
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1693672014
Short name T94
Test name
Test status
Simulation time 1038715251 ps
CPU time 3.22 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:35 PM PDT 24
Peak memory 199692 kb
Host smart-78931ce0-693f-4f56-be6b-a4d9f2a6a002
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693672014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1693672014
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3200299480
Short name T625
Test name
Test status
Simulation time 452190120 ps
CPU time 5.2 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:41 PM PDT 24
Peak memory 199736 kb
Host smart-0dc82f00-dc59-4025-b68d-533630d87d9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200299480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3200299480
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.467449448
Short name T89
Test name
Test status
Simulation time 69512477 ps
CPU time 0.87 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 199528 kb
Host smart-90b51fe7-2e2c-48d2-af76-40a3a9b98b1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467449448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.467449448
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2730560765
Short name T611
Test name
Test status
Simulation time 72396410 ps
CPU time 1.25 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:31 PM PDT 24
Peak memory 199704 kb
Host smart-1bd67fa1-a51c-4d58-bc43-7ac7483166bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730560765 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2730560765
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1141130227
Short name T101
Test name
Test status
Simulation time 19055378 ps
CPU time 0.7 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 197312 kb
Host smart-67534366-c1d4-4582-91f2-e9bd17624581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141130227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1141130227
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3326107551
Short name T634
Test name
Test status
Simulation time 13130474 ps
CPU time 0.56 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 194576 kb
Host smart-43a8f5d9-0f32-47ec-8c94-9a654cabd09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326107551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3326107551
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.306611077
Short name T102
Test name
Test status
Simulation time 35342348 ps
CPU time 1.62 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199560 kb
Host smart-4c097e76-b6cc-4c25-b917-35e9ee997252
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306611077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.306611077
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.515448770
Short name T541
Test name
Test status
Simulation time 277861344 ps
CPU time 3.98 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:40 PM PDT 24
Peak memory 199796 kb
Host smart-08a3f19f-936d-4c20-ad74-312ffcd4e910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515448770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.515448770
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2564467878
Short name T128
Test name
Test status
Simulation time 85625330 ps
CPU time 2.74 seconds
Started Jul 18 06:45:17 PM PDT 24
Finished Jul 18 06:45:23 PM PDT 24
Peak memory 199800 kb
Host smart-5aec7cb6-c714-497f-a889-84b015b8ca9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564467878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2564467878
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.908882521
Short name T578
Test name
Test status
Simulation time 16094905 ps
CPU time 0.62 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 194612 kb
Host smart-bddd7880-49d1-457f-bbd1-e81f03c98faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908882521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.908882521
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2526303472
Short name T606
Test name
Test status
Simulation time 15187114 ps
CPU time 0.64 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 194600 kb
Host smart-d977c9d5-9771-4dc8-8984-1f1d609e1c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526303472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2526303472
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.5962652
Short name T658
Test name
Test status
Simulation time 17070259 ps
CPU time 0.6 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194704 kb
Host smart-393fce7f-94b1-42d0-b6a0-79fe68a8d92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5962652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.5962652
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3862260961
Short name T584
Test name
Test status
Simulation time 18959683 ps
CPU time 0.58 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:12 PM PDT 24
Peak memory 194716 kb
Host smart-4965b581-699f-4f00-b587-dac040722a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862260961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3862260961
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4027232081
Short name T562
Test name
Test status
Simulation time 17312537 ps
CPU time 0.64 seconds
Started Jul 18 06:46:05 PM PDT 24
Finished Jul 18 06:46:09 PM PDT 24
Peak memory 194660 kb
Host smart-8b762a8a-ac67-4df4-bdf4-c119ff51225d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027232081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4027232081
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2500490525
Short name T596
Test name
Test status
Simulation time 30045427 ps
CPU time 0.59 seconds
Started Jul 18 06:46:11 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194696 kb
Host smart-3c754c25-40e9-4deb-a474-643fed9eeecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500490525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2500490525
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3482346267
Short name T588
Test name
Test status
Simulation time 32481657 ps
CPU time 0.59 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194572 kb
Host smart-e03dd1d7-3a54-4aa3-82eb-5243354aa94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482346267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3482346267
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2238778402
Short name T564
Test name
Test status
Simulation time 98863104 ps
CPU time 0.62 seconds
Started Jul 18 06:46:10 PM PDT 24
Finished Jul 18 06:46:18 PM PDT 24
Peak memory 194552 kb
Host smart-bda0b87f-c420-42ea-83e5-f1eb40222501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238778402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2238778402
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.926555369
Short name T554
Test name
Test status
Simulation time 22931963 ps
CPU time 0.59 seconds
Started Jul 18 06:46:12 PM PDT 24
Finished Jul 18 06:46:20 PM PDT 24
Peak memory 194728 kb
Host smart-d3c9258b-49ee-468a-8c6c-0b1e92411f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926555369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.926555369
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3921688676
Short name T638
Test name
Test status
Simulation time 101217930 ps
CPU time 0.61 seconds
Started Jul 18 06:46:12 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 194716 kb
Host smart-27abde6c-2a97-44cb-a872-6cdb1f23160d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921688676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3921688676
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3953388597
Short name T643
Test name
Test status
Simulation time 210319885 ps
CPU time 5.48 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:40 PM PDT 24
Peak memory 198068 kb
Host smart-5e30129f-9011-4707-a272-f690c62117b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953388597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3953388597
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.569656325
Short name T534
Test name
Test status
Simulation time 761194445 ps
CPU time 11.28 seconds
Started Jul 18 06:45:24 PM PDT 24
Finished Jul 18 06:45:39 PM PDT 24
Peak memory 199732 kb
Host smart-f267bb06-c989-4c30-b731-a1c0314f30fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569656325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.569656325
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3617959685
Short name T630
Test name
Test status
Simulation time 30146006 ps
CPU time 0.73 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:33 PM PDT 24
Peak memory 197708 kb
Host smart-b57c09ec-1500-4c62-a32e-06639e4a5f85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617959685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3617959685
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3831646688
Short name T609
Test name
Test status
Simulation time 69466750 ps
CPU time 1.13 seconds
Started Jul 18 06:45:32 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199580 kb
Host smart-b2c21e26-20f7-4ea7-b1bb-261237b7ffa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831646688 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3831646688
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2411766362
Short name T612
Test name
Test status
Simulation time 127084053 ps
CPU time 0.95 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 199564 kb
Host smart-24d4e997-6aeb-431d-842f-32d6c17fbd2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411766362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2411766362
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2923271909
Short name T569
Test name
Test status
Simulation time 67754733 ps
CPU time 0.57 seconds
Started Jul 18 06:45:25 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 194772 kb
Host smart-014f6a5b-fdf4-4bc7-909c-0d2c80716237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923271909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2923271909
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3888043994
Short name T654
Test name
Test status
Simulation time 98602959 ps
CPU time 1.07 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:33 PM PDT 24
Peak memory 198224 kb
Host smart-96f0f76c-b371-4fa2-8697-31ce6fa23210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888043994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3888043994
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4079253987
Short name T598
Test name
Test status
Simulation time 1207510871 ps
CPU time 4.73 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 199788 kb
Host smart-104482e4-d790-4d3d-b6ee-5329a09c2ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079253987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4079253987
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1815605902
Short name T123
Test name
Test status
Simulation time 304270129 ps
CPU time 4.35 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:28 PM PDT 24
Peak memory 199740 kb
Host smart-6a087665-d37c-407f-9e96-050789826ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815605902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1815605902
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1561987548
Short name T559
Test name
Test status
Simulation time 14961380 ps
CPU time 0.61 seconds
Started Jul 18 06:46:06 PM PDT 24
Finished Jul 18 06:46:11 PM PDT 24
Peak memory 194752 kb
Host smart-4d2745f8-d9f9-495e-9126-9ca561ab9b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561987548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1561987548
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1556635260
Short name T548
Test name
Test status
Simulation time 18391804 ps
CPU time 0.64 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:14 PM PDT 24
Peak memory 194776 kb
Host smart-6410202d-d33c-488b-bd16-48e3b8490173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556635260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1556635260
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4050058095
Short name T542
Test name
Test status
Simulation time 38584108 ps
CPU time 0.57 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:14 PM PDT 24
Peak memory 194572 kb
Host smart-a460e831-e2f6-4da2-97a1-27d9cf75326b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050058095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4050058095
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2387748588
Short name T593
Test name
Test status
Simulation time 27885087 ps
CPU time 0.6 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:30 PM PDT 24
Peak memory 194688 kb
Host smart-e84f9d53-3031-4585-a292-a9d2460aa33c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387748588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2387748588
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2430128806
Short name T591
Test name
Test status
Simulation time 30688436 ps
CPU time 0.6 seconds
Started Jul 18 06:46:20 PM PDT 24
Finished Jul 18 06:46:23 PM PDT 24
Peak memory 194640 kb
Host smart-739f7af4-32a0-428b-bf9a-78209e6d5a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430128806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2430128806
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3979863836
Short name T582
Test name
Test status
Simulation time 46777569 ps
CPU time 0.62 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:33 PM PDT 24
Peak memory 194640 kb
Host smart-e32a1191-4e9b-4695-967e-7d5dd2cc2001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979863836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3979863836
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3191905037
Short name T539
Test name
Test status
Simulation time 24924569 ps
CPU time 0.62 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 194836 kb
Host smart-6ddace0a-b265-4897-993a-b54fb323d197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191905037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3191905037
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.645146508
Short name T601
Test name
Test status
Simulation time 14283070 ps
CPU time 0.6 seconds
Started Jul 18 06:46:20 PM PDT 24
Finished Jul 18 06:46:23 PM PDT 24
Peak memory 194700 kb
Host smart-cfda2c0b-062a-455b-a2a4-48221bc08311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645146508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.645146508
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.312142716
Short name T620
Test name
Test status
Simulation time 11142931 ps
CPU time 0.6 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 194688 kb
Host smart-60780972-d688-41b0-b467-ee8ff82d240b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312142716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.312142716
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1614093347
Short name T647
Test name
Test status
Simulation time 12396278 ps
CPU time 0.62 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:27 PM PDT 24
Peak memory 194680 kb
Host smart-1534388a-890f-4732-8e65-d2c59b7dd516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614093347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1614093347
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3218244462
Short name T535
Test name
Test status
Simulation time 182380137 ps
CPU time 1.26 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:31 PM PDT 24
Peak memory 199624 kb
Host smart-797f970e-0a5e-4aa4-8959-6b2a4a7dc77e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218244462 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3218244462
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2113088654
Short name T108
Test name
Test status
Simulation time 14852140 ps
CPU time 0.77 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 198648 kb
Host smart-051b4a7e-43fa-4a3d-a29b-57956f436b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113088654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2113088654
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2205634350
Short name T575
Test name
Test status
Simulation time 78129698 ps
CPU time 0.56 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 194596 kb
Host smart-9bf7fa2c-c777-4ca8-b4c1-2d0c0af19a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205634350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2205634350
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1862559766
Short name T105
Test name
Test status
Simulation time 706117099 ps
CPU time 2.17 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 199728 kb
Host smart-82d14256-c031-4dfd-a8f7-2bd0defba1c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862559766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1862559766
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1363941521
Short name T567
Test name
Test status
Simulation time 58551577 ps
CPU time 2.92 seconds
Started Jul 18 06:45:24 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 199744 kb
Host smart-125f9018-97c8-44b8-a46e-8be44a71ad57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363941521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1363941521
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1238013404
Short name T652
Test name
Test status
Simulation time 363092534 ps
CPU time 1.87 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199812 kb
Host smart-53295767-20d8-4fc0-aab9-f58beeb3c2cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238013404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1238013404
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1750837007
Short name T607
Test name
Test status
Simulation time 158671523 ps
CPU time 2.35 seconds
Started Jul 18 06:45:25 PM PDT 24
Finished Jul 18 06:45:32 PM PDT 24
Peak memory 208020 kb
Host smart-4fffdac2-6320-4b4b-9040-4765ae6cc533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750837007 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1750837007
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2892497483
Short name T110
Test name
Test status
Simulation time 29368781 ps
CPU time 0.84 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 199292 kb
Host smart-2c3c7ec0-c3b3-4e53-bf60-f3d4a271e1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892497483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2892497483
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.654449225
Short name T536
Test name
Test status
Simulation time 43224984 ps
CPU time 0.63 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:33 PM PDT 24
Peak memory 194704 kb
Host smart-dca5d694-9266-478a-bb86-d817df1d7bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654449225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.654449225
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2656857342
Short name T645
Test name
Test status
Simulation time 21594702 ps
CPU time 1.13 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:35 PM PDT 24
Peak memory 199560 kb
Host smart-a5be6dc0-c671-4973-b5ec-d9185354c117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656857342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2656857342
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.949756430
Short name T552
Test name
Test status
Simulation time 839617214 ps
CPU time 2.15 seconds
Started Jul 18 06:45:24 PM PDT 24
Finished Jul 18 06:45:29 PM PDT 24
Peak memory 199692 kb
Host smart-2e85e907-8b4e-495a-8374-78d9eb0c952c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949756430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.949756430
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3506702482
Short name T624
Test name
Test status
Simulation time 112055426 ps
CPU time 1.86 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199724 kb
Host smart-2697c419-18a4-4c70-8e56-c62aa733dd1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506702482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3506702482
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2675377144
Short name T610
Test name
Test status
Simulation time 1650235651 ps
CPU time 2.36 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 199708 kb
Host smart-4ebc3559-015a-416f-9aa2-ebf6e2fed0ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675377144 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2675377144
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3268992199
Short name T87
Test name
Test status
Simulation time 202729594 ps
CPU time 0.69 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 197324 kb
Host smart-60f43cd9-751c-4988-b4ca-499958b7b138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268992199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3268992199
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.703095156
Short name T546
Test name
Test status
Simulation time 16401546 ps
CPU time 0.57 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 194592 kb
Host smart-ac554a0f-46ef-4c7a-ba90-f95783efa68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703095156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.703095156
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3291097514
Short name T570
Test name
Test status
Simulation time 283142861 ps
CPU time 1.63 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199808 kb
Host smart-43e73afc-69a0-41c3-b419-0b0b6280a374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291097514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3291097514
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1358724638
Short name T653
Test name
Test status
Simulation time 247718327 ps
CPU time 3 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:38 PM PDT 24
Peak memory 199164 kb
Host smart-cdfff790-a82b-41ce-8398-9d9a406c6323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358724638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1358724638
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2900897892
Short name T580
Test name
Test status
Simulation time 970565108 ps
CPU time 4.41 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:39 PM PDT 24
Peak memory 199748 kb
Host smart-6f04b7ad-0177-4342-9eeb-8421f480c773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900897892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2900897892
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2857784805
Short name T602
Test name
Test status
Simulation time 38820788 ps
CPU time 1.14 seconds
Started Jul 18 06:45:28 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 199720 kb
Host smart-c845ca8b-dae4-4d1c-99bc-395323330a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857784805 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2857784805
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1591089895
Short name T97
Test name
Test status
Simulation time 20236617 ps
CPU time 0.95 seconds
Started Jul 18 06:45:27 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 199568 kb
Host smart-c0f1421d-5215-4372-9749-9b21aba4b4ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591089895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1591089895
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3669910022
Short name T623
Test name
Test status
Simulation time 50000921 ps
CPU time 0.57 seconds
Started Jul 18 06:45:31 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 194584 kb
Host smart-5533e6da-3d73-4c60-ae51-ed7f4f146234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669910022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3669910022
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3564805712
Short name T640
Test name
Test status
Simulation time 124667529 ps
CPU time 1.15 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:36 PM PDT 24
Peak memory 199592 kb
Host smart-3a2ce308-eb36-49b6-967f-b05a1030e0c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564805712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3564805712
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4116436474
Short name T587
Test name
Test status
Simulation time 104084140 ps
CPU time 2.94 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 199924 kb
Host smart-20cf44aa-2eaa-487a-928a-0da21d1e3bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116436474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4116436474
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3897564489
Short name T631
Test name
Test status
Simulation time 409710409 ps
CPU time 2.86 seconds
Started Jul 18 06:45:32 PM PDT 24
Finished Jul 18 06:45:39 PM PDT 24
Peak memory 199764 kb
Host smart-ba16c6c2-e515-4f7c-849a-4cc3068e012a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897564489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3897564489
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1167715415
Short name T543
Test name
Test status
Simulation time 90264823623 ps
CPU time 961.23 seconds
Started Jul 18 06:46:04 PM PDT 24
Finished Jul 18 07:02:07 PM PDT 24
Peak memory 224452 kb
Host smart-ac50e570-b657-4c89-932d-940efec02bbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167715415 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1167715415
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3349659161
Short name T99
Test name
Test status
Simulation time 35220859 ps
CPU time 0.88 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:36 PM PDT 24
Peak memory 199448 kb
Host smart-e4ad9218-860c-440e-91c7-78b8548ded24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349659161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3349659161
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4209468435
Short name T545
Test name
Test status
Simulation time 72703867 ps
CPU time 0.56 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:34 PM PDT 24
Peak memory 194576 kb
Host smart-ce46fc59-e8b7-46e9-83f7-197c9654a8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209468435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4209468435
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3335002259
Short name T566
Test name
Test status
Simulation time 86626109 ps
CPU time 1.12 seconds
Started Jul 18 06:46:07 PM PDT 24
Finished Jul 18 06:46:15 PM PDT 24
Peak memory 198284 kb
Host smart-1ef8f923-3c88-4b20-b744-8eb92280f8ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335002259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3335002259
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4257712373
Short name T617
Test name
Test status
Simulation time 208134337 ps
CPU time 4.07 seconds
Started Jul 18 06:45:29 PM PDT 24
Finished Jul 18 06:45:39 PM PDT 24
Peak memory 199752 kb
Host smart-7fbef378-c536-46d7-ae5a-59483a3aa2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257712373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4257712373
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4158797306
Short name T639
Test name
Test status
Simulation time 132365947 ps
CPU time 3.99 seconds
Started Jul 18 06:45:26 PM PDT 24
Finished Jul 18 06:45:35 PM PDT 24
Peak memory 199664 kb
Host smart-0c6e0253-aa2c-4e7c-b828-e99e1a7b8e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158797306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4158797306
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2957965371
Short name T392
Test name
Test status
Simulation time 12876141 ps
CPU time 0.58 seconds
Started Jul 18 05:36:16 PM PDT 24
Finished Jul 18 05:36:25 PM PDT 24
Peak memory 195140 kb
Host smart-bfca28c8-75a3-4688-91bb-f688b266350f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957965371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2957965371
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2647570032
Short name T499
Test name
Test status
Simulation time 2131837484 ps
CPU time 58.52 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:37:12 PM PDT 24
Peak memory 200156 kb
Host smart-a5408d46-c41f-4acf-af8e-a6cd823f9776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647570032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2647570032
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1825589090
Short name T319
Test name
Test status
Simulation time 469414379 ps
CPU time 12.38 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:27 PM PDT 24
Peak memory 200240 kb
Host smart-b044e971-800e-4478-9646-fea61ba10d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825589090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1825589090
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3861075505
Short name T326
Test name
Test status
Simulation time 13940978438 ps
CPU time 613.81 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 724368 kb
Host smart-db2785a3-1d73-41a4-b79e-c0792a7d17c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861075505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3861075505
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1674503865
Short name T313
Test name
Test status
Simulation time 323884033 ps
CPU time 1.08 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:15 PM PDT 24
Peak memory 199224 kb
Host smart-27192673-0c57-44b9-ad90-9093af0b7396
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674503865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1674503865
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1286768097
Short name T367
Test name
Test status
Simulation time 22643645328 ps
CPU time 199.59 seconds
Started Jul 18 05:36:26 PM PDT 24
Finished Jul 18 05:39:49 PM PDT 24
Peak memory 200208 kb
Host smart-fffe5770-3743-4708-b3c4-45b36cac155b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286768097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1286768097
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3432882955
Short name T48
Test name
Test status
Simulation time 124570413 ps
CPU time 0.81 seconds
Started Jul 18 05:36:16 PM PDT 24
Finished Jul 18 05:36:26 PM PDT 24
Peak memory 218476 kb
Host smart-fbaf7921-eb3e-44b3-9aeb-31c01d0f8cf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432882955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3432882955
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.978095051
Short name T520
Test name
Test status
Simulation time 1213092048 ps
CPU time 10.69 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:23 PM PDT 24
Peak memory 200240 kb
Host smart-8e9910ab-b7a4-4c01-9d59-6d7efb8a0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978095051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.978095051
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1267650096
Short name T443
Test name
Test status
Simulation time 11340351695 ps
CPU time 193.95 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:39:29 PM PDT 24
Peak memory 216628 kb
Host smart-a422a0cb-7101-48ca-8ba0-33825da5b876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267650096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1267650096
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.4105276874
Short name T7
Test name
Test status
Simulation time 88736596292 ps
CPU time 486.71 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 254104 kb
Host smart-78035d37-ed21-4f6b-bc25-8d595717e116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105276874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.4105276874
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1229971244
Short name T182
Test name
Test status
Simulation time 4783369785 ps
CPU time 77.17 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:37:25 PM PDT 24
Peak memory 200300 kb
Host smart-47c7f912-8baa-457e-b5c1-f71a93716396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1229971244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1229971244
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.320887540
Short name T434
Test name
Test status
Simulation time 19428585478 ps
CPU time 112.02 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:38:01 PM PDT 24
Peak memory 200192 kb
Host smart-e9edadea-34b4-4e30-bce4-665ce396dc78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=320887540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.320887540
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.618440364
Short name T38
Test name
Test status
Simulation time 30521422057 ps
CPU time 119.63 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:38:16 PM PDT 24
Peak memory 200300 kb
Host smart-732a2054-ab7f-451e-913c-f953b7332c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=618440364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.618440364
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3835311027
Short name T336
Test name
Test status
Simulation time 11127284090 ps
CPU time 618.61 seconds
Started Jul 18 05:36:14 PM PDT 24
Finished Jul 18 05:46:42 PM PDT 24
Peak memory 200288 kb
Host smart-2ed1eb68-17a6-408f-aedd-4c647ded8c6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3835311027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3835311027
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2448114082
Short name T277
Test name
Test status
Simulation time 36229463185 ps
CPU time 2107.93 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 06:11:16 PM PDT 24
Peak memory 215804 kb
Host smart-0504d090-c0f0-47c0-bccf-d0376dd692c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2448114082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2448114082
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3466416799
Short name T344
Test name
Test status
Simulation time 567768911181 ps
CPU time 2442.47 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 06:16:57 PM PDT 24
Peak memory 216380 kb
Host smart-9413243f-0966-4929-90d3-d7e8241ce636
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3466416799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3466416799
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3773005856
Short name T379
Test name
Test status
Simulation time 5454447682 ps
CPU time 71.28 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 05:37:30 PM PDT 24
Peak memory 200260 kb
Host smart-7ac50523-fb3c-446d-919b-469a1e6f2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773005856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3773005856
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2103373543
Short name T237
Test name
Test status
Simulation time 94725005 ps
CPU time 0.61 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:16 PM PDT 24
Peak memory 196068 kb
Host smart-2635b39a-f3ee-4cab-b639-742486d61390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103373543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2103373543
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2878208811
Short name T373
Test name
Test status
Simulation time 5933075895 ps
CPU time 79.94 seconds
Started Jul 18 05:36:15 PM PDT 24
Finished Jul 18 05:37:44 PM PDT 24
Peak memory 200308 kb
Host smart-0659c786-6d5f-4025-a83b-82412163f748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878208811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2878208811
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2101619447
Short name T488
Test name
Test status
Simulation time 1496672348 ps
CPU time 9.57 seconds
Started Jul 18 05:36:10 PM PDT 24
Finished Jul 18 05:36:27 PM PDT 24
Peak memory 200212 kb
Host smart-442f82a8-07cd-432e-8862-fa5592347081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101619447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2101619447
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.686207301
Short name T232
Test name
Test status
Simulation time 2871345027 ps
CPU time 113.03 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:38:01 PM PDT 24
Peak memory 414632 kb
Host smart-28a0b638-d96e-4dc9-ada4-54bac113e3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686207301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.686207301
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4065707251
Short name T165
Test name
Test status
Simulation time 6321571881 ps
CPU time 30.51 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:47 PM PDT 24
Peak memory 200156 kb
Host smart-8a2e10e5-40ef-438a-9e98-b24255400005
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065707251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4065707251
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3485426694
Short name T459
Test name
Test status
Simulation time 2114897478 ps
CPU time 111.37 seconds
Started Jul 18 05:36:16 PM PDT 24
Finished Jul 18 05:38:16 PM PDT 24
Peak memory 200228 kb
Host smart-e01d151d-ae77-4bbb-82c1-150453516ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485426694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3485426694
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3619909498
Short name T49
Test name
Test status
Simulation time 115651210 ps
CPU time 0.93 seconds
Started Jul 18 05:36:21 PM PDT 24
Finished Jul 18 05:36:29 PM PDT 24
Peak memory 218656 kb
Host smart-b1b628d6-2e60-4e58-bb7a-4d8ee29a5d54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619909498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3619909498
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1440250706
Short name T438
Test name
Test status
Simulation time 3521427005 ps
CPU time 5.07 seconds
Started Jul 18 05:36:10 PM PDT 24
Finished Jul 18 05:36:22 PM PDT 24
Peak memory 200316 kb
Host smart-6d6f5b58-837c-4333-b77e-1fb4dad12a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440250706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1440250706
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1588377285
Short name T360
Test name
Test status
Simulation time 33366014404 ps
CPU time 147.39 seconds
Started Jul 18 05:36:16 PM PDT 24
Finished Jul 18 05:38:52 PM PDT 24
Peak memory 208692 kb
Host smart-11c65e1b-2dcf-4dc2-8485-332d3ccb0ede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588377285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1588377285
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2217431754
Short name T62
Test name
Test status
Simulation time 65326936827 ps
CPU time 1824.61 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 06:06:37 PM PDT 24
Peak memory 728732 kb
Host smart-01364b2b-7b04-42b6-bd67-fa516ec3e46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217431754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2217431754
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.769089795
Short name T191
Test name
Test status
Simulation time 6621087816 ps
CPU time 38.95 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:36:52 PM PDT 24
Peak memory 200200 kb
Host smart-9de6661b-b26f-490c-adec-f8a72dd5a10d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=769089795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.769089795
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3564426470
Short name T353
Test name
Test status
Simulation time 6401597794 ps
CPU time 52.86 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:37:01 PM PDT 24
Peak memory 200248 kb
Host smart-20d32bf0-bf5e-4ff6-b103-77b686cc3a59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3564426470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3564426470
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.306164209
Short name T231
Test name
Test status
Simulation time 17240158988 ps
CPU time 136.51 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:38:30 PM PDT 24
Peak memory 200272 kb
Host smart-9bdd5b13-cc9b-4126-86fe-7f0c6324a1e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306164209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.306164209
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1737361620
Short name T501
Test name
Test status
Simulation time 100451426905 ps
CPU time 514.79 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:44:46 PM PDT 24
Peak memory 200244 kb
Host smart-fda6f69e-c987-45c1-913f-c905a4e8820e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1737361620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1737361620
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2318462106
Short name T325
Test name
Test status
Simulation time 206447867483 ps
CPU time 2644.87 seconds
Started Jul 18 05:36:12 PM PDT 24
Finished Jul 18 06:20:26 PM PDT 24
Peak memory 215828 kb
Host smart-4fa85693-c818-4e90-9f6f-59a3d24f80c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2318462106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2318462106
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4111503979
Short name T216
Test name
Test status
Simulation time 1430080163407 ps
CPU time 2705.67 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 06:21:17 PM PDT 24
Peak memory 215796 kb
Host smart-f4ae8dc7-accc-4aeb-8912-5ab88243fce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4111503979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4111503979
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1005763050
Short name T396
Test name
Test status
Simulation time 1261322795 ps
CPU time 66.61 seconds
Started Jul 18 05:36:21 PM PDT 24
Finished Jul 18 05:37:35 PM PDT 24
Peak memory 200344 kb
Host smart-236c4667-0d4d-4838-8973-c542d324e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005763050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1005763050
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3728246355
Short name T207
Test name
Test status
Simulation time 17003135 ps
CPU time 0.57 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:36:57 PM PDT 24
Peak memory 195812 kb
Host smart-d0223705-e5e1-4f1d-b034-8b4eb5f87649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728246355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3728246355
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.460793771
Short name T500
Test name
Test status
Simulation time 6978841885 ps
CPU time 101.32 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:38:36 PM PDT 24
Peak memory 215932 kb
Host smart-ec806c4f-c0f2-45d1-be52-904e54b953aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460793771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.460793771
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.807937476
Short name T262
Test name
Test status
Simulation time 543267953 ps
CPU time 90.94 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:38:28 PM PDT 24
Peak memory 429308 kb
Host smart-81d73503-d093-4f62-8eb2-5ad436c3de19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807937476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.807937476
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2575762061
Short name T337
Test name
Test status
Simulation time 1865526196 ps
CPU time 35.25 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:37:32 PM PDT 24
Peak memory 200192 kb
Host smart-994774fb-aab5-43ec-a80d-0cf1276a9f91
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575762061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2575762061
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3265431326
Short name T224
Test name
Test status
Simulation time 5324677431 ps
CPU time 157.69 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:39:32 PM PDT 24
Peak memory 200344 kb
Host smart-f3603632-2536-414b-a071-87d0e563371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265431326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3265431326
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4093996786
Short name T383
Test name
Test status
Simulation time 2356606173 ps
CPU time 10.04 seconds
Started Jul 18 05:36:36 PM PDT 24
Finished Jul 18 05:36:48 PM PDT 24
Peak memory 200264 kb
Host smart-679b18c7-9916-4bd8-b7be-83272edc12d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093996786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4093996786
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1271052041
Short name T462
Test name
Test status
Simulation time 4293613496 ps
CPU time 208.53 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:40:14 PM PDT 24
Peak memory 200216 kb
Host smart-81c93837-03c5-4f8c-96e7-c16f02e1739f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271052041 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1271052041
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2888209361
Short name T223
Test name
Test status
Simulation time 788917132 ps
CPU time 18.64 seconds
Started Jul 18 05:36:41 PM PDT 24
Finished Jul 18 05:37:03 PM PDT 24
Peak memory 200216 kb
Host smart-9e4b33ae-ae1e-4f43-9d01-7cefe138ba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888209361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2888209361
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4252745915
Short name T300
Test name
Test status
Simulation time 78590917 ps
CPU time 0.61 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:36:52 PM PDT 24
Peak memory 196776 kb
Host smart-c2b359dd-1003-4aec-82d4-f347822b7894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252745915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4252745915
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.822782667
Short name T431
Test name
Test status
Simulation time 3367662058 ps
CPU time 65.67 seconds
Started Jul 18 05:36:41 PM PDT 24
Finished Jul 18 05:37:50 PM PDT 24
Peak memory 200296 kb
Host smart-8faadc0b-e4c9-4571-bd8a-8fac140e54d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822782667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.822782667
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4146992877
Short name T335
Test name
Test status
Simulation time 5207836360 ps
CPU time 22.94 seconds
Started Jul 18 05:36:36 PM PDT 24
Finished Jul 18 05:37:00 PM PDT 24
Peak memory 200248 kb
Host smart-db0078e9-e415-4ef2-90d2-693f59952d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146992877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4146992877
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3405364779
Short name T172
Test name
Test status
Simulation time 15991628645 ps
CPU time 711.34 seconds
Started Jul 18 05:36:37 PM PDT 24
Finished Jul 18 05:48:30 PM PDT 24
Peak memory 690152 kb
Host smart-0473589c-1dab-4f66-b19b-34a2e6d5375a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405364779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3405364779
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.860413501
Short name T159
Test name
Test status
Simulation time 893215734 ps
CPU time 47.9 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:37:38 PM PDT 24
Peak memory 200180 kb
Host smart-85d6347f-4313-43c0-b484-b5a31237f9a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860413501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.860413501
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.791914482
Short name T34
Test name
Test status
Simulation time 406188123 ps
CPU time 11.78 seconds
Started Jul 18 05:36:33 PM PDT 24
Finished Jul 18 05:36:46 PM PDT 24
Peak memory 200224 kb
Host smart-19125b62-ccbb-432e-9f98-cc745ccaa23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791914482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.791914482
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.311768265
Short name T279
Test name
Test status
Simulation time 532657182 ps
CPU time 7.07 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:47 PM PDT 24
Peak memory 200148 kb
Host smart-31d0c5f0-ddd7-40f0-84c9-0347c0ac2061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311768265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.311768265
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2569377527
Short name T341
Test name
Test status
Simulation time 585655612155 ps
CPU time 915.24 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:52:07 PM PDT 24
Peak memory 659180 kb
Host smart-1ca4dce9-c7b8-4b1c-bf1e-25473283697e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569377527 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2569377527
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.993770969
Short name T113
Test name
Test status
Simulation time 7166110446 ps
CPU time 113.44 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:38:41 PM PDT 24
Peak memory 200220 kb
Host smart-9c0a64d4-711f-406f-bbb4-36f6ac5f04d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993770969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.993770969
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3293497872
Short name T21
Test name
Test status
Simulation time 6036394229 ps
CPU time 60.41 seconds
Started Jul 18 05:36:35 PM PDT 24
Finished Jul 18 05:37:37 PM PDT 24
Peak memory 200312 kb
Host smart-c5e39e57-9aef-44db-9ebf-6a657a45d1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3293497872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3293497872
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1097221878
Short name T366
Test name
Test status
Simulation time 969544039 ps
CPU time 11.15 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:36:54 PM PDT 24
Peak memory 200180 kb
Host smart-d8afd841-f009-472e-800b-f1794dd5ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097221878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1097221878
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.992805404
Short name T81
Test name
Test status
Simulation time 1872346159 ps
CPU time 76.19 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:38:02 PM PDT 24
Peak memory 395204 kb
Host smart-73dc7cf9-0c44-4902-914d-cdefea64d147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992805404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.992805404
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1020958606
Short name T309
Test name
Test status
Simulation time 1307928892 ps
CPU time 9.81 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:36:51 PM PDT 24
Peak memory 200164 kb
Host smart-51815262-aee9-4071-9aec-4ac70b894f47
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020958606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1020958606
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3497479443
Short name T378
Test name
Test status
Simulation time 4059389785 ps
CPU time 114.03 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:38:51 PM PDT 24
Peak memory 200248 kb
Host smart-8e2d12f4-2e64-4a53-93df-be4a7165158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497479443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3497479443
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1661386537
Short name T198
Test name
Test status
Simulation time 709652339 ps
CPU time 8.63 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:36:56 PM PDT 24
Peak memory 200212 kb
Host smart-24168d61-cc3f-4c48-8aae-ff9ec16d98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661386537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1661386537
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2485861244
Short name T351
Test name
Test status
Simulation time 79277853831 ps
CPU time 3797.3 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 06:40:07 PM PDT 24
Peak memory 852364 kb
Host smart-76d21aae-69b9-4884-a5b2-4a184766645d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485861244 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2485861244
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2829773282
Short name T167
Test name
Test status
Simulation time 387455036 ps
CPU time 4.06 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:36:57 PM PDT 24
Peak memory 200156 kb
Host smart-81b25312-15c5-4185-ac2f-5125ffbac552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829773282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2829773282
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1784802232
Short name T350
Test name
Test status
Simulation time 41295263 ps
CPU time 0.59 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:36:56 PM PDT 24
Peak memory 196796 kb
Host smart-b3a34608-a46b-4851-afe5-407f033cafd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784802232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1784802232
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2688430366
Short name T219
Test name
Test status
Simulation time 2064880692 ps
CPU time 31.49 seconds
Started Jul 18 05:36:36 PM PDT 24
Finished Jul 18 05:37:09 PM PDT 24
Peak memory 200152 kb
Host smart-40f1ef84-daf4-4c6b-8db4-0eeb12b17398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688430366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2688430366
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4142181291
Short name T144
Test name
Test status
Simulation time 1598824536 ps
CPU time 28.15 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:37:20 PM PDT 24
Peak memory 200244 kb
Host smart-81e5411d-703e-4be0-bb0a-7b8e73e67190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142181291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4142181291
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.842639095
Short name T43
Test name
Test status
Simulation time 4431051265 ps
CPU time 775.39 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:49:51 PM PDT 24
Peak memory 737712 kb
Host smart-bff1b319-c55d-4aaf-8348-0f84b4d49224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842639095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.842639095
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1239313433
Short name T365
Test name
Test status
Simulation time 6081141119 ps
CPU time 70.45 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:37:52 PM PDT 24
Peak memory 200324 kb
Host smart-1e14da72-c836-417d-8d4c-7d24547ec9cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239313433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1239313433
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2881507310
Short name T368
Test name
Test status
Simulation time 12209756554 ps
CPU time 75.22 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:38:12 PM PDT 24
Peak memory 200308 kb
Host smart-2d20ebcc-a1a8-4c2c-adfb-059d4745664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881507310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2881507310
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.872276128
Short name T409
Test name
Test status
Simulation time 310098728 ps
CPU time 7.21 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:36:48 PM PDT 24
Peak memory 200152 kb
Host smart-3cab81bc-4df1-46d4-82fb-9411111a9eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872276128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.872276128
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3255765385
Short name T22
Test name
Test status
Simulation time 77171506713 ps
CPU time 1886.26 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 06:08:23 PM PDT 24
Peak memory 755160 kb
Host smart-2e7d1fb2-b0e9-436c-ba4d-d1705cf7aef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255765385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3255765385
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3965406492
Short name T2
Test name
Test status
Simulation time 5064851832 ps
CPU time 99.06 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:38:19 PM PDT 24
Peak memory 200300 kb
Host smart-6fd57d95-ace3-44f4-97bf-6cca55842f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965406492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3965406492
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1589284578
Short name T410
Test name
Test status
Simulation time 40003334 ps
CPU time 0.6 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:36:52 PM PDT 24
Peak memory 196112 kb
Host smart-8742eada-3089-42cc-873a-31e60a3d0a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589284578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1589284578
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3304919668
Short name T332
Test name
Test status
Simulation time 973476618 ps
CPU time 26.71 seconds
Started Jul 18 05:36:37 PM PDT 24
Finished Jul 18 05:37:05 PM PDT 24
Peak memory 200216 kb
Host smart-0d285991-d636-42f3-8d7b-35feb0dbc141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304919668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3304919668
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2587636964
Short name T487
Test name
Test status
Simulation time 2502389456 ps
CPU time 18.62 seconds
Started Jul 18 05:36:37 PM PDT 24
Finished Jul 18 05:36:58 PM PDT 24
Peak memory 200264 kb
Host smart-935c27c0-bbfc-4fa7-879d-60bce334ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587636964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2587636964
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1062214822
Short name T395
Test name
Test status
Simulation time 656031479 ps
CPU time 132.07 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:39:00 PM PDT 24
Peak memory 612944 kb
Host smart-ad5becda-1574-4b10-87cd-5d3becc259c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062214822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1062214822
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4038344922
Short name T422
Test name
Test status
Simulation time 3064282358 ps
CPU time 171.02 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:39:36 PM PDT 24
Peak memory 200228 kb
Host smart-a0a57b12-0ef0-44e1-92e8-5504402bcdd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038344922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4038344922
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.701115632
Short name T82
Test name
Test status
Simulation time 28688979866 ps
CPU time 89.28 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:38:27 PM PDT 24
Peak memory 200308 kb
Host smart-6c8bef4d-663c-4038-8abf-d1d2012ba07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701115632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.701115632
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2684632204
Short name T130
Test name
Test status
Simulation time 1764243122 ps
CPU time 8.22 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:37:00 PM PDT 24
Peak memory 200180 kb
Host smart-fb3af3bb-6c2d-4a98-9536-e0c3261a9c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684632204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2684632204
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2372038877
Short name T204
Test name
Test status
Simulation time 588403038491 ps
CPU time 2839.55 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 06:24:05 PM PDT 24
Peak memory 815128 kb
Host smart-bd501778-c8f5-40a2-90e6-a932aa1a2440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372038877 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2372038877
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4219380935
Short name T250
Test name
Test status
Simulation time 7537925844 ps
CPU time 96.56 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:38:29 PM PDT 24
Peak memory 200312 kb
Host smart-ad822c1e-e026-4028-9d3d-9318575b2d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219380935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4219380935
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3960563495
Short name T479
Test name
Test status
Simulation time 65343030 ps
CPU time 0.56 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 195052 kb
Host smart-babb2886-3e95-4ef7-9531-4b984fb8a7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960563495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3960563495
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3811714614
Short name T404
Test name
Test status
Simulation time 6190784859 ps
CPU time 98.26 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:38:24 PM PDT 24
Peak memory 208476 kb
Host smart-801a4333-0607-4071-84b6-960a371f52f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811714614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3811714614
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2611399576
Short name T229
Test name
Test status
Simulation time 258545703 ps
CPU time 13.64 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 200228 kb
Host smart-793bfee3-7b36-477e-98b9-17d7b4708591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611399576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2611399576
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.370415992
Short name T470
Test name
Test status
Simulation time 1512798009 ps
CPU time 241.42 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:40:45 PM PDT 24
Peak memory 465968 kb
Host smart-2d79897e-74ce-4118-b5b3-dc697bcde7b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370415992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.370415992
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3067892113
Short name T357
Test name
Test status
Simulation time 31683368727 ps
CPU time 161.47 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:39:25 PM PDT 24
Peak memory 200224 kb
Host smart-a96ae7b9-0dc9-4925-8db1-907d33e99e73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067892113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3067892113
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1954473140
Short name T230
Test name
Test status
Simulation time 1759619566 ps
CPU time 48.03 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:37:28 PM PDT 24
Peak memory 200228 kb
Host smart-ebe85fb9-f4cc-4269-808d-30704cc38889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954473140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1954473140
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.300084044
Short name T51
Test name
Test status
Simulation time 130358988 ps
CPU time 4.32 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:36:53 PM PDT 24
Peak memory 199588 kb
Host smart-96dc5b0a-9fb6-4e16-9b1f-23f69e05f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300084044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.300084044
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1970135062
Short name T142
Test name
Test status
Simulation time 38536316074 ps
CPU time 2585.04 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 06:19:52 PM PDT 24
Peak memory 745616 kb
Host smart-db1d6812-db48-4331-a3a4-2bad3edbd769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970135062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1970135062
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.351964319
Short name T529
Test name
Test status
Simulation time 3107081912 ps
CPU time 17.02 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 200364 kb
Host smart-01e8b89d-b59c-49f7-8489-f63968115838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351964319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.351964319
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.135460567
Short name T24
Test name
Test status
Simulation time 43050994 ps
CPU time 0.58 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:36:48 PM PDT 24
Peak memory 195080 kb
Host smart-a3f4ee7d-b67a-48d6-aa80-8a65ef0e255a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135460567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.135460567
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1168621620
Short name T166
Test name
Test status
Simulation time 965108520 ps
CPU time 22.49 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:37:06 PM PDT 24
Peak memory 200200 kb
Host smart-d850e267-a512-4c59-8788-de0fe5e5e258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168621620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1168621620
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3508205596
Short name T19
Test name
Test status
Simulation time 193660412 ps
CPU time 10.92 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:37:04 PM PDT 24
Peak memory 200216 kb
Host smart-205eb968-8ff5-4cf4-8000-e084eaf1f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508205596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3508205596
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.271411950
Short name T189
Test name
Test status
Simulation time 25800381305 ps
CPU time 1390.51 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:59:46 PM PDT 24
Peak memory 748016 kb
Host smart-fb07bc04-ab8c-44a3-824c-c9ff4834aa7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271411950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.271411950
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2784870269
Short name T215
Test name
Test status
Simulation time 17295746781 ps
CPU time 78.61 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:38:17 PM PDT 24
Peak memory 200216 kb
Host smart-6963416f-73fd-43f9-8a82-ab88ee6a406a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784870269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2784870269
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.258840363
Short name T507
Test name
Test status
Simulation time 11235665236 ps
CPU time 156.95 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:39:21 PM PDT 24
Peak memory 200280 kb
Host smart-83615476-e729-405c-b2bb-9144669b45b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258840363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.258840363
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2990206217
Short name T453
Test name
Test status
Simulation time 1158290714 ps
CPU time 7.86 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:48 PM PDT 24
Peak memory 200220 kb
Host smart-f442cf89-7306-425e-b21f-1f6d0f5bf5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990206217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2990206217
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3394674609
Short name T66
Test name
Test status
Simulation time 12130907871 ps
CPU time 181.9 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:39:58 PM PDT 24
Peak memory 309000 kb
Host smart-4e979136-8eaa-4931-b6e3-1f04dbd0aea6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394674609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3394674609
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2506314054
Short name T112
Test name
Test status
Simulation time 6881321354 ps
CPU time 121.26 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:38:36 PM PDT 24
Peak memory 200236 kb
Host smart-481ff22d-21d7-48d5-9abc-b21c441442de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506314054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2506314054
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3924982480
Short name T296
Test name
Test status
Simulation time 25535183 ps
CPU time 0.63 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:36:37 PM PDT 24
Peak memory 195888 kb
Host smart-5519f51e-1df7-46d5-9655-4c2331fa01f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924982480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3924982480
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3155860120
Short name T41
Test name
Test status
Simulation time 6202969978 ps
CPU time 87.79 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:38:18 PM PDT 24
Peak memory 208424 kb
Host smart-a93d4bde-ec23-42d1-ae31-bfb8133ceb61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155860120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3155860120
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.514810717
Short name T464
Test name
Test status
Simulation time 2222534894 ps
CPU time 55.8 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:37:43 PM PDT 24
Peak memory 200212 kb
Host smart-761f9ca6-93e7-4e2d-b718-b84b29bd9ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514810717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.514810717
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3333348662
Short name T497
Test name
Test status
Simulation time 545236689 ps
CPU time 88.27 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:38:25 PM PDT 24
Peak memory 444292 kb
Host smart-adfa0b29-21b0-42ad-9c7c-cab5ace29c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333348662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3333348662
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.928482574
Short name T315
Test name
Test status
Simulation time 6782848122 ps
CPU time 187.39 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:39:43 PM PDT 24
Peak memory 200232 kb
Host smart-61bb4d9e-5a72-4913-8750-378ffbd35c4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928482574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.928482574
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2024695653
Short name T137
Test name
Test status
Simulation time 126138112069 ps
CPU time 138.29 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:39:06 PM PDT 24
Peak memory 200516 kb
Host smart-22591344-08b7-4594-8536-74ed165ea4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024695653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2024695653
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2475956231
Short name T451
Test name
Test status
Simulation time 716734003 ps
CPU time 9.26 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:37:08 PM PDT 24
Peak memory 200172 kb
Host smart-bffa28c7-1dbd-4681-894d-c21017cdd51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475956231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2475956231
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3516731409
Short name T68
Test name
Test status
Simulation time 161662991042 ps
CPU time 501.38 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:45:19 PM PDT 24
Peak memory 218608 kb
Host smart-aee45927-ad9f-4719-800f-ebc6000b7862
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516731409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3516731409
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1941512725
Short name T253
Test name
Test status
Simulation time 19335334924 ps
CPU time 77.95 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:38:01 PM PDT 24
Peak memory 200296 kb
Host smart-b1b796d9-587a-44e2-9d27-23e6aa11c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941512725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1941512725
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3587236329
Short name T83
Test name
Test status
Simulation time 15806429 ps
CPU time 0.62 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:36:50 PM PDT 24
Peak memory 196856 kb
Host smart-1dcc18f0-8837-46da-baa7-e019cf49c0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587236329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3587236329
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1860905515
Short name T310
Test name
Test status
Simulation time 90801755 ps
CPU time 5.47 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:36:48 PM PDT 24
Peak memory 200044 kb
Host smart-18b85bd5-3aee-4e49-930a-cd5c125350de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860905515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1860905515
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4126420795
Short name T419
Test name
Test status
Simulation time 110564999 ps
CPU time 5.7 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:36:49 PM PDT 24
Peak memory 200228 kb
Host smart-b5395656-8047-494d-b658-d0303c2dc479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126420795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4126420795
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1193782067
Short name T432
Test name
Test status
Simulation time 553924055 ps
CPU time 159.03 seconds
Started Jul 18 05:36:35 PM PDT 24
Finished Jul 18 05:39:16 PM PDT 24
Peak memory 609072 kb
Host smart-c3fa160e-2482-40ac-8209-e4b1c7e9dc09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193782067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1193782067
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2435183891
Short name T472
Test name
Test status
Simulation time 1488843473 ps
CPU time 84.36 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:38:20 PM PDT 24
Peak memory 200008 kb
Host smart-08e3b05d-ec86-407e-b66c-e986229adab5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435183891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2435183891
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.11851965
Short name T233
Test name
Test status
Simulation time 3713578510 ps
CPU time 12.44 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:52 PM PDT 24
Peak memory 200308 kb
Host smart-0963399f-b0df-43b0-93d0-d20638068db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11851965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.11851965
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1119356536
Short name T36
Test name
Test status
Simulation time 102510465 ps
CPU time 4.88 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:36:40 PM PDT 24
Peak memory 200152 kb
Host smart-f45a57dd-164a-44cb-a0a1-bded4b9da652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119356536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1119356536
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.72554891
Short name T414
Test name
Test status
Simulation time 256611763950 ps
CPU time 2084.42 seconds
Started Jul 18 05:36:35 PM PDT 24
Finished Jul 18 06:11:21 PM PDT 24
Peak memory 768748 kb
Host smart-e414bdb3-2b5c-4346-ab8c-38566f9c49c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72554891 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.72554891
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.917503516
Short name T55
Test name
Test status
Simulation time 2191096339 ps
CPU time 109.51 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:38:41 PM PDT 24
Peak memory 200264 kb
Host smart-4fb78311-9b5b-486f-8905-7913e4a171d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917503516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.917503516
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3647658512
Short name T517
Test name
Test status
Simulation time 23336955 ps
CPU time 0.57 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:36:54 PM PDT 24
Peak memory 196184 kb
Host smart-e8756ba3-f82a-4339-bead-00a4b0c8d51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647658512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3647658512
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4193228441
Short name T314
Test name
Test status
Simulation time 268456750 ps
CPU time 15.08 seconds
Started Jul 18 05:36:31 PM PDT 24
Finished Jul 18 05:36:48 PM PDT 24
Peak memory 200128 kb
Host smart-f8b53e69-6ba4-4f3f-adfa-b3b4c5b6f748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193228441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4193228441
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.4037895810
Short name T311
Test name
Test status
Simulation time 508966441 ps
CPU time 20.48 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:37:15 PM PDT 24
Peak memory 200232 kb
Host smart-381f902b-849a-474b-b5c5-1c6a6e65df43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037895810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4037895810
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3224928370
Short name T246
Test name
Test status
Simulation time 986490637 ps
CPU time 176.49 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:39:48 PM PDT 24
Peak memory 471380 kb
Host smart-211efb67-f6b9-477b-9696-d6a6e6df6d28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224928370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3224928370
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4036974666
Short name T202
Test name
Test status
Simulation time 13278322563 ps
CPU time 167.41 seconds
Started Jul 18 05:36:36 PM PDT 24
Finished Jul 18 05:39:25 PM PDT 24
Peak memory 200196 kb
Host smart-05cfe5d1-75c0-438a-afd8-31606a734470
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036974666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4036974666
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3496990882
Short name T408
Test name
Test status
Simulation time 696418410 ps
CPU time 39.39 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:37:28 PM PDT 24
Peak memory 200208 kb
Host smart-f3004729-0bac-468d-975b-276180871da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496990882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3496990882
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1426605382
Short name T85
Test name
Test status
Simulation time 247493104 ps
CPU time 5.67 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:47 PM PDT 24
Peak memory 200280 kb
Host smart-e2d3ca5f-b8b6-4237-8a86-c2677158df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426605382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1426605382
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.97902397
Short name T40
Test name
Test status
Simulation time 14320277557 ps
CPU time 185 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:39:57 PM PDT 24
Peak memory 208400 kb
Host smart-aaf6de86-9fea-4b3c-84ec-c602be455f83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97902397 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.97902397
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1814469546
Short name T20
Test name
Test status
Simulation time 243822160 ps
CPU time 10.82 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 200184 kb
Host smart-71eb13d2-b556-43e7-98f3-aa576abce1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814469546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1814469546
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2452881233
Short name T272
Test name
Test status
Simulation time 33288269 ps
CPU time 0.58 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 195104 kb
Host smart-295416c3-d5e4-49bd-8d4c-1315e9f7a2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452881233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2452881233
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1458013761
Short name T489
Test name
Test status
Simulation time 405830531 ps
CPU time 5.88 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 05:36:25 PM PDT 24
Peak memory 200076 kb
Host smart-6eb2d502-21a6-49ae-a5b3-7abd2c163568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458013761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1458013761
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3097297749
Short name T416
Test name
Test status
Simulation time 364059473 ps
CPU time 3.16 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:19 PM PDT 24
Peak memory 200248 kb
Host smart-cfde4b66-7c61-4083-8a20-e4ee00faeb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097297749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3097297749
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3654234734
Short name T187
Test name
Test status
Simulation time 17998241546 ps
CPU time 577.8 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 633848 kb
Host smart-bcac935f-c120-4212-8257-fa5a4a63956d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654234734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3654234734
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.823838506
Short name T155
Test name
Test status
Simulation time 23351906762 ps
CPU time 76.77 seconds
Started Jul 18 05:36:14 PM PDT 24
Finished Jul 18 05:37:40 PM PDT 24
Peak memory 200292 kb
Host smart-a070a9c1-b1e3-4e9b-8ed6-7440be343dec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823838506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.823838506
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1439333418
Short name T361
Test name
Test status
Simulation time 2416021096 ps
CPU time 31.8 seconds
Started Jul 18 05:36:15 PM PDT 24
Finished Jul 18 05:36:56 PM PDT 24
Peak memory 200308 kb
Host smart-c2755d45-8ebb-4957-ad77-465b49637bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439333418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1439333418
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3154849445
Short name T50
Test name
Test status
Simulation time 565107287 ps
CPU time 1.16 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:36:17 PM PDT 24
Peak memory 219600 kb
Host smart-7a9e8470-c2fe-4664-b451-24807d348c28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154849445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3154849445
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3280540643
Short name T377
Test name
Test status
Simulation time 221575364 ps
CPU time 9.85 seconds
Started Jul 18 05:36:13 PM PDT 24
Finished Jul 18 05:36:31 PM PDT 24
Peak memory 200136 kb
Host smart-1dcb3945-7939-42c1-b57c-6679122d55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280540643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3280540643
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1378854952
Short name T194
Test name
Test status
Simulation time 356998902795 ps
CPU time 1087.6 seconds
Started Jul 18 05:36:14 PM PDT 24
Finished Jul 18 05:54:31 PM PDT 24
Peak memory 715980 kb
Host smart-9e8a16f3-03b7-4b27-8d62-6cd47a356d34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378854952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1378854952
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2974424385
Short name T176
Test name
Test status
Simulation time 3425254039 ps
CPU time 40.49 seconds
Started Jul 18 05:36:21 PM PDT 24
Finished Jul 18 05:37:08 PM PDT 24
Peak memory 200316 kb
Host smart-b33488df-848e-4733-9353-806af09037a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2974424385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2974424385
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2588909305
Short name T380
Test name
Test status
Simulation time 87151634029 ps
CPU time 66.83 seconds
Started Jul 18 05:36:14 PM PDT 24
Finished Jul 18 05:37:30 PM PDT 24
Peak memory 200316 kb
Host smart-f6a442d3-d364-49fd-8652-22bd6bfb44c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2588909305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2588909305
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2153787908
Short name T346
Test name
Test status
Simulation time 17204970787 ps
CPU time 76.08 seconds
Started Jul 18 05:36:15 PM PDT 24
Finished Jul 18 05:37:40 PM PDT 24
Peak memory 200364 kb
Host smart-429c4910-3bae-4679-996d-4bcaa82e367f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2153787908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2153787908
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2000221320
Short name T193
Test name
Test status
Simulation time 77630383951 ps
CPU time 588.1 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 200352 kb
Host smart-580180d4-af9c-42f3-b096-393f6b19bbb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2000221320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2000221320
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1235750
Short name T3
Test name
Test status
Simulation time 82447314704 ps
CPU time 2171.38 seconds
Started Jul 18 05:36:26 PM PDT 24
Finished Jul 18 06:12:41 PM PDT 24
Peak memory 215784 kb
Host smart-ff4fff76-4854-43f4-89f8-3fa28852ca89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1235750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1235750
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.114941950
Short name T420
Test name
Test status
Simulation time 911112436607 ps
CPU time 2524.23 seconds
Started Jul 18 05:36:28 PM PDT 24
Finished Jul 18 06:18:35 PM PDT 24
Peak memory 216472 kb
Host smart-de947f71-b5f6-4b69-bd33-886c762321d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=114941950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.114941950
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3082317548
Short name T384
Test name
Test status
Simulation time 7465624428 ps
CPU time 86.5 seconds
Started Jul 18 05:36:15 PM PDT 24
Finished Jul 18 05:37:50 PM PDT 24
Peak memory 199804 kb
Host smart-51b82de4-3929-403f-bcee-9be43c3ab939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082317548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3082317548
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2333577824
Short name T461
Test name
Test status
Simulation time 11186619 ps
CPU time 0.58 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:00 PM PDT 24
Peak memory 195100 kb
Host smart-ecb760ab-18c2-46dd-b5a1-098f41cd00bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333577824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2333577824
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4280783881
Short name T401
Test name
Test status
Simulation time 7283224017 ps
CPU time 50.41 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:37:34 PM PDT 24
Peak memory 200220 kb
Host smart-0fb1dd85-0bdd-413c-a883-be9f1dbb85f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280783881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4280783881
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3251100393
Short name T391
Test name
Test status
Simulation time 3537424371 ps
CPU time 44.11 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:37:39 PM PDT 24
Peak memory 200316 kb
Host smart-8556dd40-7b16-4747-af8d-bdfa83fd24a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251100393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3251100393
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.575889697
Short name T290
Test name
Test status
Simulation time 7664973505 ps
CPU time 746.06 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:49:24 PM PDT 24
Peak memory 690616 kb
Host smart-de03c217-645f-4922-a03c-6f350bca91f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575889697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.575889697
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.221988341
Short name T261
Test name
Test status
Simulation time 17815025580 ps
CPU time 224.8 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:40:44 PM PDT 24
Peak memory 200288 kb
Host smart-ee9829bd-f91a-40fc-a849-7d5112f10a6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221988341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.221988341
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3752732766
Short name T138
Test name
Test status
Simulation time 21265299747 ps
CPU time 197.3 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:40:11 PM PDT 24
Peak memory 216636 kb
Host smart-81749f96-0d89-44c2-9a62-a14e7f5df03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752732766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3752732766
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2921258909
Short name T525
Test name
Test status
Simulation time 176382586 ps
CPU time 9.2 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:36:45 PM PDT 24
Peak memory 200200 kb
Host smart-320251b1-a7e7-4eda-b67a-bde8441876e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921258909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2921258909
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3859310500
Short name T119
Test name
Test status
Simulation time 223302189745 ps
CPU time 2073.01 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 06:11:35 PM PDT 24
Peak memory 768680 kb
Host smart-4e8c9ecb-5bd3-4055-b729-317375504f7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859310500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3859310500
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3240548265
Short name T33
Test name
Test status
Simulation time 2864393038 ps
CPU time 38.85 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:37:33 PM PDT 24
Peak memory 200356 kb
Host smart-75d85dcb-cfb0-403d-8637-0695884b71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240548265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3240548265
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2309481517
Short name T80
Test name
Test status
Simulation time 13578116 ps
CPU time 0.61 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:36:56 PM PDT 24
Peak memory 196092 kb
Host smart-9120a244-a6fa-42ab-8b82-2e470c091638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309481517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2309481517
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2890690634
Short name T6
Test name
Test status
Simulation time 6315225482 ps
CPU time 100.16 seconds
Started Jul 18 05:36:53 PM PDT 24
Finished Jul 18 05:38:40 PM PDT 24
Peak memory 200180 kb
Host smart-46b717be-a67f-4249-9d00-a5da895e7255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890690634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2890690634
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.830194021
Short name T170
Test name
Test status
Simulation time 12398487485 ps
CPU time 71.19 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:38:11 PM PDT 24
Peak memory 200360 kb
Host smart-6b141504-9d56-4d5e-a1b6-3b54a5c27bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830194021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.830194021
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2903275262
Short name T164
Test name
Test status
Simulation time 19756040613 ps
CPU time 543.62 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 683136 kb
Host smart-740391be-4682-4f25-9b03-8f7e0fe5fd65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903275262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2903275262
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3764775102
Short name T519
Test name
Test status
Simulation time 12477527522 ps
CPU time 104.18 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:38:29 PM PDT 24
Peak memory 200228 kb
Host smart-2f4694ed-74fd-419e-aa36-7e1a083c194e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764775102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3764775102
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_smoke.557730413
Short name T320
Test name
Test status
Simulation time 6525964750 ps
CPU time 13.65 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:37:10 PM PDT 24
Peak memory 200368 kb
Host smart-06327e49-9d11-488e-9d45-db5fc29de426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557730413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.557730413
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2228219869
Short name T445
Test name
Test status
Simulation time 87832033170 ps
CPU time 896.69 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 709856 kb
Host smart-09f4c417-5bb3-4c39-a053-78fad9f1592a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228219869 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2228219869
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.477274780
Short name T115
Test name
Test status
Simulation time 9018850072 ps
CPU time 100.92 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:38:40 PM PDT 24
Peak memory 200296 kb
Host smart-51a556cb-5434-4c56-89d9-089871107d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477274780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.477274780
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2711670006
Short name T370
Test name
Test status
Simulation time 32139520 ps
CPU time 0.57 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 195856 kb
Host smart-c31add46-8ff6-4b8b-8e63-d8d99fc3cb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711670006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2711670006
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2001415221
Short name T530
Test name
Test status
Simulation time 933912767 ps
CPU time 55.32 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:37:54 PM PDT 24
Peak memory 200108 kb
Host smart-963e8921-d5a2-4d89-98eb-40ed3a72e0a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001415221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2001415221
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4146636849
Short name T214
Test name
Test status
Simulation time 1099467429 ps
CPU time 20.4 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:37:18 PM PDT 24
Peak memory 200152 kb
Host smart-9db64c2e-f9e3-407a-8e81-be07a47abe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146636849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4146636849
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2138068006
Short name T169
Test name
Test status
Simulation time 505871432 ps
CPU time 74.61 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:38:10 PM PDT 24
Peak memory 404656 kb
Host smart-f9c4b769-fafb-4b9b-8cb8-d95b898f714f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138068006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2138068006
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.27812208
Short name T302
Test name
Test status
Simulation time 28383670257 ps
CPU time 113.55 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:38:41 PM PDT 24
Peak memory 200212 kb
Host smart-a52189ec-b6a2-42f0-bafe-2353281ed9dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.27812208
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3062916032
Short name T255
Test name
Test status
Simulation time 3259057389 ps
CPU time 187.85 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:40:01 PM PDT 24
Peak memory 200336 kb
Host smart-d216058d-9f61-4219-a784-2eb1217b8ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062916032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3062916032
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1037399057
Short name T426
Test name
Test status
Simulation time 326361175 ps
CPU time 3.32 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:36:46 PM PDT 24
Peak memory 200240 kb
Host smart-a9ec4f64-8db3-488f-8cf8-3bb53b1fda7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037399057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1037399057
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3282655307
Short name T328
Test name
Test status
Simulation time 23160999096 ps
CPU time 657.45 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:48:05 PM PDT 24
Peak memory 242992 kb
Host smart-41e77fbc-3c47-4c54-b48b-2181358b7153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282655307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3282655307
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.19889601
Short name T242
Test name
Test status
Simulation time 1048662876 ps
CPU time 15.89 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:16 PM PDT 24
Peak memory 200188 kb
Host smart-3be8338b-ba4b-46ec-b675-180a3ffd84f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19889601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.19889601
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2982665308
Short name T259
Test name
Test status
Simulation time 29996420 ps
CPU time 0.59 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:36:52 PM PDT 24
Peak memory 195784 kb
Host smart-10420767-29c1-4b59-b344-f6b1f9e69f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982665308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2982665308
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2070883400
Short name T243
Test name
Test status
Simulation time 5600844134 ps
CPU time 72.69 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:38:13 PM PDT 24
Peak memory 200192 kb
Host smart-fcacbc71-7013-4d26-837b-0b608a4462ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070883400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2070883400
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.20991869
Short name T317
Test name
Test status
Simulation time 222603197 ps
CPU time 9.75 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:10 PM PDT 24
Peak memory 200232 kb
Host smart-2ec3bd87-5a4d-4893-9303-e6d72026647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20991869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.20991869
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3167156986
Short name T222
Test name
Test status
Simulation time 3821211615 ps
CPU time 612.62 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 723036 kb
Host smart-2225d920-1331-4aec-a7fb-a8f6272c8d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167156986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3167156986
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3230739462
Short name T467
Test name
Test status
Simulation time 11775847465 ps
CPU time 141.47 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:39:13 PM PDT 24
Peak memory 200268 kb
Host smart-e453a639-f905-46ed-bf0a-379cbb9db600
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230739462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3230739462
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3100230842
Short name T412
Test name
Test status
Simulation time 151336622 ps
CPU time 8.62 seconds
Started Jul 18 05:36:41 PM PDT 24
Finished Jul 18 05:36:53 PM PDT 24
Peak memory 200176 kb
Host smart-8fb77692-80e5-4b6c-adc9-b058d140ea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100230842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3100230842
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4041606391
Short name T362
Test name
Test status
Simulation time 1314904962 ps
CPU time 10.53 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:37:12 PM PDT 24
Peak memory 200184 kb
Host smart-0c6efa1a-1477-48e9-98ce-e29384db5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041606391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4041606391
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4080558446
Short name T403
Test name
Test status
Simulation time 21706316954 ps
CPU time 415.39 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:44:01 PM PDT 24
Peak memory 216800 kb
Host smart-4b5a33f1-e1f9-4f6a-927f-528ee0ba64cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080558446 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4080558446
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1333310621
Short name T248
Test name
Test status
Simulation time 17853081263 ps
CPU time 68.47 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:38:04 PM PDT 24
Peak memory 200300 kb
Host smart-e1e9b05b-d47b-496f-8347-7bcaf8d96199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333310621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1333310621
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.436092457
Short name T295
Test name
Test status
Simulation time 12423301 ps
CPU time 0.59 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:37:00 PM PDT 24
Peak memory 195820 kb
Host smart-ff98eca0-ca44-4cd6-956d-71282e8be095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436092457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.436092457
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3429726341
Short name T289
Test name
Test status
Simulation time 3488825735 ps
CPU time 100.26 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:38:48 PM PDT 24
Peak memory 200348 kb
Host smart-73438376-8cfd-44bc-9633-62b1e59ae6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429726341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3429726341
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3185529944
Short name T252
Test name
Test status
Simulation time 375274465 ps
CPU time 1.95 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:42 PM PDT 24
Peak memory 200252 kb
Host smart-6d573f0b-0f61-403f-b946-47450d3a3ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185529944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3185529944
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3086157164
Short name T56
Test name
Test status
Simulation time 3789931900 ps
CPU time 161.39 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:39:24 PM PDT 24
Peak memory 598632 kb
Host smart-c6f6efc9-818a-492f-a44a-c7946d7b1481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086157164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3086157164
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1490438794
Short name T338
Test name
Test status
Simulation time 10169336259 ps
CPU time 153.35 seconds
Started Jul 18 05:36:55 PM PDT 24
Finished Jul 18 05:39:36 PM PDT 24
Peak memory 200228 kb
Host smart-b9c98296-566d-4f64-b9f5-36ccd676978c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490438794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1490438794
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2461328241
Short name T221
Test name
Test status
Simulation time 1357561302 ps
CPU time 78.06 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:38:02 PM PDT 24
Peak memory 200256 kb
Host smart-f7838dc9-fa08-43b1-863c-e1e1031638ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461328241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2461328241
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.869772311
Short name T450
Test name
Test status
Simulation time 1323751886 ps
CPU time 15.78 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:37:17 PM PDT 24
Peak memory 200240 kb
Host smart-78733b92-a5c0-4aab-bacf-6086100c95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869772311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.869772311
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.727931208
Short name T143
Test name
Test status
Simulation time 12859223090 ps
CPU time 1449.03 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 06:01:08 PM PDT 24
Peak memory 719916 kb
Host smart-8b258e0a-c316-40f5-b549-3a7c6022dd45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727931208 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.727931208
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3489447271
Short name T376
Test name
Test status
Simulation time 3543939069 ps
CPU time 47.74 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:37:50 PM PDT 24
Peak memory 200248 kb
Host smart-d240f0fb-f0bc-456c-8bd3-d4bfddb0f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489447271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3489447271
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3215401738
Short name T263
Test name
Test status
Simulation time 42814491 ps
CPU time 0.58 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:36:49 PM PDT 24
Peak memory 195764 kb
Host smart-b69e609d-07bc-4145-8568-378f3282c4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215401738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3215401738
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4084471972
Short name T483
Test name
Test status
Simulation time 5995891907 ps
CPU time 91.96 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:38:32 PM PDT 24
Peak memory 200228 kb
Host smart-366b5a5f-4c81-41c2-a016-02d422a05769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084471972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4084471972
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4100094166
Short name T264
Test name
Test status
Simulation time 10560805109 ps
CPU time 35.58 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 05:37:19 PM PDT 24
Peak memory 208564 kb
Host smart-ee171494-2003-410f-a758-079764445f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100094166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4100094166
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1389024177
Short name T528
Test name
Test status
Simulation time 2123239998 ps
CPU time 107.81 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:38:46 PM PDT 24
Peak memory 568740 kb
Host smart-f393c4a2-41f7-47cc-971e-e3acf368471a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389024177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1389024177
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2399490530
Short name T118
Test name
Test status
Simulation time 630894648 ps
CPU time 8.54 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:37:01 PM PDT 24
Peak memory 200164 kb
Host smart-1544fc69-f485-4c9e-9a41-2a63a6135367
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399490530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2399490530
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3792258406
Short name T285
Test name
Test status
Simulation time 72901643009 ps
CPU time 189.8 seconds
Started Jul 18 05:36:55 PM PDT 24
Finished Jul 18 05:40:12 PM PDT 24
Peak memory 200316 kb
Host smart-496de9fa-f2ce-4ab5-952f-c68190d90db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792258406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3792258406
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1748519313
Short name T234
Test name
Test status
Simulation time 71562952 ps
CPU time 3.37 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:36:54 PM PDT 24
Peak memory 200172 kb
Host smart-7e026ab5-abc8-4276-92c9-ca37946df84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748519313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1748519313
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1101341378
Short name T139
Test name
Test status
Simulation time 58962164686 ps
CPU time 831.52 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:50:49 PM PDT 24
Peak memory 200228 kb
Host smart-85bab178-df15-463a-9b84-2bce4420725e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101341378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1101341378
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2369174829
Short name T327
Test name
Test status
Simulation time 5727442742 ps
CPU time 49.42 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:37:47 PM PDT 24
Peak memory 200248 kb
Host smart-efdafef2-1fbb-49c7-9d66-a889e87b966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369174829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2369174829
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4199590556
Short name T45
Test name
Test status
Simulation time 36461770 ps
CPU time 0.57 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:36:52 PM PDT 24
Peak memory 196876 kb
Host smart-b2ddaafa-1cf1-43d0-a28e-4860d3050255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199590556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4199590556
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4189293862
Short name T281
Test name
Test status
Simulation time 1566309904 ps
CPU time 88.72 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:38:23 PM PDT 24
Peak memory 200216 kb
Host smart-33456d78-7f75-444c-9da3-a7a91c434bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189293862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4189293862
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3669886388
Short name T282
Test name
Test status
Simulation time 1535795479 ps
CPU time 22.48 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:23 PM PDT 24
Peak memory 200244 kb
Host smart-e5feb965-f089-4c77-9c19-6149623556f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669886388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3669886388
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1945594603
Short name T363
Test name
Test status
Simulation time 7657048801 ps
CPU time 322.14 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:42:22 PM PDT 24
Peak memory 398800 kb
Host smart-e75395e6-567f-4596-961c-69f0399e22c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945594603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1945594603
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2173527484
Short name T162
Test name
Test status
Simulation time 29088718721 ps
CPU time 100.14 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:38:40 PM PDT 24
Peak memory 200272 kb
Host smart-bd7b6bbd-270c-43e4-ab0c-866931118dce
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173527484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2173527484
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1440590306
Short name T241
Test name
Test status
Simulation time 9739416285 ps
CPU time 107.04 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:38:45 PM PDT 24
Peak memory 200332 kb
Host smart-feb3defa-4d90-4aa0-8f4d-d4342a9ad22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440590306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1440590306
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2846064674
Short name T218
Test name
Test status
Simulation time 2501838899 ps
CPU time 15.03 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:15 PM PDT 24
Peak memory 200428 kb
Host smart-51521864-83f8-4e88-82d2-020c279f32ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846064674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2846064674
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3108624236
Short name T70
Test name
Test status
Simulation time 442181267944 ps
CPU time 1996.12 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 06:10:15 PM PDT 24
Peak memory 782300 kb
Host smart-593d13de-19fc-4c6a-bb35-90c45a86811d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108624236 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3108624236
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.747223820
Short name T452
Test name
Test status
Simulation time 2307067397 ps
CPU time 105.8 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:38:42 PM PDT 24
Peak memory 200308 kb
Host smart-b22efa50-7290-4f32-b1d5-583a6c02eb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747223820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.747223820
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.656975945
Short name T29
Test name
Test status
Simulation time 67645165 ps
CPU time 0.59 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 196204 kb
Host smart-20559fb5-71be-4767-b1a9-5cb2c28e5329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656975945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.656975945
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1618537138
Short name T9
Test name
Test status
Simulation time 1566581397 ps
CPU time 46.92 seconds
Started Jul 18 05:36:56 PM PDT 24
Finished Jul 18 05:37:50 PM PDT 24
Peak memory 200224 kb
Host smart-30a374f0-4bdc-4272-aeb5-feda26ea7972
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618537138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1618537138
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.203894260
Short name T468
Test name
Test status
Simulation time 929083618 ps
CPU time 53.14 seconds
Started Jul 18 05:36:56 PM PDT 24
Finished Jul 18 05:37:57 PM PDT 24
Peak memory 200172 kb
Host smart-2298fa50-bfd7-4416-95c1-b3834e23bcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203894260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.203894260
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2785049987
Short name T390
Test name
Test status
Simulation time 15026200659 ps
CPU time 1291.45 seconds
Started Jul 18 05:36:51 PM PDT 24
Finished Jul 18 05:58:31 PM PDT 24
Peak memory 747296 kb
Host smart-efb99747-a667-454c-8c50-418b39ea5005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785049987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2785049987
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1915510486
Short name T333
Test name
Test status
Simulation time 2986067266 ps
CPU time 90.05 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:38:28 PM PDT 24
Peak memory 200504 kb
Host smart-e98e4e50-82be-48b8-a50a-dc20689841f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915510486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1915510486
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3310020892
Short name T195
Test name
Test status
Simulation time 7521819839 ps
CPU time 50.26 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:37:44 PM PDT 24
Peak memory 200304 kb
Host smart-90a3b727-01be-4304-a574-469d604f0518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310020892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3310020892
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2602317146
Short name T399
Test name
Test status
Simulation time 117737840 ps
CPU time 0.97 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:37:02 PM PDT 24
Peak memory 199972 kb
Host smart-b0b8a7b0-c062-42a0-9a4c-e37610a3d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602317146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2602317146
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.387683803
Short name T69
Test name
Test status
Simulation time 38477115450 ps
CPU time 249.38 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:40:56 PM PDT 24
Peak memory 216628 kb
Host smart-df29d9be-0c8e-4aff-b4dc-47bf0fa091f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387683803 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.387683803
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.136887092
Short name T260
Test name
Test status
Simulation time 12822926742 ps
CPU time 128.39 seconds
Started Jul 18 05:36:57 PM PDT 24
Finished Jul 18 05:39:12 PM PDT 24
Peak memory 200208 kb
Host smart-a0ce36ae-7201-4b41-8e89-1390a3831629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136887092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.136887092
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.705670330
Short name T270
Test name
Test status
Simulation time 16079668 ps
CPU time 0.62 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:36:53 PM PDT 24
Peak memory 196808 kb
Host smart-7a05eef5-9685-4154-abdc-7b5d4c629294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705670330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.705670330
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2082922929
Short name T437
Test name
Test status
Simulation time 1822669162 ps
CPU time 50.85 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:37:47 PM PDT 24
Peak memory 200248 kb
Host smart-75b3b300-b23f-44d4-91ea-b41a1d5030aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082922929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2082922929
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.317389084
Short name T288
Test name
Test status
Simulation time 1222508889 ps
CPU time 22.7 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:22 PM PDT 24
Peak memory 200184 kb
Host smart-25221691-b4d3-4472-a113-08d5afc5ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317389084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.317389084
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3671204584
Short name T382
Test name
Test status
Simulation time 1479858381 ps
CPU time 27.83 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:37:25 PM PDT 24
Peak memory 243844 kb
Host smart-5ac64226-7f0c-4232-98ac-1e6d8d723f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671204584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3671204584
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.563808773
Short name T460
Test name
Test status
Simulation time 6127201303 ps
CPU time 160.23 seconds
Started Jul 18 05:36:42 PM PDT 24
Finished Jul 18 05:39:25 PM PDT 24
Peak memory 200228 kb
Host smart-aba9f7e1-3126-445e-88ce-90d60331f95e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563808773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.563808773
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2510338032
Short name T305
Test name
Test status
Simulation time 7449753112 ps
CPU time 134.24 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:39:08 PM PDT 24
Peak memory 216516 kb
Host smart-b5663e60-a1e3-4d80-a3e2-d3c847d9190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510338032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2510338032
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3394875410
Short name T498
Test name
Test status
Simulation time 50366543 ps
CPU time 0.79 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:37:00 PM PDT 24
Peak memory 198832 kb
Host smart-b68c37f7-d761-4944-8ed3-d477bb0151d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394875410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3394875410
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2861851054
Short name T490
Test name
Test status
Simulation time 6715471453 ps
CPU time 1201.2 seconds
Started Jul 18 05:36:52 PM PDT 24
Finished Jul 18 05:57:01 PM PDT 24
Peak memory 757240 kb
Host smart-0ea7a74b-3e61-4946-bca1-5ab4e9d634a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861851054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2861851054
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3670303709
Short name T486
Test name
Test status
Simulation time 6451878431 ps
CPU time 119.96 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:39:05 PM PDT 24
Peak memory 200288 kb
Host smart-f7ca2dde-ddb2-465a-84d5-dba146b0f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670303709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3670303709
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1335082817
Short name T456
Test name
Test status
Simulation time 37965597 ps
CPU time 0.61 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:19 PM PDT 24
Peak memory 196204 kb
Host smart-046c94eb-1a7e-42f7-9dff-23e3ef322071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335082817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1335082817
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3975811629
Short name T44
Test name
Test status
Simulation time 1203272904 ps
CPU time 69.09 seconds
Started Jul 18 05:37:06 PM PDT 24
Finished Jul 18 05:38:20 PM PDT 24
Peak memory 200164 kb
Host smart-e7b99c24-2e50-480b-aa19-fa449c22a252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975811629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3975811629
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.383718570
Short name T339
Test name
Test status
Simulation time 9900427363 ps
CPU time 46.08 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:37:57 PM PDT 24
Peak memory 200320 kb
Host smart-c1848589-b655-4e1a-b717-7df8230f160f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383718570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.383718570
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3266941188
Short name T173
Test name
Test status
Simulation time 2216017911 ps
CPU time 417.05 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 679592 kb
Host smart-cd7e4af6-a676-4ac3-95da-da078315a257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266941188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3266941188
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2416377176
Short name T146
Test name
Test status
Simulation time 14735433663 ps
CPU time 41.44 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:37:50 PM PDT 24
Peak memory 200228 kb
Host smart-af14e3e8-b152-4ac6-b5a1-be3b3b95ab0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416377176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2416377176
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2453798508
Short name T145
Test name
Test status
Simulation time 274272989 ps
CPU time 14.23 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:37:20 PM PDT 24
Peak memory 200252 kb
Host smart-a9e1965b-f973-454e-9a75-b9689273d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453798508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2453798508
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3630926866
Short name T387
Test name
Test status
Simulation time 337947562 ps
CPU time 10.37 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:37:07 PM PDT 24
Peak memory 200252 kb
Host smart-e2fc8a4a-fec6-443e-938e-9ee5d697bb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630926866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3630926866
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.191235842
Short name T73
Test name
Test status
Simulation time 134108362119 ps
CPU time 3980.06 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 06:43:28 PM PDT 24
Peak memory 807252 kb
Host smart-1e9d858e-7ba0-4128-9ba8-ed8063226caa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191235842 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.191235842
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2025455596
Short name T77
Test name
Test status
Simulation time 2016309943 ps
CPU time 86.86 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:38:38 PM PDT 24
Peak memory 200200 kb
Host smart-09b7588c-7037-4e11-bea1-8e139c5cb8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025455596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2025455596
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1954975768
Short name T465
Test name
Test status
Simulation time 26962332 ps
CPU time 0.61 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:36:51 PM PDT 24
Peak memory 196840 kb
Host smart-c67d7250-dba5-4717-a50e-5ab9ce9962bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954975768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1954975768
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1385174636
Short name T322
Test name
Test status
Simulation time 10108636752 ps
CPU time 109.62 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:38:03 PM PDT 24
Peak memory 200304 kb
Host smart-3327534c-0a68-4cf7-9d6a-4821af8003f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385174636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1385174636
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1426365129
Short name T513
Test name
Test status
Simulation time 4606994347 ps
CPU time 58.91 seconds
Started Jul 18 05:36:10 PM PDT 24
Finished Jul 18 05:37:16 PM PDT 24
Peak memory 200304 kb
Host smart-6da3e761-2967-474f-9dde-3b6069e25041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426365129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1426365129
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.822137718
Short name T157
Test name
Test status
Simulation time 5912298923 ps
CPU time 455.64 seconds
Started Jul 18 05:36:05 PM PDT 24
Finished Jul 18 05:43:42 PM PDT 24
Peak memory 613284 kb
Host smart-0bb3e13f-8ea9-4fcd-a6dc-1b2cbde6ecda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822137718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.822137718
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2750947647
Short name T280
Test name
Test status
Simulation time 9393545446 ps
CPU time 172.85 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:39:07 PM PDT 24
Peak memory 200016 kb
Host smart-5ab89589-f43a-423f-8071-b38d391a1ca0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750947647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2750947647
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2604404529
Short name T184
Test name
Test status
Simulation time 39526784039 ps
CPU time 155.68 seconds
Started Jul 18 05:36:11 PM PDT 24
Finished Jul 18 05:38:54 PM PDT 24
Peak memory 208456 kb
Host smart-29cf378e-d15d-494c-8740-49419fdda4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604404529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2604404529
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.936486246
Short name T481
Test name
Test status
Simulation time 1390130676 ps
CPU time 8.28 seconds
Started Jul 18 05:36:09 PM PDT 24
Finished Jul 18 05:36:25 PM PDT 24
Peak memory 200080 kb
Host smart-16b793a5-a240-472e-9808-d5ad6a5ac0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936486246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.936486246
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3574518358
Short name T249
Test name
Test status
Simulation time 102820403062 ps
CPU time 2560.59 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 06:19:25 PM PDT 24
Peak memory 780340 kb
Host smart-94e45d25-ef20-4abd-99c8-72add1d63918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574518358 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3574518358
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1278237567
Short name T14
Test name
Test status
Simulation time 4683207347 ps
CPU time 44.11 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 05:36:55 PM PDT 24
Peak memory 200308 kb
Host smart-eb5b253d-0527-4438-94d0-63f0e4d337e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1278237567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1278237567
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1657898805
Short name T516
Test name
Test status
Simulation time 29885222790 ps
CPU time 90.91 seconds
Started Jul 18 05:36:27 PM PDT 24
Finished Jul 18 05:38:01 PM PDT 24
Peak memory 200316 kb
Host smart-ecfbc794-8645-4700-a20e-068f86ccd16a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1657898805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1657898805
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.768876929
Short name T340
Test name
Test status
Simulation time 4291751126 ps
CPU time 71.11 seconds
Started Jul 18 05:36:36 PM PDT 24
Finished Jul 18 05:37:49 PM PDT 24
Peak memory 200304 kb
Host smart-9fda6306-7377-4a0b-9093-39a5cffae852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=768876929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.768876929
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.380608991
Short name T436
Test name
Test status
Simulation time 36898687897 ps
CPU time 504.67 seconds
Started Jul 18 05:36:08 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 200304 kb
Host smart-e4e184bb-1c6f-4810-8267-becd7a9f1494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=380608991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.380608991
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1596981169
Short name T132
Test name
Test status
Simulation time 218759715806 ps
CPU time 2734.46 seconds
Started Jul 18 05:36:10 PM PDT 24
Finished Jul 18 06:21:52 PM PDT 24
Peak memory 215732 kb
Host smart-25324d44-c7d2-4d65-bacb-e61a9d8ffd5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1596981169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1596981169
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2244505187
Short name T26
Test name
Test status
Simulation time 513523547686 ps
CPU time 2286.96 seconds
Started Jul 18 05:36:07 PM PDT 24
Finished Jul 18 06:14:19 PM PDT 24
Peak memory 216284 kb
Host smart-fcb2b143-4dc3-4500-bc3b-c653c75ef586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2244505187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2244505187
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4172445750
Short name T515
Test name
Test status
Simulation time 3143889821 ps
CPU time 73.59 seconds
Started Jul 18 05:36:06 PM PDT 24
Finished Jul 18 05:37:23 PM PDT 24
Peak memory 200204 kb
Host smart-5fc2f6c2-834e-4485-95c5-7be718381e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172445750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4172445750
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1049348058
Short name T291
Test name
Test status
Simulation time 40629558 ps
CPU time 0.6 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:37:02 PM PDT 24
Peak memory 196864 kb
Host smart-77100d32-fca2-4777-90f0-c5238eb177eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049348058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1049348058
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.423404216
Short name T30
Test name
Test status
Simulation time 23609117842 ps
CPU time 84.2 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:38:31 PM PDT 24
Peak memory 200300 kb
Host smart-860cfed4-fc93-4e8d-acee-9a7f5bdfeebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423404216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.423404216
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4168669145
Short name T527
Test name
Test status
Simulation time 4793126993 ps
CPU time 23.04 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:37:28 PM PDT 24
Peak memory 200312 kb
Host smart-8c9015c9-d78a-40e4-b6e9-545585391c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168669145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4168669145
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2619663468
Short name T494
Test name
Test status
Simulation time 2296951302 ps
CPU time 374.17 seconds
Started Jul 18 05:37:08 PM PDT 24
Finished Jul 18 05:43:27 PM PDT 24
Peak memory 501564 kb
Host smart-9accd9ba-a763-4807-979b-7dd73a5eb261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2619663468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2619663468
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4088916112
Short name T200
Test name
Test status
Simulation time 7857225952 ps
CPU time 66.25 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:38:13 PM PDT 24
Peak memory 200336 kb
Host smart-9a008172-ffac-42e9-b98d-cb3f0a6053ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088916112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4088916112
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.314996517
Short name T304
Test name
Test status
Simulation time 6409130494 ps
CPU time 85.94 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:38:31 PM PDT 24
Peak memory 200328 kb
Host smart-21553835-5150-4f68-9530-600a248d500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314996517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.314996517
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2130230365
Short name T133
Test name
Test status
Simulation time 967457278 ps
CPU time 14.64 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:37:27 PM PDT 24
Peak memory 200212 kb
Host smart-10e0de37-8cf1-4c53-8594-355877870c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130230365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2130230365
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.17974980
Short name T213
Test name
Test status
Simulation time 14208334858 ps
CPU time 1475.85 seconds
Started Jul 18 05:36:55 PM PDT 24
Finished Jul 18 06:01:39 PM PDT 24
Peak memory 765504 kb
Host smart-f396521a-4a55-4550-9439-ec54c9c1f733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17974980 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.17974980
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.164528089
Short name T430
Test name
Test status
Simulation time 9661200532 ps
CPU time 88.43 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:38:34 PM PDT 24
Peak memory 200252 kb
Host smart-f9931771-cda6-44c4-9611-fb80cc97b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164528089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.164528089
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1144377962
Short name T153
Test name
Test status
Simulation time 48948135 ps
CPU time 0.63 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:37:08 PM PDT 24
Peak memory 196184 kb
Host smart-8cd3c4fc-e8da-44af-876f-89d839a6fa20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144377962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1144377962
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1952732677
Short name T480
Test name
Test status
Simulation time 41371823 ps
CPU time 2.17 seconds
Started Jul 18 05:37:03 PM PDT 24
Finished Jul 18 05:37:11 PM PDT 24
Peak memory 200160 kb
Host smart-79470457-b21c-44b8-abc0-27e9356e226b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952732677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1952732677
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.184914818
Short name T331
Test name
Test status
Simulation time 3504192217 ps
CPU time 49.49 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:37:55 PM PDT 24
Peak memory 200332 kb
Host smart-25ae57eb-21c3-442e-af1d-06dd077f95af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184914818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.184914818
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2052166705
Short name T42
Test name
Test status
Simulation time 21133438447 ps
CPU time 816.74 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 643616 kb
Host smart-1992c420-24e2-47b4-bb89-c01bea2097db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052166705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2052166705
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3642469379
Short name T158
Test name
Test status
Simulation time 8972022124 ps
CPU time 32.56 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:37:41 PM PDT 24
Peak memory 200504 kb
Host smart-66152bf7-6690-454c-8a3b-ffc27e48db6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642469379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3642469379
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1149893035
Short name T251
Test name
Test status
Simulation time 3976555578 ps
CPU time 113.1 seconds
Started Jul 18 05:36:55 PM PDT 24
Finished Jul 18 05:38:56 PM PDT 24
Peak memory 208460 kb
Host smart-130adf47-d89a-4e1a-a63d-e1f2a17f68ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149893035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1149893035
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4119316874
Short name T190
Test name
Test status
Simulation time 4086658710 ps
CPU time 10.87 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:37:18 PM PDT 24
Peak memory 200284 kb
Host smart-1c3af21d-4f05-454d-a67f-5e504f73c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119316874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4119316874
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2302885206
Short name T31
Test name
Test status
Simulation time 214726118217 ps
CPU time 2098.85 seconds
Started Jul 18 05:37:06 PM PDT 24
Finished Jul 18 06:12:10 PM PDT 24
Peak memory 705372 kb
Host smart-d2be3d44-a3fd-4a67-8808-46f7719252e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302885206 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2302885206
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1369625343
Short name T273
Test name
Test status
Simulation time 4576002873 ps
CPU time 20.87 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:37:26 PM PDT 24
Peak memory 200300 kb
Host smart-7f2bc1db-ce52-49e0-a6e3-33a496bb75a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369625343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1369625343
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.996740044
Short name T228
Test name
Test status
Simulation time 37203741 ps
CPU time 0.59 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:37:06 PM PDT 24
Peak memory 195768 kb
Host smart-28762527-c776-42f3-bbda-f587a2c57b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996740044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.996740044
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3034561478
Short name T457
Test name
Test status
Simulation time 11157841072 ps
CPU time 52.15 seconds
Started Jul 18 05:37:04 PM PDT 24
Finished Jul 18 05:38:02 PM PDT 24
Peak memory 208400 kb
Host smart-fc295798-db0a-408b-ae29-b05b8a770289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034561478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3034561478
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2195495733
Short name T258
Test name
Test status
Simulation time 4428540315 ps
CPU time 57.15 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:38:05 PM PDT 24
Peak memory 208496 kb
Host smart-f13d8630-eb7a-405b-aa4c-cd7648f7ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195495733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2195495733
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_error.4011724712
Short name T210
Test name
Test status
Simulation time 36946510385 ps
CPU time 172.57 seconds
Started Jul 18 05:37:04 PM PDT 24
Finished Jul 18 05:40:02 PM PDT 24
Peak memory 200296 kb
Host smart-1057c37a-5f64-41e0-ada9-39753b713f42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011724712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4011724712
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3557207679
Short name T349
Test name
Test status
Simulation time 56130833768 ps
CPU time 160.12 seconds
Started Jul 18 05:36:53 PM PDT 24
Finished Jul 18 05:39:40 PM PDT 24
Peak memory 200220 kb
Host smart-1faf0099-8d89-4ea3-8f81-f16e06e3247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557207679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3557207679
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2186809069
Short name T131
Test name
Test status
Simulation time 12243974015 ps
CPU time 11.4 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:37:17 PM PDT 24
Peak memory 200288 kb
Host smart-655382df-10ba-4687-9524-efddcf776b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186809069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2186809069
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2524439229
Short name T386
Test name
Test status
Simulation time 243269792339 ps
CPU time 428.76 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:44:13 PM PDT 24
Peak memory 200204 kb
Host smart-b2744536-0183-4aad-96ac-19dc67f6c17a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524439229 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2524439229
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3703726720
Short name T227
Test name
Test status
Simulation time 24691870571 ps
CPU time 106.44 seconds
Started Jul 18 05:37:06 PM PDT 24
Finished Jul 18 05:38:58 PM PDT 24
Peak memory 200244 kb
Host smart-11693446-b9d6-420b-a92a-6afbd90c8368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703726720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3703726720
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.712333917
Short name T374
Test name
Test status
Simulation time 14228566 ps
CPU time 0.59 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:37:07 PM PDT 24
Peak memory 196176 kb
Host smart-0416abc4-f0d1-45cb-a3ac-a641765c2c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712333917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.712333917
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1230085150
Short name T168
Test name
Test status
Simulation time 1880472045 ps
CPU time 50.23 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:37:56 PM PDT 24
Peak memory 200304 kb
Host smart-20057173-0e14-47d0-b0b8-8baaf0057ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230085150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1230085150
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.926251194
Short name T283
Test name
Test status
Simulation time 1257640453 ps
CPU time 59.15 seconds
Started Jul 18 05:37:18 PM PDT 24
Finished Jul 18 05:38:21 PM PDT 24
Peak memory 200164 kb
Host smart-d09779c8-3b13-4211-934c-8196979fb47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926251194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.926251194
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1608030911
Short name T359
Test name
Test status
Simulation time 74652221786 ps
CPU time 938.61 seconds
Started Jul 18 05:36:56 PM PDT 24
Finished Jul 18 05:52:42 PM PDT 24
Peak memory 704748 kb
Host smart-6e40892e-a407-44a1-b49d-eb0f3a2edeb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608030911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1608030911
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2290226985
Short name T502
Test name
Test status
Simulation time 14156928210 ps
CPU time 91.15 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:38:37 PM PDT 24
Peak memory 200220 kb
Host smart-9fcd5dcf-96a7-49e4-9eea-dd79c747150d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290226985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2290226985
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3612651258
Short name T369
Test name
Test status
Simulation time 11723025217 ps
CPU time 131.01 seconds
Started Jul 18 05:37:08 PM PDT 24
Finished Jul 18 05:39:23 PM PDT 24
Peak memory 200316 kb
Host smart-d64ed199-b69b-458d-b9bf-d1cd825bc8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612651258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3612651258
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4028473948
Short name T358
Test name
Test status
Simulation time 4194063306 ps
CPU time 11.48 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:37:23 PM PDT 24
Peak memory 200332 kb
Host smart-313969fe-eaa7-4a25-9def-d20cfb6b3418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028473948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4028473948
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1083999574
Short name T71
Test name
Test status
Simulation time 267826742121 ps
CPU time 2973.47 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 06:26:44 PM PDT 24
Peak memory 821544 kb
Host smart-42b8b5bc-c1ad-4b62-b708-1cce55b812cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083999574 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1083999574
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.967692353
Short name T458
Test name
Test status
Simulation time 18352228661 ps
CPU time 106.91 seconds
Started Jul 18 05:37:08 PM PDT 24
Finished Jul 18 05:38:59 PM PDT 24
Peak memory 200348 kb
Host smart-2c4dc228-22cc-42ec-932c-91db19eacaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967692353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.967692353
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2486136311
Short name T491
Test name
Test status
Simulation time 24061878 ps
CPU time 0.63 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:37:11 PM PDT 24
Peak memory 196208 kb
Host smart-59719d18-3d1b-465c-a3c3-c9eb38e16b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486136311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2486136311
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.821288016
Short name T455
Test name
Test status
Simulation time 5297910324 ps
CPU time 92.42 seconds
Started Jul 18 05:36:55 PM PDT 24
Finished Jul 18 05:38:35 PM PDT 24
Peak memory 200244 kb
Host smart-20152bc9-c0e9-47ad-952a-250a66030074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821288016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.821288016
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.845833094
Short name T352
Test name
Test status
Simulation time 1062796598 ps
CPU time 13.87 seconds
Started Jul 18 05:36:56 PM PDT 24
Finished Jul 18 05:37:18 PM PDT 24
Peak memory 200228 kb
Host smart-4be06356-9c70-4886-8293-9d3867ff61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845833094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.845833094
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4192534891
Short name T421
Test name
Test status
Simulation time 1064238285 ps
CPU time 64.69 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:38:17 PM PDT 24
Peak memory 324416 kb
Host smart-30f36aff-55dd-4d8f-ae38-06be5e4073f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192534891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4192534891
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2960296604
Short name T504
Test name
Test status
Simulation time 68005679478 ps
CPU time 118.78 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:39:05 PM PDT 24
Peak memory 200280 kb
Host smart-ee6a3f3d-3c67-46bf-93af-00db09b19027
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960296604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2960296604
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.408091998
Short name T276
Test name
Test status
Simulation time 2565119357 ps
CPU time 75.09 seconds
Started Jul 18 05:36:55 PM PDT 24
Finished Jul 18 05:38:18 PM PDT 24
Peak memory 200232 kb
Host smart-a555e7b3-9f78-4bd2-aab2-6701b650e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408091998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.408091998
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2408160499
Short name T211
Test name
Test status
Simulation time 288573063 ps
CPU time 3.62 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:37:10 PM PDT 24
Peak memory 200292 kb
Host smart-06dff2d0-b50f-4ae8-8770-7b8b3e1eab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408160499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2408160499
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2718328900
Short name T201
Test name
Test status
Simulation time 14868560696 ps
CPU time 1692.06 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 06:05:24 PM PDT 24
Peak memory 730612 kb
Host smart-ea52a2ec-2f21-4cda-9cb3-dfb2fd840505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718328900 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2718328900
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2230096634
Short name T265
Test name
Test status
Simulation time 6094456029 ps
CPU time 106.47 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:38:51 PM PDT 24
Peak memory 200252 kb
Host smart-05ee6564-3d09-43d1-a8b8-fe795edbfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230096634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2230096634
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3614145607
Short name T151
Test name
Test status
Simulation time 45693395 ps
CPU time 0.58 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:37:05 PM PDT 24
Peak memory 196136 kb
Host smart-c094dce3-4cbc-4f29-977b-1907ad14d710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614145607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3614145607
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2489676355
Short name T477
Test name
Test status
Simulation time 134543795 ps
CPU time 2.04 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:37:04 PM PDT 24
Peak memory 200108 kb
Host smart-50861827-c2bc-48c5-ae8b-47bd4a59e413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489676355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2489676355
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2188743301
Short name T375
Test name
Test status
Simulation time 794839824 ps
CPU time 36.65 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:37:44 PM PDT 24
Peak memory 200304 kb
Host smart-551b7d99-6bb3-401f-b2f0-2ba0dbbd07be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188743301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2188743301
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2333599901
Short name T160
Test name
Test status
Simulation time 12881808559 ps
CPU time 1082.93 seconds
Started Jul 18 05:36:54 PM PDT 24
Finished Jul 18 05:55:04 PM PDT 24
Peak memory 743984 kb
Host smart-7364918f-c0ca-4c40-b321-9c446df8b1c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333599901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2333599901
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3953344663
Short name T512
Test name
Test status
Simulation time 18470285259 ps
CPU time 249.14 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:41:14 PM PDT 24
Peak memory 200276 kb
Host smart-fc083745-207c-4362-8e8c-a7e4defdc5e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953344663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3953344663
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1106276895
Short name T316
Test name
Test status
Simulation time 43350183 ps
CPU time 2.43 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:37:10 PM PDT 24
Peak memory 200180 kb
Host smart-fe22125a-1c0c-4e61-adf0-58e58019b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106276895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1106276895
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3580844808
Short name T475
Test name
Test status
Simulation time 127298657953 ps
CPU time 1089.21 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:55:14 PM PDT 24
Peak memory 200296 kb
Host smart-40c2dbf0-411a-4bd5-8452-e9c5538c46b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580844808 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3580844808
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2140640506
Short name T493
Test name
Test status
Simulation time 79293749321 ps
CPU time 75.51 seconds
Started Jul 18 05:37:04 PM PDT 24
Finished Jul 18 05:38:26 PM PDT 24
Peak memory 200368 kb
Host smart-e50f8838-f38e-4983-b772-a71306ee916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140640506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2140640506
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2411891791
Short name T334
Test name
Test status
Simulation time 12612640 ps
CPU time 0.6 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:37:12 PM PDT 24
Peak memory 196092 kb
Host smart-6d6bce16-8882-4880-b2d6-096bcd8687f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411891791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2411891791
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.576116466
Short name T161
Test name
Test status
Simulation time 1690529286 ps
CPU time 13.28 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:37:24 PM PDT 24
Peak memory 200240 kb
Host smart-86d00cb2-d213-43b3-ba2d-9c23696c2cd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576116466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.576116466
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2671799609
Short name T287
Test name
Test status
Simulation time 821498394 ps
CPU time 11.41 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:37:28 PM PDT 24
Peak memory 200148 kb
Host smart-b8a6626b-e975-4dfd-a9fa-e1aa0e7a4cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671799609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2671799609
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.167397422
Short name T178
Test name
Test status
Simulation time 5813398460 ps
CPU time 216.26 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:40:41 PM PDT 24
Peak memory 434740 kb
Host smart-d95f79bf-92b3-461c-b661-caefdc9cdbb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167397422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.167397422
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.746189257
Short name T301
Test name
Test status
Simulation time 53024217378 ps
CPU time 164.88 seconds
Started Jul 18 05:37:03 PM PDT 24
Finished Jul 18 05:39:54 PM PDT 24
Peak memory 200476 kb
Host smart-0ae7a156-8110-4dab-a99a-0188ac050986
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746189257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.746189257
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.337844272
Short name T476
Test name
Test status
Simulation time 6459705182 ps
CPU time 30.74 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:37:43 PM PDT 24
Peak memory 216504 kb
Host smart-cb3931bf-2c6c-4714-8684-78ff40360e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337844272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.337844272
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.713696720
Short name T428
Test name
Test status
Simulation time 2928859523 ps
CPU time 10.61 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:37:19 PM PDT 24
Peak memory 200244 kb
Host smart-6b410a91-cd65-47c0-8df4-beb25c096fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713696720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.713696720
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3481045311
Short name T372
Test name
Test status
Simulation time 136828958945 ps
CPU time 896.54 seconds
Started Jul 18 05:36:57 PM PDT 24
Finished Jul 18 05:52:01 PM PDT 24
Peak memory 200252 kb
Host smart-c669bb3c-4d70-4a43-bbab-b4246213e773
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481045311 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3481045311
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.379502809
Short name T402
Test name
Test status
Simulation time 8931613109 ps
CPU time 44.8 seconds
Started Jul 18 05:37:04 PM PDT 24
Finished Jul 18 05:37:55 PM PDT 24
Peak memory 200368 kb
Host smart-fe507269-f9bd-4d0e-be40-d9be08bf3319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379502809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.379502809
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3843092719
Short name T152
Test name
Test status
Simulation time 11311015 ps
CPU time 0.63 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:37:09 PM PDT 24
Peak memory 195752 kb
Host smart-24509b28-96aa-4796-8716-e18f611eb6e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843092719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3843092719
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2418016483
Short name T156
Test name
Test status
Simulation time 386828705 ps
CPU time 5.97 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:37:13 PM PDT 24
Peak memory 199824 kb
Host smart-8277a324-4571-4774-b763-c0de5fcc9ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418016483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2418016483
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2821552599
Short name T134
Test name
Test status
Simulation time 1175183717 ps
CPU time 21.83 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:37:32 PM PDT 24
Peak memory 200264 kb
Host smart-86b80bc1-a2f4-4774-8212-6a10d162a602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821552599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2821552599
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3969097671
Short name T57
Test name
Test status
Simulation time 22379470606 ps
CPU time 575.97 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:46:42 PM PDT 24
Peak memory 683644 kb
Host smart-1ecff8ce-c105-4102-81fe-960fad613c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969097671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3969097671
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4139370888
Short name T308
Test name
Test status
Simulation time 12448567736 ps
CPU time 78.92 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:38:25 PM PDT 24
Peak memory 200296 kb
Host smart-f6e64b81-ebf2-4c0f-bc44-497076e9d690
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139370888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4139370888
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4287247585
Short name T244
Test name
Test status
Simulation time 4847586878 ps
CPU time 9.22 seconds
Started Jul 18 05:37:06 PM PDT 24
Finished Jul 18 05:37:21 PM PDT 24
Peak memory 200360 kb
Host smart-6e6c79f8-deda-4cc3-9f87-bc9a01927fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287247585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4287247585
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4150485536
Short name T297
Test name
Test status
Simulation time 1594954723 ps
CPU time 9.84 seconds
Started Jul 18 05:37:04 PM PDT 24
Finished Jul 18 05:37:19 PM PDT 24
Peak memory 200160 kb
Host smart-f33b90eb-c4ac-4a3a-a0ee-320d719fd817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150485536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4150485536
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2858531553
Short name T345
Test name
Test status
Simulation time 67881734923 ps
CPU time 1199.49 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:57:10 PM PDT 24
Peak memory 672076 kb
Host smart-409ed3a8-b40a-4b12-846c-9bd5acd33126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858531553 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2858531553
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1885017537
Short name T449
Test name
Test status
Simulation time 2288072861 ps
CPU time 107.15 seconds
Started Jul 18 05:37:06 PM PDT 24
Finished Jul 18 05:38:59 PM PDT 24
Peak memory 200252 kb
Host smart-c2fb65a9-0296-4ae0-8a65-ef1e8870bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885017537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1885017537
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2689974738
Short name T435
Test name
Test status
Simulation time 69647960 ps
CPU time 0.66 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:37:07 PM PDT 24
Peak memory 196192 kb
Host smart-d65e9b34-3e31-46b0-86f6-89044eefa14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689974738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2689974738
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.647891990
Short name T175
Test name
Test status
Simulation time 736796876 ps
CPU time 41.61 seconds
Started Jul 18 05:37:04 PM PDT 24
Finished Jul 18 05:37:52 PM PDT 24
Peak memory 200144 kb
Host smart-7bc923b5-8058-42a7-bc9e-302667e2ba62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647891990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.647891990
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2107283322
Short name T181
Test name
Test status
Simulation time 5933958626 ps
CPU time 78.45 seconds
Started Jul 18 05:36:59 PM PDT 24
Finished Jul 18 05:38:24 PM PDT 24
Peak memory 200288 kb
Host smart-eacb7895-be63-49ef-a573-833e93916eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107283322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2107283322
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4209165767
Short name T52
Test name
Test status
Simulation time 3895861577 ps
CPU time 703.71 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:48:55 PM PDT 24
Peak memory 734560 kb
Host smart-154fd4ee-3c6d-48df-9832-b04e880a175e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209165767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4209165767
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3312530431
Short name T271
Test name
Test status
Simulation time 17586635756 ps
CPU time 79.52 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:38:41 PM PDT 24
Peak memory 200300 kb
Host smart-595b3d83-1491-4e99-9d39-5c71d7ba4caa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312530431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3312530431
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.832437615
Short name T318
Test name
Test status
Simulation time 8931766022 ps
CPU time 159.01 seconds
Started Jul 18 05:36:57 PM PDT 24
Finished Jul 18 05:39:43 PM PDT 24
Peak memory 200296 kb
Host smart-08d467d5-4950-4075-8e09-3f012e38072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832437615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.832437615
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.490303183
Short name T411
Test name
Test status
Simulation time 1538778213 ps
CPU time 18.56 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:37:36 PM PDT 24
Peak memory 200316 kb
Host smart-34378265-3474-4677-87f9-958e680de7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490303183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.490303183
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.779170382
Short name T117
Test name
Test status
Simulation time 32636850157 ps
CPU time 142.7 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:39:28 PM PDT 24
Peak memory 200308 kb
Host smart-f098e668-4972-4668-a42d-8855f65d12a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779170382 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.779170382
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.260177874
Short name T269
Test name
Test status
Simulation time 23581025066 ps
CPU time 54.84 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:38:02 PM PDT 24
Peak memory 200296 kb
Host smart-16992feb-f237-4527-a356-32393ea4c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260177874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.260177874
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1252436342
Short name T307
Test name
Test status
Simulation time 21691197 ps
CPU time 0.58 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:37:18 PM PDT 24
Peak memory 195836 kb
Host smart-7e1390d8-c8ad-4ee0-a449-df2680786f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252436342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1252436342
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3511414719
Short name T524
Test name
Test status
Simulation time 250602000 ps
CPU time 7.87 seconds
Started Jul 18 05:37:46 PM PDT 24
Finished Jul 18 05:37:56 PM PDT 24
Peak memory 200172 kb
Host smart-dd46a3e1-cb76-43ec-a73c-d5cd3b9d1767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511414719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3511414719
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1572698068
Short name T247
Test name
Test status
Simulation time 8513249416 ps
CPU time 35.67 seconds
Started Jul 18 05:37:00 PM PDT 24
Finished Jul 18 05:37:43 PM PDT 24
Peak memory 208568 kb
Host smart-2117540c-0864-4429-a145-f0d99efa5679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572698068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1572698068
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1081030898
Short name T220
Test name
Test status
Simulation time 2967310117 ps
CPU time 475.73 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:45:04 PM PDT 24
Peak memory 643152 kb
Host smart-930c769e-db7b-412e-8929-f7f5a1654150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081030898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1081030898
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1749304661
Short name T381
Test name
Test status
Simulation time 5429342017 ps
CPU time 22.02 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:37:29 PM PDT 24
Peak memory 200212 kb
Host smart-a224e53b-2f0b-4233-9a88-ee6312e04ce0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749304661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1749304661
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3999005224
Short name T180
Test name
Test status
Simulation time 2176366519 ps
CPU time 118.08 seconds
Started Jul 18 05:36:57 PM PDT 24
Finished Jul 18 05:39:02 PM PDT 24
Peak memory 200404 kb
Host smart-fa38441d-603d-4057-94cc-0351e1202201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999005224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3999005224
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.256567389
Short name T174
Test name
Test status
Simulation time 1124289295 ps
CPU time 14.24 seconds
Started Jul 18 05:36:53 PM PDT 24
Finished Jul 18 05:37:15 PM PDT 24
Peak memory 200328 kb
Host smart-b50ab212-f629-4e94-983e-e806764f43da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256567389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.256567389
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1572649303
Short name T446
Test name
Test status
Simulation time 66266480434 ps
CPU time 1017.32 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:54:05 PM PDT 24
Peak memory 666068 kb
Host smart-8de3d812-2f29-4335-b6c1-a280656ba4d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572649303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1572649303
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3079618468
Short name T209
Test name
Test status
Simulation time 1701383829 ps
CPU time 11.43 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:30 PM PDT 24
Peak memory 200244 kb
Host smart-85d19806-8887-4029-97d2-c8be9629b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079618468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3079618468
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2279110477
Short name T217
Test name
Test status
Simulation time 11627701 ps
CPU time 0.6 seconds
Started Jul 18 05:36:22 PM PDT 24
Finished Jul 18 05:36:29 PM PDT 24
Peak memory 196204 kb
Host smart-a66df400-7218-4b46-8de0-0a241dcc9725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279110477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2279110477
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3625623257
Short name T11
Test name
Test status
Simulation time 6387112236 ps
CPU time 101.66 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:38:32 PM PDT 24
Peak memory 208484 kb
Host smart-64592092-53ed-4831-951b-21d346ba3fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625623257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3625623257
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3812540353
Short name T514
Test name
Test status
Simulation time 3927455421 ps
CPU time 57.14 seconds
Started Jul 18 05:36:25 PM PDT 24
Finished Jul 18 05:37:27 PM PDT 24
Peak memory 200260 kb
Host smart-f4dad201-661d-4a2d-94d0-6a1f3e695e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812540353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3812540353
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2068530868
Short name T208
Test name
Test status
Simulation time 6812489591 ps
CPU time 590.58 seconds
Started Jul 18 05:36:29 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 679620 kb
Host smart-d373b809-642c-4986-a986-4b49ac38edd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068530868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2068530868
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3916034780
Short name T196
Test name
Test status
Simulation time 251902939594 ps
CPU time 283.63 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:41:19 PM PDT 24
Peak memory 200224 kb
Host smart-5e8e81bb-db64-443f-ad4b-d59f5253a75f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916034780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3916034780
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1207836466
Short name T185
Test name
Test status
Simulation time 409169172 ps
CPU time 21.19 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:37:03 PM PDT 24
Peak memory 200156 kb
Host smart-2f3c236e-f612-456c-9422-880de1d562fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207836466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1207836466
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2865606754
Short name T46
Test name
Test status
Simulation time 130285600 ps
CPU time 0.82 seconds
Started Jul 18 05:36:32 PM PDT 24
Finished Jul 18 05:36:33 PM PDT 24
Peak memory 218508 kb
Host smart-a3afcaad-dad4-4a6b-a4d4-95128426ccf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865606754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2865606754
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2882170960
Short name T256
Test name
Test status
Simulation time 855184251 ps
CPU time 9.38 seconds
Started Jul 18 05:36:31 PM PDT 24
Finished Jul 18 05:36:42 PM PDT 24
Peak memory 200224 kb
Host smart-832e2110-e9bf-4aad-b48c-6d10dd2d7fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882170960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2882170960
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2440272841
Short name T114
Test name
Test status
Simulation time 28797872575 ps
CPU time 538.67 seconds
Started Jul 18 05:36:26 PM PDT 24
Finished Jul 18 05:45:29 PM PDT 24
Peak memory 208492 kb
Host smart-974857e4-02d3-4644-a4f0-d93a7b34d20e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440272841 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2440272841
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1574168927
Short name T64
Test name
Test status
Simulation time 19428031448 ps
CPU time 752.45 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:49:24 PM PDT 24
Peak memory 706172 kb
Host smart-dae47d79-e9d1-43c7-9e21-0da3f07ed740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574168927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1574168927
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1460318778
Short name T454
Test name
Test status
Simulation time 17406437390 ps
CPU time 82.36 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 05:38:14 PM PDT 24
Peak memory 200468 kb
Host smart-1d2f7342-a6f7-4e8d-a99e-3c5c54605952
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1460318778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1460318778
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.4227512576
Short name T236
Test name
Test status
Simulation time 1801124421 ps
CPU time 62.43 seconds
Started Jul 18 05:36:32 PM PDT 24
Finished Jul 18 05:37:36 PM PDT 24
Peak memory 200176 kb
Host smart-18be0b41-72b4-4153-af53-85814dfd329d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4227512576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4227512576
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.430934452
Short name T150
Test name
Test status
Simulation time 2070234005 ps
CPU time 67.32 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:37:50 PM PDT 24
Peak memory 200172 kb
Host smart-7d1641fe-774e-47ae-b19c-9bd28d3d9186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=430934452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.430934452
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1352660379
Short name T440
Test name
Test status
Simulation time 19702522882 ps
CPU time 537.76 seconds
Started Jul 18 05:36:20 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 200260 kb
Host smart-dbe53ca4-640c-49ef-89ea-94656182ffd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1352660379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1352660379
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2905656284
Short name T299
Test name
Test status
Simulation time 536780232186 ps
CPU time 2516.47 seconds
Started Jul 18 05:36:22 PM PDT 24
Finished Jul 18 06:18:25 PM PDT 24
Peak memory 208576 kb
Host smart-d7a1b39d-4bc6-420d-ab92-78e8e48aec39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2905656284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2905656284
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.466325657
Short name T496
Test name
Test status
Simulation time 404035597205 ps
CPU time 2257.06 seconds
Started Jul 18 05:36:45 PM PDT 24
Finished Jul 18 06:14:28 PM PDT 24
Peak memory 216644 kb
Host smart-e6e1651c-6d0c-4f2e-9b17-8f31da8331aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=466325657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.466325657
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2752438338
Short name T447
Test name
Test status
Simulation time 12725543330 ps
CPU time 58.6 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:37:40 PM PDT 24
Peak memory 200232 kb
Host smart-9fde9e1d-8111-44a2-82b0-89c36e09a26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752438338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2752438338
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.788734184
Short name T203
Test name
Test status
Simulation time 43289074 ps
CPU time 0.61 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:37:11 PM PDT 24
Peak memory 195068 kb
Host smart-f3e1a8ad-6b1f-4e67-844c-cfc3df76981e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788734184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.788734184
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3221711217
Short name T389
Test name
Test status
Simulation time 1542536658 ps
CPU time 91.56 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:38:50 PM PDT 24
Peak memory 200140 kb
Host smart-d82c3e84-2479-44af-b6e4-2dfd7dbb513b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221711217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3221711217
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3198911535
Short name T275
Test name
Test status
Simulation time 922657008 ps
CPU time 8.72 seconds
Started Jul 18 05:36:58 PM PDT 24
Finished Jul 18 05:37:14 PM PDT 24
Peak memory 200228 kb
Host smart-ad4d5f13-48b2-44cb-8072-a83b9ee6f1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198911535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3198911535
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3646790568
Short name T148
Test name
Test status
Simulation time 923881529 ps
CPU time 151.68 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:39:42 PM PDT 24
Peak memory 466664 kb
Host smart-08654e11-ca3d-40ce-885a-07d079e5db3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646790568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3646790568
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.785230699
Short name T400
Test name
Test status
Simulation time 43008332780 ps
CPU time 188.91 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:40:21 PM PDT 24
Peak memory 200336 kb
Host smart-aaeb6276-832c-47af-9a03-de397cf0af93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785230699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.785230699
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.755303915
Short name T415
Test name
Test status
Simulation time 47189109506 ps
CPU time 147.75 seconds
Started Jul 18 05:37:09 PM PDT 24
Finished Jul 18 05:39:41 PM PDT 24
Peak memory 200324 kb
Host smart-629dfec8-8b41-444c-b15b-9635f308f3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755303915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.755303915
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2940798752
Short name T463
Test name
Test status
Simulation time 1109156191 ps
CPU time 2.37 seconds
Started Jul 18 05:37:03 PM PDT 24
Finished Jul 18 05:37:12 PM PDT 24
Peak memory 200248 kb
Host smart-d194602f-a69d-4288-93b6-508710c38ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940798752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2940798752
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3334620968
Short name T76
Test name
Test status
Simulation time 232872255637 ps
CPU time 718.99 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 05:49:10 PM PDT 24
Peak memory 200208 kb
Host smart-31142183-63b5-4629-a13f-6e430f381721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334620968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3334620968
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3104191479
Short name T75
Test name
Test status
Simulation time 6682910417 ps
CPU time 21.07 seconds
Started Jul 18 05:37:03 PM PDT 24
Finished Jul 18 05:37:30 PM PDT 24
Peak memory 200364 kb
Host smart-dea0506f-9c08-4385-9b70-40f8cdd92f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104191479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3104191479
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2214009931
Short name T154
Test name
Test status
Simulation time 66147747 ps
CPU time 0.6 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:37:09 PM PDT 24
Peak memory 196312 kb
Host smart-5f3b58f6-e67b-4f8a-97e6-bc17ada62687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214009931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2214009931
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.87860331
Short name T407
Test name
Test status
Simulation time 621885520 ps
CPU time 7.5 seconds
Started Jul 18 05:37:11 PM PDT 24
Finished Jul 18 05:37:22 PM PDT 24
Peak memory 200172 kb
Host smart-e63cb6aa-374a-490a-9650-e50e209343a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87860331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.87860331
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4024691825
Short name T186
Test name
Test status
Simulation time 16769706231 ps
CPU time 51.6 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:38:12 PM PDT 24
Peak memory 200300 kb
Host smart-3f0b0de5-5ed5-4e0c-9421-f0948eb678eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024691825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4024691825
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2031627553
Short name T442
Test name
Test status
Simulation time 5491457354 ps
CPU time 827.3 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:51:08 PM PDT 24
Peak memory 682220 kb
Host smart-9d4d177e-7b7d-4cc4-8ab9-f59eff76c881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031627553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2031627553
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1063126373
Short name T298
Test name
Test status
Simulation time 31143718689 ps
CPU time 145.13 seconds
Started Jul 18 05:37:03 PM PDT 24
Finished Jul 18 05:39:34 PM PDT 24
Peak memory 200296 kb
Host smart-8828fcd4-8824-41d8-a976-d883f7797fc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063126373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1063126373
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2675090405
Short name T518
Test name
Test status
Simulation time 7381455769 ps
CPU time 104.97 seconds
Started Jul 18 05:37:07 PM PDT 24
Finished Jul 18 05:38:57 PM PDT 24
Peak memory 208500 kb
Host smart-3bdc2af8-24fa-4629-b514-9f3f11393f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675090405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2675090405
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3512302736
Short name T235
Test name
Test status
Simulation time 1729737169 ps
CPU time 5.4 seconds
Started Jul 18 05:37:02 PM PDT 24
Finished Jul 18 05:37:14 PM PDT 24
Peak memory 200232 kb
Host smart-a01cf7c8-eb09-4d06-be94-30ba4a704a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512302736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3512302736
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.884983457
Short name T484
Test name
Test status
Simulation time 27236889794 ps
CPU time 3328.9 seconds
Started Jul 18 05:37:05 PM PDT 24
Finished Jul 18 06:32:40 PM PDT 24
Peak memory 784644 kb
Host smart-cab1a6b4-0712-492e-b384-b7a052a30d36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884983457 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.884983457
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.662197690
Short name T267
Test name
Test status
Simulation time 1901762778 ps
CPU time 51.33 seconds
Started Jul 18 05:37:01 PM PDT 24
Finished Jul 18 05:37:59 PM PDT 24
Peak memory 200144 kb
Host smart-87eb95ed-873f-4700-99ff-7b08211ebd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662197690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.662197690
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2628036866
Short name T397
Test name
Test status
Simulation time 11368683 ps
CPU time 0.6 seconds
Started Jul 18 05:37:21 PM PDT 24
Finished Jul 18 05:37:24 PM PDT 24
Peak memory 195164 kb
Host smart-15b4cdab-0bea-4f57-b5b5-1e1909cafe99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628036866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2628036866
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3906932651
Short name T257
Test name
Test status
Simulation time 1741163452 ps
CPU time 52.05 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:38:11 PM PDT 24
Peak memory 200164 kb
Host smart-2d4b101f-2251-4b91-aff8-068d463b93b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906932651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3906932651
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3368613189
Short name T197
Test name
Test status
Simulation time 70660226 ps
CPU time 0.66 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:37:17 PM PDT 24
Peak memory 196932 kb
Host smart-d57dde6f-8e6a-4f35-be69-b887b8c644db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368613189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3368613189
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.139676865
Short name T312
Test name
Test status
Simulation time 15206153053 ps
CPU time 586.33 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:47:05 PM PDT 24
Peak memory 682032 kb
Host smart-36fe0de2-5b41-41a5-bfeb-777192696bce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139676865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.139676865
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.950997567
Short name T163
Test name
Test status
Simulation time 1559943484 ps
CPU time 47.69 seconds
Started Jul 18 05:37:31 PM PDT 24
Finished Jul 18 05:38:24 PM PDT 24
Peak memory 200436 kb
Host smart-3d49ee45-75fb-4203-897e-650a70e6dda2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950997567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.950997567
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.160948684
Short name T199
Test name
Test status
Simulation time 19782997673 ps
CPU time 173.71 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:40:14 PM PDT 24
Peak memory 200264 kb
Host smart-0ddcac79-9b70-4235-abb9-b6506d6235f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160948684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.160948684
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1426252354
Short name T171
Test name
Test status
Simulation time 2614950999 ps
CPU time 7.47 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:27 PM PDT 24
Peak memory 200308 kb
Host smart-88c5ca9a-aa94-41c2-a61b-c64d582ad71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426252354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1426252354
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.914827263
Short name T324
Test name
Test status
Simulation time 32175079557 ps
CPU time 298.22 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:42:15 PM PDT 24
Peak memory 200276 kb
Host smart-8793adbe-a0ba-443b-8bd6-857d7f6f000e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914827263 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.914827263
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3307923457
Short name T116
Test name
Test status
Simulation time 2559230349 ps
CPU time 45.96 seconds
Started Jul 18 05:37:21 PM PDT 24
Finished Jul 18 05:38:09 PM PDT 24
Peak memory 200308 kb
Host smart-794253c5-3044-4da1-b331-9819037d25ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307923457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3307923457
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2936864778
Short name T149
Test name
Test status
Simulation time 128444628 ps
CPU time 0.6 seconds
Started Jul 18 05:37:31 PM PDT 24
Finished Jul 18 05:37:36 PM PDT 24
Peak memory 196184 kb
Host smart-0b704188-9d51-46c2-ac54-ac05dbdacf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936864778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2936864778
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.636490064
Short name T177
Test name
Test status
Simulation time 304798387 ps
CPU time 4.91 seconds
Started Jul 18 05:37:33 PM PDT 24
Finished Jul 18 05:37:42 PM PDT 24
Peak memory 200140 kb
Host smart-3588919a-78c9-43b6-9344-962d201276ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636490064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.636490064
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2694846520
Short name T511
Test name
Test status
Simulation time 6774532132 ps
CPU time 272.48 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:41:50 PM PDT 24
Peak memory 429112 kb
Host smart-30e2b532-c151-4bc0-bff3-d3e26e32d901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694846520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2694846520
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1932655512
Short name T321
Test name
Test status
Simulation time 20326145327 ps
CPU time 138.49 seconds
Started Jul 18 05:37:20 PM PDT 24
Finished Jul 18 05:39:41 PM PDT 24
Peak memory 200428 kb
Host smart-66a2c39a-098d-4a8b-b6b7-8d3559d65db4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932655512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1932655512
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2459836424
Short name T294
Test name
Test status
Simulation time 10610584957 ps
CPU time 35.99 seconds
Started Jul 18 05:37:26 PM PDT 24
Finished Jul 18 05:38:06 PM PDT 24
Peak memory 200376 kb
Host smart-e75faf02-c199-4d11-8e0c-9c96beb14131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459836424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2459836424
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.735513733
Short name T423
Test name
Test status
Simulation time 101878991 ps
CPU time 1.18 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:21 PM PDT 24
Peak memory 200164 kb
Host smart-34297105-3285-419f-b45a-e592a5d7ae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735513733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.735513733
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2393279182
Short name T74
Test name
Test status
Simulation time 27710066802 ps
CPU time 179.4 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:40:17 PM PDT 24
Peak memory 200208 kb
Host smart-333dcfb4-3dbe-4364-90d9-512011c38761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393279182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2393279182
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.444608463
Short name T522
Test name
Test status
Simulation time 682405011 ps
CPU time 4.04 seconds
Started Jul 18 05:37:25 PM PDT 24
Finished Jul 18 05:37:31 PM PDT 24
Peak memory 200484 kb
Host smart-d846cd5c-e7d7-4d4a-a6dc-4df8af2cc5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444608463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.444608463
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1087562078
Short name T254
Test name
Test status
Simulation time 15532245 ps
CPU time 0.6 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:37:22 PM PDT 24
Peak memory 196144 kb
Host smart-8fb1fd9f-5a8f-4eaf-b5aa-d0a41d95acaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087562078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1087562078
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2668301430
Short name T18
Test name
Test status
Simulation time 3931927167 ps
CPU time 86.69 seconds
Started Jul 18 05:37:19 PM PDT 24
Finished Jul 18 05:38:49 PM PDT 24
Peak memory 200256 kb
Host smart-68c9d921-73f5-4de1-938c-2b3023b858ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668301430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2668301430
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2513282702
Short name T343
Test name
Test status
Simulation time 2317079960 ps
CPU time 8.26 seconds
Started Jul 18 05:37:20 PM PDT 24
Finished Jul 18 05:37:31 PM PDT 24
Peak memory 200152 kb
Host smart-23dc63bd-257a-40fa-b463-3817d06fd88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513282702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2513282702
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1457380843
Short name T505
Test name
Test status
Simulation time 7328684193 ps
CPU time 1080.25 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:55:21 PM PDT 24
Peak memory 733508 kb
Host smart-18bf6a48-1de9-40c6-b858-804b3361c5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457380843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1457380843
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2728425287
Short name T129
Test name
Test status
Simulation time 47650949423 ps
CPU time 198.23 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:40:38 PM PDT 24
Peak memory 200428 kb
Host smart-91c16c22-4e40-400a-b287-1ebbd08345f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728425287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2728425287
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4286499046
Short name T205
Test name
Test status
Simulation time 1793209214 ps
CPU time 101 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:38:58 PM PDT 24
Peak memory 200304 kb
Host smart-f22ce123-a881-445f-9867-ca74cf2ea26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286499046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4286499046
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.480495887
Short name T28
Test name
Test status
Simulation time 879444462 ps
CPU time 12.23 seconds
Started Jul 18 05:37:18 PM PDT 24
Finished Jul 18 05:37:33 PM PDT 24
Peak memory 200192 kb
Host smart-19b8e50f-47db-4e6a-bcaf-dcbfec1d0cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480495887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.480495887
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1944840432
Short name T79
Test name
Test status
Simulation time 6343857667 ps
CPU time 21.47 seconds
Started Jul 18 05:37:34 PM PDT 24
Finished Jul 18 05:38:01 PM PDT 24
Peak memory 200320 kb
Host smart-fc57e904-8c59-4db8-a08e-2addce9eeb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944840432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1944840432
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.220010931
Short name T466
Test name
Test status
Simulation time 15121049 ps
CPU time 0.59 seconds
Started Jul 18 05:37:28 PM PDT 24
Finished Jul 18 05:37:32 PM PDT 24
Peak memory 196856 kb
Host smart-36322e06-5f79-4a58-89f6-2b79947a127a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220010931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.220010931
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2868021758
Short name T86
Test name
Test status
Simulation time 1269066363 ps
CPU time 69.8 seconds
Started Jul 18 05:37:18 PM PDT 24
Finished Jul 18 05:38:32 PM PDT 24
Peak memory 200196 kb
Host smart-898c9284-ca04-407b-8703-d294a63ffa45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868021758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2868021758
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2525646893
Short name T508
Test name
Test status
Simulation time 14811139452 ps
CPU time 26.05 seconds
Started Jul 18 05:37:29 PM PDT 24
Finished Jul 18 05:37:58 PM PDT 24
Peak memory 200308 kb
Host smart-fa6f9597-08de-43aa-8f92-3fa578ba7cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525646893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2525646893
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2927333628
Short name T274
Test name
Test status
Simulation time 3691372720 ps
CPU time 743.14 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:49:40 PM PDT 24
Peak memory 682700 kb
Host smart-d6aaa166-b69f-4727-a802-eb140c0863c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927333628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2927333628
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.931764530
Short name T348
Test name
Test status
Simulation time 10687150918 ps
CPU time 91.78 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:38:49 PM PDT 24
Peak memory 200284 kb
Host smart-f92eeba3-a3c4-4899-be3c-3e89f0ecad4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931764530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.931764530
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4255504662
Short name T54
Test name
Test status
Simulation time 863507885 ps
CPU time 8.29 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:37:24 PM PDT 24
Peak memory 200240 kb
Host smart-93cfd74d-d880-4092-b3d5-eeec9776223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255504662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4255504662
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2236946016
Short name T239
Test name
Test status
Simulation time 1172823787 ps
CPU time 16.21 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:37:34 PM PDT 24
Peak memory 200196 kb
Host smart-242664cc-50f3-40ed-afed-274f1396c39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236946016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2236946016
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1264995869
Short name T405
Test name
Test status
Simulation time 209095514900 ps
CPU time 1412.42 seconds
Started Jul 18 05:37:30 PM PDT 24
Finished Jul 18 06:01:07 PM PDT 24
Peak memory 759400 kb
Host smart-b95b5259-19ae-4f2f-bfda-d5e5da10123c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264995869 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1264995869
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.845982902
Short name T323
Test name
Test status
Simulation time 6637616084 ps
CPU time 107.73 seconds
Started Jul 18 05:37:31 PM PDT 24
Finished Jul 18 05:39:23 PM PDT 24
Peak memory 200316 kb
Host smart-fe1984a3-6111-4e96-a203-3cb3510b04a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845982902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.845982902
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4247632063
Short name T444
Test name
Test status
Simulation time 35353778 ps
CPU time 0.58 seconds
Started Jul 18 05:37:18 PM PDT 24
Finished Jul 18 05:37:22 PM PDT 24
Peak memory 195180 kb
Host smart-524d1597-7690-4c93-b3ce-6ead79a95616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247632063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4247632063
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3763049879
Short name T238
Test name
Test status
Simulation time 106307756 ps
CPU time 5.04 seconds
Started Jul 18 05:37:19 PM PDT 24
Finished Jul 18 05:37:27 PM PDT 24
Peak memory 200256 kb
Host smart-f32a22e9-d20e-4c95-a5ff-50cb267ded4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763049879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3763049879
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2999486412
Short name T347
Test name
Test status
Simulation time 12804664423 ps
CPU time 45.16 seconds
Started Jul 18 05:37:35 PM PDT 24
Finished Jul 18 05:38:25 PM PDT 24
Peak memory 208524 kb
Host smart-e6bf9491-a0de-4197-9141-8a7b241390c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999486412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2999486412
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2297221319
Short name T364
Test name
Test status
Simulation time 16911087007 ps
CPU time 1620.64 seconds
Started Jul 18 05:37:28 PM PDT 24
Finished Jul 18 06:04:32 PM PDT 24
Peak memory 788432 kb
Host smart-f8efb0d8-4883-4e2b-b932-a98bb6a9783a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297221319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2297221319
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2446942693
Short name T147
Test name
Test status
Simulation time 902740011 ps
CPU time 6.21 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:37:23 PM PDT 24
Peak memory 200168 kb
Host smart-12d81cad-fb71-40f1-a968-a590353b7431
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446942693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2446942693
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.385207500
Short name T388
Test name
Test status
Simulation time 11571434652 ps
CPU time 143.64 seconds
Started Jul 18 05:37:16 PM PDT 24
Finished Jul 18 05:39:44 PM PDT 24
Peak memory 216576 kb
Host smart-5187c5dd-d2bd-4547-8abb-bbc760567e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385207500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.385207500
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.782974424
Short name T268
Test name
Test status
Simulation time 457485422 ps
CPU time 5.7 seconds
Started Jul 18 05:37:17 PM PDT 24
Finished Jul 18 05:37:26 PM PDT 24
Peak memory 200256 kb
Host smart-2c570c1b-26e1-49dc-a80f-86482c22c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782974424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.782974424
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1572657204
Short name T72
Test name
Test status
Simulation time 1245624527592 ps
CPU time 1452.31 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 747440 kb
Host smart-e6e19861-9f11-41f1-876e-26b9110faeb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572657204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1572657204
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.384425974
Short name T473
Test name
Test status
Simulation time 3076733986 ps
CPU time 54.34 seconds
Started Jul 18 05:37:18 PM PDT 24
Finished Jul 18 05:38:16 PM PDT 24
Peak memory 200212 kb
Host smart-04fe903b-a358-4b29-a897-498c997c73c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384425974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.384425974
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.652430599
Short name T448
Test name
Test status
Simulation time 22292081 ps
CPU time 0.59 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:20 PM PDT 24
Peak memory 195836 kb
Host smart-3443e6b5-69cd-46d2-86b5-03d8644bb82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652430599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.652430599
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4179391253
Short name T225
Test name
Test status
Simulation time 7233899481 ps
CPU time 56.93 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:38:15 PM PDT 24
Peak memory 200160 kb
Host smart-b4d97dcb-10b0-432d-9d27-28b9eace4d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179391253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4179391253
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.412482891
Short name T15
Test name
Test status
Simulation time 3302681927 ps
CPU time 41.81 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:38:02 PM PDT 24
Peak memory 200368 kb
Host smart-acd3b454-ac07-45fa-bd5f-298ee8c62382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412482891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.412482891
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3691989921
Short name T212
Test name
Test status
Simulation time 28957030820 ps
CPU time 813.09 seconds
Started Jul 18 05:37:13 PM PDT 24
Finished Jul 18 05:50:50 PM PDT 24
Peak memory 705356 kb
Host smart-557210c9-1357-46f1-ada5-6f52d92ab15e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691989921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3691989921
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3975287302
Short name T393
Test name
Test status
Simulation time 5088613782 ps
CPU time 88.18 seconds
Started Jul 18 05:37:33 PM PDT 24
Finished Jul 18 05:39:07 PM PDT 24
Peak memory 200300 kb
Host smart-53f9b7d0-1799-4cea-9085-d129deade1ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975287302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3975287302
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2140637942
Short name T5
Test name
Test status
Simulation time 71022852920 ps
CPU time 241.72 seconds
Started Jul 18 05:37:32 PM PDT 24
Finished Jul 18 05:41:39 PM PDT 24
Peak memory 208524 kb
Host smart-594f4cca-e937-4e70-9c95-1906caa8de15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140637942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2140637942
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.521645625
Short name T439
Test name
Test status
Simulation time 142336163 ps
CPU time 1.94 seconds
Started Jul 18 05:37:12 PM PDT 24
Finished Jul 18 05:37:17 PM PDT 24
Peak memory 200216 kb
Host smart-d43cabbd-91c9-482a-a4be-8d6974daeee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521645625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.521645625
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.599978121
Short name T506
Test name
Test status
Simulation time 23491779922 ps
CPU time 619.21 seconds
Started Jul 18 05:37:18 PM PDT 24
Finished Jul 18 05:47:41 PM PDT 24
Peak memory 215744 kb
Host smart-ab7ea81c-4774-49f5-b9c9-70c90337ecad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599978121 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.599978121
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3949468838
Short name T78
Test name
Test status
Simulation time 7571210197 ps
CPU time 135.44 seconds
Started Jul 18 05:37:25 PM PDT 24
Finished Jul 18 05:39:43 PM PDT 24
Peak memory 200316 kb
Host smart-7aa9580d-cc0a-4468-9c7f-e7042e374f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949468838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3949468838
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.931630947
Short name T471
Test name
Test status
Simulation time 67060610 ps
CPU time 0.57 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:37:19 PM PDT 24
Peak memory 195836 kb
Host smart-d010033f-9874-4ee2-b1f1-ceea9f351613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931630947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.931630947
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1253924188
Short name T292
Test name
Test status
Simulation time 613125286 ps
CPU time 35.6 seconds
Started Jul 18 05:37:19 PM PDT 24
Finished Jul 18 05:37:58 PM PDT 24
Peak memory 200180 kb
Host smart-62435c12-f843-44e8-a133-2813c3ca55c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253924188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1253924188
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.553050886
Short name T398
Test name
Test status
Simulation time 1033095359 ps
CPU time 52.84 seconds
Started Jul 18 05:37:12 PM PDT 24
Finished Jul 18 05:38:08 PM PDT 24
Peak memory 200268 kb
Host smart-d18a1e06-2cb8-4a54-b0a4-ceb549e9eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553050886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.553050886
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2134302014
Short name T482
Test name
Test status
Simulation time 7300239047 ps
CPU time 406.1 seconds
Started Jul 18 05:37:31 PM PDT 24
Finished Jul 18 05:44:21 PM PDT 24
Peak memory 664184 kb
Host smart-fa1a0623-19f9-419c-9329-3ca1342f77dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134302014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2134302014
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1288945708
Short name T417
Test name
Test status
Simulation time 10099964539 ps
CPU time 87.52 seconds
Started Jul 18 05:37:29 PM PDT 24
Finished Jul 18 05:39:00 PM PDT 24
Peak memory 200340 kb
Host smart-3f4014d2-aeac-4b1a-bf18-14248e735393
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288945708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1288945708
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1201021066
Short name T183
Test name
Test status
Simulation time 17843260067 ps
CPU time 133.83 seconds
Started Jul 18 05:37:25 PM PDT 24
Finished Jul 18 05:39:40 PM PDT 24
Peak memory 200228 kb
Host smart-ec3da7d3-0fb7-48ea-b988-171f81c23ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201021066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1201021066
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2319598015
Short name T278
Test name
Test status
Simulation time 213116512 ps
CPU time 3.57 seconds
Started Jul 18 05:37:23 PM PDT 24
Finished Jul 18 05:37:28 PM PDT 24
Peak memory 200184 kb
Host smart-30ed3394-312c-4ab8-b584-82afa62094d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319598015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2319598015
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3511663144
Short name T354
Test name
Test status
Simulation time 7832723691 ps
CPU time 101.24 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:38:59 PM PDT 24
Peak memory 200312 kb
Host smart-1f5b999d-a008-4810-a658-457832a0641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511663144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3511663144
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.665363497
Short name T478
Test name
Test status
Simulation time 41483173 ps
CPU time 0.61 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:20 PM PDT 24
Peak memory 196132 kb
Host smart-5189b8f6-4fd4-4000-8554-6b6ac8cf7e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665363497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.665363497
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2488766476
Short name T385
Test name
Test status
Simulation time 421936518 ps
CPU time 24.85 seconds
Started Jul 18 05:37:12 PM PDT 24
Finished Jul 18 05:37:40 PM PDT 24
Peak memory 200180 kb
Host smart-01851e33-764d-4db4-a5f9-1152e2070e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488766476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2488766476
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.524654487
Short name T293
Test name
Test status
Simulation time 14454168931 ps
CPU time 45.26 seconds
Started Jul 18 05:37:12 PM PDT 24
Finished Jul 18 05:38:01 PM PDT 24
Peak memory 200260 kb
Host smart-324fe8be-fc1d-4da0-be17-fc459f9cbbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524654487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.524654487
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.766087543
Short name T286
Test name
Test status
Simulation time 21249076453 ps
CPU time 1130.39 seconds
Started Jul 18 05:37:14 PM PDT 24
Finished Jul 18 05:56:08 PM PDT 24
Peak memory 742552 kb
Host smart-278c144f-da93-4e79-9b0a-72c3a80abae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766087543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.766087543
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2724397344
Short name T526
Test name
Test status
Simulation time 181932731 ps
CPU time 10.12 seconds
Started Jul 18 05:37:28 PM PDT 24
Finished Jul 18 05:37:41 PM PDT 24
Peak memory 200224 kb
Host smart-086f675e-4267-4ce5-8458-5c8012267893
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724397344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2724397344
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3833372640
Short name T136
Test name
Test status
Simulation time 6708939646 ps
CPU time 118.45 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:39:18 PM PDT 24
Peak memory 200632 kb
Host smart-5db18090-1db5-4755-8d36-9950d95b8c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833372640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3833372640
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2478126507
Short name T355
Test name
Test status
Simulation time 631247174 ps
CPU time 17.22 seconds
Started Jul 18 05:37:12 PM PDT 24
Finished Jul 18 05:37:33 PM PDT 24
Peak memory 200136 kb
Host smart-9e6bbe79-d702-47e2-8e53-5d7a2b3a509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478126507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2478126507
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2913240392
Short name T303
Test name
Test status
Simulation time 5350177587 ps
CPU time 25.75 seconds
Started Jul 18 05:37:15 PM PDT 24
Finished Jul 18 05:37:45 PM PDT 24
Peak memory 200244 kb
Host smart-577a18dd-12cc-4c26-8ad4-2482cc9373e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913240392 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2913240392
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.17887784
Short name T188
Test name
Test status
Simulation time 48939216308 ps
CPU time 135.71 seconds
Started Jul 18 05:37:27 PM PDT 24
Finished Jul 18 05:39:47 PM PDT 24
Peak memory 200252 kb
Host smart-f6f0d3c4-91dd-4cf5-b927-26fa4845f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17887784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.17887784
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3542753933
Short name T39
Test name
Test status
Simulation time 25243839 ps
CPU time 0.61 seconds
Started Jul 18 05:36:22 PM PDT 24
Finished Jul 18 05:36:29 PM PDT 24
Peak memory 196132 kb
Host smart-ad43b7e4-5c23-4edb-9ef1-c5c8c1e5c9a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542753933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3542753933
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3706838747
Short name T4
Test name
Test status
Simulation time 2631614929 ps
CPU time 75.57 seconds
Started Jul 18 05:36:37 PM PDT 24
Finished Jul 18 05:37:54 PM PDT 24
Peak memory 200556 kb
Host smart-852f4522-689d-49d5-af3e-c25c4fe7e204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706838747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3706838747
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2318499011
Short name T474
Test name
Test status
Simulation time 24875131538 ps
CPU time 19.97 seconds
Started Jul 18 05:36:17 PM PDT 24
Finished Jul 18 05:36:45 PM PDT 24
Peak memory 200296 kb
Host smart-afac43fe-1ddc-42f9-96ad-037e110348d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318499011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2318499011
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4128588880
Short name T485
Test name
Test status
Simulation time 857890793 ps
CPU time 126.52 seconds
Started Jul 18 05:36:25 PM PDT 24
Finished Jul 18 05:38:36 PM PDT 24
Peak memory 449636 kb
Host smart-dc50fd7d-c41e-4b2d-baac-e2364614f532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128588880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4128588880
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3729848369
Short name T192
Test name
Test status
Simulation time 90615056653 ps
CPU time 302.35 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:41:56 PM PDT 24
Peak memory 200232 kb
Host smart-6f01a714-c3d7-455e-8137-5c201e920181
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729848369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3729848369
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2480305798
Short name T53
Test name
Test status
Simulation time 427740993 ps
CPU time 22.28 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:37:12 PM PDT 24
Peak memory 200228 kb
Host smart-c0889c6a-c053-4fb4-b016-586f37177157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480305798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2480305798
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.508150378
Short name T329
Test name
Test status
Simulation time 754436655 ps
CPU time 5.24 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:36:46 PM PDT 24
Peak memory 200276 kb
Host smart-7075ff99-bbad-49d4-b81d-d8085d83463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508150378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.508150378
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1279892390
Short name T413
Test name
Test status
Simulation time 73944114022 ps
CPU time 1615.64 seconds
Started Jul 18 05:36:32 PM PDT 24
Finished Jul 18 06:03:30 PM PDT 24
Peak memory 774848 kb
Host smart-264dfe38-4428-4c6b-8060-0bb418157845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279892390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1279892390
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.813016386
Short name T330
Test name
Test status
Simulation time 3802487923 ps
CPU time 25.28 seconds
Started Jul 18 05:36:25 PM PDT 24
Finished Jul 18 05:36:55 PM PDT 24
Peak memory 200312 kb
Host smart-67c284c6-95d8-4c3c-8f1d-9982e130863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813016386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.813016386
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.375099050
Short name T429
Test name
Test status
Simulation time 44993619 ps
CPU time 0.6 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:36:37 PM PDT 24
Peak memory 195108 kb
Host smart-597b01c8-2f6a-4c0d-8868-a2aaf79b70dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375099050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.375099050
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.801466790
Short name T394
Test name
Test status
Simulation time 3363811935 ps
CPU time 104.82 seconds
Started Jul 18 05:36:33 PM PDT 24
Finished Jul 18 05:38:20 PM PDT 24
Peak memory 200264 kb
Host smart-1408681d-b627-4610-a83c-90c1b10144d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801466790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.801466790
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2720895396
Short name T371
Test name
Test status
Simulation time 628842752 ps
CPU time 35.06 seconds
Started Jul 18 05:36:23 PM PDT 24
Finished Jul 18 05:37:04 PM PDT 24
Peak memory 200220 kb
Host smart-e16e423f-4ad0-4e05-8927-593842d5a80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720895396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2720895396
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.461658591
Short name T266
Test name
Test status
Simulation time 35697915582 ps
CPU time 288.67 seconds
Started Jul 18 05:36:31 PM PDT 24
Finished Jul 18 05:41:26 PM PDT 24
Peak memory 497416 kb
Host smart-d60b317e-729d-483d-99e6-d7463c137954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461658591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.461658591
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1902934980
Short name T427
Test name
Test status
Simulation time 123537901 ps
CPU time 1.14 seconds
Started Jul 18 05:36:31 PM PDT 24
Finished Jul 18 05:36:33 PM PDT 24
Peak memory 200292 kb
Host smart-84450f80-6ac9-4459-b9ff-28e0a8bd876e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902934980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1902934980
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2463179560
Short name T179
Test name
Test status
Simulation time 4637384325 ps
CPU time 13.94 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:37:01 PM PDT 24
Peak memory 200500 kb
Host smart-2627a75a-7cc9-4360-a21c-0562f8f9cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463179560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2463179560
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1312697982
Short name T406
Test name
Test status
Simulation time 1446491554 ps
CPU time 13.24 seconds
Started Jul 18 05:36:21 PM PDT 24
Finished Jul 18 05:36:41 PM PDT 24
Peak memory 200184 kb
Host smart-7d03425f-92b6-496d-95f0-c9ae380a607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312697982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1312697982
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1677871186
Short name T492
Test name
Test status
Simulation time 180477225286 ps
CPU time 4168.46 seconds
Started Jul 18 05:36:20 PM PDT 24
Finished Jul 18 06:45:56 PM PDT 24
Peak memory 851544 kb
Host smart-9336ccf7-6f47-4db2-b11f-0751f8494124
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677871186 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1677871186
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.321618758
Short name T63
Test name
Test status
Simulation time 21416327469 ps
CPU time 729.82 seconds
Started Jul 18 05:36:30 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 700388 kb
Host smart-b5d79f00-d383-4c72-ae4a-e91ce3babfcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321618758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.321618758
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3352794141
Short name T111
Test name
Test status
Simulation time 1966392058 ps
CPU time 103.43 seconds
Started Jul 18 05:36:23 PM PDT 24
Finished Jul 18 05:38:12 PM PDT 24
Peak memory 200240 kb
Host smart-760c9cd3-a258-498d-abc5-6df057f8ba5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352794141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3352794141
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3978880764
Short name T342
Test name
Test status
Simulation time 11032833 ps
CPU time 0.58 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:36:55 PM PDT 24
Peak memory 195288 kb
Host smart-16d1051b-f416-4efa-988f-3b59cd8e04a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978880764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3978880764
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1013528033
Short name T425
Test name
Test status
Simulation time 3959380942 ps
CPU time 58.67 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:37:41 PM PDT 24
Peak memory 200296 kb
Host smart-e3a96055-d70a-42ef-b955-b1e832076189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013528033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1013528033
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2378926365
Short name T306
Test name
Test status
Simulation time 882893535 ps
CPU time 12.03 seconds
Started Jul 18 05:36:41 PM PDT 24
Finished Jul 18 05:36:57 PM PDT 24
Peak memory 200180 kb
Host smart-cb9a7e27-5306-4606-b3b2-005e29077c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378926365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2378926365
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2559475170
Short name T441
Test name
Test status
Simulation time 20041376091 ps
CPU time 836.62 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 05:50:38 PM PDT 24
Peak memory 689440 kb
Host smart-f15d01e8-b78d-48dc-9823-7b192a058275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559475170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2559475170
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.138681742
Short name T356
Test name
Test status
Simulation time 3945147030 ps
CPU time 24.71 seconds
Started Jul 18 05:36:30 PM PDT 24
Finished Jul 18 05:36:56 PM PDT 24
Peak memory 200216 kb
Host smart-6b9c93ec-54f9-4bc6-8845-a316bea02db6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138681742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.138681742
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2066784825
Short name T35
Test name
Test status
Simulation time 4568224776 ps
CPU time 78.86 seconds
Started Jul 18 05:36:49 PM PDT 24
Finished Jul 18 05:38:16 PM PDT 24
Peak memory 200328 kb
Host smart-378713fc-3942-45a6-91b5-21b7ea8eb9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066784825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2066784825
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2732548296
Short name T509
Test name
Test status
Simulation time 1078377239 ps
CPU time 12.74 seconds
Started Jul 18 05:36:21 PM PDT 24
Finished Jul 18 05:36:40 PM PDT 24
Peak memory 200240 kb
Host smart-081f3b78-0e7d-4a1c-b910-6acb65d32c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732548296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2732548296
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2266924553
Short name T141
Test name
Test status
Simulation time 40291188876 ps
CPU time 2016.51 seconds
Started Jul 18 05:36:40 PM PDT 24
Finished Jul 18 06:10:20 PM PDT 24
Peak memory 774472 kb
Host smart-480c1cd8-0f60-45ff-89b3-749064b787b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266924553 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2266924553
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2939022092
Short name T13
Test name
Test status
Simulation time 213238443239 ps
CPU time 353.96 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:42:40 PM PDT 24
Peak memory 209524 kb
Host smart-2626be5c-c205-4bf3-bce6-41a804389b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939022092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2939022092
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1429522213
Short name T206
Test name
Test status
Simulation time 2653125171 ps
CPU time 37.1 seconds
Started Jul 18 05:36:34 PM PDT 24
Finished Jul 18 05:37:13 PM PDT 24
Peak memory 200220 kb
Host smart-91240c5f-4f24-4aac-a9eb-72834944d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429522213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1429522213
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3531851736
Short name T424
Test name
Test status
Simulation time 24954006 ps
CPU time 0.6 seconds
Started Jul 18 05:36:33 PM PDT 24
Finished Jul 18 05:36:36 PM PDT 24
Peak memory 195044 kb
Host smart-12279f65-3607-4f22-bc92-01a94ff05526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531851736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3531851736
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.364019582
Short name T284
Test name
Test status
Simulation time 822992991 ps
CPU time 45.21 seconds
Started Jul 18 05:36:47 PM PDT 24
Finished Jul 18 05:37:40 PM PDT 24
Peak memory 200176 kb
Host smart-c351ef6e-b9fe-4061-8949-07757a5274a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364019582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.364019582
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4117592006
Short name T510
Test name
Test status
Simulation time 1237841140 ps
CPU time 6.07 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:36:53 PM PDT 24
Peak memory 200124 kb
Host smart-67c36a97-39ae-4ee4-af54-7fcd20304194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117592006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4117592006
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1839847596
Short name T503
Test name
Test status
Simulation time 8092926070 ps
CPU time 339.32 seconds
Started Jul 18 05:36:25 PM PDT 24
Finished Jul 18 05:42:09 PM PDT 24
Peak memory 479116 kb
Host smart-4620c164-fc85-4085-adc2-fd3eaa25598c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839847596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1839847596
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2560524738
Short name T37
Test name
Test status
Simulation time 25701258273 ps
CPU time 111.13 seconds
Started Jul 18 05:36:41 PM PDT 24
Finished Jul 18 05:38:36 PM PDT 24
Peak memory 200220 kb
Host smart-6d7c3a76-79e2-418c-be8e-fc2b5292555d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560524738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2560524738
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.683886832
Short name T58
Test name
Test status
Simulation time 2222703402 ps
CPU time 29.64 seconds
Started Jul 18 05:36:25 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 200240 kb
Host smart-25437e4b-4790-43b2-8739-f6943d5b1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683886832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.683886832
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4166308086
Short name T433
Test name
Test status
Simulation time 992777201 ps
CPU time 8.55 seconds
Started Jul 18 05:36:25 PM PDT 24
Finished Jul 18 05:36:38 PM PDT 24
Peak memory 200292 kb
Host smart-92965c17-0f33-4d4a-8984-55cd728582e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166308086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4166308086
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2727968080
Short name T8
Test name
Test status
Simulation time 361006634363 ps
CPU time 2140.04 seconds
Started Jul 18 05:36:39 PM PDT 24
Finished Jul 18 06:12:21 PM PDT 24
Peak memory 772256 kb
Host smart-003c85b1-ec43-44bb-8103-dd8cac5614fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727968080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2727968080
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2761125240
Short name T469
Test name
Test status
Simulation time 19079471339 ps
CPU time 128.74 seconds
Started Jul 18 05:36:37 PM PDT 24
Finished Jul 18 05:38:48 PM PDT 24
Peak memory 200220 kb
Host smart-15e1424b-0662-40af-925f-93cc5bd06bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761125240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2761125240
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.703686409
Short name T245
Test name
Test status
Simulation time 14999381 ps
CPU time 0.61 seconds
Started Jul 18 05:36:50 PM PDT 24
Finished Jul 18 05:36:59 PM PDT 24
Peak memory 196244 kb
Host smart-91c23a74-8bae-4279-918c-8af7c25996e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703686409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.703686409
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.196174423
Short name T240
Test name
Test status
Simulation time 5158898610 ps
CPU time 76.83 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:38:06 PM PDT 24
Peak memory 200220 kb
Host smart-d314266a-aff5-4fd1-979a-4e5f73c4b9bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196174423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.196174423
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2132724339
Short name T418
Test name
Test status
Simulation time 9037969625 ps
CPU time 62.25 seconds
Started Jul 18 05:36:38 PM PDT 24
Finished Jul 18 05:37:43 PM PDT 24
Peak memory 200224 kb
Host smart-96c9df8e-5a50-4e59-bda8-0244ee98b03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132724339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2132724339
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3472163413
Short name T521
Test name
Test status
Simulation time 1714621500 ps
CPU time 244.32 seconds
Started Jul 18 05:36:46 PM PDT 24
Finished Jul 18 05:40:58 PM PDT 24
Peak memory 602028 kb
Host smart-15af15cb-f099-416f-854f-e368c14120f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472163413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3472163413
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.173661419
Short name T25
Test name
Test status
Simulation time 3077324060 ps
CPU time 164.19 seconds
Started Jul 18 05:36:32 PM PDT 24
Finished Jul 18 05:39:18 PM PDT 24
Peak memory 200196 kb
Host smart-776bacd8-f9fa-4600-93a8-f23af8dc7d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173661419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.173661419
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3269577084
Short name T226
Test name
Test status
Simulation time 10953540428 ps
CPU time 47.39 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:37:34 PM PDT 24
Peak memory 200192 kb
Host smart-f6294650-a05d-4c43-917e-c03b413ba9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269577084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3269577084
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1178989826
Short name T495
Test name
Test status
Simulation time 745016557 ps
CPU time 8.41 seconds
Started Jul 18 05:36:43 PM PDT 24
Finished Jul 18 05:36:55 PM PDT 24
Peak memory 200176 kb
Host smart-f0d3c1c4-a649-4d72-9286-2ee7dd2a9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178989826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1178989826
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2681219524
Short name T84
Test name
Test status
Simulation time 267989677711 ps
CPU time 1143.32 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:55:52 PM PDT 24
Peak memory 216104 kb
Host smart-1222c013-ae37-4040-b205-81ff2309d739
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681219524 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2681219524
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.814657300
Short name T65
Test name
Test status
Simulation time 268961483126 ps
CPU time 736.57 seconds
Started Jul 18 05:36:44 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 210228 kb
Host smart-e97461cf-d00d-42d1-9392-4ff32fc45f01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814657300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.814657300
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1037413562
Short name T523
Test name
Test status
Simulation time 2683840156 ps
CPU time 47.26 seconds
Started Jul 18 05:36:48 PM PDT 24
Finished Jul 18 05:37:44 PM PDT 24
Peak memory 200308 kb
Host smart-7d89c5cd-586e-4bb1-b96f-655edcc96bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037413562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1037413562
Directory /workspace/9.hmac_wipe_secret/latest
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