Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19116554	1			T1	10552		T2	530180		T3	1527
all_values[1]	19116554	1			T1	10552		T2	530180		T3	1527
all_values[2]	19116554	1			T1	10552		T2	530180		T3	1527

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

220820

1

T2

300

T5

3080

T16

43

auto[1]

57128842

1

T1

31656

T2

159024

T3

4581

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48764019

1

T1

31431

T2

133958

T3

4091

auto[1]

8585643

1

T1

225

T2

250959

T3

490

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96082	1			T2	13		T5	3080		T16	43
all_values[0]	auto[0]	auto[1]	333	1			T2	3		T22	1		T26	2
all_values[0]	auto[1]	auto[0]	18999037	1			T1	10327		T2	529659		T3	1499
all_values[0]	auto[1]	auto[1]	21102	1			T1	225		T2	505		T3	28
all_values[1]	auto[0]	auto[0]	59682	1			T2	10		T21	73		T22	1
all_values[1]	auto[0]	auto[1]	200	1			T2	5		T42	1		T45	2
all_values[1]	auto[1]	auto[0]	19056337	1			T1	10552		T2	530156		T3	1527
all_values[1]	auto[1]	auto[1]	335	1			T2	9		T22	1		T24	1
all_values[2]	auto[0]	auto[0]	33613	1			T2	258		T23	1063		T22	2
all_values[2]	auto[0]	auto[1]	30910	1			T2	11		T41	2		T42	522
all_values[2]	auto[1]	auto[0]	10519268	1			T1	10552		T2	279485		T3	1065
all_values[2]	auto[1]	auto[1]	8532763	1			T2	250426		T3	462		T4	3126