Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138393

1

T2

4146

T3

52

T4

20

auto[1]

152688

1

T1

226

T2

7804

T3

14

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	114460	1			T2	5300		T4	13		T8	27
len_1026_2046	7605	1			T2	130		T3	3		T8	1
len_514_1022	3280	1			T2	59		T16	2		T17	1
len_2_510	4472	1			T2	73		T3	5		T8	57
len_2056	228	1			T2	14		T3	1		T22	3
len_2048	406	1			T2	17		T3	2		T17	5
len_2040	178	1			T2	10		T16	1		T17	2
len_1032	220	1			T2	11		T3	4		T16	3
len_1024	1850	1			T1	113		T2	14		T3	1
len_1016	350	1			T2	8		T3	3		T16	6
len_520	228	1			T2	29		T3	2		T16	1
len_512	441	1			T2	23		T3	7		T8	2
len_504	273	1			T2	10		T17	2		T22	5
len_8	1015	1			T2	33		T8	1		T5	2
len_0	10532	1			T2	244		T3	5		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

123

1

T2

5

T130

1

T131

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	55719	1			T2	1824		T4	8		T8	27
auto[0]	len_1026_2046	2740	1			T2	42		T3	2		T8	1
auto[0]	len_514_1022	1684	1			T2	26		T16	1		T132	1
auto[0]	len_2_510	3041	1			T2	27		T3	4		T8	57
auto[0]	len_2056	120	1			T2	6		T3	1		T22	1
auto[0]	len_2048	190	1			T2	3		T3	2		T17	3
auto[0]	len_2040	104	1			T2	4		T16	1		T22	1
auto[0]	len_1032	110	1			T2	7		T3	4		T16	1
auto[0]	len_1024	308	1			T2	6		T3	1		T4	1
auto[0]	len_1016	140	1			T2	5		T3	2		T16	4
auto[0]	len_520	132	1			T2	8		T3	2		T16	1
auto[0]	len_512	258	1			T2	11		T3	4		T8	2
auto[0]	len_504	127	1			T2	5		T22	5		T6	2
auto[0]	len_8	23	1			T8	1		T6	1		T133	1
auto[0]	len_0	4498	1			T2	99		T3	4		T4	1
auto[1]	len_2050_plus	58741	1			T2	3476		T4	5		T5	13
auto[1]	len_1026_2046	4865	1			T2	88		T3	1		T16	4
auto[1]	len_514_1022	1596	1			T2	33		T16	1		T17	1
auto[1]	len_2_510	1431	1			T2	46		T3	1		T82	2
auto[1]	len_2056	108	1			T2	8		T22	2		T42	3
auto[1]	len_2048	216	1			T2	14		T17	2		T134	1
auto[1]	len_2040	74	1			T2	6		T17	2		T22	3
auto[1]	len_1032	110	1			T2	4		T16	2		T22	2
auto[1]	len_1024	1542	1			T1	113		T2	8		T17	1
auto[1]	len_1016	210	1			T2	3		T3	1		T16	2
auto[1]	len_520	96	1			T2	21		T22	3		T42	4
auto[1]	len_512	183	1			T2	12		T3	3		T5	1
auto[1]	len_504	146	1			T2	5		T17	2		T6	5
auto[1]	len_8	992	1			T2	33		T5	2		T134	5
auto[1]	len_0	6034	1			T2	145		T3	1		T5	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

70

1

T2

4

T131

2

T135

1

auto[1]

len_upper

53

1

T2

1

T130

1

T136

2