Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4791246

1

T1

5257

T2

117936

T3

267

auto[1]

3041098

1

T2

120242

T3

444

T4

11

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2970210

1

T2

111148

T3

424

T4

7

auto[1]

4862134

1

T1

5257

T2

127030

T3

287

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3576427

1

T2

65952

T3

547

T4

10

auto[1]

4255917

1

T1

5257

T2

172226

T3

164

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4784955

1

T1

5257

T2

128617

T3

370

auto[1]

3047389

1

T2

109561

T3

341

T4

8

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7058744	1			T1	4861		T2	202064		T3	704
fifo_depth[1]	127044	1			T1	162		T2	4052		T3	3
fifo_depth[2]	98225	1			T1	123		T2	3902		T3	2
fifo_depth[3]	77695	1			T1	66		T2	3450		T3	2
fifo_depth[4]	69492	1			T1	28		T2	3252		T4	1
fifo_depth[5]	53714	1			T1	15		T2	2651		T5	503
fifo_depth[6]	42801	1			T1	1		T2	2184		T4	1
fifo_depth[7]	28312	1			T1	1		T2	1435		T5	210

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

773600

1

T1

396

T2

36114

T3

7

auto[1]

7058744

1

T1

4861

T2

202064

T3

704

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7819748

1

T1

5257

T2

237486

T3

711

auto[1]

12596

1

T2

692

T24

2

T25

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

34549

1

T2

1085

T16

1

T23

245

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34842

1

T2

775

T4

1

T22

23

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

40582

1

T2

2119

T17

3

T23

86

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

37037

1

T2

1122

T17

12

T21

81

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

161038

1

T2

2680

T8

849

T17

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

34588

1

T2

869

T16

1

T23

81

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43131

1

T2

1160

T4

2

T22

77

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32607

1

T2

2308

T4

2

T83

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42410

1

T2

4440

T4

1

T5

605

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43471

1

T2

2069

T4

1

T16

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

34876

1

T2

4139

T3

2

T5

729

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46099

1

T2

3865

T16

2

T22

13

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58521

1

T1

396

T2

3111

T5

1153

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35956

1

T2

3072

T3

5

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41164

1

T2

1658

T17

16

T23

326

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

52729

1

T2

1642

T5

745

T16

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

202071

1

T2

4764

T3

28

T16

37

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

201558

1

T2

3983

T3

34

T16

74

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

207655

1

T2

6885

T3

171

T16

27

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

204154

1

T2

11490

T3

86

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1736988

1

T2

4188

T3

67

T8

36823

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

185920

1

T2

3351

T3

24

T16

49

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

210323

1

T2

8301

T3

81

T4

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

209384

1

T2

10872

T3

56

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

487295

1

T2

29045

T3

1

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

464969

1

T2

12585

T3

82

T5

2146

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

401247

1

T2

8287

T3

19

T4

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

487395

1

T2

14495

T3

1

T4

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

577048

1

T1

4861

T2

26776

T5

6125

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

490022

1

T2

15143

T3

26

T5

5757

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

506057

1

T2

19979

T3

1

T5

1400

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

486658

1

T2

21920

T3

27

T5

2523

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

236193

1

T2

5849

T3

28

T16

38

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

235371

1

T2

4758

T3

34

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

247912

1

T2

8999

T3

171

T16

27

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

240835

1

T2

12612

T3

86

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1896901

1

T2

6789

T3

67

T8

37672

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

219539

1

T2

4220

T3

24

T16

50

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

251032

1

T2

9440

T3

81

T4

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

241026

1

T2

13166

T3

56

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

528767

1

T2

33103

T3

1

T4

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

508265

1

T2

14653

T3

82

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

435659

1

T2

12346

T3

21

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

532853

1

T2

18320

T3

1

T4

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

635238

1

T1

5257

T2

29887

T5

7278

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

525449

1

T2

18165

T3

31

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

546295

1

T2

21628

T3

1

T5

1400

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

538413

1

T2

23551

T3

27

T5

3268

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

427

1

T39

4

T7

13

T9

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1029

1

T19

13

T86

6

T7

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

325

1

T2

5

T39

3

T7

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

356

1

T45

13

T86

3

T39

34

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1125

1

T2

79

T45

18

T86

49

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

969

1

T45

10

T86

25

T7

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2422

1

T2

21

T25

3

T45

108

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

965

1

T2

14

T45

36

T6

35

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

938

1

T2

382

T9

135

T139

16

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

175

1

T2

1

T45

26

T86

73

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

464

1

T2

80

T45

2

T86

62

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

641

1

T2

40

T24

2

T45

84

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

331

1

T45

143

T86

27

T140

19

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

529

1

T2

50

T39

130

T76

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

926

1

T2

9

T39

21

T7

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

974

1

T2

11

T45

26

T19

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

202071

1

T2

4764

T3

28

T16

37

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

201558

1

T2

3983

T3

34

T16

74

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

207655

1

T2

6885

T3

171

T16

27

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

204154

1

T2

11490

T3

86

T4

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1736988

1

T2

4188

T3

67

T8

36823

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

185920

1

T2

3351

T3

24

T16

49

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

210323

1

T2

8301

T3

81

T4

3

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

209384

1

T2

10872

T3

56

T4

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

487295

1

T2

29045

T3

1

T4

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

464969

1

T2

12585

T3

82

T5

2146

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

401247

1

T2

8287

T3

19

T4

1

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

487395

1

T2

14495

T3

1

T4

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

577048

1

T1

4861

T2

26776

T5

6125

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

490022

1

T2

15143

T3

26

T5

5757

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

506057

1

T2

19979

T3

1

T5

1400

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

486658

1

T2

21920

T3

27

T5

2523

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4211

1

T2

238

T16

1

T23

48

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3746

1

T2

134

T22

11

T26

42

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

5056

1

T2

198

T17

1

T23

12

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4433

1

T2

317

T17

2

T21

17

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

43540

1

T2

156

T8

710

T17

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3870

1

T2

90

T16

1

T23

17

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4240

1

T2

72

T22

62

T26

17

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4403

1

T2

250

T4

1

T83

2

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6050

1

T2

646

T5

120

T17

2

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7278

1

T2

248

T16

3

T22

2

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5471

1

T2

217

T3

1

T5

105

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5730

1

T2

312

T16

2

T22

12

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9494

1

T1

162

T2

389

T5

206

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6348

1

T2

268

T3

2

T5

74

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6284

1

T2

270

T17

2

T23

61

fifo_depth[1]

auto[1]

auto[1]

auto[1]

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5

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14

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14

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45

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T2

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T2

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107

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T2

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T1

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193

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T2

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57

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T2

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18

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3

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T2

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T2

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T2

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113

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53

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T2

260

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6

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1

T1

28

T2

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1

T2

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59

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T2

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4

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17

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T2

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T2

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27

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T2

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T2

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T2

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9

T141

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T2

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T2

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T2

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37

fifo_depth[5]

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T2

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T2

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fifo_depth[5]

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T2

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21

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25

fifo_depth[6]

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T2

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fifo_depth[6]

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1

T2

99

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7

T141

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fifo_depth[6]

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1

T2

58

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4

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T2

49

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6

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2

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1

T2

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2

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1

T2

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48

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1

T2

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53

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1

fifo_depth[6]

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T2

148

T5

71

T134

26

fifo_depth[6]

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1

T2

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T24

8

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fifo_depth[6]

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1

T1

1

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358

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118

fifo_depth[6]

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1

T2

164

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33

T23

13

fifo_depth[6]

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1

T2

136

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1

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33

fifo_depth[6]

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1

T2

94

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85

T21

15

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1

T2

54

T23

10

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45

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1

T2

31

T26

11

T45

7

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1

T2

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1

T23

9

fifo_depth[7]

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1

T2

40

T21

3

T26

5

fifo_depth[7]

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1

T2

72

T17

2

T21

8

fifo_depth[7]

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T2

40

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4

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17

fifo_depth[7]

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1

T2

47

T26

5

T45

59

fifo_depth[7]

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1

T2

67

T45

18

T114

2

fifo_depth[7]

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1

T2

211

T5

25

T17

1

fifo_depth[7]

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1

T2

119

T134

36

T43

9

fifo_depth[7]

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1

T2

50

T5

51

T134

18

fifo_depth[7]

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1

T2

159

T42

2

T45

67

fifo_depth[7]

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1

T1

1

T2

184

T5

67

fifo_depth[7]

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1

T2

121

T5

11

T23

7

fifo_depth[7]

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1

T2

90

T17

2

T23

18

fifo_depth[7]

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1971

1

T2

62

T5

56

T21

11