Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19116554	1			T1	10552		T2	530180		T3	1527
all_pins[1]	19116554	1			T1	10552		T2	530180		T3	1527
all_pins[2]	19116554	1			T1	10552		T2	530180		T3	1527

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48794574	1			T1	31431		T2	133957		T3	4089
values[0x1]	8555088	1			T1	225		T2	250968		T3	492
transitions[0x0=>0x1]	8554902	1			T1	225		T2	250964		T3	492
transitions[0x1=>0x0]	8554919	1			T1	225		T2	250964		T3	492

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19094589	1			T1	10327		T2	529647		T3	1497
all_pins[0]	values[0x1]	21965	1			T1	225		T2	533		T3	30
all_pins[0]	transitions[0x0=>0x1]	21868	1			T1	225		T2	529		T3	30
all_pins[0]	transitions[0x1=>0x0]	8532683	1			T2	250422		T3	462		T4	3126
all_pins[1]	values[0x0]	19116194	1			T1	10552		T2	530171		T3	1527
all_pins[1]	values[0x1]	360	1			T2	9		T22	1		T24	1
all_pins[1]	transitions[0x0=>0x1]	314	1			T2	9		T22	1		T24	1
all_pins[1]	transitions[0x1=>0x0]	21919	1			T1	225		T2	533		T3	30
all_pins[2]	values[0x0]	10583791	1			T1	10552		T2	279754		T3	1065
all_pins[2]	values[0x1]	8532763	1			T2	250426		T3	462		T4	3126
all_pins[2]	transitions[0x0=>0x1]	8532720	1			T2	250426		T3	462		T4	3126
all_pins[2]	transitions[0x1=>0x0]	317	1			T2	9		T22	1		T24	1