Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1001 1 T2 25 T22 7 T42 4
all_values[1] 1001 1 T2 25 T22 7 T42 4
all_values[2] 1001 1 T2 25 T22 7 T42 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1477 1 T2 43 T22 4 T42 9
auto[1] 1526 1 T2 32 T22 17 T42 3


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1096 1 T2 27 T22 13 T42 6
auto[1] 1907 1 T2 48 T22 8 T42 6


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1712 1 T2 48 T22 15 T42 8
auto[1] 1291 1 T2 27 T22 6 T42 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 204 1 T2 9 T22 1 T42 1
all_values[0] auto[0] auto[0] auto[1] 89 1 T2 2 T42 1 T45 1
all_values[0] auto[0] auto[1] auto[0] 181 1 T2 3 T22 2 T42 1
all_values[0] auto[0] auto[1] auto[1] 100 1 T2 3 T22 1 T45 1
all_values[0] auto[1] auto[0] auto[1] 197 1 T2 4 T22 1 T42 1
all_values[0] auto[1] auto[1] auto[1] 230 1 T2 4 T22 2 T45 2
all_values[1] auto[0] auto[0] auto[0] 163 1 T2 5 T42 2 T45 1
all_values[1] auto[0] auto[0] auto[1] 132 1 T2 2 T42 1 T45 2
all_values[1] auto[0] auto[1] auto[0] 171 1 T2 7 T22 5 T45 3
all_values[1] auto[0] auto[1] auto[1] 121 1 T2 3 T22 1 T6 2
all_values[1] auto[1] auto[0] auto[1] 201 1 T2 6 T45 2 T6 2
all_values[1] auto[1] auto[1] auto[1] 213 1 T2 2 T22 1 T42 1
all_values[2] auto[0] auto[0] auto[0] 189 1 T2 2 T22 2 T42 2
all_values[2] auto[0] auto[0] auto[1] 78 1 T2 7 T6 1 T86 3
all_values[2] auto[0] auto[1] auto[0] 188 1 T2 1 T22 3 T45 2
all_values[2] auto[0] auto[1] auto[1] 96 1 T2 4 T45 1 T6 3
all_values[2] auto[1] auto[0] auto[1] 224 1 T2 6 T42 1 T6 8
all_values[2] auto[1] auto[1] auto[1] 226 1 T2 5 T22 2 T42 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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