Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4626	1			T2	180		T3	6		T4	2
sha2_none	4634	1			T2	207		T3	9		T4	2
sha2_512	8103	1			T1	225		T2	180		T3	9
sha2_384	7850	1			T2	195		T3	11		T4	6
sha2_256	6802	1			T2	216		T3	4		T4	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19838

1

T1

225

T2

476

T3

14

auto[1]

12582

1

T2

516

T3

25

T4

12

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12337

1

T2

472

T3

22

T4

7

auto[1]

20083

1

T1

225

T2

520

T3

17

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16529

1

T1

225

T2

558

T3

11

disabled

15891

1

T2

434

T3

28

T4

11

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5123	1			T2	206		T3	5		T4	4
key_none	8136	1			T2	144		T3	4		T4	1
key_1024	4665	1			T1	225		T2	123		T3	6
key_512	4101	1			T2	118		T3	8		T4	6
key_384	3729	1			T2	135		T3	2		T4	2
key_256	3388	1			T2	142		T3	9		T4	1
key_128	3194	1			T2	120		T3	5		T4	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20115

1

T1

225

T2

513

T3

22

auto[1]

12305

1

T2

479

T3

17

T4

8

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32173

1

T1

225

T2

985

T3

39

disabled

247

1

T2

7

T22

4

T42

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1714

1

T2

73

T3

1

T4

2

enabled

auto[0]

auto[0]

auto[1]

1695

1

T2

53

T3

2

T4

1

enabled

auto[0]

auto[1]

auto[0]

1693

1

T2

65

T3

2

T4

1

enabled

auto[0]

auto[1]

auto[1]

1699

1

T2

62

T3

1

T4

1

enabled

auto[1]

auto[0]

auto[0]

4457

1

T1

225

T2

72

T5

4

enabled

auto[1]

auto[0]

auto[1]

1676

1

T2

73

T3

2

T4

1

enabled

auto[1]

auto[1]

auto[0]

1856

1

T2

85

T3

1

T5

3

enabled

auto[1]

auto[1]

auto[1]

1739

1

T2

75

T3

2

T5

2

disabled

auto[0]

auto[0]

auto[0]

1381

1

T2

56

T3

2

T16

1

disabled

auto[0]

auto[0]

auto[1]

1342

1

T2

52

T3

2

T4

1

disabled

auto[0]

auto[1]

auto[0]

1417

1

T2

59

T3

8

T16

1

disabled

auto[0]

auto[1]

auto[1]

1396

1

T2

52

T3

4

T4

1

disabled

auto[1]

auto[0]

auto[0]

6215

1

T2

46

T3

3

T8

194

disabled

auto[1]

auto[0]

auto[1]

1358

1

T2

51

T3

2

T16

2

disabled

auto[1]

auto[1]

auto[0]

1382

1

T2

57

T3

5

T4

6

disabled

auto[1]

auto[1]

auto[1]

1400

1

T2

61

T3

2

T4

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16431

1

T1

225

T2

555

T3

11

enabled

disabled

98

1

T2

3

T22

1

T42

1

disabled

disabled

149

1

T2

4

T22

3

T6

5

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15742

1

T2

430

T3

28

T4

11

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1271	1			T2	51		T3	2		T4	1
key_invalid	sha2_none	965	1			T2	37		T3	1		T16	1
key_invalid	sha2_512	896	1			T2	24		T5	1		T23	1
key_invalid	sha2_384	941	1			T2	40		T3	1		T4	2
key_invalid	sha2_256	948	1			T2	49		T3	1		T5	1
key_none	sha2_invalid	555	1			T2	21		T3	1		T4	1
key_none	sha2_none	624	1			T2	30		T5	1		T21	1
key_none	sha2_512	2611	1			T2	27		T16	1		T23	1
key_none	sha2_384	2631	1			T2	35		T3	1		T5	1
key_none	sha2_256	1665	1			T2	31		T3	2		T8	194
key_1024	sha2_invalid	579	1			T2	21		T16	1		T17	2
key_1024	sha2_none	623	1			T2	29		T3	2		T5	1
key_1024	sha2_512	1816	1			T1	225		T2	24		T3	3
key_1024	sha2_384	975	1			T2	25		T16	1		T22	7
key_512	sha2_invalid	586	1			T2	23		T3	2		T5	1
key_512	sha2_none	624	1			T2	23		T3	1		T4	1
key_512	sha2_512	691	1			T2	28		T3	3		T4	3
key_512	sha2_384	1260	1			T2	18		T3	2		T4	2
key_512	sha2_256	889	1			T2	26		T5	1		T22	2
key_384	sha2_invalid	571	1			T2	19		T5	1		T16	1
key_384	sha2_none	551	1			T2	31		T4	1		T17	1
key_384	sha2_512	723	1			T2	25		T3	1		T5	2
key_384	sha2_384	669	1			T2	23		T3	1		T17	1
key_384	sha2_256	1168	1			T2	33		T4	1		T16	1
key_256	sha2_invalid	529	1			T2	25		T16	3		T22	4
key_256	sha2_none	644	1			T2	28		T3	3		T16	1
key_256	sha2_512	676	1			T2	27		T3	2		T4	1
key_256	sha2_384	693	1			T2	30		T3	4		T5	1
key_256	sha2_256	795	1			T2	29		T5	1		T16	2
key_128	sha2_invalid	517	1			T2	18		T3	1		T5	1
key_128	sha2_none	585	1			T2	29		T3	2		T5	1
key_128	sha2_512	681	1			T2	25		T5	1		T16	1
key_128	sha2_384	664	1			T2	24		T3	2		T4	2
key_128	sha2_256	696	1			T2	24		T4	1		T5	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

622

1

T2

23

T3

1

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1271	1			T2	51		T3	2		T4	1
key_invalid	sha2_none	965	1			T2	37		T3	1		T16	1
key_invalid	sha2_512	896	1			T2	24		T5	1		T23	1
key_invalid	sha2_384	941	1			T2	40		T3	1		T4	2
key_invalid	sha2_256	948	1			T2	49		T3	1		T5	1
key_none	sha2_invalid	555	1			T2	21		T3	1		T4	1
key_none	sha2_none	624	1			T2	30		T5	1		T21	1
key_none	sha2_512	2611	1			T2	27		T16	1		T23	1
key_none	sha2_384	2631	1			T2	35		T3	1		T5	1
key_none	sha2_256	1665	1			T2	31		T3	2		T8	194
key_1024	sha2_invalid	579	1			T2	21		T16	1		T17	2
key_1024	sha2_none	623	1			T2	29		T3	2		T5	1
key_1024	sha2_512	1816	1			T1	225		T2	24		T3	3
key_1024	sha2_384	975	1			T2	25		T16	1		T22	7
key_1024	sha2_256	622	1			T2	23		T3	1		T5	1
key_512	sha2_invalid	586	1			T2	23		T3	2		T5	1
key_512	sha2_none	624	1			T2	23		T3	1		T4	1
key_512	sha2_512	691	1			T2	28		T3	3		T4	3
key_512	sha2_384	1260	1			T2	18		T3	2		T4	2
key_512	sha2_256	889	1			T2	26		T5	1		T22	2
key_384	sha2_invalid	571	1			T2	19		T5	1		T16	1
key_384	sha2_none	551	1			T2	31		T4	1		T17	1
key_384	sha2_512	723	1			T2	25		T3	1		T5	2
key_384	sha2_384	669	1			T2	23		T3	1		T17	1
key_384	sha2_256	1168	1			T2	33		T4	1		T16	1
key_256	sha2_invalid	529	1			T2	25		T16	3		T22	4
key_256	sha2_none	644	1			T2	28		T3	3		T16	1
key_256	sha2_512	676	1			T2	27		T3	2		T4	1
key_256	sha2_384	693	1			T2	30		T3	4		T5	1
key_256	sha2_256	795	1			T2	29		T5	1		T16	2
key_128	sha2_invalid	517	1			T2	18		T3	1		T5	1
key_128	sha2_none	585	1			T2	29		T3	2		T5	1
key_128	sha2_512	681	1			T2	25		T5	1		T16	1
key_128	sha2_384	664	1			T2	24		T3	2		T4	2
key_128	sha2_256	696	1			T2	24		T4	1		T5	2