Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 659
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T534 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3446969812 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 43184382 ps
T106 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1229923594 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:27 PM PDT 24 177772845 ps
T535 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3882728366 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 58653115 ps
T95 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4078944065 Jul 19 04:42:06 PM PDT 24 Jul 19 04:42:09 PM PDT 24 87980627 ps
T61 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.279259994 Jul 19 04:42:28 PM PDT 24 Jul 19 04:42:42 PM PDT 24 137914929 ps
T107 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3482394368 Jul 19 04:42:27 PM PDT 24 Jul 19 04:42:38 PM PDT 24 149159148 ps
T62 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3497930328 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:30 PM PDT 24 311929593 ps
T536 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.600767480 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:03 PM PDT 24 42503332 ps
T122 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3750868055 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:22 PM PDT 24 182958595 ps
T108 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.987875378 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:17 PM PDT 24 26379368 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.52184764 Jul 19 04:42:02 PM PDT 24 Jul 19 04:42:05 PM PDT 24 73086931 ps
T537 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2063401977 Jul 19 04:42:23 PM PDT 24 Jul 19 04:50:16 PM PDT 24 131163704897 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1969687720 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:03 PM PDT 24 89850604 ps
T538 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1457278952 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:25 PM PDT 24 19014336 ps
T119 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3923033774 Jul 19 04:42:02 PM PDT 24 Jul 19 04:42:06 PM PDT 24 86701131 ps
T123 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3333230011 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:22 PM PDT 24 615104967 ps
T539 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2060669096 Jul 19 04:42:03 PM PDT 24 Jul 19 04:42:06 PM PDT 24 72347227 ps
T540 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2063628759 Jul 19 04:42:25 PM PDT 24 Jul 19 04:42:35 PM PDT 24 53993145 ps
T541 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1572524199 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:19 PM PDT 24 42870101 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2908700968 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:30 PM PDT 24 558729700 ps
T542 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2673797795 Jul 19 04:42:09 PM PDT 24 Jul 19 04:42:16 PM PDT 24 190656364 ps
T543 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1255294729 Jul 19 04:42:28 PM PDT 24 Jul 19 04:42:38 PM PDT 24 12438061 ps
T544 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1820164264 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:20 PM PDT 24 142970072 ps
T545 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.846579645 Jul 19 04:42:28 PM PDT 24 Jul 19 04:42:38 PM PDT 24 25615003 ps
T546 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.359692881 Jul 19 04:42:26 PM PDT 24 Jul 19 04:42:38 PM PDT 24 254305953 ps
T547 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1278809007 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:20 PM PDT 24 121521510 ps
T128 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2571607259 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:18 PM PDT 24 160900243 ps
T111 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.467163899 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:18 PM PDT 24 39544726 ps
T548 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3454771185 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:22 PM PDT 24 429905326 ps
T549 /workspace/coverage/cover_reg_top/7.hmac_intr_test.612466556 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:18 PM PDT 24 11950452 ps
T550 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3573522227 Jul 19 04:42:27 PM PDT 24 Jul 19 04:42:37 PM PDT 24 13074625 ps
T551 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1170794879 Jul 19 04:42:03 PM PDT 24 Jul 19 04:42:05 PM PDT 24 13906083 ps
T552 /workspace/coverage/cover_reg_top/1.hmac_intr_test.299086632 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:03 PM PDT 24 15082645 ps
T112 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3429858031 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:20 PM PDT 24 65566455 ps
T120 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.562036961 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:21 PM PDT 24 1020389632 ps
T553 /workspace/coverage/cover_reg_top/45.hmac_intr_test.435023747 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:29 PM PDT 24 62843472 ps
T97 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4065896319 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:18 PM PDT 24 96850897 ps
T554 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.32977372 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:06 PM PDT 24 39048580 ps
T555 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1181639751 Jul 19 04:42:27 PM PDT 24 Jul 19 04:42:37 PM PDT 24 67611911 ps
T556 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2774018677 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:19 PM PDT 24 18019306 ps
T557 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2441103960 Jul 19 04:42:15 PM PDT 24 Jul 19 04:42:22 PM PDT 24 134911218 ps
T558 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.190266151 Jul 19 04:42:02 PM PDT 24 Jul 19 04:42:06 PM PDT 24 22043948 ps
T559 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3810279153 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:18 PM PDT 24 83674221 ps
T560 /workspace/coverage/cover_reg_top/22.hmac_intr_test.57174093 Jul 19 04:42:24 PM PDT 24 Jul 19 04:42:31 PM PDT 24 18606033 ps
T561 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3858755872 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:19 PM PDT 24 137760423 ps
T562 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1266173614 Jul 19 04:42:15 PM PDT 24 Jul 19 04:58:45 PM PDT 24 98159786106 ps
T98 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.445980266 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:19 PM PDT 24 13810801 ps
T563 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3913921934 Jul 19 04:42:18 PM PDT 24 Jul 19 04:42:26 PM PDT 24 270198201 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2777399867 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:03 PM PDT 24 16326319 ps
T565 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3071868155 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:29 PM PDT 24 1021569171 ps
T566 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3392860596 Jul 19 04:42:18 PM PDT 24 Jul 19 04:42:23 PM PDT 24 51552845 ps
T567 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1196818090 Jul 19 04:41:58 PM PDT 24 Jul 19 04:42:04 PM PDT 24 94655685 ps
T568 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.176030276 Jul 19 04:42:21 PM PDT 24 Jul 19 04:42:28 PM PDT 24 540971708 ps
T569 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3434630622 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:14 PM PDT 24 2902076604 ps
T99 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4162358175 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:19 PM PDT 24 77672304 ps
T124 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3701631886 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:03 PM PDT 24 310950712 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2162430285 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:05 PM PDT 24 35132096 ps
T570 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1820375159 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:18 PM PDT 24 83684553 ps
T571 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1606161229 Jul 19 04:42:03 PM PDT 24 Jul 19 04:42:05 PM PDT 24 77739605 ps
T572 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1688380329 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:33 PM PDT 24 359500770 ps
T573 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.17705738 Jul 19 04:42:15 PM PDT 24 Jul 19 04:42:22 PM PDT 24 257272005 ps
T574 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3611846881 Jul 19 04:42:29 PM PDT 24 Jul 19 04:42:40 PM PDT 24 119157499 ps
T575 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1924084175 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:29 PM PDT 24 13976110 ps
T576 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2838314497 Jul 19 04:42:02 PM PDT 24 Jul 19 04:42:07 PM PDT 24 48637109 ps
T577 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3308677089 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:19 PM PDT 24 190648044 ps
T578 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1939375940 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:11 PM PDT 24 822791942 ps
T129 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3764303720 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:31 PM PDT 24 1544493202 ps
T579 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1711756090 Jul 19 04:42:19 PM PDT 24 Jul 19 04:42:26 PM PDT 24 60418812 ps
T580 /workspace/coverage/cover_reg_top/19.hmac_intr_test.445908340 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 57391655 ps
T581 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1959816266 Jul 19 04:42:12 PM PDT 24 Jul 19 05:13:17 PM PDT 24 436392975489 ps
T101 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4037442252 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:04 PM PDT 24 32015309 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2239433984 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:07 PM PDT 24 420731742 ps
T582 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1948124932 Jul 19 04:42:21 PM PDT 24 Jul 19 04:42:27 PM PDT 24 49902406 ps
T121 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.561406846 Jul 19 04:42:15 PM PDT 24 Jul 19 04:42:21 PM PDT 24 53127583 ps
T583 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2068772761 Jul 19 04:42:18 PM PDT 24 Jul 19 04:42:24 PM PDT 24 22519749 ps
T103 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2508642097 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:26 PM PDT 24 23685845 ps
T584 /workspace/coverage/cover_reg_top/20.hmac_intr_test.589072736 Jul 19 04:42:28 PM PDT 24 Jul 19 04:42:39 PM PDT 24 14778117 ps
T585 /workspace/coverage/cover_reg_top/9.hmac_intr_test.26140978 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:18 PM PDT 24 37094615 ps
T586 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1241991880 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:19 PM PDT 24 45643417 ps
T587 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3583065484 Jul 19 04:41:58 PM PDT 24 Jul 19 04:42:03 PM PDT 24 89968897 ps
T588 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2242750798 Jul 19 04:42:25 PM PDT 24 Jul 19 04:42:34 PM PDT 24 294622123 ps
T104 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3951137688 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:03 PM PDT 24 16139272 ps
T589 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3183397734 Jul 19 04:42:26 PM PDT 24 Jul 19 04:42:35 PM PDT 24 185724003 ps
T590 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2261091237 Jul 19 04:42:03 PM PDT 24 Jul 19 04:42:07 PM PDT 24 143277287 ps
T591 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2962310942 Jul 19 04:42:18 PM PDT 24 Jul 19 04:42:25 PM PDT 24 399397211 ps
T125 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2914627056 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:19 PM PDT 24 82401949 ps
T592 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.411582547 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:03 PM PDT 24 39435118 ps
T593 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3606461817 Jul 19 04:42:34 PM PDT 24 Jul 19 04:42:46 PM PDT 24 15129927 ps
T594 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3243902304 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:04 PM PDT 24 24888352 ps
T127 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1794343460 Jul 19 04:42:21 PM PDT 24 Jul 19 04:42:29 PM PDT 24 157689485 ps
T595 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2813358456 Jul 19 04:42:30 PM PDT 24 Jul 19 04:42:41 PM PDT 24 17530485 ps
T596 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2225772515 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:27 PM PDT 24 13590926 ps
T597 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3642376291 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:03 PM PDT 24 30757604 ps
T598 /workspace/coverage/cover_reg_top/34.hmac_intr_test.772900788 Jul 19 04:42:26 PM PDT 24 Jul 19 04:42:36 PM PDT 24 11284797 ps
T118 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3179155852 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:21 PM PDT 24 588857207 ps
T599 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1014426486 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:20 PM PDT 24 166423024 ps
T600 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1059511891 Jul 19 04:41:52 PM PDT 24 Jul 19 04:41:59 PM PDT 24 118814732 ps
T601 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1983161931 Jul 19 04:41:55 PM PDT 24 Jul 19 04:41:59 PM PDT 24 25315001 ps
T602 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.673620717 Jul 19 04:42:15 PM PDT 24 Jul 19 04:42:22 PM PDT 24 25114038 ps
T603 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2880588598 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 48244769 ps
T604 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2388085396 Jul 19 04:42:11 PM PDT 24 Jul 19 04:42:15 PM PDT 24 72959662 ps
T605 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1393542010 Jul 19 04:41:54 PM PDT 24 Jul 19 04:42:00 PM PDT 24 287232309 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1788055038 Jul 19 04:42:02 PM PDT 24 Jul 19 04:42:10 PM PDT 24 354363943 ps
T606 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2925229072 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:18 PM PDT 24 23223717 ps
T607 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4036883796 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 175203009 ps
T608 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1402830819 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:17 PM PDT 24 58031637 ps
T609 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.195613489 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:19 PM PDT 24 80716950 ps
T610 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1887494312 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:19 PM PDT 24 14487300 ps
T611 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3075199650 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:19 PM PDT 24 15374271 ps
T612 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3052823784 Jul 19 04:42:19 PM PDT 24 Jul 19 04:42:25 PM PDT 24 22369035 ps
T613 /workspace/coverage/cover_reg_top/25.hmac_intr_test.482617239 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:29 PM PDT 24 15637521 ps
T614 /workspace/coverage/cover_reg_top/48.hmac_intr_test.55307866 Jul 19 04:42:28 PM PDT 24 Jul 19 04:42:39 PM PDT 24 16881587 ps
T615 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3515108249 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:21 PM PDT 24 571957553 ps
T616 /workspace/coverage/cover_reg_top/35.hmac_intr_test.409200331 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:28 PM PDT 24 14926450 ps
T617 /workspace/coverage/cover_reg_top/39.hmac_intr_test.550671001 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 13467481 ps
T618 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2158341306 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:04 PM PDT 24 22685945 ps
T619 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3392811462 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:30 PM PDT 24 26780470 ps
T620 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4131109880 Jul 19 04:42:22 PM PDT 24 Jul 19 04:42:28 PM PDT 24 14896895 ps
T621 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1291925210 Jul 19 04:42:17 PM PDT 24 Jul 19 04:42:23 PM PDT 24 61653842 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3384322030 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:17 PM PDT 24 36425203 ps
T623 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1531148243 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:26 PM PDT 24 12027460 ps
T624 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1588547533 Jul 19 04:42:29 PM PDT 24 Jul 19 04:42:40 PM PDT 24 34172395 ps
T625 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1076615671 Jul 19 04:42:10 PM PDT 24 Jul 19 04:42:15 PM PDT 24 167744242 ps
T626 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3563247133 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:27 PM PDT 24 33645525 ps
T627 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.640358177 Jul 19 04:42:25 PM PDT 24 Jul 19 04:42:36 PM PDT 24 73841987 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3660677354 Jul 19 04:41:53 PM PDT 24 Jul 19 04:42:05 PM PDT 24 4082363847 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4216877500 Jul 19 04:42:03 PM PDT 24 Jul 19 04:42:08 PM PDT 24 375276875 ps
T630 /workspace/coverage/cover_reg_top/26.hmac_intr_test.681140275 Jul 19 04:42:30 PM PDT 24 Jul 19 04:42:41 PM PDT 24 12771461 ps
T631 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.934033395 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:09 PM PDT 24 2643521317 ps
T632 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.240994945 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:04 PM PDT 24 52933000 ps
T633 /workspace/coverage/cover_reg_top/41.hmac_intr_test.212133805 Jul 19 04:42:29 PM PDT 24 Jul 19 04:42:40 PM PDT 24 18955742 ps
T634 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2530228498 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:25 PM PDT 24 129380241 ps
T635 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.501679238 Jul 19 04:42:11 PM PDT 24 Jul 19 04:42:17 PM PDT 24 150633264 ps
T636 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1456171493 Jul 19 04:42:01 PM PDT 24 Jul 19 04:42:15 PM PDT 24 1832829339 ps
T637 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2810247075 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:20 PM PDT 24 123893694 ps
T638 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4257964963 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:18 PM PDT 24 144499393 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2115012639 Jul 19 04:42:25 PM PDT 24 Jul 19 04:42:34 PM PDT 24 53958310 ps
T640 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4190536663 Jul 19 04:42:27 PM PDT 24 Jul 19 04:42:40 PM PDT 24 186301809 ps
T641 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3665301725 Jul 19 04:42:25 PM PDT 24 Jul 19 04:42:35 PM PDT 24 107224132 ps
T642 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.867946969 Jul 19 04:42:02 PM PDT 24 Jul 19 04:42:06 PM PDT 24 107176181 ps
T643 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3569770917 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:05 PM PDT 24 3629343704 ps
T644 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1062093017 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:22 PM PDT 24 369757568 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3868214949 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:04 PM PDT 24 105159661 ps
T646 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2702872375 Jul 19 04:42:27 PM PDT 24 Jul 19 04:42:36 PM PDT 24 14703370 ps
T647 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1009539131 Jul 19 04:41:54 PM PDT 24 Jul 19 04:41:57 PM PDT 24 196296658 ps
T648 /workspace/coverage/cover_reg_top/23.hmac_intr_test.962192658 Jul 19 04:42:23 PM PDT 24 Jul 19 04:42:29 PM PDT 24 27698337 ps
T649 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1667828482 Jul 19 04:42:12 PM PDT 24 Jul 19 04:42:17 PM PDT 24 17930046 ps
T650 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1842573358 Jul 19 04:42:10 PM PDT 24 Jul 19 04:42:15 PM PDT 24 1716106443 ps
T651 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2219543309 Jul 19 04:42:21 PM PDT 24 Jul 19 04:42:30 PM PDT 24 179398063 ps
T652 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2575094 Jul 19 04:42:24 PM PDT 24 Jul 19 04:42:32 PM PDT 24 41817550 ps
T653 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2313504801 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:20 PM PDT 24 243272795 ps
T63 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2453364710 Jul 19 04:42:00 PM PDT 24 Jul 19 04:42:05 PM PDT 24 262510824 ps
T654 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1903404514 Jul 19 04:42:14 PM PDT 24 Jul 19 04:42:19 PM PDT 24 75551435 ps
T655 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2274040659 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:27 PM PDT 24 379770905 ps
T656 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1427863231 Jul 19 04:42:20 PM PDT 24 Jul 19 04:42:25 PM PDT 24 82127306 ps
T657 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2028702259 Jul 19 04:42:26 PM PDT 24 Jul 19 04:42:36 PM PDT 24 41212559 ps
T658 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.371971331 Jul 19 04:41:59 PM PDT 24 Jul 19 04:42:03 PM PDT 24 463706299 ps
T126 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1672792912 Jul 19 04:42:28 PM PDT 24 Jul 19 04:42:40 PM PDT 24 539156194 ps
T659 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.78350209 Jul 19 04:42:13 PM PDT 24 Jul 19 04:42:21 PM PDT 24 157063718 ps

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3997043351
Short name T2
Test name
Test status
Simulation time 320765496837 ps
CPU time 7255.9 seconds
Started Jul 19 04:55:42 PM PDT 24
Finished Jul 19 06:56:40 PM PDT 24
Peak memory 874408 kb
Host smart-d04b78d4-61b0-4b8e-95de-a19fc7b33184
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997043351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3997043351
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.211330247
Short name T8
Test name
Test status
Simulation time 43918917136 ps
CPU time 601.81 seconds
Started Jul 19 04:55:34 PM PDT 24
Finished Jul 19 05:05:39 PM PDT 24
Peak memory 200224 kb
Host smart-c7408d88-3dac-4b83-b7df-98d73ab5fbaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=211330247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.211330247
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.716613241
Short name T60
Test name
Test status
Simulation time 127756909 ps
CPU time 4.1 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 199800 kb
Host smart-670df2a0-33e1-43f7-8406-71c360ab1aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716613241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.716613241
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1955310437
Short name T20
Test name
Test status
Simulation time 280559568426 ps
CPU time 6432.8 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 06:43:04 PM PDT 24
Peak memory 830616 kb
Host smart-ac3241df-962a-4328-9ff4-050d02ec1ace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955310437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1955310437
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1598453835
Short name T46
Test name
Test status
Simulation time 74865047 ps
CPU time 0.82 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 04:55:27 PM PDT 24
Peak memory 218492 kb
Host smart-4800d731-64c0-44fa-bc16-25d34087dc51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598453835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1598453835
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2949435773
Short name T10
Test name
Test status
Simulation time 5575894910 ps
CPU time 81 seconds
Started Jul 19 04:57:46 PM PDT 24
Finished Jul 19 04:59:08 PM PDT 24
Peak memory 200324 kb
Host smart-4391008d-f2ce-4e0f-8024-24f868647891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949435773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2949435773
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3333230011
Short name T123
Test name
Test status
Simulation time 615104967 ps
CPU time 3.03 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 199548 kb
Host smart-658a05b7-75fc-4492-aae7-2252ca248381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333230011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3333230011
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.114770937
Short name T92
Test name
Test status
Simulation time 40272076 ps
CPU time 0.71 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 197212 kb
Host smart-248f99cd-cc4d-4b0d-835a-0ef638480f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114770937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.114770937
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1573405269
Short name T154
Test name
Test status
Simulation time 20018002 ps
CPU time 0.6 seconds
Started Jul 19 04:55:28 PM PDT 24
Finished Jul 19 04:55:31 PM PDT 24
Peak memory 196176 kb
Host smart-89ad8c64-193e-4708-8f8b-518754aadb5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573405269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1573405269
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3159346812
Short name T11
Test name
Test status
Simulation time 71726285833 ps
CPU time 384.51 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 467388 kb
Host smart-eac090d9-5586-4cb6-be32-4aeb09c3956e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159346812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3159346812
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2914627056
Short name T125
Test name
Test status
Simulation time 82401949 ps
CPU time 1.93 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199644 kb
Host smart-851efe41-d605-4ea0-950b-bcc2caa9b4ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914627056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2914627056
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_smoke.3617212839
Short name T17
Test name
Test status
Simulation time 2143707584 ps
CPU time 9.63 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:31 PM PDT 24
Peak memory 200244 kb
Host smart-7aa530ad-e9cb-43b5-ac58-9fbb92c8453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617212839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3617212839
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.177230903
Short name T261
Test name
Test status
Simulation time 1152259824 ps
CPU time 57.08 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:56:46 PM PDT 24
Peak memory 200268 kb
Host smart-f19f99d6-cac5-42f2-a4e7-747cf5252022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177230903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.177230903
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2453364710
Short name T63
Test name
Test status
Simulation time 262510824 ps
CPU time 3.1 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 199648 kb
Host smart-958bb194-38aa-4f2e-93c9-65e2bd0f3a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453364710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2453364710
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1059511891
Short name T600
Test name
Test status
Simulation time 118814732 ps
CPU time 5.37 seconds
Started Jul 19 04:41:52 PM PDT 24
Finished Jul 19 04:41:59 PM PDT 24
Peak memory 199612 kb
Host smart-8b16e479-952b-429b-97e4-528e9017e299
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059511891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1059511891
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3660677354
Short name T628
Test name
Test status
Simulation time 4082363847 ps
CPU time 9.67 seconds
Started Jul 19 04:41:53 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 199696 kb
Host smart-c0ace23b-1681-48f4-abf3-4b08f535a4d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660677354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3660677354
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.371971331
Short name T658
Test name
Test status
Simulation time 463706299 ps
CPU time 1.01 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199244 kb
Host smart-b319fa34-b9e1-40c5-9b7a-0f28998b298c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371971331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.371971331
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.600767480
Short name T536
Test name
Test status
Simulation time 42503332 ps
CPU time 1.27 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199536 kb
Host smart-29379d59-a972-4a27-a3b9-56796227bd8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600767480 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.600767480
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3642376291
Short name T597
Test name
Test status
Simulation time 30757604 ps
CPU time 0.96 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199392 kb
Host smart-9d9c8710-30fe-4a95-ad24-16ce9689a4b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642376291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3642376291
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1009539131
Short name T647
Test name
Test status
Simulation time 196296658 ps
CPU time 0.59 seconds
Started Jul 19 04:41:54 PM PDT 24
Finished Jul 19 04:41:57 PM PDT 24
Peak memory 194536 kb
Host smart-79b0e1e6-da8e-485e-915e-bd214484f320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009539131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1009539131
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2261091237
Short name T590
Test name
Test status
Simulation time 143277287 ps
CPU time 2.34 seconds
Started Jul 19 04:42:03 PM PDT 24
Finished Jul 19 04:42:07 PM PDT 24
Peak memory 199696 kb
Host smart-91b79f10-4b23-44d4-988d-e95af7828770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261091237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2261091237
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1983161931
Short name T601
Test name
Test status
Simulation time 25315001 ps
CPU time 1.32 seconds
Started Jul 19 04:41:55 PM PDT 24
Finished Jul 19 04:41:59 PM PDT 24
Peak memory 199656 kb
Host smart-3e104a8b-f638-49d7-b56f-9e6b5ba306b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983161931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1983161931
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1393542010
Short name T605
Test name
Test status
Simulation time 287232309 ps
CPU time 2.96 seconds
Started Jul 19 04:41:54 PM PDT 24
Finished Jul 19 04:42:00 PM PDT 24
Peak memory 199652 kb
Host smart-dd10785c-eda9-4d5f-bb37-87b1c60df980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393542010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1393542010
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3569770917
Short name T643
Test name
Test status
Simulation time 3629343704 ps
CPU time 3.46 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 199660 kb
Host smart-b017ec7f-0fc9-4b93-b988-57d8638b8db0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569770917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3569770917
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1939375940
Short name T578
Test name
Test status
Simulation time 822791942 ps
CPU time 9.79 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:11 PM PDT 24
Peak memory 199640 kb
Host smart-fb00d342-acb3-4647-a66b-7cd183bab178
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939375940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1939375940
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3868214949
Short name T645
Test name
Test status
Simulation time 105159661 ps
CPU time 0.99 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 199468 kb
Host smart-9027c91e-94c3-46ca-9f19-6c4a86e64632
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868214949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3868214949
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3583065484
Short name T587
Test name
Test status
Simulation time 89968897 ps
CPU time 2.35 seconds
Started Jul 19 04:41:58 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199692 kb
Host smart-05ee6005-c446-474d-a7b5-e14a033e3471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583065484 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3583065484
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4037442252
Short name T101
Test name
Test status
Simulation time 32015309 ps
CPU time 0.93 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 199224 kb
Host smart-d467e0eb-7d0c-4eac-88df-e45944e7af62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037442252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4037442252
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.299086632
Short name T552
Test name
Test status
Simulation time 15082645 ps
CPU time 0.63 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 194516 kb
Host smart-857636b6-4606-48f7-b9cc-5972910aaaac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299086632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.299086632
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1969687720
Short name T109
Test name
Test status
Simulation time 89850604 ps
CPU time 1.16 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 198312 kb
Host smart-9a5b5bc5-f8c4-4ee4-a0cc-52d4f1f40c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969687720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1969687720
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3071868155
Short name T565
Test name
Test status
Simulation time 1021569171 ps
CPU time 4.42 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 199788 kb
Host smart-db7d3673-e6af-4b61-a43c-44329245a9b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071868155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3071868155
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3701631886
Short name T124
Test name
Test status
Simulation time 310950712 ps
CPU time 1.82 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199616 kb
Host smart-621a9ec3-c763-4f52-979f-6d608159b4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701631886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3701631886
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1572524199
Short name T541
Test name
Test status
Simulation time 42870101 ps
CPU time 1.23 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199468 kb
Host smart-3e83bdab-e311-472c-92fa-3bb7acb47c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572524199 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1572524199
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2774018677
Short name T556
Test name
Test status
Simulation time 18019306 ps
CPU time 0.76 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 198536 kb
Host smart-93d6a0c5-da39-467a-96ee-c2f7a44bb019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774018677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2774018677
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1402830819
Short name T608
Test name
Test status
Simulation time 58031637 ps
CPU time 0.64 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 194644 kb
Host smart-ac54eafe-865a-4791-81c7-03acc6e2cf00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402830819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1402830819
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.195613489
Short name T609
Test name
Test status
Simulation time 80716950 ps
CPU time 2.04 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199808 kb
Host smart-053e235f-ec7f-4f37-81fc-86010b65998d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195613489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.195613489
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2219543309
Short name T651
Test name
Test status
Simulation time 179398063 ps
CPU time 3.78 seconds
Started Jul 19 04:42:21 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 199668 kb
Host smart-c3001bd4-5853-4711-9847-8b140be167d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219543309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2219543309
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.561406846
Short name T121
Test name
Test status
Simulation time 53127583 ps
CPU time 1.76 seconds
Started Jul 19 04:42:15 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 199724 kb
Host smart-c0424af7-b96b-496e-9412-ba7da3bb82cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561406846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.561406846
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1014426486
Short name T599
Test name
Test status
Simulation time 166423024 ps
CPU time 2.12 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199692 kb
Host smart-7a57c604-f030-4081-89c2-47647ba0dda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014426486 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1014426486
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1903404514
Short name T654
Test name
Test status
Simulation time 75551435 ps
CPU time 0.61 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 194572 kb
Host smart-21fd800a-2178-4b3f-95b7-e43aa81ecf12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903404514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1903404514
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2810247075
Short name T637
Test name
Test status
Simulation time 123893694 ps
CPU time 2.42 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199728 kb
Host smart-92fd9232-95b2-4c4c-bffc-311b0bc60f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810247075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2810247075
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1062093017
Short name T644
Test name
Test status
Simulation time 369757568 ps
CPU time 4.06 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 199688 kb
Host smart-42353498-f7fd-4517-b8ae-796a9b5bfaae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062093017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1062093017
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2313504801
Short name T653
Test name
Test status
Simulation time 243272795 ps
CPU time 1.14 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199568 kb
Host smart-3a118f4f-e02b-4c61-bfc5-5b07d983298c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313504801 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2313504801
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4065896319
Short name T97
Test name
Test status
Simulation time 96850897 ps
CPU time 0.81 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 199440 kb
Host smart-ee1f8e6f-bbed-499b-9134-fc8bdca43526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065896319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4065896319
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1887494312
Short name T610
Test name
Test status
Simulation time 14487300 ps
CPU time 0.6 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 194628 kb
Host smart-1de4f795-992a-4766-a8e2-f1bc71b1c969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887494312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1887494312
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2388085396
Short name T604
Test name
Test status
Simulation time 72959662 ps
CPU time 1.06 seconds
Started Jul 19 04:42:11 PM PDT 24
Finished Jul 19 04:42:15 PM PDT 24
Peak memory 199772 kb
Host smart-1dbf647a-8d72-42c3-a12e-aa06ee17b25b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388085396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2388085396
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1820164264
Short name T544
Test name
Test status
Simulation time 142970072 ps
CPU time 2.84 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199632 kb
Host smart-bf8e1767-d439-4de9-b652-f43736a4061c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820164264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1820164264
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3179155852
Short name T118
Test name
Test status
Simulation time 588857207 ps
CPU time 3.3 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 199716 kb
Host smart-3f0a829e-df6d-4983-8e11-aff3e538f798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179155852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3179155852
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3913921934
Short name T563
Test name
Test status
Simulation time 270198201 ps
CPU time 2.62 seconds
Started Jul 19 04:42:18 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 199700 kb
Host smart-7eda2903-ebc6-4f44-b3b5-f1c4ed9d3aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913921934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3913921934
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.840301658
Short name T93
Test name
Test status
Simulation time 161807176 ps
CPU time 0.96 seconds
Started Jul 19 04:42:15 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199300 kb
Host smart-f84ab6f6-71d5-4ae5-b195-39d848508f54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840301658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.840301658
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4257964963
Short name T638
Test name
Test status
Simulation time 144499393 ps
CPU time 0.6 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 194696 kb
Host smart-f757c0a3-67c5-4a55-9598-827626f54faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257964963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4257964963
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1711756090
Short name T579
Test name
Test status
Simulation time 60418812 ps
CPU time 1.67 seconds
Started Jul 19 04:42:19 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 199632 kb
Host smart-c6d494ee-6ae7-491a-99ba-3e569c93caca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711756090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1711756090
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.17705738
Short name T573
Test name
Test status
Simulation time 257272005 ps
CPU time 2.89 seconds
Started Jul 19 04:42:15 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 199648 kb
Host smart-296c4fd6-baf5-4b39-b9e4-6ff7d0147411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17705738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.17705738
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3665301725
Short name T641
Test name
Test status
Simulation time 107224132 ps
CPU time 2.38 seconds
Started Jul 19 04:42:25 PM PDT 24
Finished Jul 19 04:42:35 PM PDT 24
Peak memory 199628 kb
Host smart-be5e9935-1c08-4bf4-8f02-31c773ec2751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665301725 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3665301725
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1291925210
Short name T621
Test name
Test status
Simulation time 61653842 ps
CPU time 0.92 seconds
Started Jul 19 04:42:17 PM PDT 24
Finished Jul 19 04:42:23 PM PDT 24
Peak memory 199328 kb
Host smart-9a690b44-96dc-483d-80f7-82b40de7152b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291925210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1291925210
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2925229072
Short name T606
Test name
Test status
Simulation time 23223717 ps
CPU time 0.59 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 194568 kb
Host smart-3d96e4e8-5892-408b-8601-4dec7ef87961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925229072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2925229072
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3429858031
Short name T112
Test name
Test status
Simulation time 65566455 ps
CPU time 1.54 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199664 kb
Host smart-bf7d85d4-0707-453d-8b48-9a3688b61b7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429858031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3429858031
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2962310942
Short name T591
Test name
Test status
Simulation time 399397211 ps
CPU time 2.19 seconds
Started Jul 19 04:42:18 PM PDT 24
Finished Jul 19 04:42:25 PM PDT 24
Peak memory 199700 kb
Host smart-060771e0-fa81-466e-bf85-5627fe415697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962310942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2962310942
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3750868055
Short name T122
Test name
Test status
Simulation time 182958595 ps
CPU time 3.19 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 199636 kb
Host smart-c293eafc-23e7-45e5-bfd3-c48288171239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750868055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3750868055
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.640358177
Short name T627
Test name
Test status
Simulation time 73841987 ps
CPU time 1.76 seconds
Started Jul 19 04:42:25 PM PDT 24
Finished Jul 19 04:42:36 PM PDT 24
Peak memory 199812 kb
Host smart-1cf2fe19-76ff-4d74-be21-c7d42632da12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640358177 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.640358177
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1948124932
Short name T582
Test name
Test status
Simulation time 49902406 ps
CPU time 0.87 seconds
Started Jul 19 04:42:21 PM PDT 24
Finished Jul 19 04:42:27 PM PDT 24
Peak memory 199632 kb
Host smart-3e61f159-a94a-499e-b247-710cee0f307a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948124932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1948124932
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2530228498
Short name T634
Test name
Test status
Simulation time 129380241 ps
CPU time 0.6 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:25 PM PDT 24
Peak memory 194524 kb
Host smart-6e02e0d1-140d-484f-bac4-f0da6133b531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530228498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2530228498
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2242750798
Short name T588
Test name
Test status
Simulation time 294622123 ps
CPU time 1.65 seconds
Started Jul 19 04:42:25 PM PDT 24
Finished Jul 19 04:42:34 PM PDT 24
Peak memory 199644 kb
Host smart-9ceadb30-18ac-44f0-a256-009e8f8e6d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242750798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2242750798
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4036883796
Short name T607
Test name
Test status
Simulation time 175203009 ps
CPU time 1.32 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 199664 kb
Host smart-24c676f7-f9c0-4eff-b3a1-a13165dbbecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036883796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4036883796
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3497930328
Short name T62
Test name
Test status
Simulation time 311929593 ps
CPU time 2.84 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 199628 kb
Host smart-ae1254ea-1d24-42a2-8d4b-040a57fcbbfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497930328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3497930328
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2575094
Short name T652
Test name
Test status
Simulation time 41817550 ps
CPU time 1.21 seconds
Started Jul 19 04:42:24 PM PDT 24
Finished Jul 19 04:42:32 PM PDT 24
Peak memory 199464 kb
Host smart-87db5eb0-e1c7-48c4-9419-b69fe772bb8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575094 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2575094
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1793182605
Short name T94
Test name
Test status
Simulation time 127943872 ps
CPU time 0.77 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 199440 kb
Host smart-f7fff578-7c5f-4335-9aea-a50d8d1bbc77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793182605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1793182605
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3392811462
Short name T619
Test name
Test status
Simulation time 26780470 ps
CPU time 0.65 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 194580 kb
Host smart-a2094e4e-d136-41b3-ae85-6e734a8d7dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392811462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3392811462
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2908700968
Short name T110
Test name
Test status
Simulation time 558729700 ps
CPU time 2.47 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 199660 kb
Host smart-f88eb9cb-33a2-438e-b161-e9766bfd08b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908700968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2908700968
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.359692881
Short name T546
Test name
Test status
Simulation time 254305953 ps
CPU time 4.17 seconds
Started Jul 19 04:42:26 PM PDT 24
Finished Jul 19 04:42:38 PM PDT 24
Peak memory 199644 kb
Host smart-0f25eee5-73d3-4500-8851-60e851289f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359692881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.359692881
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3764303720
Short name T129
Test name
Test status
Simulation time 1544493202 ps
CPU time 4.29 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:31 PM PDT 24
Peak memory 199700 kb
Host smart-96a72307-9d8d-4633-8962-0b0970216033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764303720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3764303720
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2063401977
Short name T537
Test name
Test status
Simulation time 131163704897 ps
CPU time 466.96 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:50:16 PM PDT 24
Peak memory 215780 kb
Host smart-46decafb-a74e-48bc-a13a-70a5a51683d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063401977 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2063401977
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.846579645
Short name T545
Test name
Test status
Simulation time 25615003 ps
CPU time 0.84 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:38 PM PDT 24
Peak memory 199480 kb
Host smart-19f93c9d-5021-420b-a39d-c86d6e7bdce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846579645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.846579645
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1531148243
Short name T623
Test name
Test status
Simulation time 12027460 ps
CPU time 0.6 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 194424 kb
Host smart-05575f25-c866-4c33-81d8-8fb198009d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531148243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1531148243
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.176030276
Short name T568
Test name
Test status
Simulation time 540971708 ps
CPU time 1.22 seconds
Started Jul 19 04:42:21 PM PDT 24
Finished Jul 19 04:42:28 PM PDT 24
Peak memory 199708 kb
Host smart-822f4edd-493d-45b1-939d-75c05f2b99a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176030276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.176030276
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1688380329
Short name T572
Test name
Test status
Simulation time 359500770 ps
CPU time 3.24 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:33 PM PDT 24
Peak memory 199636 kb
Host smart-214d1b74-764b-4e11-9f10-fcc545b2f636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688380329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1688380329
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.279259994
Short name T61
Test name
Test status
Simulation time 137914929 ps
CPU time 3.89 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:42 PM PDT 24
Peak memory 199784 kb
Host smart-c18d5d77-2dd7-4b6f-a4f8-360bac0b9c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279259994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.279259994
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1181639751
Short name T555
Test name
Test status
Simulation time 67611911 ps
CPU time 1.83 seconds
Started Jul 19 04:42:27 PM PDT 24
Finished Jul 19 04:42:37 PM PDT 24
Peak memory 199604 kb
Host smart-8d1483a3-a82b-4e25-a684-e79c9ebf3bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181639751 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1181639751
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2508642097
Short name T103
Test name
Test status
Simulation time 23685845 ps
CPU time 0.87 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:26 PM PDT 24
Peak memory 199132 kb
Host smart-77e9a7f5-cbb8-4c5d-9f61-ea44acd5d9e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508642097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2508642097
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3052823784
Short name T612
Test name
Test status
Simulation time 22369035 ps
CPU time 0.64 seconds
Started Jul 19 04:42:19 PM PDT 24
Finished Jul 19 04:42:25 PM PDT 24
Peak memory 194588 kb
Host smart-82db89ab-60d5-48b5-9550-087708062e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052823784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3052823784
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3482394368
Short name T107
Test name
Test status
Simulation time 149159148 ps
CPU time 2.38 seconds
Started Jul 19 04:42:27 PM PDT 24
Finished Jul 19 04:42:38 PM PDT 24
Peak memory 199612 kb
Host smart-bb842fb0-8536-476b-b21c-b49dc35a5a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482394368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3482394368
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2115012639
Short name T639
Test name
Test status
Simulation time 53958310 ps
CPU time 1.48 seconds
Started Jul 19 04:42:25 PM PDT 24
Finished Jul 19 04:42:34 PM PDT 24
Peak memory 199664 kb
Host smart-794b8345-3fbc-4079-b607-0d9c4c5e6645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115012639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2115012639
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1672792912
Short name T126
Test name
Test status
Simulation time 539156194 ps
CPU time 2.71 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:40 PM PDT 24
Peak memory 199704 kb
Host smart-543bec99-f812-4ac4-960f-36f7d37ce890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672792912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1672792912
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3563247133
Short name T626
Test name
Test status
Simulation time 33645525 ps
CPU time 2.08 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:27 PM PDT 24
Peak memory 199724 kb
Host smart-0b722657-ddf2-41fa-ad2d-f4595b715510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563247133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3563247133
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1457278952
Short name T538
Test name
Test status
Simulation time 19014336 ps
CPU time 0.79 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:25 PM PDT 24
Peak memory 197756 kb
Host smart-64156dcf-0f50-42ae-9313-346d863dd31c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457278952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1457278952
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.445908340
Short name T580
Test name
Test status
Simulation time 57391655 ps
CPU time 0.59 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 194724 kb
Host smart-23669e0b-f3f2-4131-8ccb-1a9408fccac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445908340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.445908340
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1229923594
Short name T106
Test name
Test status
Simulation time 177772845 ps
CPU time 1.72 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:27 PM PDT 24
Peak memory 199716 kb
Host smart-bdd67440-02fe-4112-b132-ddd538abd9ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229923594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1229923594
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4190536663
Short name T640
Test name
Test status
Simulation time 186301809 ps
CPU time 3.37 seconds
Started Jul 19 04:42:27 PM PDT 24
Finished Jul 19 04:42:40 PM PDT 24
Peak memory 199696 kb
Host smart-504febd4-5402-4d9c-a823-888dfd5e1265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190536663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.4190536663
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2274040659
Short name T655
Test name
Test status
Simulation time 379770905 ps
CPU time 1.81 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:27 PM PDT 24
Peak memory 199728 kb
Host smart-28318d6c-1368-4422-bfe2-e63d2398d8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274040659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2274040659
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1788055038
Short name T105
Test name
Test status
Simulation time 354363943 ps
CPU time 5.87 seconds
Started Jul 19 04:42:02 PM PDT 24
Finished Jul 19 04:42:10 PM PDT 24
Peak memory 199592 kb
Host smart-a18dcb72-6231-4ec1-909a-909d97dd37c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788055038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1788055038
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3434630622
Short name T569
Test name
Test status
Simulation time 2902076604 ps
CPU time 10.63 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:14 PM PDT 24
Peak memory 199756 kb
Host smart-4c37240b-b300-4b73-87b2-05c5ea422feb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434630622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3434630622
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2777399867
Short name T564
Test name
Test status
Simulation time 16326319 ps
CPU time 0.76 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 197624 kb
Host smart-db422438-ac8b-42a4-953a-e4a92f58c269
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777399867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2777399867
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.32977372
Short name T554
Test name
Test status
Simulation time 39048580 ps
CPU time 2.03 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 199688 kb
Host smart-770ddba0-fefc-4a7a-8b6c-915ed92ca450
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32977372 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.32977372
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3951137688
Short name T104
Test name
Test status
Simulation time 16139272 ps
CPU time 0.85 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 198860 kb
Host smart-f059ba16-aa5a-4766-ae5f-5a3a4b62d489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951137688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3951137688
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2158341306
Short name T618
Test name
Test status
Simulation time 22685945 ps
CPU time 0.57 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 194476 kb
Host smart-9511e56b-4549-4f4d-987c-6ad99e7252c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158341306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2158341306
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2838314497
Short name T576
Test name
Test status
Simulation time 48637109 ps
CPU time 2.29 seconds
Started Jul 19 04:42:02 PM PDT 24
Finished Jul 19 04:42:07 PM PDT 24
Peak memory 199660 kb
Host smart-46d78326-d3fd-4f49-bb10-8ed6add433d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838314497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2838314497
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2060669096
Short name T539
Test name
Test status
Simulation time 72347227 ps
CPU time 1.64 seconds
Started Jul 19 04:42:03 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 199636 kb
Host smart-eb25788f-abd7-4504-a5d1-87d97e97b2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060669096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2060669096
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1196818090
Short name T567
Test name
Test status
Simulation time 94655685 ps
CPU time 2.87 seconds
Started Jul 19 04:41:58 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 199712 kb
Host smart-76de0ca5-f511-49b4-9497-79d832dbaf1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196818090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1196818090
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.589072736
Short name T584
Test name
Test status
Simulation time 14778117 ps
CPU time 0.61 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:39 PM PDT 24
Peak memory 194652 kb
Host smart-e884340d-fa82-4f2b-ac4b-e8e83c378be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589072736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.589072736
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2068772761
Short name T583
Test name
Test status
Simulation time 22519749 ps
CPU time 0.6 seconds
Started Jul 19 04:42:18 PM PDT 24
Finished Jul 19 04:42:24 PM PDT 24
Peak memory 194772 kb
Host smart-fcfb8f3a-2287-4360-9903-3e70313b7aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068772761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2068772761
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.57174093
Short name T560
Test name
Test status
Simulation time 18606033 ps
CPU time 0.63 seconds
Started Jul 19 04:42:24 PM PDT 24
Finished Jul 19 04:42:31 PM PDT 24
Peak memory 194632 kb
Host smart-16a5f12e-ce76-4ece-8a0a-11f682937f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57174093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.57174093
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.962192658
Short name T648
Test name
Test status
Simulation time 27698337 ps
CPU time 0.58 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 194564 kb
Host smart-6fa5ef4d-9307-42a7-8554-d067d1fac8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962192658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.962192658
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1427863231
Short name T656
Test name
Test status
Simulation time 82127306 ps
CPU time 0.57 seconds
Started Jul 19 04:42:20 PM PDT 24
Finished Jul 19 04:42:25 PM PDT 24
Peak memory 194520 kb
Host smart-bc9797ea-2b87-4817-9d32-1410d4575175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427863231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1427863231
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.482617239
Short name T613
Test name
Test status
Simulation time 15637521 ps
CPU time 0.6 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 194600 kb
Host smart-18b51d5b-b36c-45b9-b416-63359b02ad6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482617239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.482617239
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.681140275
Short name T630
Test name
Test status
Simulation time 12771461 ps
CPU time 0.59 seconds
Started Jul 19 04:42:30 PM PDT 24
Finished Jul 19 04:42:41 PM PDT 24
Peak memory 194560 kb
Host smart-1f881e12-def8-42b1-a822-c73a053b9c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681140275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.681140275
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3183397734
Short name T589
Test name
Test status
Simulation time 185724003 ps
CPU time 0.56 seconds
Started Jul 19 04:42:26 PM PDT 24
Finished Jul 19 04:42:35 PM PDT 24
Peak memory 194608 kb
Host smart-eeb6079e-5f55-4111-b098-09b58d1239fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183397734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3183397734
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1255294729
Short name T543
Test name
Test status
Simulation time 12438061 ps
CPU time 0.57 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:38 PM PDT 24
Peak memory 194564 kb
Host smart-b016048c-9380-4411-8aaf-9b146a7f290c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255294729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1255294729
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2813358456
Short name T595
Test name
Test status
Simulation time 17530485 ps
CPU time 0.59 seconds
Started Jul 19 04:42:30 PM PDT 24
Finished Jul 19 04:42:41 PM PDT 24
Peak memory 194512 kb
Host smart-5abae740-9fef-4bfd-92da-37bde21200c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813358456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2813358456
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2239433984
Short name T102
Test name
Test status
Simulation time 420731742 ps
CPU time 5.63 seconds
Started Jul 19 04:41:59 PM PDT 24
Finished Jul 19 04:42:07 PM PDT 24
Peak memory 199616 kb
Host smart-bd5768c5-4089-49f3-ad70-4dce720e8ff2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239433984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2239433984
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.934033395
Short name T631
Test name
Test status
Simulation time 2643521317 ps
CPU time 5.79 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:09 PM PDT 24
Peak memory 199352 kb
Host smart-531ec825-9154-4dc9-a168-0fdfb64e9ef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934033395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.934033395
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4078944065
Short name T95
Test name
Test status
Simulation time 87980627 ps
CPU time 0.86 seconds
Started Jul 19 04:42:06 PM PDT 24
Finished Jul 19 04:42:09 PM PDT 24
Peak memory 198816 kb
Host smart-5d317346-b4d0-41e5-a417-55c72acaad6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078944065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4078944065
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.411582547
Short name T592
Test name
Test status
Simulation time 39435118 ps
CPU time 1.19 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:03 PM PDT 24
Peak memory 199544 kb
Host smart-dc654fa3-6f3b-4a3e-866e-48822adfa510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411582547 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.411582547
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3243902304
Short name T594
Test name
Test status
Simulation time 24888352 ps
CPU time 0.7 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 197128 kb
Host smart-0a9b780a-12c3-40e8-9b0a-53ca62d8787d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243902304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3243902304
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1606161229
Short name T571
Test name
Test status
Simulation time 77739605 ps
CPU time 0.67 seconds
Started Jul 19 04:42:03 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 194608 kb
Host smart-2ca5ca75-2b1e-4695-91b9-00bf55ccd7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606161229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1606161229
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.190266151
Short name T558
Test name
Test status
Simulation time 22043948 ps
CPU time 1.09 seconds
Started Jul 19 04:42:02 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 199536 kb
Host smart-37728f65-de8a-40a1-8e19-57def1e95f03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190266151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.190266151
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.240994945
Short name T632
Test name
Test status
Simulation time 52933000 ps
CPU time 1.48 seconds
Started Jul 19 04:42:00 PM PDT 24
Finished Jul 19 04:42:04 PM PDT 24
Peak memory 199636 kb
Host smart-aa76030a-a351-4294-80d1-887ae9bf11e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240994945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.240994945
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1588547533
Short name T624
Test name
Test status
Simulation time 34172395 ps
CPU time 0.57 seconds
Started Jul 19 04:42:29 PM PDT 24
Finished Jul 19 04:42:40 PM PDT 24
Peak memory 194460 kb
Host smart-e7f6d24d-b088-4cfc-b855-aa4d7ed1e48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588547533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1588547533
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1924084175
Short name T575
Test name
Test status
Simulation time 13976110 ps
CPU time 0.56 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 194496 kb
Host smart-84d87596-b229-4a0c-aff4-59073e571d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924084175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1924084175
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3882728366
Short name T535
Test name
Test status
Simulation time 58653115 ps
CPU time 0.57 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 194496 kb
Host smart-f273027e-8679-4403-b154-a52d96b0707c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882728366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3882728366
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2702872375
Short name T646
Test name
Test status
Simulation time 14703370 ps
CPU time 0.62 seconds
Started Jul 19 04:42:27 PM PDT 24
Finished Jul 19 04:42:36 PM PDT 24
Peak memory 194536 kb
Host smart-275cf087-5ac8-4f25-aa30-631c30ccb109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702872375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2702872375
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.772900788
Short name T598
Test name
Test status
Simulation time 11284797 ps
CPU time 0.58 seconds
Started Jul 19 04:42:26 PM PDT 24
Finished Jul 19 04:42:36 PM PDT 24
Peak memory 194460 kb
Host smart-bfd3e305-7812-4b81-a777-6bb55fe75d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772900788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.772900788
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.409200331
Short name T616
Test name
Test status
Simulation time 14926450 ps
CPU time 0.57 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:28 PM PDT 24
Peak memory 194500 kb
Host smart-4fe0fdd0-77d3-4e40-a7b9-bfa8779f20e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409200331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.409200331
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2225772515
Short name T596
Test name
Test status
Simulation time 13590926 ps
CPU time 0.63 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:27 PM PDT 24
Peak memory 194608 kb
Host smart-b7305e27-467b-4185-aa3e-0ca86a2e442b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225772515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2225772515
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2028702259
Short name T657
Test name
Test status
Simulation time 41212559 ps
CPU time 0.61 seconds
Started Jul 19 04:42:26 PM PDT 24
Finished Jul 19 04:42:36 PM PDT 24
Peak memory 194592 kb
Host smart-e26b0ba9-9e4c-46eb-bf48-c6063073374b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028702259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2028702259
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3446969812
Short name T534
Test name
Test status
Simulation time 43184382 ps
CPU time 0.63 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 194488 kb
Host smart-8f9eaf09-447b-44f9-a6c1-f6583004ee35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446969812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3446969812
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.550671001
Short name T617
Test name
Test status
Simulation time 13467481 ps
CPU time 0.61 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 194576 kb
Host smart-be2173b9-635f-4fad-a616-f581d2221c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550671001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.550671001
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4216877500
Short name T629
Test name
Test status
Simulation time 375276875 ps
CPU time 3.53 seconds
Started Jul 19 04:42:03 PM PDT 24
Finished Jul 19 04:42:08 PM PDT 24
Peak memory 199628 kb
Host smart-728845a9-fef4-4627-b1b4-48eed89ab9af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216877500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4216877500
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1456171493
Short name T636
Test name
Test status
Simulation time 1832829339 ps
CPU time 10.91 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:15 PM PDT 24
Peak memory 199712 kb
Host smart-2643a523-4db5-48af-819e-f59ca5a59f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456171493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1456171493
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.52184764
Short name T96
Test name
Test status
Simulation time 73086931 ps
CPU time 1 seconds
Started Jul 19 04:42:02 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 199512 kb
Host smart-7ef40359-cf65-439a-aeb2-222112d8d6c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52184764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.52184764
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3515108249
Short name T615
Test name
Test status
Simulation time 571957553 ps
CPU time 2.31 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 199712 kb
Host smart-663bf994-4f4b-4e0c-8b4e-64d0b7fb160e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515108249 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3515108249
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2162430285
Short name T100
Test name
Test status
Simulation time 35132096 ps
CPU time 0.96 seconds
Started Jul 19 04:42:01 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 199428 kb
Host smart-b6c39701-c018-4c76-9d42-08837c864279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162430285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2162430285
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1170794879
Short name T551
Test name
Test status
Simulation time 13906083 ps
CPU time 0.59 seconds
Started Jul 19 04:42:03 PM PDT 24
Finished Jul 19 04:42:05 PM PDT 24
Peak memory 194560 kb
Host smart-8ee2404a-a164-4f17-9ca9-ff0f073eb592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170794879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1170794879
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3810279153
Short name T559
Test name
Test status
Simulation time 83674221 ps
CPU time 1.12 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 199496 kb
Host smart-ad7873d2-a887-4120-9f41-75a9ee8e4e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810279153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3810279153
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.867946969
Short name T642
Test name
Test status
Simulation time 107176181 ps
CPU time 1.54 seconds
Started Jul 19 04:42:02 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 199720 kb
Host smart-53518202-1a1b-49d5-a32e-3bc1037a886e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867946969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.867946969
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3923033774
Short name T119
Test name
Test status
Simulation time 86701131 ps
CPU time 1.91 seconds
Started Jul 19 04:42:02 PM PDT 24
Finished Jul 19 04:42:06 PM PDT 24
Peak memory 199752 kb
Host smart-13331f29-3ba5-4566-a989-1099db36b247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923033774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3923033774
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3611846881
Short name T574
Test name
Test status
Simulation time 119157499 ps
CPU time 0.62 seconds
Started Jul 19 04:42:29 PM PDT 24
Finished Jul 19 04:42:40 PM PDT 24
Peak memory 194620 kb
Host smart-d4d74ef6-cbba-4337-896e-eb48afd7ca19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611846881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3611846881
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.212133805
Short name T633
Test name
Test status
Simulation time 18955742 ps
CPU time 0.64 seconds
Started Jul 19 04:42:29 PM PDT 24
Finished Jul 19 04:42:40 PM PDT 24
Peak memory 194652 kb
Host smart-64d3268b-167f-4f7f-9588-6c72be002c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212133805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.212133805
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3606461817
Short name T593
Test name
Test status
Simulation time 15129927 ps
CPU time 0.58 seconds
Started Jul 19 04:42:34 PM PDT 24
Finished Jul 19 04:42:46 PM PDT 24
Peak memory 194608 kb
Host smart-eb0cbfec-4191-481b-949f-1f1f9a8d42e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606461817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3606461817
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3573522227
Short name T550
Test name
Test status
Simulation time 13074625 ps
CPU time 0.59 seconds
Started Jul 19 04:42:27 PM PDT 24
Finished Jul 19 04:42:37 PM PDT 24
Peak memory 194512 kb
Host smart-ca2cebb5-fb9a-4958-85cb-e15c99f3918a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573522227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3573522227
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2880588598
Short name T603
Test name
Test status
Simulation time 48244769 ps
CPU time 0.6 seconds
Started Jul 19 04:42:23 PM PDT 24
Finished Jul 19 04:42:30 PM PDT 24
Peak memory 194508 kb
Host smart-9c5c191c-47db-4fdc-a0c9-07bfe9e3bbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880588598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2880588598
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.435023747
Short name T553
Test name
Test status
Simulation time 62843472 ps
CPU time 0.61 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 194560 kb
Host smart-2c376ba2-fd93-40de-845a-292a43178c88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435023747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.435023747
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2063628759
Short name T540
Test name
Test status
Simulation time 53993145 ps
CPU time 0.62 seconds
Started Jul 19 04:42:25 PM PDT 24
Finished Jul 19 04:42:35 PM PDT 24
Peak memory 194540 kb
Host smart-e8007fc5-2a19-48be-8399-763788d4a8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063628759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2063628759
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3444781361
Short name T533
Test name
Test status
Simulation time 43484415 ps
CPU time 0.6 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:39 PM PDT 24
Peak memory 194732 kb
Host smart-c6a88353-93d7-484a-9457-9c9f6c565033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444781361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3444781361
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.55307866
Short name T614
Test name
Test status
Simulation time 16881587 ps
CPU time 0.59 seconds
Started Jul 19 04:42:28 PM PDT 24
Finished Jul 19 04:42:39 PM PDT 24
Peak memory 194596 kb
Host smart-8bef672e-dd5f-4eab-a473-bf401f5cdd3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55307866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.55307866
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4131109880
Short name T620
Test name
Test status
Simulation time 14896895 ps
CPU time 0.67 seconds
Started Jul 19 04:42:22 PM PDT 24
Finished Jul 19 04:42:28 PM PDT 24
Peak memory 194620 kb
Host smart-58edb2f0-0fa8-498f-ac19-62e6a9b890ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131109880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4131109880
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1266173614
Short name T562
Test name
Test status
Simulation time 98159786106 ps
CPU time 985.06 seconds
Started Jul 19 04:42:15 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 216236 kb
Host smart-a5955f7b-db27-4a5c-bb3d-5a8833c15555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266173614 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1266173614
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.445980266
Short name T98
Test name
Test status
Simulation time 13810801 ps
CPU time 0.81 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199000 kb
Host smart-a6fe86f3-30bf-4930-a807-f50b33edbc1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445980266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.445980266
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3384322030
Short name T622
Test name
Test status
Simulation time 36425203 ps
CPU time 0.63 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 194608 kb
Host smart-5602c088-7523-4026-b1fc-566f883b5032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384322030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3384322030
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1076615671
Short name T625
Test name
Test status
Simulation time 167744242 ps
CPU time 1.1 seconds
Started Jul 19 04:42:10 PM PDT 24
Finished Jul 19 04:42:15 PM PDT 24
Peak memory 199616 kb
Host smart-25d69f25-c090-4748-b126-f00a0b4101e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076615671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1076615671
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3308677089
Short name T577
Test name
Test status
Simulation time 190648044 ps
CPU time 1.29 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199660 kb
Host smart-38374d73-8fab-4da7-b760-5bd806e2d01d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308677089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3308677089
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2571607259
Short name T128
Test name
Test status
Simulation time 160900243 ps
CPU time 1.86 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 199708 kb
Host smart-aa80d4ef-0536-4b98-aaeb-d0c10cc00f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571607259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2571607259
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1959816266
Short name T581
Test name
Test status
Simulation time 436392975489 ps
CPU time 1859.84 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 05:13:17 PM PDT 24
Peak memory 233444 kb
Host smart-6042eb68-30ad-4a29-bc88-afa8543e5729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959816266 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1959816266
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4162358175
Short name T99
Test name
Test status
Simulation time 77672304 ps
CPU time 0.9 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199032 kb
Host smart-def5788f-f41a-4412-9f40-8c79ce31e8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162358175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4162358175
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1667828482
Short name T649
Test name
Test status
Simulation time 17930046 ps
CPU time 0.62 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 194660 kb
Host smart-6bb0537c-18d4-4e8c-905b-5632df0083ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667828482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1667828482
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1241991880
Short name T586
Test name
Test status
Simulation time 45643417 ps
CPU time 1.16 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199668 kb
Host smart-0ed80e6b-2b39-4747-b6d9-6550ec4ab6d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241991880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1241991880
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2673797795
Short name T542
Test name
Test status
Simulation time 190656364 ps
CPU time 3.91 seconds
Started Jul 19 04:42:09 PM PDT 24
Finished Jul 19 04:42:16 PM PDT 24
Peak memory 199616 kb
Host smart-6f8d50ce-bd8c-4296-b1be-61543fa7d278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673797795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2673797795
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.78350209
Short name T659
Test name
Test status
Simulation time 157063718 ps
CPU time 3.05 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 199696 kb
Host smart-c09af2bb-1146-4382-b047-24b295814ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78350209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.78350209
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1492680330
Short name T532
Test name
Test status
Simulation time 114772234 ps
CPU time 1.12 seconds
Started Jul 19 04:42:11 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 199416 kb
Host smart-525ea294-44a0-45d7-ace9-835ff4b51bfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492680330 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1492680330
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.987875378
Short name T108
Test name
Test status
Simulation time 26379368 ps
CPU time 0.7 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 197572 kb
Host smart-b3726ead-603b-483d-aef3-09a2b7b2d431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987875378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.987875378
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.612466556
Short name T549
Test name
Test status
Simulation time 11950452 ps
CPU time 0.59 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 194472 kb
Host smart-0d5bb2a4-7e11-4748-aa40-0f5f03b11d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612466556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.612466556
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3858755872
Short name T561
Test name
Test status
Simulation time 137760423 ps
CPU time 1.04 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 199476 kb
Host smart-cda3ad8d-2edd-45ee-b169-8410be96c8c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858755872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3858755872
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.673620717
Short name T602
Test name
Test status
Simulation time 25114038 ps
CPU time 1.37 seconds
Started Jul 19 04:42:15 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 199664 kb
Host smart-07715270-759e-46a6-bd70-3ea1c919752f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673620717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.673620717
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.562036961
Short name T120
Test name
Test status
Simulation time 1020389632 ps
CPU time 4.3 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:21 PM PDT 24
Peak memory 199712 kb
Host smart-c9476557-8f7a-4902-b5c6-082df842b0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562036961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.562036961
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1278809007
Short name T547
Test name
Test status
Simulation time 121521510 ps
CPU time 1.72 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:20 PM PDT 24
Peak memory 199808 kb
Host smart-7319b0bb-e04e-46c9-b2c5-2942fb477ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278809007 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1278809007
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.467163899
Short name T111
Test name
Test status
Simulation time 39544726 ps
CPU time 0.79 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 198436 kb
Host smart-860c874e-2e3d-4814-aac3-6c0ebca45aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467163899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.467163899
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3075199650
Short name T611
Test name
Test status
Simulation time 15374271 ps
CPU time 0.64 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:19 PM PDT 24
Peak memory 194528 kb
Host smart-4bfe7931-429e-4a80-bd13-cf9a2aba15a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075199650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3075199650
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1842573358
Short name T650
Test name
Test status
Simulation time 1716106443 ps
CPU time 2.1 seconds
Started Jul 19 04:42:10 PM PDT 24
Finished Jul 19 04:42:15 PM PDT 24
Peak memory 199368 kb
Host smart-584f33c1-2a02-4be6-8f73-5aad57c2346d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842573358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1842573358
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3454771185
Short name T548
Test name
Test status
Simulation time 429905326 ps
CPU time 3.57 seconds
Started Jul 19 04:42:14 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 199652 kb
Host smart-f84e68ff-02fb-4b37-8c74-35f72987ecdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454771185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3454771185
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2441103960
Short name T557
Test name
Test status
Simulation time 134911218 ps
CPU time 2.1 seconds
Started Jul 19 04:42:15 PM PDT 24
Finished Jul 19 04:42:22 PM PDT 24
Peak memory 208076 kb
Host smart-d90036f8-ce56-41fd-8b03-b5fef995309c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441103960 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2441103960
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3392860596
Short name T566
Test name
Test status
Simulation time 51552845 ps
CPU time 0.7 seconds
Started Jul 19 04:42:18 PM PDT 24
Finished Jul 19 04:42:23 PM PDT 24
Peak memory 197880 kb
Host smart-2ae81073-0326-499e-99db-aef1cb717313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392860596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3392860596
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.26140978
Short name T585
Test name
Test status
Simulation time 37094615 ps
CPU time 0.64 seconds
Started Jul 19 04:42:13 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 194560 kb
Host smart-42d6fc1d-6b25-4e56-b0ec-e1975b7cd87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.26140978
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.501679238
Short name T635
Test name
Test status
Simulation time 150633264 ps
CPU time 1.91 seconds
Started Jul 19 04:42:11 PM PDT 24
Finished Jul 19 04:42:17 PM PDT 24
Peak memory 199632 kb
Host smart-dfda3a4e-3f86-4606-88d0-de616900d0ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501679238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.501679238
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1820375159
Short name T570
Test name
Test status
Simulation time 83684553 ps
CPU time 1.26 seconds
Started Jul 19 04:42:12 PM PDT 24
Finished Jul 19 04:42:18 PM PDT 24
Peak memory 199644 kb
Host smart-1f4b17c8-64ec-4498-b20f-9038ae067a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820375159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1820375159
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1794343460
Short name T127
Test name
Test status
Simulation time 157689485 ps
CPU time 3.17 seconds
Started Jul 19 04:42:21 PM PDT 24
Finished Jul 19 04:42:29 PM PDT 24
Peak memory 199704 kb
Host smart-14af894c-1fe6-4d25-84a2-0a635e71b489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794343460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1794343460
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2855140837
Short name T4
Test name
Test status
Simulation time 2734669012 ps
CPU time 39.78 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:56:01 PM PDT 24
Peak memory 200280 kb
Host smart-1b2f06f1-be44-4aca-b174-94184b85e75d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855140837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2855140837
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3935396361
Short name T500
Test name
Test status
Simulation time 2363985682 ps
CPU time 65.42 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:56:28 PM PDT 24
Peak memory 200196 kb
Host smart-aca6d864-0323-4eb5-98a9-f14080952ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935396361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3935396361
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1976190388
Short name T363
Test name
Test status
Simulation time 99017362 ps
CPU time 0.82 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 198892 kb
Host smart-ab517ed2-d759-4a9d-b736-1ec96832f7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976190388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1976190388
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.472726191
Short name T210
Test name
Test status
Simulation time 23313051326 ps
CPU time 126.21 seconds
Started Jul 19 04:55:17 PM PDT 24
Finished Jul 19 04:57:29 PM PDT 24
Peak memory 200200 kb
Host smart-b4889e74-ca43-44e4-86b2-b07d2c0b3d9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472726191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.472726191
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3177398514
Short name T375
Test name
Test status
Simulation time 41317441365 ps
CPU time 203.73 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:58:46 PM PDT 24
Peak memory 200324 kb
Host smart-ef890c58-0b73-4599-b90e-28ed44eec739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177398514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3177398514
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1023302574
Short name T47
Test name
Test status
Simulation time 59097686 ps
CPU time 0.87 seconds
Started Jul 19 04:55:23 PM PDT 24
Finished Jul 19 04:55:28 PM PDT 24
Peak memory 218472 kb
Host smart-08795e04-5e9d-415d-ac22-9027cf8e6b71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023302574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1023302574
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_stress_all.460053215
Short name T494
Test name
Test status
Simulation time 194687013430 ps
CPU time 1263.26 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 05:16:25 PM PDT 24
Peak memory 200204 kb
Host smart-5636fa17-37a5-4267-abc9-f0dfcf39610a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460053215 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.460053215
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.39154530
Short name T521
Test name
Test status
Simulation time 12359077283 ps
CPU time 74.56 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:56:36 PM PDT 24
Peak memory 200336 kb
Host smart-a3935b67-8ad9-426f-83b9-f56cb306383e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=39154530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.39154530
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3201929137
Short name T35
Test name
Test status
Simulation time 9971470903 ps
CPU time 97.61 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:57:00 PM PDT 24
Peak memory 200372 kb
Host smart-8478d6a9-7c70-4a4d-9c4a-a1961d9a894a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3201929137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3201929137
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2517351883
Short name T524
Test name
Test status
Simulation time 5075051808 ps
CPU time 118.72 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:57:20 PM PDT 24
Peak memory 200192 kb
Host smart-29d84090-b1be-480f-ab8c-a8340bf1f64d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2517351883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2517351883
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2155416149
Short name T525
Test name
Test status
Simulation time 47543457517 ps
CPU time 656.98 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 05:06:19 PM PDT 24
Peak memory 200288 kb
Host smart-fda60df5-f6a8-4af9-8e8d-345f964802e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2155416149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2155416149
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2925516434
Short name T283
Test name
Test status
Simulation time 221980261255 ps
CPU time 2737.93 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 05:41:00 PM PDT 24
Peak memory 216152 kb
Host smart-0452d330-b11c-4da3-b0f5-c004976e55d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2925516434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2925516434
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.111218575
Short name T492
Test name
Test status
Simulation time 40375619973 ps
CPU time 2291 seconds
Started Jul 19 04:55:17 PM PDT 24
Finished Jul 19 05:33:34 PM PDT 24
Peak memory 216268 kb
Host smart-c4d243e8-0cc1-4a34-b4a8-22974a50df35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=111218575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.111218575
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3769288391
Short name T30
Test name
Test status
Simulation time 12866133486 ps
CPU time 127.15 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:57:26 PM PDT 24
Peak memory 200220 kb
Host smart-1759e8ba-bde1-4d49-a5a1-6e4acbcfba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769288391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3769288391
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2830007733
Short name T273
Test name
Test status
Simulation time 29229846 ps
CPU time 0.59 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:55:36 PM PDT 24
Peak memory 195148 kb
Host smart-1c79542b-27f1-4068-85f0-8cc176c00eac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830007733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2830007733
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.384337508
Short name T240
Test name
Test status
Simulation time 3969618958 ps
CPU time 63.03 seconds
Started Jul 19 04:55:28 PM PDT 24
Finished Jul 19 04:56:33 PM PDT 24
Peak memory 200304 kb
Host smart-53ba101c-dfd3-4f54-a7fd-d8ba732db871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384337508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.384337508
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2272518070
Short name T24
Test name
Test status
Simulation time 160477118 ps
CPU time 2.33 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 04:55:28 PM PDT 24
Peak memory 200236 kb
Host smart-45a4fab9-e143-45a4-85d1-2fd018584f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272518070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2272518070
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3912080736
Short name T296
Test name
Test status
Simulation time 24792806861 ps
CPU time 1211.34 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 05:15:37 PM PDT 24
Peak memory 733520 kb
Host smart-92fc0285-1f77-451d-aa37-7885e2f4395d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912080736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3912080736
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.892879351
Short name T505
Test name
Test status
Simulation time 3158687035 ps
CPU time 175.19 seconds
Started Jul 19 04:55:26 PM PDT 24
Finished Jul 19 04:58:25 PM PDT 24
Peak memory 200200 kb
Host smart-4a272edf-b948-4bb3-a4bd-ab1dc0311a0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892879351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.892879351
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2814803374
Short name T146
Test name
Test status
Simulation time 130768177704 ps
CPU time 105.8 seconds
Started Jul 19 04:55:28 PM PDT 24
Finished Jul 19 04:57:16 PM PDT 24
Peak memory 200336 kb
Host smart-d4714774-4425-4297-89f8-7dd8c8cdb715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814803374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2814803374
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.2161880643
Short name T156
Test name
Test status
Simulation time 1081574629 ps
CPU time 3.72 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 04:55:30 PM PDT 24
Peak memory 200288 kb
Host smart-5ab948a4-d650-4d23-88ff-58c1a090d481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161880643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2161880643
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3555714840
Short name T267
Test name
Test status
Simulation time 4927711126 ps
CPU time 795.41 seconds
Started Jul 19 04:55:24 PM PDT 24
Finished Jul 19 05:08:43 PM PDT 24
Peak memory 677696 kb
Host smart-1e89f50b-1ce1-4713-970a-a8ea673666e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555714840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3555714840
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3273421139
Short name T6
Test name
Test status
Simulation time 46009017633 ps
CPU time 2906.02 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 05:43:52 PM PDT 24
Peak memory 707660 kb
Host smart-80132d8f-00a7-4755-aa02-7ad89063dac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273421139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3273421139
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2144575214
Short name T233
Test name
Test status
Simulation time 2639842097 ps
CPU time 41.89 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 04:56:08 PM PDT 24
Peak memory 200312 kb
Host smart-576c2cd1-a0af-449e-ad02-2c6e5f304e85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2144575214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2144575214
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.832194085
Short name T143
Test name
Test status
Simulation time 29410116200 ps
CPU time 61.78 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 04:56:28 PM PDT 24
Peak memory 200292 kb
Host smart-5c42c2f8-d2ca-4e66-abd0-a7cf293e51a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=832194085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.832194085
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.91524730
Short name T1
Test name
Test status
Simulation time 20993370182 ps
CPU time 74.52 seconds
Started Jul 19 04:55:23 PM PDT 24
Finished Jul 19 04:56:41 PM PDT 24
Peak memory 200312 kb
Host smart-6b590b7a-8019-47ac-9ccc-030ca6bb50c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=91524730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.91524730
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1550715967
Short name T276
Test name
Test status
Simulation time 143887574956 ps
CPU time 663.33 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 05:06:29 PM PDT 24
Peak memory 200184 kb
Host smart-910128a3-851f-467b-937c-8cd1175d37a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1550715967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1550715967
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3506802091
Short name T429
Test name
Test status
Simulation time 2827632365253 ps
CPU time 2534.03 seconds
Started Jul 19 04:55:22 PM PDT 24
Finished Jul 19 05:37:40 PM PDT 24
Peak memory 215788 kb
Host smart-48194d34-4935-423d-8ebf-1ba1c01c2d01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3506802091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3506802091
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2085464542
Short name T141
Test name
Test status
Simulation time 113696785345 ps
CPU time 2131.03 seconds
Started Jul 19 04:55:21 PM PDT 24
Finished Jul 19 05:30:57 PM PDT 24
Peak memory 216472 kb
Host smart-122a4018-ab7f-44da-85e9-dd0423c1374a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2085464542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2085464542
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2324869462
Short name T412
Test name
Test status
Simulation time 4500922837 ps
CPU time 45.85 seconds
Started Jul 19 04:55:25 PM PDT 24
Finished Jul 19 04:56:14 PM PDT 24
Peak memory 200300 kb
Host smart-ce18f910-71fa-4b5e-9265-e49928c7a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324869462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2324869462
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.144703029
Short name T215
Test name
Test status
Simulation time 47447959 ps
CPU time 0.58 seconds
Started Jul 19 04:55:50 PM PDT 24
Finished Jul 19 04:55:53 PM PDT 24
Peak memory 195068 kb
Host smart-c381707b-8375-4e20-8207-1ad5f94dbeb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144703029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.144703029
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1346428601
Short name T522
Test name
Test status
Simulation time 836788457 ps
CPU time 14.51 seconds
Started Jul 19 04:55:50 PM PDT 24
Finished Jul 19 04:56:08 PM PDT 24
Peak memory 200176 kb
Host smart-e04a3265-128e-4455-a901-2616fc6de0e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346428601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1346428601
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1089015413
Short name T419
Test name
Test status
Simulation time 7414604313 ps
CPU time 331.84 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 05:01:22 PM PDT 24
Peak memory 644800 kb
Host smart-b48d2808-3000-4931-a290-57bc2f471fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089015413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1089015413
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2766331256
Short name T237
Test name
Test status
Simulation time 34141365476 ps
CPU time 206.66 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:59:17 PM PDT 24
Peak memory 200348 kb
Host smart-14a1556d-3d41-4bfe-83e5-15acc3e66ad2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766331256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2766331256
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2981515296
Short name T23
Test name
Test status
Simulation time 2448449129 ps
CPU time 74.06 seconds
Started Jul 19 04:56:01 PM PDT 24
Finished Jul 19 04:57:17 PM PDT 24
Peak memory 200188 kb
Host smart-85bd6d04-a659-4ddb-8e8d-ea7161cf0cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981515296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2981515296
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4123124272
Short name T292
Test name
Test status
Simulation time 3285735602 ps
CPU time 12.01 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:56:02 PM PDT 24
Peak memory 200320 kb
Host smart-df64e32e-ba02-43fc-8f1c-cb2d1e4675ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123124272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4123124272
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3423630346
Short name T70
Test name
Test status
Simulation time 82908298725 ps
CPU time 1136.16 seconds
Started Jul 19 04:55:50 PM PDT 24
Finished Jul 19 05:14:49 PM PDT 24
Peak memory 200256 kb
Host smart-72c9e139-f88d-4cdf-ab7d-fd8582f5c921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423630346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3423630346
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2923881735
Short name T82
Test name
Test status
Simulation time 5746276399 ps
CPU time 50.17 seconds
Started Jul 19 04:56:02 PM PDT 24
Finished Jul 19 04:56:54 PM PDT 24
Peak memory 200180 kb
Host smart-08552a3b-37df-493a-a55c-198cfeb41ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923881735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2923881735
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3159430169
Short name T15
Test name
Test status
Simulation time 40314677 ps
CPU time 0.59 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:55:59 PM PDT 24
Peak memory 195052 kb
Host smart-f538256e-2c5b-4d39-96b0-12e13749f7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159430169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3159430169
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.106894572
Short name T321
Test name
Test status
Simulation time 1470192629 ps
CPU time 42.39 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:56:32 PM PDT 24
Peak memory 200184 kb
Host smart-6889a284-c9d9-4838-aaaa-864b80878347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106894572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.106894572
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.428395338
Short name T218
Test name
Test status
Simulation time 3567326722 ps
CPU time 23.3 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:56:13 PM PDT 24
Peak memory 200388 kb
Host smart-25795e04-6d89-4ccc-a003-3f4b6e54ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428395338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.428395338
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4245259220
Short name T449
Test name
Test status
Simulation time 30620927972 ps
CPU time 1448.15 seconds
Started Jul 19 04:56:02 PM PDT 24
Finished Jul 19 05:20:12 PM PDT 24
Peak memory 769488 kb
Host smart-c72a54e2-396e-41e8-8773-927e1b08c60e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245259220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4245259220
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1368432359
Short name T51
Test name
Test status
Simulation time 33046741884 ps
CPU time 138.53 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:58:08 PM PDT 24
Peak memory 200288 kb
Host smart-3c48eadb-47ae-4ff8-993c-d7d2cef85315
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368432359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1368432359
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1229384478
Short name T197
Test name
Test status
Simulation time 19068117536 ps
CPU time 154.86 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:58:24 PM PDT 24
Peak memory 200504 kb
Host smart-f15a12f5-205b-44db-8517-c1a512aa0475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229384478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1229384478
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.5904553
Short name T457
Test name
Test status
Simulation time 219492713 ps
CPU time 5.13 seconds
Started Jul 19 04:55:51 PM PDT 24
Finished Jul 19 04:55:59 PM PDT 24
Peak memory 200128 kb
Host smart-a486d9e6-3a90-48a1-9935-514da2831eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5904553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.5904553
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3078708030
Short name T306
Test name
Test status
Simulation time 107536368241 ps
CPU time 2406.62 seconds
Started Jul 19 04:55:57 PM PDT 24
Finished Jul 19 05:36:07 PM PDT 24
Peak memory 794024 kb
Host smart-c293351b-7637-40ac-b499-cbd9e902bacf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078708030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3078708030
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2714373815
Short name T85
Test name
Test status
Simulation time 24670182566 ps
CPU time 87.63 seconds
Started Jul 19 04:55:57 PM PDT 24
Finished Jul 19 04:57:28 PM PDT 24
Peak memory 200360 kb
Host smart-b7e61a57-b41c-4595-8df5-89e0ed279326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714373815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2714373815
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.908988771
Short name T322
Test name
Test status
Simulation time 31989270 ps
CPU time 0.6 seconds
Started Jul 19 04:56:00 PM PDT 24
Finished Jul 19 04:56:03 PM PDT 24
Peak memory 196196 kb
Host smart-26fab847-3488-4906-b94e-2dc4095934cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908988771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.908988771
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3592644404
Short name T279
Test name
Test status
Simulation time 4989529377 ps
CPU time 89.24 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:57:28 PM PDT 24
Peak memory 200284 kb
Host smart-88f13550-735a-4d0a-b20b-a8b22a91e5ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592644404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3592644404
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.182804906
Short name T491
Test name
Test status
Simulation time 2446160673 ps
CPU time 33.16 seconds
Started Jul 19 04:55:57 PM PDT 24
Finished Jul 19 04:56:33 PM PDT 24
Peak memory 200312 kb
Host smart-866bba36-5789-4310-80a6-a2c92523017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182804906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.182804906
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4215850811
Short name T142
Test name
Test status
Simulation time 2281231667 ps
CPU time 467.49 seconds
Started Jul 19 04:56:01 PM PDT 24
Finished Jul 19 05:03:50 PM PDT 24
Peak memory 641164 kb
Host smart-edc0e385-6d88-4642-8d24-88e251511a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215850811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4215850811
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.77768231
Short name T318
Test name
Test status
Simulation time 17948757205 ps
CPU time 111.12 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:57:51 PM PDT 24
Peak memory 200300 kb
Host smart-0236cd4e-2a52-47ec-96de-0a0fc08fa287
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77768231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.77768231
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2209745416
Short name T253
Test name
Test status
Simulation time 1909955433 ps
CPU time 36.73 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:56:36 PM PDT 24
Peak memory 200252 kb
Host smart-e1d57420-7bc0-41bb-83a6-acf6e37d85af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209745416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2209745416
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.948528566
Short name T349
Test name
Test status
Simulation time 1758350936 ps
CPU time 4.76 seconds
Started Jul 19 04:55:58 PM PDT 24
Finished Jul 19 04:56:06 PM PDT 24
Peak memory 200268 kb
Host smart-72b62cad-d13c-44ba-8468-bee8ea7bb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948528566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.948528566
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2140097550
Short name T22
Test name
Test status
Simulation time 92378848157 ps
CPU time 304.25 seconds
Started Jul 19 04:55:57 PM PDT 24
Finished Jul 19 05:01:04 PM PDT 24
Peak memory 200344 kb
Host smart-88621a0c-f7e7-4d76-9384-1c1a60b73bcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140097550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2140097550
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2463901567
Short name T241
Test name
Test status
Simulation time 6396070496 ps
CPU time 84.31 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:57:24 PM PDT 24
Peak memory 200356 kb
Host smart-0ca5beb2-a819-444a-8be9-a920eb654b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463901567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2463901567
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3405689803
Short name T330
Test name
Test status
Simulation time 21816715 ps
CPU time 0.6 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:55:59 PM PDT 24
Peak memory 196044 kb
Host smart-c629cfc0-6993-4b9b-bcef-a98fedfbb705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405689803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3405689803
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1530712329
Short name T355
Test name
Test status
Simulation time 869410872 ps
CPU time 26.43 seconds
Started Jul 19 04:55:59 PM PDT 24
Finished Jul 19 04:56:28 PM PDT 24
Peak memory 200192 kb
Host smart-07249ae5-a3da-42a9-ae92-a283b8627aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530712329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1530712329
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2371649670
Short name T400
Test name
Test status
Simulation time 5890732157 ps
CPU time 77.29 seconds
Started Jul 19 04:55:59 PM PDT 24
Finished Jul 19 04:57:19 PM PDT 24
Peak memory 200264 kb
Host smart-13d38b09-d030-4b01-be77-61c82999fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371649670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2371649670
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1090717521
Short name T180
Test name
Test status
Simulation time 3984650380 ps
CPU time 827.86 seconds
Started Jul 19 04:56:01 PM PDT 24
Finished Jul 19 05:09:51 PM PDT 24
Peak memory 762248 kb
Host smart-31130652-65c6-4fab-85c0-0d9ea77c2f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090717521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1090717521
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.988263540
Short name T158
Test name
Test status
Simulation time 7227426511 ps
CPU time 30.94 seconds
Started Jul 19 04:55:58 PM PDT 24
Finished Jul 19 04:56:32 PM PDT 24
Peak memory 200336 kb
Host smart-4bb5d0a2-023f-46e1-ae64-a5f51951a73f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988263540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.988263540
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4234529370
Short name T359
Test name
Test status
Simulation time 1079982316 ps
CPU time 8 seconds
Started Jul 19 04:55:57 PM PDT 24
Finished Jul 19 04:56:08 PM PDT 24
Peak memory 200256 kb
Host smart-c476dbc2-792a-4f8a-aa8a-5d415d7d3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234529370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4234529370
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2559135959
Short name T482
Test name
Test status
Simulation time 399274675 ps
CPU time 5.64 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:56:05 PM PDT 24
Peak memory 200248 kb
Host smart-1c35f3cc-72e1-49a2-a8fa-1dd4e8876928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559135959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2559135959
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.112001160
Short name T155
Test name
Test status
Simulation time 3444400725 ps
CPU time 32.62 seconds
Started Jul 19 04:56:00 PM PDT 24
Finished Jul 19 04:56:35 PM PDT 24
Peak memory 208504 kb
Host smart-e8736350-e16f-41d5-9ffa-821421c2250b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112001160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.112001160
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3083962484
Short name T475
Test name
Test status
Simulation time 1816324625 ps
CPU time 22.77 seconds
Started Jul 19 04:55:58 PM PDT 24
Finished Jul 19 04:56:24 PM PDT 24
Peak memory 200236 kb
Host smart-e31ce25a-05c6-4633-8148-237aad843e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083962484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3083962484
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.791410779
Short name T343
Test name
Test status
Simulation time 51113703 ps
CPU time 0.67 seconds
Started Jul 19 04:56:10 PM PDT 24
Finished Jul 19 04:56:12 PM PDT 24
Peak memory 196120 kb
Host smart-59aad07a-ed2b-4858-aadc-cc22f55bbcfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791410779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.791410779
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.62644907
Short name T53
Test name
Test status
Simulation time 597699030 ps
CPU time 37.9 seconds
Started Jul 19 04:55:59 PM PDT 24
Finished Jul 19 04:56:40 PM PDT 24
Peak memory 200232 kb
Host smart-9509ac0d-e204-4a56-9f2c-cef2afcb230d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62644907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.62644907
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2618607970
Short name T451
Test name
Test status
Simulation time 2028330771 ps
CPU time 9.66 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:56:19 PM PDT 24
Peak memory 200292 kb
Host smart-5adc83e0-94fd-41db-ab44-658e38046ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618607970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2618607970
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2313190782
Short name T5
Test name
Test status
Simulation time 44394746564 ps
CPU time 1097.26 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 05:14:26 PM PDT 24
Peak memory 791740 kb
Host smart-9731866f-7ede-405b-8d39-260204f544a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313190782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2313190782
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2953278213
Short name T173
Test name
Test status
Simulation time 14602412422 ps
CPU time 93.73 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:57:41 PM PDT 24
Peak memory 200168 kb
Host smart-7c1380a1-7212-4752-8655-4214ec173791
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953278213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2953278213
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.6763574
Short name T79
Test name
Test status
Simulation time 10583798013 ps
CPU time 108.18 seconds
Started Jul 19 04:55:59 PM PDT 24
Finished Jul 19 04:57:50 PM PDT 24
Peak memory 200232 kb
Host smart-9b39353d-09f5-4096-bdd1-4ee484a77173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6763574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.6763574
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3856717024
Short name T294
Test name
Test status
Simulation time 22963372 ps
CPU time 0.88 seconds
Started Jul 19 04:55:56 PM PDT 24
Finished Jul 19 04:56:00 PM PDT 24
Peak memory 198732 kb
Host smart-a59f4fbb-618e-4338-8f7a-fe30de818ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856717024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3856717024
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2892892497
Short name T86
Test name
Test status
Simulation time 22750244299 ps
CPU time 529.51 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 05:04:58 PM PDT 24
Peak memory 200216 kb
Host smart-e92f272c-a136-4767-930f-94029176c692
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892892497 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2892892497
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3026574778
Short name T361
Test name
Test status
Simulation time 572606514 ps
CPU time 31.87 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:56:42 PM PDT 24
Peak memory 200296 kb
Host smart-5ebb405c-c951-4dfe-8e16-a240e1d6de59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026574778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3026574778
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1002005661
Short name T208
Test name
Test status
Simulation time 21118941 ps
CPU time 0.59 seconds
Started Jul 19 04:56:13 PM PDT 24
Finished Jul 19 04:56:15 PM PDT 24
Peak memory 196104 kb
Host smart-9f2cc04a-6b80-438f-8bce-aee9101521c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002005661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1002005661
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2310254392
Short name T178
Test name
Test status
Simulation time 464009688 ps
CPU time 26.12 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:56:35 PM PDT 24
Peak memory 200216 kb
Host smart-3ee8cec8-6986-40e8-82e9-8c678d9ddb4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310254392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2310254392
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3693464159
Short name T83
Test name
Test status
Simulation time 9622992943 ps
CPU time 63.73 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:57:13 PM PDT 24
Peak memory 200360 kb
Host smart-9600f657-96a7-402e-80fd-3b01826fa311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693464159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3693464159
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1953930385
Short name T383
Test name
Test status
Simulation time 25031823780 ps
CPU time 1203.84 seconds
Started Jul 19 04:56:05 PM PDT 24
Finished Jul 19 05:16:11 PM PDT 24
Peak memory 742336 kb
Host smart-6f23313d-4053-4ffe-a5ad-4677bd43798c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953930385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1953930385
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1533949520
Short name T401
Test name
Test status
Simulation time 9552466031 ps
CPU time 154.34 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:58:41 PM PDT 24
Peak memory 200252 kb
Host smart-6abcbb1c-af9d-4b45-a6c9-492358d6b90e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533949520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1533949520
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2170578190
Short name T190
Test name
Test status
Simulation time 12762846526 ps
CPU time 109.82 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:57:55 PM PDT 24
Peak memory 200288 kb
Host smart-6a9d19f9-8967-479f-aaa8-58f2c021837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170578190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2170578190
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3487052459
Short name T399
Test name
Test status
Simulation time 31448305 ps
CPU time 1.6 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:56:11 PM PDT 24
Peak memory 200244 kb
Host smart-39d9e488-1788-48c9-ae29-b1cbf20a5b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487052459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3487052459
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1938152865
Short name T175
Test name
Test status
Simulation time 23530857263 ps
CPU time 433.1 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 05:03:22 PM PDT 24
Peak memory 200144 kb
Host smart-3cdf8e0a-5c5f-4c5d-aac0-889a55f6e4b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938152865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1938152865
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2059328518
Short name T116
Test name
Test status
Simulation time 541486224 ps
CPU time 26.88 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:56:34 PM PDT 24
Peak memory 200136 kb
Host smart-4f27d552-d6cd-42ea-a505-b00efb31c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059328518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2059328518
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.527881395
Short name T166
Test name
Test status
Simulation time 33320011 ps
CPU time 0.56 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:56:10 PM PDT 24
Peak memory 196196 kb
Host smart-66afa28b-9434-475d-af31-8d4c6cfbdc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527881395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.527881395
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.134491399
Short name T58
Test name
Test status
Simulation time 12595684035 ps
CPU time 88.87 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:57:35 PM PDT 24
Peak memory 200396 kb
Host smart-64aa7325-7537-44d6-bb7c-7c4a64ba8e7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134491399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.134491399
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.983977524
Short name T138
Test name
Test status
Simulation time 28669515114 ps
CPU time 54.73 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:57:04 PM PDT 24
Peak memory 200404 kb
Host smart-c00e0b55-3bea-45bb-b077-5bdfb79e3cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983977524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.983977524
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1307284873
Short name T302
Test name
Test status
Simulation time 20570686857 ps
CPU time 961.69 seconds
Started Jul 19 04:56:15 PM PDT 24
Finished Jul 19 05:12:19 PM PDT 24
Peak memory 742060 kb
Host smart-cd86e774-1ef5-4715-a77d-9785de0d7d7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307284873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1307284873
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1623118009
Short name T281
Test name
Test status
Simulation time 6118512563 ps
CPU time 105.22 seconds
Started Jul 19 04:56:03 PM PDT 24
Finished Jul 19 04:57:50 PM PDT 24
Peak memory 200244 kb
Host smart-9d739a4c-69b4-442a-b46d-221e83e2de90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623118009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1623118009
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1729865404
Short name T21
Test name
Test status
Simulation time 2799279384 ps
CPU time 37.99 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:56:48 PM PDT 24
Peak memory 200356 kb
Host smart-8e4df22b-a91e-448c-8a52-4f4a9b6fc065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729865404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1729865404
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3505480652
Short name T262
Test name
Test status
Simulation time 1047305204 ps
CPU time 12.95 seconds
Started Jul 19 04:56:03 PM PDT 24
Finished Jul 19 04:56:18 PM PDT 24
Peak memory 200236 kb
Host smart-a827147a-34ab-461b-bd9c-27304c77d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505480652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3505480652
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2700979847
Short name T324
Test name
Test status
Simulation time 80329927209 ps
CPU time 804.79 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 05:09:31 PM PDT 24
Peak memory 583600 kb
Host smart-d53e4b92-f366-4cad-b8c1-e449f6eabfb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700979847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2700979847
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1843241076
Short name T516
Test name
Test status
Simulation time 9564768796 ps
CPU time 56.47 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:57:03 PM PDT 24
Peak memory 200300 kb
Host smart-4a595dd3-a37f-4eea-8b5c-d8a916553abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843241076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1843241076
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2472368318
Short name T266
Test name
Test status
Simulation time 26115450 ps
CPU time 0.62 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:56:10 PM PDT 24
Peak memory 196212 kb
Host smart-8f9e683d-0d2a-4544-8fab-3ecbd848061d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472368318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2472368318
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2654980100
Short name T377
Test name
Test status
Simulation time 1516821245 ps
CPU time 87.1 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:57:34 PM PDT 24
Peak memory 200228 kb
Host smart-664c329e-20f6-4250-aa9a-61a89596b8e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654980100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2654980100
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1196265531
Short name T441
Test name
Test status
Simulation time 13509602984 ps
CPU time 70.89 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:57:20 PM PDT 24
Peak memory 208416 kb
Host smart-76bacdaf-5fbb-46c9-abdc-e900801fdc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196265531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1196265531
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2884643102
Short name T360
Test name
Test status
Simulation time 56081893821 ps
CPU time 1612.45 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 05:23:01 PM PDT 24
Peak memory 783332 kb
Host smart-6bb8e75f-1d9d-441f-8f2a-f0fca81841c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884643102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2884643102
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3293314109
Short name T436
Test name
Test status
Simulation time 1715579637 ps
CPU time 99.64 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:57:46 PM PDT 24
Peak memory 200284 kb
Host smart-3e5b61ae-854d-4a1d-b5b8-076745b04f9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293314109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3293314109
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.138050795
Short name T382
Test name
Test status
Simulation time 5805836528 ps
CPU time 81.21 seconds
Started Jul 19 04:56:05 PM PDT 24
Finished Jul 19 04:57:29 PM PDT 24
Peak memory 200284 kb
Host smart-9b39c050-774c-400f-89af-34d31f29ee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138050795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.138050795
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3728491494
Short name T376
Test name
Test status
Simulation time 3313683223 ps
CPU time 13.69 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:56:23 PM PDT 24
Peak memory 200368 kb
Host smart-11dadb95-8280-49a7-ad38-f3096ebc62e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728491494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3728491494
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.574021818
Short name T69
Test name
Test status
Simulation time 5452241663 ps
CPU time 76.09 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:57:26 PM PDT 24
Peak memory 200300 kb
Host smart-4b0cfe50-fbc1-485c-89ba-75da3f516a36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574021818 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.574021818
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3532152421
Short name T404
Test name
Test status
Simulation time 2281384321 ps
CPU time 20.78 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:56:27 PM PDT 24
Peak memory 200216 kb
Host smart-c001de1e-b0bd-4207-bf53-8e4b43c00632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532152421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3532152421
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2277021134
Short name T371
Test name
Test status
Simulation time 15481832 ps
CPU time 0.62 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:56:10 PM PDT 24
Peak memory 196868 kb
Host smart-3cc1b388-c44b-42df-9f74-026b4fb1fc45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277021134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2277021134
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1534403588
Short name T424
Test name
Test status
Simulation time 783898791 ps
CPU time 22.3 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:56:28 PM PDT 24
Peak memory 200176 kb
Host smart-15ac6cd4-0396-4461-ad3d-938807e32642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534403588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1534403588
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1544561550
Short name T242
Test name
Test status
Simulation time 1423728648 ps
CPU time 24 seconds
Started Jul 19 04:56:05 PM PDT 24
Finished Jul 19 04:56:32 PM PDT 24
Peak memory 200272 kb
Host smart-114f1a66-555a-4256-a80b-527fee98e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544561550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1544561550
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3775361980
Short name T41
Test name
Test status
Simulation time 3451029322 ps
CPU time 688.31 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 05:07:34 PM PDT 24
Peak memory 722588 kb
Host smart-84cfd454-af54-4e69-978f-6d18dfbefe24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775361980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3775361980
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3174181401
Short name T323
Test name
Test status
Simulation time 12576706252 ps
CPU time 39.66 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:56:46 PM PDT 24
Peak memory 200220 kb
Host smart-c1d97441-9088-4bb5-9cf0-757c8e8f11c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174181401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3174181401
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1419215993
Short name T387
Test name
Test status
Simulation time 103886584632 ps
CPU time 167.03 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 208444 kb
Host smart-5bd89d2f-633a-446a-9ec4-496c0f00875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419215993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1419215993
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.938195118
Short name T170
Test name
Test status
Simulation time 214882662 ps
CPU time 9.72 seconds
Started Jul 19 04:56:07 PM PDT 24
Finished Jul 19 04:56:19 PM PDT 24
Peak memory 200244 kb
Host smart-b7a1192a-9b45-4bba-a621-4e1dcc87e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938195118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.938195118
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2444566965
Short name T423
Test name
Test status
Simulation time 240859203044 ps
CPU time 1652.91 seconds
Started Jul 19 04:56:05 PM PDT 24
Finished Jul 19 05:23:41 PM PDT 24
Peak memory 711504 kb
Host smart-50683cbf-0106-4ff9-ade5-964ecc3ad8a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444566965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2444566965
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.484894829
Short name T514
Test name
Test status
Simulation time 11764766409 ps
CPU time 142.61 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:58:32 PM PDT 24
Peak memory 200292 kb
Host smart-5396f15c-40bb-4743-b2b7-742a8966666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484894829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.484894829
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1208676787
Short name T194
Test name
Test status
Simulation time 19823931 ps
CPU time 0.6 seconds
Started Jul 19 04:56:12 PM PDT 24
Finished Jul 19 04:56:13 PM PDT 24
Peak memory 196216 kb
Host smart-466e5e29-2f3f-4a5b-80ff-a5ec0182fdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208676787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1208676787
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.620024958
Short name T257
Test name
Test status
Simulation time 5093200647 ps
CPU time 70.27 seconds
Started Jul 19 04:56:05 PM PDT 24
Finished Jul 19 04:57:18 PM PDT 24
Peak memory 200392 kb
Host smart-c52a4d86-245b-45e7-9223-c86e14845039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620024958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.620024958
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.82720793
Short name T75
Test name
Test status
Simulation time 2869765305 ps
CPU time 56.52 seconds
Started Jul 19 04:56:06 PM PDT 24
Finished Jul 19 04:57:06 PM PDT 24
Peak memory 200324 kb
Host smart-88b10a7b-a50f-478a-98f0-43f00e1603bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82720793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.82720793
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4025335739
Short name T221
Test name
Test status
Simulation time 46934150318 ps
CPU time 1028.52 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 05:13:14 PM PDT 24
Peak memory 761532 kb
Host smart-bc0c45eb-5c51-4932-bb39-48bb955fa4de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025335739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4025335739
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2828527219
Short name T199
Test name
Test status
Simulation time 31772635021 ps
CPU time 104.95 seconds
Started Jul 19 04:56:18 PM PDT 24
Finished Jul 19 04:58:04 PM PDT 24
Peak memory 200080 kb
Host smart-7c5d63ec-2ebb-47d2-8bb7-24053d17600a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828527219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2828527219
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2022730181
Short name T362
Test name
Test status
Simulation time 2101186171 ps
CPU time 126.5 seconds
Started Jul 19 04:56:05 PM PDT 24
Finished Jul 19 04:58:14 PM PDT 24
Peak memory 200168 kb
Host smart-fb5c0ef6-fa11-4329-8880-377614934227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022730181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2022730181
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.896886894
Short name T201
Test name
Test status
Simulation time 155504391 ps
CPU time 6.83 seconds
Started Jul 19 04:56:04 PM PDT 24
Finished Jul 19 04:56:12 PM PDT 24
Peak memory 200296 kb
Host smart-57ed1220-fdc0-4880-acc8-fb80abb49bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896886894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.896886894
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3705387775
Short name T205
Test name
Test status
Simulation time 32346823587 ps
CPU time 563.98 seconds
Started Jul 19 04:56:12 PM PDT 24
Finished Jul 19 05:05:38 PM PDT 24
Peak memory 663084 kb
Host smart-f3635871-dc74-4d12-be50-0e4fb11b92c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705387775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3705387775
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3466899407
Short name T466
Test name
Test status
Simulation time 10486963459 ps
CPU time 87.6 seconds
Started Jul 19 04:56:13 PM PDT 24
Finished Jul 19 04:57:42 PM PDT 24
Peak memory 200312 kb
Host smart-902a1e24-a2bb-4271-ac5a-695958445608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466899407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3466899407
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3508373259
Short name T271
Test name
Test status
Simulation time 82836094 ps
CPU time 0.59 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:55:35 PM PDT 24
Peak memory 196212 kb
Host smart-8c581215-2a3e-4bde-a920-e470849f8e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508373259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3508373259
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4012503260
Short name T131
Test name
Test status
Simulation time 4673021943 ps
CPU time 65.65 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:56:39 PM PDT 24
Peak memory 200484 kb
Host smart-30211a61-7964-4312-96f1-41509cf1a259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012503260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4012503260
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1081792663
Short name T230
Test name
Test status
Simulation time 13086475315 ps
CPU time 55.37 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:56:30 PM PDT 24
Peak memory 200320 kb
Host smart-e3cf088b-dbcc-443b-8b34-f7519843e22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081792663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1081792663
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2249734822
Short name T176
Test name
Test status
Simulation time 4300914376 ps
CPU time 316.97 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 05:00:54 PM PDT 24
Peak memory 452472 kb
Host smart-9221a519-4542-44d2-96ff-87ed831463b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249734822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2249734822
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2474356954
Short name T515
Test name
Test status
Simulation time 93885673440 ps
CPU time 112.28 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:57:27 PM PDT 24
Peak memory 200280 kb
Host smart-e0d6e36a-4393-4c44-84f9-c272bf74c682
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474356954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2474356954
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1189549804
Short name T476
Test name
Test status
Simulation time 2230136434 ps
CPU time 64.57 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:56:38 PM PDT 24
Peak memory 200268 kb
Host smart-56bf6282-a264-4580-b935-70475e48a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189549804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1189549804
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2434949521
Short name T49
Test name
Test status
Simulation time 126061402 ps
CPU time 1.2 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:55:34 PM PDT 24
Peak memory 219632 kb
Host smart-40e55511-3e0e-4e7f-b85d-432e0d4871e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434949521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2434949521
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3368547334
Short name T439
Test name
Test status
Simulation time 2498942061 ps
CPU time 10.53 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 04:55:47 PM PDT 24
Peak memory 200324 kb
Host smart-0ab98cd6-f368-4c3e-8ca9-8ef92cd91c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368547334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3368547334
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2142793615
Short name T310
Test name
Test status
Simulation time 69290673180 ps
CPU time 1409.87 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 05:19:07 PM PDT 24
Peak memory 734324 kb
Host smart-3730772a-e6ac-4ee4-83ac-37247279b312
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142793615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2142793615
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2012135965
Short name T12
Test name
Test status
Simulation time 346959859549 ps
CPU time 3313.65 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 05:50:51 PM PDT 24
Peak memory 763724 kb
Host smart-10190eca-39ac-4d18-bb47-bc0198902211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012135965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2012135965
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1305971805
Short name T167
Test name
Test status
Simulation time 6130045917 ps
CPU time 79.02 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:56:52 PM PDT 24
Peak memory 200220 kb
Host smart-9f7ac7db-fff9-4247-aeaf-f951bde4f319
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1305971805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1305971805
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3832537790
Short name T406
Test name
Test status
Simulation time 14993260570 ps
CPU time 91.47 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:57:05 PM PDT 24
Peak memory 200248 kb
Host smart-2d4779cb-2706-4e92-9bf5-6f8022022bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3832537790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3832537790
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.115621096
Short name T259
Test name
Test status
Simulation time 11684033087 ps
CPU time 127.1 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:57:40 PM PDT 24
Peak memory 200280 kb
Host smart-28538b76-af8b-4cc5-adb4-0effd6773841
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=115621096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.115621096
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3863661757
Short name T411
Test name
Test status
Simulation time 143982948915 ps
CPU time 2497.18 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 05:37:12 PM PDT 24
Peak memory 216108 kb
Host smart-a84ed482-90cd-4534-8744-e48c34ea57a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3863661757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3863661757
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3665286834
Short name T527
Test name
Test status
Simulation time 244069033922 ps
CPU time 2464.33 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 05:36:38 PM PDT 24
Peak memory 215864 kb
Host smart-2519b205-58f3-4c49-b0b9-30db78ca588a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3665286834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3665286834
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3798289700
Short name T381
Test name
Test status
Simulation time 9108483756 ps
CPU time 26.75 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:56:01 PM PDT 24
Peak memory 200260 kb
Host smart-a61e9a99-e2ce-4ae5-8212-c3247b504263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798289700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3798289700
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.900604379
Short name T14
Test name
Test status
Simulation time 35827172 ps
CPU time 0.58 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:56:17 PM PDT 24
Peak memory 195752 kb
Host smart-deb97046-e527-4db4-9bd8-0aa1bd5ee96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900604379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.900604379
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2682604260
Short name T229
Test name
Test status
Simulation time 1582151780 ps
CPU time 19.45 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:56:35 PM PDT 24
Peak memory 200224 kb
Host smart-2fada5db-4ccf-4c67-8c8b-dd1adbd7aaee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682604260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2682604260
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2296598832
Short name T336
Test name
Test status
Simulation time 3996816343 ps
CPU time 55.98 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:57:12 PM PDT 24
Peak memory 200316 kb
Host smart-c1548ed2-a18a-4684-9d19-95819134364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296598832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2296598832
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1707906938
Short name T447
Test name
Test status
Simulation time 572589713 ps
CPU time 87.35 seconds
Started Jul 19 04:56:11 PM PDT 24
Finished Jul 19 04:57:40 PM PDT 24
Peak memory 412948 kb
Host smart-b2150ab8-e4fe-473c-95ca-fbf8b064baf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707906938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1707906938
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1709702789
Short name T528
Test name
Test status
Simulation time 20373699189 ps
CPU time 152.42 seconds
Started Jul 19 04:56:15 PM PDT 24
Finished Jul 19 04:58:49 PM PDT 24
Peak memory 200288 kb
Host smart-1878512e-2e16-4b0d-866d-8dd8b2d7fb55
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709702789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1709702789
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1987779565
Short name T356
Test name
Test status
Simulation time 4740248397 ps
CPU time 79.39 seconds
Started Jul 19 04:56:13 PM PDT 24
Finished Jul 19 04:57:33 PM PDT 24
Peak memory 200328 kb
Host smart-4656660c-f4c8-45c4-8a6c-a6e6f23a7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987779565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1987779565
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3597446095
Short name T431
Test name
Test status
Simulation time 628193066 ps
CPU time 6.38 seconds
Started Jul 19 04:56:16 PM PDT 24
Finished Jul 19 04:56:24 PM PDT 24
Peak memory 200152 kb
Host smart-45610833-d107-4b0a-8d8b-e666fda116c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597446095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3597446095
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2793526945
Short name T467
Test name
Test status
Simulation time 9109234975 ps
CPU time 13.23 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:56:30 PM PDT 24
Peak memory 200312 kb
Host smart-752930e5-e902-49ac-a1cd-b5c4711547be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793526945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2793526945
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3686618586
Short name T117
Test name
Test status
Simulation time 9371651733 ps
CPU time 68.32 seconds
Started Jul 19 04:56:12 PM PDT 24
Finished Jul 19 04:57:22 PM PDT 24
Peak memory 200256 kb
Host smart-9966a47d-19d1-41d6-93d7-e11af65130a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686618586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3686618586
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.475363821
Short name T149
Test name
Test status
Simulation time 19922711 ps
CPU time 0.58 seconds
Started Jul 19 04:56:16 PM PDT 24
Finished Jul 19 04:56:18 PM PDT 24
Peak memory 195172 kb
Host smart-2252c56c-3998-40db-b71b-d879e165c8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475363821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.475363821
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3310678543
Short name T531
Test name
Test status
Simulation time 7745396411 ps
CPU time 92.91 seconds
Started Jul 19 04:56:12 PM PDT 24
Finished Jul 19 04:57:47 PM PDT 24
Peak memory 200288 kb
Host smart-810bc4ff-ab85-43d9-b650-e0b76a3b07f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310678543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3310678543
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3923264659
Short name T325
Test name
Test status
Simulation time 608352813 ps
CPU time 32.35 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:56:48 PM PDT 24
Peak memory 200196 kb
Host smart-748307d8-4586-4abb-ba20-3613598cc4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923264659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3923264659
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.225133466
Short name T490
Test name
Test status
Simulation time 97479050 ps
CPU time 1.56 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:56:18 PM PDT 24
Peak memory 200196 kb
Host smart-8328ffbf-b73f-4389-8e03-e227dc5b4caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225133466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.225133466
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2330754459
Short name T244
Test name
Test status
Simulation time 7179583448 ps
CPU time 191.25 seconds
Started Jul 19 04:56:15 PM PDT 24
Finished Jul 19 04:59:28 PM PDT 24
Peak memory 200356 kb
Host smart-b19a4b85-0049-49e3-8ae0-619a0606263e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330754459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2330754459
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3408972685
Short name T334
Test name
Test status
Simulation time 99563778906 ps
CPU time 128.1 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:58:24 PM PDT 24
Peak memory 200200 kb
Host smart-75538e65-245b-43cb-9262-f292d2eedeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408972685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3408972685
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3941447147
Short name T445
Test name
Test status
Simulation time 856341059 ps
CPU time 15 seconds
Started Jul 19 04:56:16 PM PDT 24
Finished Jul 19 04:56:33 PM PDT 24
Peak memory 200188 kb
Host smart-2754e65c-1fb9-49d6-a0c3-2bc5e77bee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941447147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3941447147
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1628306299
Short name T364
Test name
Test status
Simulation time 12216859238 ps
CPU time 1143.76 seconds
Started Jul 19 04:56:15 PM PDT 24
Finished Jul 19 05:15:21 PM PDT 24
Peak memory 662292 kb
Host smart-938e497e-f872-474a-adcf-bcb11971db00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628306299 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1628306299
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3983754379
Short name T115
Test name
Test status
Simulation time 4476394688 ps
CPU time 109.23 seconds
Started Jul 19 04:56:12 PM PDT 24
Finished Jul 19 04:58:03 PM PDT 24
Peak memory 200360 kb
Host smart-a856da0d-3128-4de9-8959-d9c9d1feef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983754379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3983754379
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2290457417
Short name T274
Test name
Test status
Simulation time 61380587 ps
CPU time 0.61 seconds
Started Jul 19 04:56:20 PM PDT 24
Finished Jul 19 04:56:21 PM PDT 24
Peak memory 196196 kb
Host smart-6d453adb-6ced-4fef-a8d4-673898b34d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290457417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2290457417
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1218507350
Short name T52
Test name
Test status
Simulation time 526196662 ps
CPU time 15.93 seconds
Started Jul 19 04:56:13 PM PDT 24
Finished Jul 19 04:56:30 PM PDT 24
Peak memory 200220 kb
Host smart-c9f5c7ce-3a8c-4e17-bdac-7c668608a7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218507350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1218507350
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2292119220
Short name T39
Test name
Test status
Simulation time 1945790052 ps
CPU time 55.01 seconds
Started Jul 19 04:56:20 PM PDT 24
Finished Jul 19 04:57:16 PM PDT 24
Peak memory 200288 kb
Host smart-3e643e4d-84aa-4f41-86bc-c030c4a959a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292119220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2292119220
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.163024412
Short name T391
Test name
Test status
Simulation time 878304979 ps
CPU time 21.96 seconds
Started Jul 19 04:56:14 PM PDT 24
Finished Jul 19 04:56:38 PM PDT 24
Peak memory 251128 kb
Host smart-44f6eef7-a42b-498f-acc7-46dd11d0f34d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163024412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.163024412
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.588141268
Short name T326
Test name
Test status
Simulation time 3933660539 ps
CPU time 219.64 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 05:00:02 PM PDT 24
Peak memory 200288 kb
Host smart-7b9af448-4981-446f-be71-73b580f32065
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588141268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.588141268
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.448995853
Short name T225
Test name
Test status
Simulation time 21236820254 ps
CPU time 77.11 seconds
Started Jul 19 04:56:16 PM PDT 24
Finished Jul 19 04:57:35 PM PDT 24
Peak memory 200304 kb
Host smart-63600d83-f53d-40e2-8549-7d19c8a4eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448995853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.448995853
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3573639854
Short name T301
Test name
Test status
Simulation time 659400233 ps
CPU time 10.86 seconds
Started Jul 19 04:56:18 PM PDT 24
Finished Jul 19 04:56:30 PM PDT 24
Peak memory 200092 kb
Host smart-4ccce0ba-9a76-4534-92de-35fefd3bea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573639854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3573639854
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3693902741
Short name T73
Test name
Test status
Simulation time 13992798134 ps
CPU time 123.56 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 04:58:27 PM PDT 24
Peak memory 208648 kb
Host smart-e38d7c98-2f32-42fc-a99a-faaa6d36c9c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693902741 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3693902741
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2017411767
Short name T203
Test name
Test status
Simulation time 3721436651 ps
CPU time 33.07 seconds
Started Jul 19 04:56:21 PM PDT 24
Finished Jul 19 04:56:55 PM PDT 24
Peak memory 200300 kb
Host smart-f9a8ef49-48d0-4ca1-9f21-92cde4b409f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017411767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2017411767
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2334899435
Short name T507
Test name
Test status
Simulation time 71612275 ps
CPU time 0.58 seconds
Started Jul 19 04:56:29 PM PDT 24
Finished Jul 19 04:56:30 PM PDT 24
Peak memory 196092 kb
Host smart-942aa8e6-a2c6-43c4-bc2f-f02b4e600f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334899435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2334899435
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2381492857
Short name T477
Test name
Test status
Simulation time 8925897258 ps
CPU time 82.93 seconds
Started Jul 19 04:56:21 PM PDT 24
Finished Jul 19 04:57:45 PM PDT 24
Peak memory 200312 kb
Host smart-1505c77b-4b3d-4a38-8918-d1f7d0ffdf12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381492857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2381492857
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2336857907
Short name T462
Test name
Test status
Simulation time 615329890 ps
CPU time 28.54 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 04:56:52 PM PDT 24
Peak memory 200216 kb
Host smart-b5da9fa2-ac76-425f-86f2-475593c70974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336857907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2336857907
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.581454384
Short name T392
Test name
Test status
Simulation time 4815036674 ps
CPU time 383.36 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 455460 kb
Host smart-6a4d0337-db17-4928-9dde-d7dcc00e122e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581454384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.581454384
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2042972369
Short name T353
Test name
Test status
Simulation time 3612360968 ps
CPU time 196.34 seconds
Started Jul 19 04:56:19 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 200292 kb
Host smart-6006e834-e5a3-4375-89c2-c23bd8600bcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042972369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2042972369
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.338536744
Short name T303
Test name
Test status
Simulation time 8937159097 ps
CPU time 186.04 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 04:59:30 PM PDT 24
Peak memory 200360 kb
Host smart-ea68eb30-aa13-4275-a170-2599da344142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338536744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.338536744
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.400805735
Short name T396
Test name
Test status
Simulation time 3993211407 ps
CPU time 12.71 seconds
Started Jul 19 04:56:19 PM PDT 24
Finished Jul 19 04:56:32 PM PDT 24
Peak memory 200224 kb
Host smart-38a5e870-791d-4865-8c3b-7631b7ff6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400805735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.400805735
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1285832467
Short name T461
Test name
Test status
Simulation time 10780272674 ps
CPU time 916.09 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 05:11:40 PM PDT 24
Peak memory 703496 kb
Host smart-df45072d-9d6c-4aca-b765-04811871fdf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285832467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1285832467
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.234368126
Short name T287
Test name
Test status
Simulation time 13709280703 ps
CPU time 94.26 seconds
Started Jul 19 04:56:22 PM PDT 24
Finished Jul 19 04:57:57 PM PDT 24
Peak memory 200292 kb
Host smart-88702b95-372a-4ef4-9131-123672f1af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234368126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.234368126
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2922694391
Short name T44
Test name
Test status
Simulation time 16789430 ps
CPU time 0.67 seconds
Started Jul 19 04:56:32 PM PDT 24
Finished Jul 19 04:56:35 PM PDT 24
Peak memory 196092 kb
Host smart-81286b4a-60d4-498a-bdad-4a1e0de5125b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922694391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2922694391
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3942401846
Short name T433
Test name
Test status
Simulation time 652567474 ps
CPU time 42.7 seconds
Started Jul 19 04:56:31 PM PDT 24
Finished Jul 19 04:57:16 PM PDT 24
Peak memory 200272 kb
Host smart-fce33448-abb1-4cc2-8ff9-1ccaf195e94b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942401846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3942401846
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.492347452
Short name T40
Test name
Test status
Simulation time 2255959797 ps
CPU time 55.73 seconds
Started Jul 19 04:56:28 PM PDT 24
Finished Jul 19 04:57:25 PM PDT 24
Peak memory 200308 kb
Host smart-d88d7b4b-8191-4a4d-953e-7024746113c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492347452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.492347452
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4047079029
Short name T157
Test name
Test status
Simulation time 12541301985 ps
CPU time 645.53 seconds
Started Jul 19 04:56:28 PM PDT 24
Finished Jul 19 05:07:14 PM PDT 24
Peak memory 690860 kb
Host smart-021b5908-125f-4bb5-8795-835fa12ffb5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047079029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4047079029
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3995176371
Short name T368
Test name
Test status
Simulation time 5617975849 ps
CPU time 154.85 seconds
Started Jul 19 04:56:30 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 200288 kb
Host smart-33cbf66b-d282-490b-ad1c-5c80eec5ef83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995176371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3995176371
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1923874464
Short name T56
Test name
Test status
Simulation time 1662162769 ps
CPU time 89.69 seconds
Started Jul 19 04:56:30 PM PDT 24
Finished Jul 19 04:58:02 PM PDT 24
Peak memory 200208 kb
Host smart-a330a248-be4d-4518-a758-efaa516b03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923874464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1923874464
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1982441584
Short name T248
Test name
Test status
Simulation time 1376700262 ps
CPU time 11.68 seconds
Started Jul 19 04:56:29 PM PDT 24
Finished Jul 19 04:56:41 PM PDT 24
Peak memory 200124 kb
Host smart-4d628ba2-8ae3-40cc-9d61-d427a9f4eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982441584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1982441584
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1842780030
Short name T357
Test name
Test status
Simulation time 358854696679 ps
CPU time 2719.11 seconds
Started Jul 19 04:56:27 PM PDT 24
Finished Jul 19 05:41:48 PM PDT 24
Peak memory 809396 kb
Host smart-d849a183-adc0-49f4-b265-d32df005edec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842780030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1842780030
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3335375145
Short name T397
Test name
Test status
Simulation time 2291397842 ps
CPU time 102.38 seconds
Started Jul 19 04:56:29 PM PDT 24
Finished Jul 19 04:58:13 PM PDT 24
Peak memory 200284 kb
Host smart-47855bb8-bb3d-49c9-a52f-761258c653df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335375145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3335375145
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2241738368
Short name T425
Test name
Test status
Simulation time 26552406 ps
CPU time 0.6 seconds
Started Jul 19 04:56:39 PM PDT 24
Finished Jul 19 04:56:42 PM PDT 24
Peak memory 196164 kb
Host smart-c73cb052-83e5-4e6d-84e3-a2c5d1fc3350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241738368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2241738368
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1080032325
Short name T28
Test name
Test status
Simulation time 352839505 ps
CPU time 19.91 seconds
Started Jul 19 04:56:29 PM PDT 24
Finished Jul 19 04:56:51 PM PDT 24
Peak memory 200276 kb
Host smart-6ff15d7e-4b20-4fad-8e8f-a140d90bfc80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080032325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1080032325
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1924190073
Short name T76
Test name
Test status
Simulation time 1780560495 ps
CPU time 45.8 seconds
Started Jul 19 04:57:27 PM PDT 24
Finished Jul 19 04:58:22 PM PDT 24
Peak memory 200304 kb
Host smart-c39cd05d-ea57-489f-9042-76f336c5c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924190073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1924190073
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1467747616
Short name T299
Test name
Test status
Simulation time 24979921933 ps
CPU time 1367.89 seconds
Started Jul 19 04:56:32 PM PDT 24
Finished Jul 19 05:19:22 PM PDT 24
Peak memory 775048 kb
Host smart-4078aee5-dcf6-4f94-ab34-37665c019d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467747616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1467747616
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2000138081
Short name T344
Test name
Test status
Simulation time 25094905971 ps
CPU time 115.18 seconds
Started Jul 19 04:56:39 PM PDT 24
Finished Jul 19 04:58:38 PM PDT 24
Peak memory 200352 kb
Host smart-8a5fcf6c-1246-44ae-8ee8-cf04a6a5ae82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000138081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2000138081
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.878982632
Short name T384
Test name
Test status
Simulation time 38022619630 ps
CPU time 174.11 seconds
Started Jul 19 04:56:28 PM PDT 24
Finished Jul 19 04:59:23 PM PDT 24
Peak memory 200448 kb
Host smart-711432aa-1285-4fb9-a38b-6bf501b1205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878982632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.878982632
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1055388368
Short name T288
Test name
Test status
Simulation time 577246460 ps
CPU time 14.37 seconds
Started Jul 19 04:56:28 PM PDT 24
Finished Jul 19 04:56:44 PM PDT 24
Peak memory 200256 kb
Host smart-93c5d4ed-1aa1-4164-99ad-1bcd1a988758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055388368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1055388368
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3779575753
Short name T209
Test name
Test status
Simulation time 5778584773 ps
CPU time 323.73 seconds
Started Jul 19 04:56:41 PM PDT 24
Finished Jul 19 05:02:08 PM PDT 24
Peak memory 216652 kb
Host smart-c02973b2-ce8a-4017-85fa-5eded2bd2922
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779575753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3779575753
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1506261420
Short name T523
Test name
Test status
Simulation time 3237367039 ps
CPU time 28.96 seconds
Started Jul 19 04:56:39 PM PDT 24
Finished Jul 19 04:57:11 PM PDT 24
Peak memory 200308 kb
Host smart-a3a8d2c4-1d74-4be4-8d29-9005e7f48357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506261420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1506261420
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1984458354
Short name T216
Test name
Test status
Simulation time 12134390 ps
CPU time 0.57 seconds
Started Jul 19 04:56:38 PM PDT 24
Finished Jul 19 04:56:41 PM PDT 24
Peak memory 195172 kb
Host smart-5f8a352c-865c-4417-85b7-ebb254033283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984458354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1984458354
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3564532074
Short name T486
Test name
Test status
Simulation time 2956575032 ps
CPU time 40.29 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:57:24 PM PDT 24
Peak memory 200196 kb
Host smart-69b9fe36-65b6-40ca-b2d6-ff5c27cb8aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564532074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3564532074
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2120228167
Short name T207
Test name
Test status
Simulation time 515734938 ps
CPU time 9.36 seconds
Started Jul 19 04:56:38 PM PDT 24
Finished Jul 19 04:56:48 PM PDT 24
Peak memory 200136 kb
Host smart-54bff848-f0ef-4f74-a046-41e307f0e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120228167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2120228167
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.294366248
Short name T459
Test name
Test status
Simulation time 19907147408 ps
CPU time 1030.06 seconds
Started Jul 19 04:56:38 PM PDT 24
Finished Jul 19 05:13:50 PM PDT 24
Peak memory 726540 kb
Host smart-7bba58af-75b9-43e0-aff7-b198a7bf6392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294366248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.294366248
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3523718944
Short name T189
Test name
Test status
Simulation time 1866071105 ps
CPU time 103.2 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:58:27 PM PDT 24
Peak memory 200180 kb
Host smart-e0835058-af3c-4fe6-8815-98d166ccfcff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523718944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3523718944
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2190186183
Short name T422
Test name
Test status
Simulation time 12874220303 ps
CPU time 80.14 seconds
Started Jul 19 04:56:39 PM PDT 24
Finished Jul 19 04:58:02 PM PDT 24
Peak memory 200216 kb
Host smart-5874854d-5b72-40e7-b966-4c65a24a245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190186183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2190186183
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4291532220
Short name T224
Test name
Test status
Simulation time 390257543 ps
CPU time 7.05 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:56:51 PM PDT 24
Peak memory 200244 kb
Host smart-3c6621ca-a4c5-4347-b9d9-a2e5e1bfe7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291532220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4291532220
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1004078838
Short name T352
Test name
Test status
Simulation time 104743774813 ps
CPU time 1327.78 seconds
Started Jul 19 04:56:38 PM PDT 24
Finished Jul 19 05:18:48 PM PDT 24
Peak memory 725616 kb
Host smart-bb324fea-5830-434c-9860-7e2e2cd97a21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004078838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1004078838
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1604712597
Short name T26
Test name
Test status
Simulation time 5929605396 ps
CPU time 68.42 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:57:52 PM PDT 24
Peak memory 200308 kb
Host smart-240f1935-15c2-4823-a2c9-7ecccabd1a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604712597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1604712597
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3136353029
Short name T239
Test name
Test status
Simulation time 48646804 ps
CPU time 0.61 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:56:52 PM PDT 24
Peak memory 196184 kb
Host smart-f2e6f19a-80aa-4724-bf4e-2b38546c4659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136353029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3136353029
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1539221564
Short name T260
Test name
Test status
Simulation time 1881425261 ps
CPU time 55.95 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:57:39 PM PDT 24
Peak memory 200112 kb
Host smart-2f016f05-6440-4287-ae7f-e47c50cd04f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539221564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1539221564
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3895789174
Short name T438
Test name
Test status
Simulation time 17312692302 ps
CPU time 71.37 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:57:54 PM PDT 24
Peak memory 200312 kb
Host smart-f830d270-3da9-4bf0-b1f1-db6c2abac1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895789174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3895789174
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.4006734670
Short name T402
Test name
Test status
Simulation time 107286549 ps
CPU time 1.25 seconds
Started Jul 19 04:56:40 PM PDT 24
Finished Jul 19 04:56:44 PM PDT 24
Peak memory 212212 kb
Host smart-f2e22d3f-d6ec-4736-98ec-fa0114b0e406
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006734670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.4006734670
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1424427894
Short name T171
Test name
Test status
Simulation time 8652400606 ps
CPU time 50.01 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 04:57:42 PM PDT 24
Peak memory 200168 kb
Host smart-801c2210-8ded-43b9-b541-eec63040f079
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424427894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1424427894
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.352164709
Short name T191
Test name
Test status
Simulation time 5026395884 ps
CPU time 68.67 seconds
Started Jul 19 04:56:39 PM PDT 24
Finished Jul 19 04:57:51 PM PDT 24
Peak memory 216560 kb
Host smart-448b69e6-ffd1-4de4-a73c-4750ae0a9986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352164709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.352164709
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1539046868
Short name T38
Test name
Test status
Simulation time 316800548 ps
CPU time 16.52 seconds
Started Jul 19 04:56:41 PM PDT 24
Finished Jul 19 04:57:00 PM PDT 24
Peak memory 200252 kb
Host smart-e9ce1d7b-2052-4be6-96b9-9517a95f284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539046868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1539046868
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.381518143
Short name T71
Test name
Test status
Simulation time 96198357204 ps
CPU time 3344.24 seconds
Started Jul 19 04:56:47 PM PDT 24
Finished Jul 19 05:52:32 PM PDT 24
Peak memory 840664 kb
Host smart-db962c39-3325-4775-af13-4b4f605b29df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381518143 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.381518143
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2813128355
Short name T84
Test name
Test status
Simulation time 2256607065 ps
CPU time 58.02 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:57:48 PM PDT 24
Peak memory 200312 kb
Host smart-b09d9bca-a188-405f-a99f-9e2f83bd936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813128355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2813128355
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1334893751
Short name T337
Test name
Test status
Simulation time 15291705 ps
CPU time 0.61 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:56:51 PM PDT 24
Peak memory 196152 kb
Host smart-3697039e-750a-4437-9f2c-cdba1069ad92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334893751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1334893751
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2142151742
Short name T222
Test name
Test status
Simulation time 225330011 ps
CPU time 6.26 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 04:56:58 PM PDT 24
Peak memory 200212 kb
Host smart-a53a0721-6880-4507-8726-d0139bab9184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142151742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2142151742
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1882722165
Short name T432
Test name
Test status
Simulation time 1203093882 ps
CPU time 67.73 seconds
Started Jul 19 04:56:51 PM PDT 24
Finished Jul 19 04:58:00 PM PDT 24
Peak memory 200248 kb
Host smart-24741c7b-6410-4595-bdb2-52e443db3c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882722165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1882722165
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4217176618
Short name T270
Test name
Test status
Simulation time 6047616231 ps
CPU time 608.52 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 05:07:00 PM PDT 24
Peak memory 732948 kb
Host smart-c87c77f6-c031-4914-8d42-8b9abb60e78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217176618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4217176618
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2167396964
Short name T508
Test name
Test status
Simulation time 33654211749 ps
CPU time 126.43 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 200276 kb
Host smart-01a0779c-1078-41bd-bb7c-1a3f76ec9734
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167396964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2167396964
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.268414456
Short name T373
Test name
Test status
Simulation time 12157614844 ps
CPU time 48.97 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 04:57:41 PM PDT 24
Peak memory 200284 kb
Host smart-4a691f4f-6255-4cb8-9f7c-66193dd3005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268414456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.268414456
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2783514776
Short name T487
Test name
Test status
Simulation time 314223281 ps
CPU time 1.74 seconds
Started Jul 19 04:56:51 PM PDT 24
Finished Jul 19 04:56:54 PM PDT 24
Peak memory 200260 kb
Host smart-9cc264d6-79e4-438c-896e-94cbaa19699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783514776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2783514776
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.374518995
Short name T45
Test name
Test status
Simulation time 39327097448 ps
CPU time 2241.85 seconds
Started Jul 19 04:56:48 PM PDT 24
Finished Jul 19 05:34:11 PM PDT 24
Peak memory 781288 kb
Host smart-9c9e704a-4b55-4e07-887c-87798011db99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374518995 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.374518995
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.405879644
Short name T282
Test name
Test status
Simulation time 9641443737 ps
CPU time 129.01 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 04:59:00 PM PDT 24
Peak memory 200168 kb
Host smart-cdb6a739-1888-4cec-909d-7570f813b2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405879644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.405879644
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4286496644
Short name T255
Test name
Test status
Simulation time 92269205 ps
CPU time 0.58 seconds
Started Jul 19 04:56:51 PM PDT 24
Finished Jul 19 04:56:53 PM PDT 24
Peak memory 195856 kb
Host smart-2d473a57-ebdc-408a-b6f9-2d8258013c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286496644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4286496644
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1288568341
Short name T211
Test name
Test status
Simulation time 2781939808 ps
CPU time 81.77 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:58:13 PM PDT 24
Peak memory 200300 kb
Host smart-7461d914-391e-41d7-ba90-3875c453907c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288568341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1288568341
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1532115508
Short name T217
Test name
Test status
Simulation time 5546614323 ps
CPU time 78.81 seconds
Started Jul 19 04:56:48 PM PDT 24
Finished Jul 19 04:58:08 PM PDT 24
Peak memory 200356 kb
Host smart-8621f96c-789f-4b9b-bda8-f8e0ed9cad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532115508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1532115508
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.915039974
Short name T386
Test name
Test status
Simulation time 11625701521 ps
CPU time 439.98 seconds
Started Jul 19 04:56:47 PM PDT 24
Finished Jul 19 05:04:08 PM PDT 24
Peak memory 625692 kb
Host smart-639e918e-4be4-46d7-b255-6e71ecdb3c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915039974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.915039974
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3768229489
Short name T219
Test name
Test status
Simulation time 11257872820 ps
CPU time 200.37 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 05:00:10 PM PDT 24
Peak memory 200288 kb
Host smart-7463fc4d-7713-4df2-9cab-f649fba63620
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768229489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3768229489
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.146089744
Short name T277
Test name
Test status
Simulation time 503594041 ps
CPU time 29.18 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:57:20 PM PDT 24
Peak memory 200240 kb
Host smart-672e3240-70e9-44f0-a1fa-e99d48c15d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146089744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.146089744
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1862415240
Short name T506
Test name
Test status
Simulation time 2970987054 ps
CPU time 12.55 seconds
Started Jul 19 04:56:47 PM PDT 24
Finished Jul 19 04:57:00 PM PDT 24
Peak memory 200356 kb
Host smart-f662219d-f2f9-431b-a5eb-70b701c28c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862415240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1862415240
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1702263823
Short name T202
Test name
Test status
Simulation time 781645215156 ps
CPU time 3179.33 seconds
Started Jul 19 04:56:51 PM PDT 24
Finished Jul 19 05:49:52 PM PDT 24
Peak memory 839072 kb
Host smart-7d2c2397-af7f-482c-a405-33f88ce91a75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702263823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1702263823
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1939436639
Short name T34
Test name
Test status
Simulation time 1304154833 ps
CPU time 61.09 seconds
Started Jul 19 04:56:48 PM PDT 24
Finished Jul 19 04:57:50 PM PDT 24
Peak memory 200248 kb
Host smart-824023e0-381f-4923-a553-93ea9ebe3078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939436639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1939436639
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3401563481
Short name T499
Test name
Test status
Simulation time 52249783 ps
CPU time 0.59 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 04:55:46 PM PDT 24
Peak memory 196092 kb
Host smart-1f7e9dc1-cecd-41e4-9581-7ac2b799d4bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401563481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3401563481
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4049595780
Short name T18
Test name
Test status
Simulation time 1300006162 ps
CPU time 18.68 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:55:54 PM PDT 24
Peak memory 200272 kb
Host smart-cd757725-c892-444d-8d52-a000f04b746a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049595780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4049595780
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1445898793
Short name T478
Test name
Test status
Simulation time 2879341231 ps
CPU time 38.5 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 04:56:12 PM PDT 24
Peak memory 208524 kb
Host smart-8c78d67b-c0de-48c2-a03e-f005c1a0dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445898793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1445898793
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2247918580
Short name T300
Test name
Test status
Simulation time 905565852 ps
CPU time 145.7 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 04:58:02 PM PDT 24
Peak memory 571828 kb
Host smart-1b26ce11-2af8-4569-8fd8-24bf4c161eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247918580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2247918580
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3170000602
Short name T43
Test name
Test status
Simulation time 1666197172 ps
CPU time 77.75 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 04:56:55 PM PDT 24
Peak memory 200168 kb
Host smart-81c3c22a-d34e-4cae-8b4f-f1e9b6ba2387
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170000602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3170000602
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1452160529
Short name T80
Test name
Test status
Simulation time 31878449412 ps
CPU time 160.68 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 04:58:16 PM PDT 24
Peak memory 200336 kb
Host smart-ea5210b7-7770-4b65-9873-182c9bb9bd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452160529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1452160529
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1881766825
Short name T50
Test name
Test status
Simulation time 90584255 ps
CPU time 1 seconds
Started Jul 19 04:55:38 PM PDT 24
Finished Jul 19 04:55:40 PM PDT 24
Peak memory 219736 kb
Host smart-bd10fd3c-3f99-46ed-b51c-c37d9f7e16bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881766825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1881766825
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.61215156
Short name T358
Test name
Test status
Simulation time 1055803754 ps
CPU time 12.59 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 04:55:49 PM PDT 24
Peak memory 200260 kb
Host smart-b5214d57-c83c-4ccc-85e5-3b9b94eb3e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61215156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.61215156
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.31141551
Short name T488
Test name
Test status
Simulation time 89629468591 ps
CPU time 2459.91 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 05:36:42 PM PDT 24
Peak memory 773888 kb
Host smart-0f6b52f7-69f7-47cb-9598-3c10e5409694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31141551 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.31141551
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1263065134
Short name T13
Test name
Test status
Simulation time 160795813647 ps
CPU time 603.75 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 05:05:46 PM PDT 24
Peak memory 216012 kb
Host smart-edc0ffe3-75b3-4713-b568-fb9ef4079da6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263065134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1263065134
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2302557856
Short name T305
Test name
Test status
Simulation time 4425839841 ps
CPU time 37.06 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 04:56:23 PM PDT 24
Peak memory 200288 kb
Host smart-ead73bec-2c0e-44ed-bf17-c4949601dc87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2302557856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2302557856
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.4285440788
Short name T420
Test name
Test status
Simulation time 35830679339 ps
CPU time 102.28 seconds
Started Jul 19 04:55:43 PM PDT 24
Finished Jul 19 04:57:27 PM PDT 24
Peak memory 200312 kb
Host smart-58593090-7b61-49b9-b78a-5ca791a6dd2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4285440788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4285440788
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1024780871
Short name T503
Test name
Test status
Simulation time 4842165326 ps
CPU time 76.71 seconds
Started Jul 19 04:55:43 PM PDT 24
Finished Jul 19 04:57:01 PM PDT 24
Peak memory 200448 kb
Host smart-eb83934c-9579-47d6-881c-836c0de4f4b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1024780871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1024780871
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.269161413
Short name T251
Test name
Test status
Simulation time 71781555526 ps
CPU time 598.58 seconds
Started Jul 19 04:55:32 PM PDT 24
Finished Jul 19 05:05:33 PM PDT 24
Peak memory 200216 kb
Host smart-f02bbf27-f236-420b-b47e-645797f4848b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=269161413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.269161413
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1573316400
Short name T148
Test name
Test status
Simulation time 522208996160 ps
CPU time 2214.63 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 05:32:28 PM PDT 24
Peak memory 216732 kb
Host smart-c8e0da6d-97c0-4d72-a24b-973e85b3fa03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1573316400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1573316400
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.4099846379
Short name T235
Test name
Test status
Simulation time 558832449603 ps
CPU time 2826.12 seconds
Started Jul 19 04:55:31 PM PDT 24
Finished Jul 19 05:42:39 PM PDT 24
Peak memory 216476 kb
Host smart-074066b0-da12-4806-bb46-312ff402ca24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4099846379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4099846379
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3821756282
Short name T27
Test name
Test status
Simulation time 741118814 ps
CPU time 14.73 seconds
Started Jul 19 04:55:33 PM PDT 24
Finished Jul 19 04:55:51 PM PDT 24
Peak memory 200040 kb
Host smart-3a7e4b09-cddc-48f9-9fd8-a3f0c379a8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821756282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3821756282
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3794497518
Short name T304
Test name
Test status
Simulation time 13079212 ps
CPU time 0.61 seconds
Started Jul 19 04:56:57 PM PDT 24
Finished Jul 19 04:56:59 PM PDT 24
Peak memory 196208 kb
Host smart-3e1a8cf9-ff42-43ba-9735-94329294b87d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794497518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3794497518
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2325795869
Short name T136
Test name
Test status
Simulation time 4600074995 ps
CPU time 75.57 seconds
Started Jul 19 04:56:49 PM PDT 24
Finished Jul 19 04:58:06 PM PDT 24
Peak memory 216628 kb
Host smart-1b32446b-01ac-43ce-a663-6363b811e5c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325795869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2325795869
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.637809008
Short name T291
Test name
Test status
Simulation time 13498393478 ps
CPU time 59.47 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 04:57:57 PM PDT 24
Peak memory 200232 kb
Host smart-bc4c5d30-be73-4cd5-b32c-e15f7f4b377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637809008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.637809008
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2975511879
Short name T350
Test name
Test status
Simulation time 7947571737 ps
CPU time 1747.94 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 05:26:00 PM PDT 24
Peak memory 779212 kb
Host smart-a76c6e26-0468-4934-9946-f07844943922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975511879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2975511879
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1311229072
Short name T214
Test name
Test status
Simulation time 14139351135 ps
CPU time 143.83 seconds
Started Jul 19 04:56:59 PM PDT 24
Finished Jul 19 04:59:24 PM PDT 24
Peak memory 200140 kb
Host smart-1c0856a5-3302-4bde-bd56-2932f16ba5f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311229072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1311229072
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2069032900
Short name T388
Test name
Test status
Simulation time 2193684711 ps
CPU time 33.14 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 04:57:25 PM PDT 24
Peak memory 200252 kb
Host smart-d393e6d0-13d2-4c0b-a18c-8a978bd994ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069032900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2069032900
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1724084746
Short name T150
Test name
Test status
Simulation time 635597154 ps
CPU time 7.69 seconds
Started Jul 19 04:56:50 PM PDT 24
Finished Jul 19 04:57:00 PM PDT 24
Peak memory 200248 kb
Host smart-b2683fdc-c5b4-431d-8cbe-57c9f2f62eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724084746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1724084746
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3158007960
Short name T454
Test name
Test status
Simulation time 29167039955 ps
CPU time 3325.6 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 05:52:22 PM PDT 24
Peak memory 833272 kb
Host smart-77a6dd9f-3a87-4c80-a089-ca08b03db7bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158007960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3158007960
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3582377040
Short name T327
Test name
Test status
Simulation time 1413605758 ps
CPU time 86.22 seconds
Started Jul 19 04:56:55 PM PDT 24
Finished Jul 19 04:58:22 PM PDT 24
Peak memory 200252 kb
Host smart-903ad888-d1cf-4c45-a7f3-3f77a518712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582377040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3582377040
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2989581822
Short name T426
Test name
Test status
Simulation time 54958779 ps
CPU time 0.6 seconds
Started Jul 19 04:56:59 PM PDT 24
Finished Jul 19 04:57:00 PM PDT 24
Peak memory 196148 kb
Host smart-39dd7363-5697-4a66-b2c7-2419eeddcd09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989581822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2989581822
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3597780640
Short name T309
Test name
Test status
Simulation time 3086879574 ps
CPU time 101.7 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 04:58:39 PM PDT 24
Peak memory 200372 kb
Host smart-33dd7dbb-74fb-4559-af99-0e3e34b358d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597780640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3597780640
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4095503296
Short name T188
Test name
Test status
Simulation time 3505710391 ps
CPU time 44.91 seconds
Started Jul 19 04:56:58 PM PDT 24
Finished Jul 19 04:57:44 PM PDT 24
Peak memory 200200 kb
Host smart-6db68a19-edcd-4fe3-90b5-2a0f247ec0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095503296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4095503296
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1300995740
Short name T78
Test name
Test status
Simulation time 1844210024 ps
CPU time 18.26 seconds
Started Jul 19 04:56:59 PM PDT 24
Finished Jul 19 04:57:18 PM PDT 24
Peak memory 230044 kb
Host smart-6cbf8e7e-c0e7-486e-81ef-3c8f4ce62aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300995740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1300995740
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3865472127
Short name T495
Test name
Test status
Simulation time 4707393047 ps
CPU time 22.49 seconds
Started Jul 19 04:56:57 PM PDT 24
Finished Jul 19 04:57:20 PM PDT 24
Peak memory 200308 kb
Host smart-dcd0409a-c43c-4a80-8b43-c2260febbefd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865472127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3865472127
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4219399518
Short name T351
Test name
Test status
Simulation time 8368626633 ps
CPU time 26.99 seconds
Started Jul 19 04:56:57 PM PDT 24
Finished Jul 19 04:57:25 PM PDT 24
Peak memory 200276 kb
Host smart-5a29a80a-5f1c-4f65-b857-9518d5c4e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219399518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4219399518
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2492964138
Short name T161
Test name
Test status
Simulation time 856168005 ps
CPU time 4.22 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 04:57:02 PM PDT 24
Peak memory 200296 kb
Host smart-996158ab-b64b-490a-9a1f-1a957fc61108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492964138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2492964138
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4097064063
Short name T177
Test name
Test status
Simulation time 18921191850 ps
CPU time 192.45 seconds
Started Jul 19 04:56:57 PM PDT 24
Finished Jul 19 05:00:11 PM PDT 24
Peak memory 200300 kb
Host smart-0dbcedcc-ad19-44b1-96fb-e3b449b7228b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097064063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4097064063
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4293411632
Short name T192
Test name
Test status
Simulation time 22777246582 ps
CPU time 105.47 seconds
Started Jul 19 04:56:57 PM PDT 24
Finished Jul 19 04:58:44 PM PDT 24
Peak memory 200300 kb
Host smart-2626c1aa-957a-4bb7-87be-538cea7c099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293411632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4293411632
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1306222923
Short name T395
Test name
Test status
Simulation time 138444948 ps
CPU time 0.6 seconds
Started Jul 19 04:57:07 PM PDT 24
Finished Jul 19 04:57:08 PM PDT 24
Peak memory 196244 kb
Host smart-4fac9c5f-30af-4a0c-a1f7-17f6ec0c15a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306222923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1306222923
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.444826572
Short name T164
Test name
Test status
Simulation time 18040076470 ps
CPU time 100.33 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 04:58:38 PM PDT 24
Peak memory 216484 kb
Host smart-c3878c2b-1e4e-478b-9bb8-e116279c9c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444826572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.444826572
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2928938291
Short name T137
Test name
Test status
Simulation time 15052818879 ps
CPU time 50.82 seconds
Started Jul 19 04:56:58 PM PDT 24
Finished Jul 19 04:57:50 PM PDT 24
Peak memory 208460 kb
Host smart-54a9e4e3-5d86-4cc2-86d4-75781f6c3ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928938291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2928938291
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2613631936
Short name T483
Test name
Test status
Simulation time 3262626295 ps
CPU time 625.42 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 05:07:23 PM PDT 24
Peak memory 714832 kb
Host smart-2d2e6bd3-9017-4f8f-8c82-60eb0fd20825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613631936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2613631936
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1641620983
Short name T529
Test name
Test status
Simulation time 1068334023 ps
CPU time 58.73 seconds
Started Jul 19 04:56:56 PM PDT 24
Finished Jul 19 04:57:55 PM PDT 24
Peak memory 200296 kb
Host smart-dd9d5a7b-1ec2-44e1-88bc-cce3fc53ea22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641620983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1641620983
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2801091693
Short name T317
Test name
Test status
Simulation time 882331970 ps
CPU time 48.64 seconds
Started Jul 19 04:56:58 PM PDT 24
Finished Jul 19 04:57:47 PM PDT 24
Peak memory 200132 kb
Host smart-77ef1314-852f-42d3-b2de-496b95eb08c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801091693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2801091693
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3303852494
Short name T443
Test name
Test status
Simulation time 209316440 ps
CPU time 2.56 seconds
Started Jul 19 04:56:59 PM PDT 24
Finished Jul 19 04:57:03 PM PDT 24
Peak memory 200188 kb
Host smart-19ba2f4b-eb57-42a7-9159-c3a710a43736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303852494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3303852494
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.4118300881
Short name T446
Test name
Test status
Simulation time 422785272 ps
CPU time 2.87 seconds
Started Jul 19 04:56:58 PM PDT 24
Finished Jul 19 04:57:02 PM PDT 24
Peak memory 200088 kb
Host smart-2f2805fc-5e78-4ac5-84f3-58323954fa6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118300881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4118300881
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.694662725
Short name T526
Test name
Test status
Simulation time 4635772058 ps
CPU time 84.9 seconds
Started Jul 19 04:56:59 PM PDT 24
Finished Jul 19 04:58:25 PM PDT 24
Peak memory 200196 kb
Host smart-339c2292-cc97-49d8-ac3a-bf9044e8bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694662725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.694662725
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.540792467
Short name T437
Test name
Test status
Simulation time 36376192 ps
CPU time 0.62 seconds
Started Jul 19 04:57:13 PM PDT 24
Finished Jul 19 04:57:15 PM PDT 24
Peak memory 196152 kb
Host smart-daa14e7b-c964-4f80-b23b-ef1ef82ad510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540792467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.540792467
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1487633111
Short name T206
Test name
Test status
Simulation time 841135875 ps
CPU time 52.03 seconds
Started Jul 19 04:57:06 PM PDT 24
Finished Jul 19 04:57:59 PM PDT 24
Peak memory 200192 kb
Host smart-abaf052b-a537-411c-b440-1434d085a7b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487633111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1487633111
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3116796970
Short name T59
Test name
Test status
Simulation time 450733362 ps
CPU time 5.73 seconds
Started Jul 19 04:57:07 PM PDT 24
Finished Jul 19 04:57:14 PM PDT 24
Peak memory 200240 kb
Host smart-68114af4-3bc3-4e8f-a8a1-ecfae89edf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116796970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3116796970
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2435453045
Short name T153
Test name
Test status
Simulation time 3573678427 ps
CPU time 611.76 seconds
Started Jul 19 04:57:04 PM PDT 24
Finished Jul 19 05:07:17 PM PDT 24
Peak memory 676796 kb
Host smart-921da1a4-3637-4571-87d7-93e017b82a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435453045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2435453045
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3272431363
Short name T410
Test name
Test status
Simulation time 438632931 ps
CPU time 6.06 seconds
Started Jul 19 04:57:02 PM PDT 24
Finished Jul 19 04:57:08 PM PDT 24
Peak memory 200140 kb
Host smart-3db90dda-aaf7-4678-8f2d-bf67150fbbdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272431363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3272431363
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3288314141
Short name T144
Test name
Test status
Simulation time 17208550721 ps
CPU time 244.48 seconds
Started Jul 19 04:57:07 PM PDT 24
Finished Jul 19 05:01:12 PM PDT 24
Peak memory 216484 kb
Host smart-c2c09982-4f47-493e-9561-3c8c78749d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288314141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3288314141
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.367163035
Short name T227
Test name
Test status
Simulation time 43218853 ps
CPU time 2 seconds
Started Jul 19 04:57:05 PM PDT 24
Finished Jul 19 04:57:08 PM PDT 24
Peak memory 200240 kb
Host smart-edcff954-1cd7-4c2b-8498-233c9393b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367163035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.367163035
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.388639995
Short name T315
Test name
Test status
Simulation time 71983156411 ps
CPU time 618.02 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 05:07:31 PM PDT 24
Peak memory 200296 kb
Host smart-4cbf67fa-4a88-4110-ac70-23859f08a876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388639995 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.388639995
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3495786086
Short name T90
Test name
Test status
Simulation time 10629465232 ps
CPU time 143.86 seconds
Started Jul 19 04:57:05 PM PDT 24
Finished Jul 19 04:59:30 PM PDT 24
Peak memory 200220 kb
Host smart-23eb4d30-ecaf-4952-be68-1ca26edc77c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495786086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3495786086
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2611112995
Short name T471
Test name
Test status
Simulation time 13869743 ps
CPU time 0.57 seconds
Started Jul 19 04:57:16 PM PDT 24
Finished Jul 19 04:57:19 PM PDT 24
Peak memory 196204 kb
Host smart-33dc8c34-1bad-4b0d-82dc-08b446807a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611112995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2611112995
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1915105436
Short name T29
Test name
Test status
Simulation time 5349507781 ps
CPU time 93.88 seconds
Started Jul 19 04:57:11 PM PDT 24
Finished Jul 19 04:58:46 PM PDT 24
Peak memory 200232 kb
Host smart-ff4d1ac2-2e2c-4533-bbae-12a57998b150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915105436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1915105436
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2570826978
Short name T342
Test name
Test status
Simulation time 1279292433 ps
CPU time 9.09 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 04:57:22 PM PDT 24
Peak memory 200236 kb
Host smart-374797e5-15ec-4e72-a437-d53b811c92b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570826978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2570826978
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.247450357
Short name T348
Test name
Test status
Simulation time 1573327084 ps
CPU time 227.15 seconds
Started Jul 19 04:57:14 PM PDT 24
Finished Jul 19 05:01:03 PM PDT 24
Peak memory 486552 kb
Host smart-6f56fa36-212d-46b3-b279-7c054431c5c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247450357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.247450357
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3931348831
Short name T54
Test name
Test status
Simulation time 14105586426 ps
CPU time 220.15 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 05:00:53 PM PDT 24
Peak memory 200232 kb
Host smart-ce26dbe8-48e9-40ab-a425-2454a52bafe7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931348831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3931348831
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3904504392
Short name T345
Test name
Test status
Simulation time 1692162864 ps
CPU time 20.61 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 04:57:34 PM PDT 24
Peak memory 200292 kb
Host smart-6637185a-e579-48f0-8d90-fa2dfa715620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904504392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3904504392
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.315476856
Short name T498
Test name
Test status
Simulation time 1971595174 ps
CPU time 12.17 seconds
Started Jul 19 04:57:15 PM PDT 24
Finished Jul 19 04:57:31 PM PDT 24
Peak memory 200152 kb
Host smart-b4ca0a6b-b64a-49bb-99f1-e5b2e491a43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315476856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.315476856
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.637848931
Short name T74
Test name
Test status
Simulation time 24586284813 ps
CPU time 161.24 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 216704 kb
Host smart-3985381f-328c-4f38-b3d2-56a1ff9882c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637848931 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.637848931
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3486824886
Short name T113
Test name
Test status
Simulation time 22023208172 ps
CPU time 96.54 seconds
Started Jul 19 04:57:16 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 200328 kb
Host smart-cfe83c45-930d-4f69-b378-e00bc829fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486824886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3486824886
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2425622634
Short name T250
Test name
Test status
Simulation time 12933683 ps
CPU time 0.58 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 04:57:14 PM PDT 24
Peak memory 195848 kb
Host smart-3024f4d5-546d-468d-b34f-9268f68e7b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425622634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2425622634
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1922154914
Short name T509
Test name
Test status
Simulation time 589773408 ps
CPU time 32.3 seconds
Started Jul 19 04:57:17 PM PDT 24
Finished Jul 19 04:57:52 PM PDT 24
Peak memory 200188 kb
Host smart-f7f4851e-13f3-4648-93f2-d4cd2576285b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922154914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1922154914
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2808680315
Short name T367
Test name
Test status
Simulation time 20749214409 ps
CPU time 65.02 seconds
Started Jul 19 04:57:17 PM PDT 24
Finished Jul 19 04:58:25 PM PDT 24
Peak memory 200440 kb
Host smart-353fa789-1c93-4e7c-8825-ff849d01d996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808680315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2808680315
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3279870454
Short name T440
Test name
Test status
Simulation time 10605978631 ps
CPU time 1117.22 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 05:15:51 PM PDT 24
Peak memory 748596 kb
Host smart-41e1245b-b978-44a2-8cda-713e5e3c85c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279870454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3279870454
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2873744578
Short name T415
Test name
Test status
Simulation time 64007623863 ps
CPU time 225.56 seconds
Started Jul 19 04:57:15 PM PDT 24
Finished Jul 19 05:01:03 PM PDT 24
Peak memory 200288 kb
Host smart-b4725d2e-10b3-4eca-8313-901803ab2e4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873744578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2873744578
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1268542670
Short name T413
Test name
Test status
Simulation time 718306584 ps
CPU time 38.72 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 04:57:52 PM PDT 24
Peak memory 200212 kb
Host smart-3dd78974-5248-43eb-9b77-eca1f8861ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268542670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1268542670
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.343985306
Short name T272
Test name
Test status
Simulation time 776575411 ps
CPU time 8.22 seconds
Started Jul 19 04:57:15 PM PDT 24
Finished Jul 19 04:57:26 PM PDT 24
Peak memory 200192 kb
Host smart-124a5ad3-dcaf-4a00-9e94-960691494e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343985306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.343985306
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4216772153
Short name T278
Test name
Test status
Simulation time 111276208430 ps
CPU time 1643.8 seconds
Started Jul 19 04:57:12 PM PDT 24
Finished Jul 19 05:24:38 PM PDT 24
Peak memory 687480 kb
Host smart-46820e93-760d-41ae-a59a-f9d33e67ce3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216772153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4216772153
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2721174092
Short name T114
Test name
Test status
Simulation time 10568072641 ps
CPU time 123.04 seconds
Started Jul 19 04:57:14 PM PDT 24
Finished Jul 19 04:59:20 PM PDT 24
Peak memory 200312 kb
Host smart-8d97983d-0371-4092-9848-54b216ceeda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721174092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2721174092
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3332101611
Short name T366
Test name
Test status
Simulation time 33291920 ps
CPU time 0.6 seconds
Started Jul 19 04:57:26 PM PDT 24
Finished Jul 19 04:57:36 PM PDT 24
Peak memory 196816 kb
Host smart-3deadb0e-5fe3-4650-a968-780d8f167d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332101611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3332101611
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1832485970
Short name T285
Test name
Test status
Simulation time 172776665 ps
CPU time 9.94 seconds
Started Jul 19 04:57:16 PM PDT 24
Finished Jul 19 04:57:29 PM PDT 24
Peak memory 200248 kb
Host smart-13a9445f-d66c-4e8c-bb14-52fa7827b542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832485970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1832485970
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1612316435
Short name T25
Test name
Test status
Simulation time 106331072 ps
CPU time 6.39 seconds
Started Jul 19 04:57:22 PM PDT 24
Finished Jul 19 04:57:36 PM PDT 24
Peak memory 200232 kb
Host smart-70176256-7691-439c-bfce-71cbdc737a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612316435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1612316435
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1459646474
Short name T134
Test name
Test status
Simulation time 11569705685 ps
CPU time 466.96 seconds
Started Jul 19 04:57:13 PM PDT 24
Finished Jul 19 05:05:02 PM PDT 24
Peak memory 697132 kb
Host smart-11ebd7c7-e0b5-49bb-9750-d40d3f0da2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459646474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1459646474
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2968186660
Short name T512
Test name
Test status
Simulation time 2558056666 ps
CPU time 151.02 seconds
Started Jul 19 04:57:24 PM PDT 24
Finished Jul 19 05:00:04 PM PDT 24
Peak memory 200288 kb
Host smart-06f08b96-ac94-4bca-ad55-abac6284051d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968186660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2968186660
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.473672139
Short name T479
Test name
Test status
Simulation time 6254325455 ps
CPU time 176.9 seconds
Started Jul 19 04:57:13 PM PDT 24
Finished Jul 19 05:00:12 PM PDT 24
Peak memory 200228 kb
Host smart-1cd65299-f8e3-4e9d-875c-adc2c9884c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473672139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.473672139
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.4146417307
Short name T484
Test name
Test status
Simulation time 3762968024 ps
CPU time 15.33 seconds
Started Jul 19 04:57:14 PM PDT 24
Finished Jul 19 04:57:31 PM PDT 24
Peak memory 208540 kb
Host smart-e1f35e91-7587-4882-a5e7-aae423ca7b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146417307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4146417307
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3287165458
Short name T389
Test name
Test status
Simulation time 312378496827 ps
CPU time 2308 seconds
Started Jul 19 04:57:23 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 770024 kb
Host smart-d5a9314e-a10e-4d51-bdb5-c62f51650711
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287165458 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3287165458
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3884811773
Short name T213
Test name
Test status
Simulation time 17672697224 ps
CPU time 111.2 seconds
Started Jul 19 04:57:23 PM PDT 24
Finished Jul 19 04:59:22 PM PDT 24
Peak memory 200312 kb
Host smart-0b5cdc2d-46ef-42b7-a8b5-5b0cc42967f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884811773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3884811773
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3490200573
Short name T151
Test name
Test status
Simulation time 11351389 ps
CPU time 0.57 seconds
Started Jul 19 04:57:24 PM PDT 24
Finished Jul 19 04:57:33 PM PDT 24
Peak memory 196196 kb
Host smart-27966d32-f744-40dd-8a88-85b63fdac134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490200573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3490200573
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3994423518
Short name T31
Test name
Test status
Simulation time 901607496 ps
CPU time 13.77 seconds
Started Jul 19 04:57:21 PM PDT 24
Finished Jul 19 04:57:43 PM PDT 24
Peak memory 200204 kb
Host smart-7ad565ee-c12f-43c8-8ab3-ea0e98745d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994423518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3994423518
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4265513676
Short name T135
Test name
Test status
Simulation time 22015333082 ps
CPU time 73.84 seconds
Started Jul 19 04:57:22 PM PDT 24
Finished Jul 19 04:58:44 PM PDT 24
Peak memory 200276 kb
Host smart-006b3b81-261c-44e9-b787-508dcca67f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265513676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4265513676
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2915284284
Short name T159
Test name
Test status
Simulation time 16612081228 ps
CPU time 1856.9 seconds
Started Jul 19 04:57:24 PM PDT 24
Finished Jul 19 05:28:30 PM PDT 24
Peak memory 745332 kb
Host smart-e7929b15-5ec7-4108-838d-1b035e9726ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915284284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2915284284
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3850242117
Short name T152
Test name
Test status
Simulation time 5492617393 ps
CPU time 81.03 seconds
Started Jul 19 04:57:23 PM PDT 24
Finished Jul 19 04:58:52 PM PDT 24
Peak memory 200224 kb
Host smart-ddd9b755-553a-41eb-9015-04acaf2fd362
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850242117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3850242117
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1188692622
Short name T470
Test name
Test status
Simulation time 548269161 ps
CPU time 9.89 seconds
Started Jul 19 04:57:23 PM PDT 24
Finished Jul 19 04:57:42 PM PDT 24
Peak memory 200256 kb
Host smart-89d3262e-d166-4477-88c5-45f60273b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188692622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1188692622
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.884342637
Short name T456
Test name
Test status
Simulation time 523977361 ps
CPU time 2.6 seconds
Started Jul 19 04:57:22 PM PDT 24
Finished Jul 19 04:57:33 PM PDT 24
Peak memory 200240 kb
Host smart-b7b98e44-0e71-4767-8f6d-43c0a194eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884342637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.884342637
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4027903017
Short name T464
Test name
Test status
Simulation time 13858030372 ps
CPU time 296.96 seconds
Started Jul 19 04:57:23 PM PDT 24
Finished Jul 19 05:02:30 PM PDT 24
Peak memory 315272 kb
Host smart-598961ec-ea31-4868-86d6-f2d4a07f3c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027903017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4027903017
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2356725291
Short name T223
Test name
Test status
Simulation time 32159103245 ps
CPU time 98.66 seconds
Started Jul 19 04:57:23 PM PDT 24
Finished Jul 19 04:59:10 PM PDT 24
Peak memory 200192 kb
Host smart-812f29a3-3974-499c-b87e-5b3c8450f119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356725291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2356725291
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.754456188
Short name T421
Test name
Test status
Simulation time 15713582 ps
CPU time 0.61 seconds
Started Jul 19 04:57:28 PM PDT 24
Finished Jul 19 04:57:37 PM PDT 24
Peak memory 196880 kb
Host smart-2d706c6d-e421-4857-aaa2-7e94709f7189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754456188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.754456188
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1251057695
Short name T502
Test name
Test status
Simulation time 545388884 ps
CPU time 8.62 seconds
Started Jul 19 04:57:24 PM PDT 24
Finished Jul 19 04:57:41 PM PDT 24
Peak memory 200232 kb
Host smart-14e84efb-4eb5-4811-902b-48f554c147ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251057695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1251057695
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.598485911
Short name T252
Test name
Test status
Simulation time 9161580758 ps
CPU time 41.14 seconds
Started Jul 19 04:57:29 PM PDT 24
Finished Jul 19 04:58:18 PM PDT 24
Peak memory 216660 kb
Host smart-dc2a0ee6-801b-4dcb-8341-8ac156394810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598485911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.598485911
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1028540098
Short name T297
Test name
Test status
Simulation time 29462013017 ps
CPU time 1487.74 seconds
Started Jul 19 04:57:28 PM PDT 24
Finished Jul 19 05:22:24 PM PDT 24
Peak memory 781224 kb
Host smart-5bbd64ed-b5b7-4f4c-ac99-e3901a24af92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028540098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1028540098
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.642643588
Short name T409
Test name
Test status
Simulation time 592942880 ps
CPU time 33.56 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 04:58:12 PM PDT 24
Peak memory 200124 kb
Host smart-cd12f3d9-da1a-46e1-8535-f4b5af615168
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642643588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.642643588
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2664580128
Short name T452
Test name
Test status
Simulation time 35585182652 ps
CPU time 115.35 seconds
Started Jul 19 04:57:26 PM PDT 24
Finished Jul 19 04:59:30 PM PDT 24
Peak memory 208508 kb
Host smart-36a0e638-b974-4f61-81bc-153e5009550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664580128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2664580128
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3119073014
Short name T185
Test name
Test status
Simulation time 3106152145 ps
CPU time 6.33 seconds
Started Jul 19 04:57:22 PM PDT 24
Finished Jul 19 04:57:36 PM PDT 24
Peak memory 200308 kb
Host smart-05d20dca-6a86-46c0-81bd-f3076b37caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119073014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3119073014
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3032252397
Short name T519
Test name
Test status
Simulation time 91053456358 ps
CPU time 1390.55 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 05:20:49 PM PDT 24
Peak memory 664056 kb
Host smart-2f2a68f5-8eaf-41ec-9b13-e24bb5a45eef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032252397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3032252397
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1368800539
Short name T168
Test name
Test status
Simulation time 14710782143 ps
CPU time 57.5 seconds
Started Jul 19 04:57:29 PM PDT 24
Finished Jul 19 04:58:34 PM PDT 24
Peak memory 200324 kb
Host smart-3dbb8ecc-d424-4ac5-909b-7d2bbca9fdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368800539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1368800539
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2939827168
Short name T518
Test name
Test status
Simulation time 13795916 ps
CPU time 0.61 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 04:57:39 PM PDT 24
Peak memory 196168 kb
Host smart-26b9b1f7-481c-40f1-ab01-e06243da9447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939827168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2939827168
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.774457321
Short name T132
Test name
Test status
Simulation time 1269312473 ps
CPU time 73.49 seconds
Started Jul 19 04:57:30 PM PDT 24
Finished Jul 19 04:58:51 PM PDT 24
Peak memory 200316 kb
Host smart-4b62d6ec-8bf8-4aab-8b2b-d67a5064b015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774457321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.774457321
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2236748499
Short name T458
Test name
Test status
Simulation time 5899910230 ps
CPU time 32.29 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 04:58:11 PM PDT 24
Peak memory 200272 kb
Host smart-9b110199-b07b-4f93-8a36-ff105b7d2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236748499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2236748499
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3166165773
Short name T328
Test name
Test status
Simulation time 4530824116 ps
CPU time 860.83 seconds
Started Jul 19 04:57:30 PM PDT 24
Finished Jul 19 05:11:59 PM PDT 24
Peak memory 771168 kb
Host smart-7aa5bf50-ae48-43c7-8929-c9833ab123e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166165773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3166165773
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3563719418
Short name T290
Test name
Test status
Simulation time 34125950296 ps
CPU time 131.63 seconds
Started Jul 19 04:57:29 PM PDT 24
Finished Jul 19 04:59:48 PM PDT 24
Peak memory 200292 kb
Host smart-2e53ca01-ce38-49f3-80c5-ccba85438704
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563719418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3563719418
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1955638241
Short name T254
Test name
Test status
Simulation time 2566971193 ps
CPU time 33.83 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 04:58:12 PM PDT 24
Peak memory 200268 kb
Host smart-755db599-3cd4-40e6-a009-f0dec1d8c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955638241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1955638241
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1396000324
Short name T435
Test name
Test status
Simulation time 8946038494 ps
CPU time 8.2 seconds
Started Jul 19 04:57:30 PM PDT 24
Finished Jul 19 04:57:46 PM PDT 24
Peak memory 200380 kb
Host smart-9e243cde-6e2d-4b6e-9b83-42dd379d0857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396000324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1396000324
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.474872292
Short name T501
Test name
Test status
Simulation time 407939478668 ps
CPU time 798.42 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 05:10:57 PM PDT 24
Peak memory 200240 kb
Host smart-ec82ec1a-8cd0-4e82-b915-70a60ac98220
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474872292 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.474872292
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3463026989
Short name T147
Test name
Test status
Simulation time 10438864475 ps
CPU time 94.06 seconds
Started Jul 19 04:57:31 PM PDT 24
Finished Jul 19 04:59:12 PM PDT 24
Peak memory 200268 kb
Host smart-c74cd8ac-2fec-4d41-ba23-025af52d59d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463026989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3463026989
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.728982799
Short name T236
Test name
Test status
Simulation time 20341697 ps
CPU time 0.67 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 04:55:41 PM PDT 24
Peak memory 196868 kb
Host smart-3c914cec-fab0-4c51-b021-9b054d2247dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728982799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.728982799
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3063266695
Short name T403
Test name
Test status
Simulation time 2243073530 ps
CPU time 70.27 seconds
Started Jul 19 04:55:45 PM PDT 24
Finished Jul 19 04:56:57 PM PDT 24
Peak memory 200364 kb
Host smart-24bfaaec-3614-4214-9f58-beea6f45a5ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063266695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3063266695
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3158344213
Short name T335
Test name
Test status
Simulation time 1053724087 ps
CPU time 52.92 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:56:36 PM PDT 24
Peak memory 200120 kb
Host smart-589965c8-c4a5-4886-b4b5-4d500f1aced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158344213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3158344213
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.118836732
Short name T398
Test name
Test status
Simulation time 12071014750 ps
CPU time 1376.11 seconds
Started Jul 19 04:55:43 PM PDT 24
Finished Jul 19 05:18:40 PM PDT 24
Peak memory 762236 kb
Host smart-3944bfb4-b632-4a75-860a-5987a6deda2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118836732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.118836732
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.209070612
Short name T145
Test name
Test status
Simulation time 258911736 ps
CPU time 4.84 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:55:48 PM PDT 24
Peak memory 200020 kb
Host smart-5469abdc-3b85-4dc4-8f88-e97466d43846
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209070612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.209070612
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.146132471
Short name T77
Test name
Test status
Simulation time 21292414271 ps
CPU time 205.14 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 216660 kb
Host smart-54b41464-56f6-45b7-98c1-dbc12868d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146132471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.146132471
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2951628554
Short name T48
Test name
Test status
Simulation time 47556180 ps
CPU time 0.85 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 04:55:43 PM PDT 24
Peak memory 218524 kb
Host smart-617736ab-9e6b-4765-bba6-677601bd37f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951628554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2951628554
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2541145984
Short name T320
Test name
Test status
Simulation time 589586637 ps
CPU time 16.4 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:55:58 PM PDT 24
Peak memory 200256 kb
Host smart-69b74ca8-6f9c-4821-932f-a64beb201b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541145984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2541145984
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1135504707
Short name T130
Test name
Test status
Simulation time 17224989136 ps
CPU time 75.41 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 04:57:01 PM PDT 24
Peak memory 208280 kb
Host smart-dd3e3679-94b8-4e22-8572-836f61466a93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135504707 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1135504707
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.475363622
Short name T7
Test name
Test status
Simulation time 117767712817 ps
CPU time 336.28 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 05:01:19 PM PDT 24
Peak memory 216764 kb
Host smart-a68d524b-d47f-47a1-8000-9dad0762b3c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475363622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.475363622
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1003589801
Short name T372
Test name
Test status
Simulation time 3314084763 ps
CPU time 72.08 seconds
Started Jul 19 04:55:45 PM PDT 24
Finished Jul 19 04:56:59 PM PDT 24
Peak memory 200328 kb
Host smart-92116f8e-ef61-4856-a630-76cb36b2c4cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1003589801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1003589801
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.249799820
Short name T212
Test name
Test status
Simulation time 6832100166 ps
CPU time 107.3 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:57:30 PM PDT 24
Peak memory 200304 kb
Host smart-78fd1d0b-f16c-4885-b195-f10d3a952e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=249799820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.249799820
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1944439960
Short name T319
Test name
Test status
Simulation time 34745651807 ps
CPU time 134.87 seconds
Started Jul 19 04:55:45 PM PDT 24
Finished Jul 19 04:58:02 PM PDT 24
Peak memory 200336 kb
Host smart-be382460-982a-4276-8824-d2a10021d466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1944439960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1944439960
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2404014614
Short name T480
Test name
Test status
Simulation time 12000371609 ps
CPU time 551.09 seconds
Started Jul 19 04:55:45 PM PDT 24
Finished Jul 19 05:04:57 PM PDT 24
Peak memory 200324 kb
Host smart-9a2c43b1-3475-4510-ac04-5f30d27aa5ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2404014614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2404014614
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.4253672733
Short name T245
Test name
Test status
Simulation time 80912769391 ps
CPU time 2396.5 seconds
Started Jul 19 04:55:41 PM PDT 24
Finished Jul 19 05:35:40 PM PDT 24
Peak memory 216000 kb
Host smart-0e83a9f9-b2cd-48a7-8102-6dacbea3d6ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4253672733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.4253672733
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.4086090382
Short name T133
Test name
Test status
Simulation time 40510212057 ps
CPU time 2240.04 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 05:33:06 PM PDT 24
Peak memory 215512 kb
Host smart-b9e58025-da29-4142-92c0-2aeedd31ffcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4086090382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.4086090382
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1011331745
Short name T165
Test name
Test status
Simulation time 30114602498 ps
CPU time 75.8 seconds
Started Jul 19 04:55:38 PM PDT 24
Finished Jul 19 04:56:55 PM PDT 24
Peak memory 200308 kb
Host smart-97071820-951c-45b0-8f50-3a7d9e941afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011331745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1011331745
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2138188806
Short name T489
Test name
Test status
Simulation time 17941219 ps
CPU time 0.56 seconds
Started Jul 19 04:57:36 PM PDT 24
Finished Jul 19 04:57:41 PM PDT 24
Peak memory 195836 kb
Host smart-57fef460-c675-4c9d-bdf2-7595b36d5137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138188806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2138188806
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.105573026
Short name T517
Test name
Test status
Simulation time 906643322 ps
CPU time 53.31 seconds
Started Jul 19 04:57:38 PM PDT 24
Finished Jul 19 04:58:35 PM PDT 24
Peak memory 200188 kb
Host smart-47eafff2-1d19-4f88-9bb5-67e4c007e0ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105573026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.105573026
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2421446627
Short name T169
Test name
Test status
Simulation time 2706621078 ps
CPU time 34.64 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 04:58:15 PM PDT 24
Peak memory 200312 kb
Host smart-3c911d70-1d35-4c39-b14c-f40274513782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421446627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2421446627
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2314985548
Short name T293
Test name
Test status
Simulation time 7962245652 ps
CPU time 817.72 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 05:11:18 PM PDT 24
Peak memory 703716 kb
Host smart-957aee43-dc8f-4ae6-8102-0a1d0c3c9454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314985548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2314985548
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1677023737
Short name T510
Test name
Test status
Simulation time 165845211139 ps
CPU time 169.76 seconds
Started Jul 19 04:57:35 PM PDT 24
Finished Jul 19 05:00:29 PM PDT 24
Peak memory 200296 kb
Host smart-595fd58c-32e3-4b59-bd81-04d38474dbe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677023737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1677023737
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1703000850
Short name T513
Test name
Test status
Simulation time 13601088246 ps
CPU time 62.17 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 04:58:43 PM PDT 24
Peak memory 200364 kb
Host smart-eb81b941-4e90-488e-a589-093e21955ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703000850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1703000850
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3332566197
Short name T307
Test name
Test status
Simulation time 5625014972 ps
CPU time 17.41 seconds
Started Jul 19 04:57:38 PM PDT 24
Finished Jul 19 04:57:59 PM PDT 24
Peak memory 200300 kb
Host smart-811d062f-9f5b-4410-81ed-e6046cf0d255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332566197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3332566197
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1365028431
Short name T9
Test name
Test status
Simulation time 9494440109 ps
CPU time 522.81 seconds
Started Jul 19 04:57:41 PM PDT 24
Finished Jul 19 05:06:25 PM PDT 24
Peak memory 215844 kb
Host smart-bccf0382-4800-4b8d-8ace-6b6189d00981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365028431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1365028431
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1356636939
Short name T179
Test name
Test status
Simulation time 2463217866 ps
CPU time 123.49 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 04:59:45 PM PDT 24
Peak memory 200180 kb
Host smart-f728cd43-5723-4b2b-8cc8-daa0fb5703a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356636939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1356636939
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.914316204
Short name T316
Test name
Test status
Simulation time 92419551 ps
CPU time 0.55 seconds
Started Jul 19 04:57:41 PM PDT 24
Finished Jul 19 04:57:43 PM PDT 24
Peak memory 195060 kb
Host smart-d67ad8be-4743-40c1-aba1-15610a9cc4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914316204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.914316204
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1058922379
Short name T530
Test name
Test status
Simulation time 1636985001 ps
CPU time 47.82 seconds
Started Jul 19 04:57:41 PM PDT 24
Finished Jul 19 04:58:30 PM PDT 24
Peak memory 200228 kb
Host smart-3ba47314-46ef-49ff-b89e-614f6bae826f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058922379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1058922379
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1257018987
Short name T474
Test name
Test status
Simulation time 5226943944 ps
CPU time 49.77 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 04:58:31 PM PDT 24
Peak memory 200320 kb
Host smart-e6936fcc-678d-49de-8439-552357ce4b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257018987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1257018987
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2940032264
Short name T314
Test name
Test status
Simulation time 4687197709 ps
CPU time 429.95 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 05:04:51 PM PDT 24
Peak memory 517292 kb
Host smart-9444927c-6f01-4a34-a192-dc31c2cab440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940032264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2940032264
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1425361029
Short name T341
Test name
Test status
Simulation time 390317493 ps
CPU time 19.79 seconds
Started Jul 19 04:57:42 PM PDT 24
Finished Jul 19 04:58:03 PM PDT 24
Peak memory 200192 kb
Host smart-6d7734ef-9d97-4f77-9997-0b1ba01176ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425361029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1425361029
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1977974213
Short name T380
Test name
Test status
Simulation time 4011876435 ps
CPU time 111.32 seconds
Started Jul 19 04:57:36 PM PDT 24
Finished Jul 19 04:59:31 PM PDT 24
Peak memory 200220 kb
Host smart-0ce08a9a-ff80-407c-9ca9-70956c3577d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977974213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1977974213
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3946682611
Short name T220
Test name
Test status
Simulation time 1028608857 ps
CPU time 11.91 seconds
Started Jul 19 04:57:41 PM PDT 24
Finished Jul 19 04:57:55 PM PDT 24
Peak memory 200144 kb
Host smart-18c0d1af-a100-4543-aa41-fc07af49673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946682611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3946682611
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1847026403
Short name T340
Test name
Test status
Simulation time 173980132065 ps
CPU time 1087.82 seconds
Started Jul 19 04:57:38 PM PDT 24
Finished Jul 19 05:15:49 PM PDT 24
Peak memory 626236 kb
Host smart-b197d83c-3a8f-41e9-9333-575e54e9a4ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847026403 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1847026403
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.575996875
Short name T481
Test name
Test status
Simulation time 2899277096 ps
CPU time 37.84 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 04:58:19 PM PDT 24
Peak memory 200304 kb
Host smart-6ba4bc91-e2ef-4a7d-afd3-6cd9f9cc32c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575996875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.575996875
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.358860669
Short name T511
Test name
Test status
Simulation time 32734269 ps
CPU time 0.59 seconds
Started Jul 19 04:57:44 PM PDT 24
Finished Jul 19 04:57:45 PM PDT 24
Peak memory 196064 kb
Host smart-1208e411-9a9e-417b-9917-54ecc6360e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358860669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.358860669
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1211065365
Short name T405
Test name
Test status
Simulation time 3304420504 ps
CPU time 25.21 seconds
Started Jul 19 04:57:36 PM PDT 24
Finished Jul 19 04:58:05 PM PDT 24
Peak memory 200356 kb
Host smart-80911d65-f3bd-4de8-a298-a54687b9e386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211065365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1211065365
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2269489863
Short name T427
Test name
Test status
Simulation time 55780243482 ps
CPU time 51.65 seconds
Started Jul 19 04:57:45 PM PDT 24
Finished Jul 19 04:58:38 PM PDT 24
Peak memory 200356 kb
Host smart-ed117240-2fdf-4bfd-90f7-99463d9ee659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269489863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2269489863
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2991850061
Short name T473
Test name
Test status
Simulation time 2276524878 ps
CPU time 365.94 seconds
Started Jul 19 04:57:42 PM PDT 24
Finished Jul 19 05:03:49 PM PDT 24
Peak memory 500016 kb
Host smart-ff64527d-6e08-46bd-987a-aaf7daa61dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991850061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2991850061
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3314016131
Short name T263
Test name
Test status
Simulation time 836344434 ps
CPU time 24.44 seconds
Started Jul 19 04:57:47 PM PDT 24
Finished Jul 19 04:58:12 PM PDT 24
Peak memory 200168 kb
Host smart-7385344a-3019-4bba-92bf-b20e669c78ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314016131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3314016131
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3297758447
Short name T394
Test name
Test status
Simulation time 22164743410 ps
CPU time 144.8 seconds
Started Jul 19 04:57:36 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 200312 kb
Host smart-a0abca18-34b9-40cc-98d3-8405b4c5b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297758447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3297758447
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.591219453
Short name T434
Test name
Test status
Simulation time 1537274105 ps
CPU time 7.81 seconds
Started Jul 19 04:57:37 PM PDT 24
Finished Jul 19 04:57:49 PM PDT 24
Peak memory 200200 kb
Host smart-4c574b64-f2e1-4aa5-ad5d-f09709da67d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591219453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.591219453
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1614916813
Short name T312
Test name
Test status
Simulation time 129283667524 ps
CPU time 2648.61 seconds
Started Jul 19 04:57:45 PM PDT 24
Finished Jul 19 05:41:55 PM PDT 24
Peak memory 758288 kb
Host smart-aaed8a32-f49a-485f-912c-f568e8cc8af8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614916813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1614916813
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2046526451
Short name T379
Test name
Test status
Simulation time 8981244100 ps
CPU time 49.75 seconds
Started Jul 19 04:57:44 PM PDT 24
Finished Jul 19 04:58:34 PM PDT 24
Peak memory 200356 kb
Host smart-ccc412c6-1376-4b02-a639-e7cb49dfb93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046526451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2046526451
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2570940570
Short name T247
Test name
Test status
Simulation time 15076845 ps
CPU time 0.59 seconds
Started Jul 19 04:57:45 PM PDT 24
Finished Jul 19 04:57:46 PM PDT 24
Peak memory 195768 kb
Host smart-979768c1-e4f4-4549-a28f-830b6ed98d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570940570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2570940570
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1679404529
Short name T463
Test name
Test status
Simulation time 295557983 ps
CPU time 8.07 seconds
Started Jul 19 04:57:49 PM PDT 24
Finished Jul 19 04:57:58 PM PDT 24
Peak memory 200160 kb
Host smart-53b344ca-367a-4933-8656-d57812489324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679404529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1679404529
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.434293022
Short name T417
Test name
Test status
Simulation time 17895871996 ps
CPU time 703.32 seconds
Started Jul 19 04:57:48 PM PDT 24
Finished Jul 19 05:09:32 PM PDT 24
Peak memory 730772 kb
Host smart-94a970b9-7627-406f-a5b9-71e0465d71c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434293022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.434293022
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.141425771
Short name T485
Test name
Test status
Simulation time 26459767742 ps
CPU time 96.3 seconds
Started Jul 19 04:57:44 PM PDT 24
Finished Jul 19 04:59:21 PM PDT 24
Peak memory 200452 kb
Host smart-21c65aed-8111-4533-85da-4c2870e627de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141425771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.141425771
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1369049256
Short name T264
Test name
Test status
Simulation time 35984828567 ps
CPU time 148.76 seconds
Started Jul 19 04:57:47 PM PDT 24
Finished Jul 19 05:00:17 PM PDT 24
Peak memory 200268 kb
Host smart-a0e8e862-b370-4c24-b3bf-e1fbde087831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369049256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1369049256
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1427066525
Short name T16
Test name
Test status
Simulation time 671509664 ps
CPU time 10.89 seconds
Started Jul 19 04:57:46 PM PDT 24
Finished Jul 19 04:57:58 PM PDT 24
Peak memory 200256 kb
Host smart-44b17625-ba7b-46e0-b4bb-8aae35c583a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427066525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1427066525
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.173055877
Short name T295
Test name
Test status
Simulation time 33726180124 ps
CPU time 1110.79 seconds
Started Jul 19 04:57:44 PM PDT 24
Finished Jul 19 05:16:16 PM PDT 24
Peak memory 659852 kb
Host smart-4348d6ef-41d6-4495-916e-49882425dbb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173055877 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.173055877
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2600494969
Short name T172
Test name
Test status
Simulation time 38795239380 ps
CPU time 67.44 seconds
Started Jul 19 04:57:48 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 200328 kb
Host smart-e3a5463a-b5b3-4017-b9ef-0e86c2fbfa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600494969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2600494969
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3139803864
Short name T428
Test name
Test status
Simulation time 49199398 ps
CPU time 0.59 seconds
Started Jul 19 04:57:55 PM PDT 24
Finished Jul 19 04:57:56 PM PDT 24
Peak memory 195816 kb
Host smart-cc1c3875-ee6b-414d-a850-2c1d1ace0422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139803864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3139803864
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2934850883
Short name T453
Test name
Test status
Simulation time 1556627350 ps
CPU time 44.05 seconds
Started Jul 19 04:57:45 PM PDT 24
Finished Jul 19 04:58:30 PM PDT 24
Peak memory 200248 kb
Host smart-335c18f7-7d41-477d-ae91-43d9858e9fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934850883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2934850883
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3649900296
Short name T19
Test name
Test status
Simulation time 515520824 ps
CPU time 14.05 seconds
Started Jul 19 04:57:54 PM PDT 24
Finished Jul 19 04:58:09 PM PDT 24
Peak memory 200244 kb
Host smart-3ed1fb5b-8afe-4566-8e4d-e82d3a8a267d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649900296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3649900296
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3620872374
Short name T442
Test name
Test status
Simulation time 4016922495 ps
CPU time 752.3 seconds
Started Jul 19 04:57:55 PM PDT 24
Finished Jul 19 05:10:28 PM PDT 24
Peak memory 680188 kb
Host smart-476f6cce-6856-403c-8be4-e5889c88f3a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620872374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3620872374
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.103620953
Short name T183
Test name
Test status
Simulation time 6145760886 ps
CPU time 105.57 seconds
Started Jul 19 04:57:54 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 200288 kb
Host smart-f919312f-b42f-49a2-9e02-fcb7ff92d5b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103620953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.103620953
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1215634424
Short name T249
Test name
Test status
Simulation time 8466368549 ps
CPU time 116.68 seconds
Started Jul 19 04:57:46 PM PDT 24
Finished Jul 19 04:59:44 PM PDT 24
Peak memory 200384 kb
Host smart-e638368e-1bec-4006-a049-f245894c769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215634424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1215634424
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3207040604
Short name T418
Test name
Test status
Simulation time 2354305260 ps
CPU time 12.65 seconds
Started Jul 19 04:57:45 PM PDT 24
Finished Jul 19 04:57:58 PM PDT 24
Peak memory 200264 kb
Host smart-9d0c705a-d477-4435-9f3f-423e5afae332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207040604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3207040604
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1972362621
Short name T198
Test name
Test status
Simulation time 39540170635 ps
CPU time 2076.11 seconds
Started Jul 19 04:57:53 PM PDT 24
Finished Jul 19 05:32:30 PM PDT 24
Peak memory 772504 kb
Host smart-8732769c-efaa-421f-b1e3-4153cd02f56d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972362621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1972362621
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1935506571
Short name T269
Test name
Test status
Simulation time 25045367685 ps
CPU time 33.23 seconds
Started Jul 19 04:57:54 PM PDT 24
Finished Jul 19 04:58:29 PM PDT 24
Peak memory 200368 kb
Host smart-89aa72f6-0381-4b33-86a5-8ee0520da8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935506571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1935506571
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.4013400678
Short name T346
Test name
Test status
Simulation time 46013714 ps
CPU time 0.62 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:58:04 PM PDT 24
Peak memory 196836 kb
Host smart-714b18fc-cb4a-4b53-bcf0-21e7c1558503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013400678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4013400678
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.208639230
Short name T472
Test name
Test status
Simulation time 2151438912 ps
CPU time 60.19 seconds
Started Jul 19 04:57:53 PM PDT 24
Finished Jul 19 04:58:54 PM PDT 24
Peak memory 200304 kb
Host smart-58dbd676-04b8-4845-9c35-d3dd3e23a6d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208639230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.208639230
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2615096200
Short name T234
Test name
Test status
Simulation time 10441647259 ps
CPU time 50.39 seconds
Started Jul 19 04:57:55 PM PDT 24
Finished Jul 19 04:58:47 PM PDT 24
Peak memory 200352 kb
Host smart-35c31fb4-b138-4b6e-a715-bad05b3ec55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615096200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2615096200
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2906854024
Short name T407
Test name
Test status
Simulation time 1636753678 ps
CPU time 145.71 seconds
Started Jul 19 04:57:54 PM PDT 24
Finished Jul 19 05:00:21 PM PDT 24
Peak memory 603700 kb
Host smart-4a952b48-cc5e-4bbc-8fdc-8edbbe9d327c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906854024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2906854024
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2956055197
Short name T186
Test name
Test status
Simulation time 380762459 ps
CPU time 10.34 seconds
Started Jul 19 04:57:55 PM PDT 24
Finished Jul 19 04:58:06 PM PDT 24
Peak memory 200120 kb
Host smart-483e7141-abe0-4a58-bd6e-0b46de56b0e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956055197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2956055197
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.496742621
Short name T385
Test name
Test status
Simulation time 11444425175 ps
CPU time 163.25 seconds
Started Jul 19 04:57:55 PM PDT 24
Finished Jul 19 05:00:39 PM PDT 24
Peak memory 200312 kb
Host smart-82c92578-d6ec-4726-bfc7-615d054074b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496742621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.496742621
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3495507193
Short name T3
Test name
Test status
Simulation time 1742066814 ps
CPU time 10.78 seconds
Started Jul 19 04:57:56 PM PDT 24
Finished Jul 19 04:58:07 PM PDT 24
Peak memory 200244 kb
Host smart-d3480455-671e-43d5-80ef-70230783be8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495507193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3495507193
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2324980508
Short name T42
Test name
Test status
Simulation time 64085508237 ps
CPU time 1306.95 seconds
Started Jul 19 04:57:57 PM PDT 24
Finished Jul 19 05:19:45 PM PDT 24
Peak memory 723816 kb
Host smart-a2562747-9570-436d-bb54-c827e89d394a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324980508 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2324980508
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1086876283
Short name T91
Test name
Test status
Simulation time 6717758711 ps
CPU time 91.25 seconds
Started Jul 19 04:57:53 PM PDT 24
Finished Jul 19 04:59:25 PM PDT 24
Peak memory 200284 kb
Host smart-34d6fb87-f151-4060-8480-92ad6c59cbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086876283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1086876283
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3963454807
Short name T455
Test name
Test status
Simulation time 15021092 ps
CPU time 0.61 seconds
Started Jul 19 04:58:02 PM PDT 24
Finished Jul 19 04:58:05 PM PDT 24
Peak memory 196876 kb
Host smart-a1c420d1-b3e2-4d32-9bf5-664d7ac1aff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963454807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3963454807
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3985005660
Short name T333
Test name
Test status
Simulation time 1485889961 ps
CPU time 45.51 seconds
Started Jul 19 04:58:03 PM PDT 24
Finished Jul 19 04:58:50 PM PDT 24
Peak memory 200224 kb
Host smart-50dc0e0d-1878-4da2-9f28-e6482d07f6f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985005660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3985005660
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1395442976
Short name T414
Test name
Test status
Simulation time 1513355081 ps
CPU time 62.37 seconds
Started Jul 19 04:58:02 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 200208 kb
Host smart-33f120c7-ff4b-4eef-b94e-c1b5f6f82664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395442976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1395442976
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3704886364
Short name T289
Test name
Test status
Simulation time 2222155244 ps
CPU time 170.8 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 05:00:53 PM PDT 24
Peak memory 355536 kb
Host smart-fe652df3-0507-4b22-8a01-f20a95d8e2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704886364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3704886364
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2638791433
Short name T232
Test name
Test status
Simulation time 1345597455 ps
CPU time 40.88 seconds
Started Jul 19 04:58:00 PM PDT 24
Finished Jul 19 04:58:41 PM PDT 24
Peak memory 200224 kb
Host smart-72b76fbe-124f-4cb3-8eb5-3d9b240f772c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638791433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2638791433
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2046476394
Short name T163
Test name
Test status
Simulation time 9814102635 ps
CPU time 136.22 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 05:00:20 PM PDT 24
Peak memory 200472 kb
Host smart-a1ae484e-8251-419c-a21b-fc640b26bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046476394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2046476394
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1544369546
Short name T196
Test name
Test status
Simulation time 3570915587 ps
CPU time 10.94 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:58:14 PM PDT 24
Peak memory 200320 kb
Host smart-6bdb707e-7aa8-49f7-abdb-f562609da617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544369546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1544369546
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.203964319
Short name T258
Test name
Test status
Simulation time 70345659367 ps
CPU time 1368.99 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 05:20:53 PM PDT 24
Peak memory 691880 kb
Host smart-547cd4d6-5888-4f31-88a1-b1dcb472b34b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203964319 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.203964319
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2664548265
Short name T268
Test name
Test status
Simulation time 5370277828 ps
CPU time 14.93 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:58:18 PM PDT 24
Peak memory 200160 kb
Host smart-e19267fe-1433-4d62-ab5d-516a9e1f63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664548265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2664548265
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1515858783
Short name T275
Test name
Test status
Simulation time 39741127 ps
CPU time 0.59 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:58:04 PM PDT 24
Peak memory 195840 kb
Host smart-4e5b9bc5-80bd-4a8c-b2a8-f3eca3816633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515858783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1515858783
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4177334144
Short name T200
Test name
Test status
Simulation time 352793400 ps
CPU time 20.05 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:58:23 PM PDT 24
Peak memory 200212 kb
Host smart-fb06a034-b9d8-4df7-adac-66181650df87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177334144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4177334144
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2558820970
Short name T369
Test name
Test status
Simulation time 1162557799 ps
CPU time 53.06 seconds
Started Jul 19 04:58:02 PM PDT 24
Finished Jul 19 04:58:57 PM PDT 24
Peak memory 200212 kb
Host smart-a8ac0d25-a3ce-4e28-aa8f-70ebb0e65d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558820970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2558820970
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1710494696
Short name T504
Test name
Test status
Simulation time 15019152756 ps
CPU time 584.73 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 05:07:48 PM PDT 24
Peak memory 656644 kb
Host smart-40698573-60f2-4940-8a39-91dc53e99ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710494696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1710494696
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3882138199
Short name T37
Test name
Test status
Simulation time 461713588 ps
CPU time 7.97 seconds
Started Jul 19 04:58:02 PM PDT 24
Finished Jul 19 04:58:12 PM PDT 24
Peak memory 200108 kb
Host smart-4fb27807-07b6-497b-b6e8-b2337b1cb13f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882138199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3882138199
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1776194544
Short name T182
Test name
Test status
Simulation time 8587378101 ps
CPU time 98.62 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:59:42 PM PDT 24
Peak memory 208472 kb
Host smart-858f6aef-9b4d-421b-96f8-3544b85f69dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776194544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1776194544
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1524303708
Short name T331
Test name
Test status
Simulation time 425484365 ps
CPU time 3.09 seconds
Started Jul 19 04:58:03 PM PDT 24
Finished Jul 19 04:58:07 PM PDT 24
Peak memory 200188 kb
Host smart-11dc847b-8031-4b29-976b-cb89ad423d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524303708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1524303708
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3360395833
Short name T460
Test name
Test status
Simulation time 560209911835 ps
CPU time 2978.09 seconds
Started Jul 19 04:58:00 PM PDT 24
Finished Jul 19 05:47:40 PM PDT 24
Peak memory 722740 kb
Host smart-8cbed7bf-44d5-4450-984d-6b7302538752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360395833 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3360395833
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.913605576
Short name T87
Test name
Test status
Simulation time 3802524312 ps
CPU time 97.44 seconds
Started Jul 19 04:58:01 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 200312 kb
Host smart-7f62e195-5664-4b94-8319-7bdd10123277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913605576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.913605576
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4246861737
Short name T246
Test name
Test status
Simulation time 90216044 ps
CPU time 0.61 seconds
Started Jul 19 04:58:10 PM PDT 24
Finished Jul 19 04:58:13 PM PDT 24
Peak memory 196140 kb
Host smart-7128360f-f2e0-44ce-bcf9-88c88f5ded3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246861737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4246861737
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.943013656
Short name T450
Test name
Test status
Simulation time 6776401044 ps
CPU time 102.19 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 04:59:53 PM PDT 24
Peak memory 200300 kb
Host smart-4405b228-2bf0-4d5a-a9f8-cd2fa7bc3ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943013656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.943013656
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1183312084
Short name T374
Test name
Test status
Simulation time 1001792782 ps
CPU time 55.33 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 04:59:06 PM PDT 24
Peak memory 200228 kb
Host smart-de0a244a-ed1e-4939-92c6-cf800d84add5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183312084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1183312084
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3110122256
Short name T36
Test name
Test status
Simulation time 1698941751 ps
CPU time 333.71 seconds
Started Jul 19 04:58:10 PM PDT 24
Finished Jul 19 05:03:46 PM PDT 24
Peak memory 625692 kb
Host smart-0f51d198-56c6-4bed-9725-3906fe8e4c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110122256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3110122256
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2766152586
Short name T55
Test name
Test status
Simulation time 6772748577 ps
CPU time 34.95 seconds
Started Jul 19 04:58:10 PM PDT 24
Finished Jul 19 04:58:46 PM PDT 24
Peak memory 200336 kb
Host smart-515ce787-6784-4e57-910f-01143d897993
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766152586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2766152586
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3259267726
Short name T57
Test name
Test status
Simulation time 3995789698 ps
CPU time 60.53 seconds
Started Jul 19 04:58:10 PM PDT 24
Finished Jul 19 04:59:12 PM PDT 24
Peak memory 200268 kb
Host smart-c26314d8-6acb-46df-9daf-27beca6356ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259267726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3259267726
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3624402427
Short name T430
Test name
Test status
Simulation time 53090464 ps
CPU time 2.84 seconds
Started Jul 19 04:58:11 PM PDT 24
Finished Jul 19 04:58:16 PM PDT 24
Peak memory 200216 kb
Host smart-9d61d967-4b9d-4056-a65c-f7c88a0851b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624402427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3624402427
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.394857750
Short name T139
Test name
Test status
Simulation time 20674785491 ps
CPU time 603.77 seconds
Started Jul 19 04:58:11 PM PDT 24
Finished Jul 19 05:08:17 PM PDT 24
Peak memory 327788 kb
Host smart-fcded628-c141-4b5f-a2d8-5cc95527000d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394857750 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.394857750
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3085764188
Short name T416
Test name
Test status
Simulation time 2234393148 ps
CPU time 32.37 seconds
Started Jul 19 04:58:10 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 200356 kb
Host smart-6b4f7fc9-50dc-444f-a967-57a106d5863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085764188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3085764188
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1733609055
Short name T339
Test name
Test status
Simulation time 13664558 ps
CPU time 0.6 seconds
Started Jul 19 04:58:08 PM PDT 24
Finished Jul 19 04:58:10 PM PDT 24
Peak memory 196196 kb
Host smart-639d2a5f-70bf-48ba-a70e-fa441ec301b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733609055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1733609055
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4021371903
Short name T370
Test name
Test status
Simulation time 955085808 ps
CPU time 55.31 seconds
Started Jul 19 04:58:10 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 200284 kb
Host smart-e440e071-65da-4d0c-a821-4d0c4bddb9c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021371903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4021371903
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1721434266
Short name T329
Test name
Test status
Simulation time 11030057734 ps
CPU time 36.58 seconds
Started Jul 19 04:58:11 PM PDT 24
Finished Jul 19 04:58:49 PM PDT 24
Peak memory 200300 kb
Host smart-e80d8155-936b-43c7-bbc0-01557897d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721434266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1721434266
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2882312190
Short name T226
Test name
Test status
Simulation time 4856258366 ps
CPU time 232.34 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 05:02:02 PM PDT 24
Peak memory 599548 kb
Host smart-ed0f4e38-0190-4fa8-99d6-78196ca5dcf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2882312190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2882312190
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1918456917
Short name T378
Test name
Test status
Simulation time 28515882128 ps
CPU time 182.47 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 05:01:13 PM PDT 24
Peak memory 200200 kb
Host smart-6ac9a36d-1388-4167-8313-4234e3a7a854
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918456917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1918456917
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1427202885
Short name T81
Test name
Test status
Simulation time 5571410896 ps
CPU time 109.11 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 05:00:00 PM PDT 24
Peak memory 200284 kb
Host smart-ead1c253-5d33-402d-adac-74e2089c4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427202885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1427202885
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2587338960
Short name T332
Test name
Test status
Simulation time 4002656436 ps
CPU time 4.97 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 04:58:16 PM PDT 24
Peak memory 200368 kb
Host smart-75f47064-f7da-4213-b19d-012c31080d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587338960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2587338960
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3225627398
Short name T67
Test name
Test status
Simulation time 846909103 ps
CPU time 12.23 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 04:58:24 PM PDT 24
Peak memory 200252 kb
Host smart-d6a297ed-7a59-4a45-957d-a6f14ffe696d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225627398 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3225627398
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4088784065
Short name T520
Test name
Test status
Simulation time 51989535285 ps
CPU time 60.36 seconds
Started Jul 19 04:58:09 PM PDT 24
Finished Jul 19 04:59:10 PM PDT 24
Peak memory 200360 kb
Host smart-233398b4-05bc-4710-b387-bb5056426c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088784065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4088784065
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.646919518
Short name T493
Test name
Test status
Simulation time 24320093 ps
CPU time 0.61 seconds
Started Jul 19 04:55:45 PM PDT 24
Finished Jul 19 04:55:47 PM PDT 24
Peak memory 196076 kb
Host smart-286ce8dc-7756-42d3-80a2-3ea5852138af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646919518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.646919518
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1670933904
Short name T181
Test name
Test status
Simulation time 161203884 ps
CPU time 9.39 seconds
Started Jul 19 04:55:45 PM PDT 24
Finished Jul 19 04:55:56 PM PDT 24
Peak memory 200244 kb
Host smart-fc1a1ccc-65e7-4bd6-a438-6cc830ac0ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670933904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1670933904
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2907267189
Short name T140
Test name
Test status
Simulation time 596591730 ps
CPU time 9.65 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:55:52 PM PDT 24
Peak memory 200216 kb
Host smart-aa05a4dd-345a-44ec-bee5-d3b64e500076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907267189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2907267189
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.812248201
Short name T160
Test name
Test status
Simulation time 2039095892 ps
CPU time 334.8 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 05:01:17 PM PDT 24
Peak memory 473412 kb
Host smart-5e191518-a795-4bba-bcd3-35ee83b4c524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812248201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.812248201
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1063675503
Short name T231
Test name
Test status
Simulation time 15375954427 ps
CPU time 232.51 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:59:35 PM PDT 24
Peak memory 200148 kb
Host smart-27ccbec9-c3ae-41e3-a4c0-a21e4162c911
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063675503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1063675503
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4047703579
Short name T184
Test name
Test status
Simulation time 4121387592 ps
CPU time 57.69 seconds
Started Jul 19 04:55:41 PM PDT 24
Finished Jul 19 04:56:41 PM PDT 24
Peak memory 200276 kb
Host smart-722ffd44-417f-4a9d-83d9-f66fc14c1f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047703579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4047703579
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1733869671
Short name T286
Test name
Test status
Simulation time 121740923 ps
CPU time 1.7 seconds
Started Jul 19 04:55:43 PM PDT 24
Finished Jul 19 04:55:46 PM PDT 24
Peak memory 200120 kb
Host smart-55da63f8-fd63-4366-89e9-1959f5a866ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733869671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1733869671
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4029519694
Short name T313
Test name
Test status
Simulation time 239279340685 ps
CPU time 796.16 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 05:08:58 PM PDT 24
Peak memory 484016 kb
Host smart-50e49f31-d4c3-491c-8ead-b9ee2570b606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029519694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4029519694
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2333084292
Short name T66
Test name
Test status
Simulation time 310576398356 ps
CPU time 2408.62 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 05:35:55 PM PDT 24
Peak memory 661300 kb
Host smart-df02f42f-ec80-451c-be41-12745d3e7e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333084292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2333084292
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.191396386
Short name T32
Test name
Test status
Simulation time 41132790722 ps
CPU time 131.82 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:57:54 PM PDT 24
Peak memory 200412 kb
Host smart-ac91a2bd-6500-4fcd-aad3-1a62201980bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191396386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.191396386
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2414887575
Short name T311
Test name
Test status
Simulation time 15039663 ps
CPU time 0.62 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 04:55:46 PM PDT 24
Peak memory 197016 kb
Host smart-9a644c62-7098-4ff0-9551-588f188cba09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414887575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2414887575
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1139597008
Short name T338
Test name
Test status
Simulation time 1176990796 ps
CPU time 72 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 04:56:57 PM PDT 24
Peak memory 200188 kb
Host smart-b38bfa09-71d7-4ca8-bab7-c7d7d1828de2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139597008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1139597008
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.762040990
Short name T408
Test name
Test status
Simulation time 491514250 ps
CPU time 25.25 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 04:56:06 PM PDT 24
Peak memory 200244 kb
Host smart-53640621-60ab-4efa-9c75-960739a6023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762040990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.762040990
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2353681939
Short name T238
Test name
Test status
Simulation time 7614408166 ps
CPU time 197.11 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 04:58:59 PM PDT 24
Peak memory 322952 kb
Host smart-8cd0eae3-b3f0-451e-b00d-348a58415a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353681939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2353681939
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.312074345
Short name T390
Test name
Test status
Simulation time 11394046488 ps
CPU time 149.97 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 04:58:15 PM PDT 24
Peak memory 200456 kb
Host smart-80865f6a-f229-4e75-9499-0f9c2f873539
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312074345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.312074345
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2313311088
Short name T468
Test name
Test status
Simulation time 1242758191 ps
CPU time 76.32 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:57:05 PM PDT 24
Peak memory 200236 kb
Host smart-b8ccd394-3556-4f4d-9217-74fd6851408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313311088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2313311088
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2367310033
Short name T365
Test name
Test status
Simulation time 13801396 ps
CPU time 0.71 seconds
Started Jul 19 04:55:41 PM PDT 24
Finished Jul 19 04:55:44 PM PDT 24
Peak memory 198260 kb
Host smart-a501da6c-a630-4662-b0a8-82c920b5d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367310033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2367310033
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4024387612
Short name T68
Test name
Test status
Simulation time 39285357838 ps
CPU time 524.87 seconds
Started Jul 19 04:55:44 PM PDT 24
Finished Jul 19 05:04:30 PM PDT 24
Peak memory 208664 kb
Host smart-ec9c9888-c695-4dfc-b2fa-bc8117b4853a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024387612 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4024387612
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.19670487
Short name T469
Test name
Test status
Simulation time 345180978 ps
CPU time 16.76 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 04:55:58 PM PDT 24
Peak memory 200180 kb
Host smart-fd3bac94-77f3-4ad9-ad02-3d6aaae0145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19670487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.19670487
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.215277911
Short name T354
Test name
Test status
Simulation time 91033361 ps
CPU time 0.62 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:55:52 PM PDT 24
Peak memory 195804 kb
Host smart-962c67d8-2048-4704-a678-9fa487dd040e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215277911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.215277911
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1667542198
Short name T174
Test name
Test status
Simulation time 3540937118 ps
CPU time 104.2 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:57:26 PM PDT 24
Peak memory 200180 kb
Host smart-1b3b2fd2-74f0-4968-a595-46c027751492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667542198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1667542198
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.210758634
Short name T195
Test name
Test status
Simulation time 284066381 ps
CPU time 30.24 seconds
Started Jul 19 04:55:43 PM PDT 24
Finished Jul 19 04:56:15 PM PDT 24
Peak memory 253668 kb
Host smart-5c4bcd20-099f-4dac-900b-09556f07d26b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210758634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.210758634
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1627183018
Short name T448
Test name
Test status
Simulation time 19252594383 ps
CPU time 128.67 seconds
Started Jul 19 04:55:39 PM PDT 24
Finished Jul 19 04:57:51 PM PDT 24
Peak memory 200244 kb
Host smart-379076a0-f051-4ac5-a1c3-b63f0550d803
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627183018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1627183018
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4168552260
Short name T298
Test name
Test status
Simulation time 54551263544 ps
CPU time 146 seconds
Started Jul 19 04:55:40 PM PDT 24
Finished Jul 19 04:58:08 PM PDT 24
Peak memory 200568 kb
Host smart-4bdf79ad-b176-4bbf-92bc-4b2d3486a5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168552260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4168552260
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1441409680
Short name T256
Test name
Test status
Simulation time 580169513 ps
CPU time 13.96 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:56:04 PM PDT 24
Peak memory 200228 kb
Host smart-48c10094-fa07-4302-9cb7-b8a932eb9e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441409680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1441409680
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3054058018
Short name T496
Test name
Test status
Simulation time 16010516251 ps
CPU time 2818.15 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 05:42:48 PM PDT 24
Peak memory 785364 kb
Host smart-69814cf6-b671-4feb-9e98-56abfa427c31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054058018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3054058018
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1667100101
Short name T65
Test name
Test status
Simulation time 79738071215 ps
CPU time 1833.84 seconds
Started Jul 19 04:55:46 PM PDT 24
Finished Jul 19 05:26:22 PM PDT 24
Peak memory 724820 kb
Host smart-2413a5e8-49ae-4e9a-889a-80b0dd1cc069
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667100101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1667100101
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2158804532
Short name T280
Test name
Test status
Simulation time 5432532574 ps
CPU time 82.74 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:57:13 PM PDT 24
Peak memory 200284 kb
Host smart-2cd25d5c-d011-4ed6-abfe-ed3aba12e1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158804532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2158804532
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3641551540
Short name T228
Test name
Test status
Simulation time 19312863 ps
CPU time 0.61 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:55:51 PM PDT 24
Peak memory 195068 kb
Host smart-0c067b3b-0bc0-44df-8259-77921426142f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641551540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3641551540
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4072970735
Short name T204
Test name
Test status
Simulation time 2474885018 ps
CPU time 77.44 seconds
Started Jul 19 04:56:02 PM PDT 24
Finished Jul 19 04:57:21 PM PDT 24
Peak memory 200164 kb
Host smart-3e17c08f-c939-4132-a7ca-22efc2f0d379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072970735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4072970735
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4145390760
Short name T308
Test name
Test status
Simulation time 2614739637 ps
CPU time 47.53 seconds
Started Jul 19 04:55:49 PM PDT 24
Finished Jul 19 04:56:39 PM PDT 24
Peak memory 200324 kb
Host smart-87b9a00b-ffd1-498e-bba0-9f894ba5db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145390760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4145390760
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2759443240
Short name T284
Test name
Test status
Simulation time 5117402162 ps
CPU time 498.75 seconds
Started Jul 19 04:56:01 PM PDT 24
Finished Jul 19 05:04:22 PM PDT 24
Peak memory 703920 kb
Host smart-aff0fe27-d91a-42a0-9302-0a068be0c3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759443240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2759443240
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1299537294
Short name T347
Test name
Test status
Simulation time 110132025516 ps
CPU time 170.75 seconds
Started Jul 19 04:56:02 PM PDT 24
Finished Jul 19 04:58:54 PM PDT 24
Peak memory 200160 kb
Host smart-d1b3a0ed-8126-43c4-a1b7-ccddf737cb6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299537294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1299537294
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.6574398
Short name T162
Test name
Test status
Simulation time 12090493580 ps
CPU time 167.45 seconds
Started Jul 19 04:55:46 PM PDT 24
Finished Jul 19 04:58:36 PM PDT 24
Peak memory 200216 kb
Host smart-ae9997fc-2288-4053-ac35-519104737bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6574398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.6574398
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.652254255
Short name T465
Test name
Test status
Simulation time 6532629060 ps
CPU time 11.84 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:56:02 PM PDT 24
Peak memory 200264 kb
Host smart-83cfc4ae-842a-4893-9452-1525715034c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652254255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.652254255
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3483707958
Short name T72
Test name
Test status
Simulation time 158874027018 ps
CPU time 1128.14 seconds
Started Jul 19 04:56:00 PM PDT 24
Finished Jul 19 05:14:50 PM PDT 24
Peak memory 200164 kb
Host smart-dbf852d0-2c46-47e6-b71d-5369c5b9a496
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483707958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3483707958
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2977827891
Short name T64
Test name
Test status
Simulation time 69696545262 ps
CPU time 386.09 seconds
Started Jul 19 04:55:50 PM PDT 24
Finished Jul 19 05:02:18 PM PDT 24
Peak memory 262172 kb
Host smart-f87d1137-1452-49d3-b767-dc694a0dda0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977827891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2977827891
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1300510390
Short name T88
Test name
Test status
Simulation time 1848853244 ps
CPU time 100.9 seconds
Started Jul 19 04:55:46 PM PDT 24
Finished Jul 19 04:57:30 PM PDT 24
Peak memory 200296 kb
Host smart-79f115d6-a6ed-404d-a0ef-f73b30b062cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300510390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1300510390
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1004945248
Short name T187
Test name
Test status
Simulation time 12647764 ps
CPU time 0.64 seconds
Started Jul 19 04:55:49 PM PDT 24
Finished Jul 19 04:55:53 PM PDT 24
Peak memory 196196 kb
Host smart-86502093-e4a4-49b4-8c9f-25dbcaf758aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004945248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1004945248
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2090187717
Short name T33
Test name
Test status
Simulation time 4824077306 ps
CPU time 66.56 seconds
Started Jul 19 04:55:49 PM PDT 24
Finished Jul 19 04:56:58 PM PDT 24
Peak memory 200340 kb
Host smart-d79b30a7-83d3-4b89-bf40-b8a450bf2f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090187717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2090187717
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3763259766
Short name T444
Test name
Test status
Simulation time 4828918877 ps
CPU time 64.74 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:56:55 PM PDT 24
Peak memory 200348 kb
Host smart-519a74db-518f-4a5b-a1ca-6e044debdeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763259766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3763259766
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3875017905
Short name T393
Test name
Test status
Simulation time 1455853342 ps
CPU time 214.6 seconds
Started Jul 19 04:55:47 PM PDT 24
Finished Jul 19 04:59:24 PM PDT 24
Peak memory 481120 kb
Host smart-9569bf0e-37d3-411c-825f-b9dcc10e1047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875017905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3875017905
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3222401979
Short name T243
Test name
Test status
Simulation time 625609123 ps
CPU time 8.47 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:55:59 PM PDT 24
Peak memory 200100 kb
Host smart-21220260-9392-45e2-864c-d7b11e1ab899
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222401979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3222401979
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1516414810
Short name T497
Test name
Test status
Simulation time 28564268561 ps
CPU time 185.07 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:58:55 PM PDT 24
Peak memory 200244 kb
Host smart-e20bce4f-b979-495c-a440-254e7ee97061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516414810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1516414810
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.4057378204
Short name T265
Test name
Test status
Simulation time 1344429399 ps
CPU time 15.93 seconds
Started Jul 19 04:55:48 PM PDT 24
Finished Jul 19 04:56:06 PM PDT 24
Peak memory 200292 kb
Host smart-13fa25be-be30-4e2e-91eb-5b91d7d4fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057378204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4057378204
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2990247895
Short name T193
Test name
Test status
Simulation time 591510930986 ps
CPU time 1535.84 seconds
Started Jul 19 04:56:02 PM PDT 24
Finished Jul 19 05:21:40 PM PDT 24
Peak memory 700644 kb
Host smart-91dbe165-9255-4c8f-b9f5-67d262373f4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990247895 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2990247895
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1376604166
Short name T89
Test name
Test status
Simulation time 1375661332 ps
CPU time 64.38 seconds
Started Jul 19 04:55:49 PM PDT 24
Finished Jul 19 04:56:56 PM PDT 24
Peak memory 200256 kb
Host smart-cf1be528-e397-4498-932b-b0e4971293c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376604166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1376604166
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%